Semiconductor device

Abstract

This semiconductor device (70) comprises an active region (50) and a termination region (60) on a first conductivity-type semiconductor substrate (1). The active region (50) has a first conductivity-type first semiconductor layer (2) and second conductivity-type second semiconductor regions (4a, 6). The termination region (60) has: the first semiconductor layer (2); a second conductivity-type first semiconductor region (30) including a plurality of second conductivity-type first small regions (31); and a second conductivity-type third semiconductor region (34) provided continuously, from the edges of the second semiconductor regions (4a, 6) to a predetermined number of the first small regions (31), to be lower in concentration than the first small regions (31), the semiconductor substrate (1)-side surface of the second conductivity-type third semiconductor region (34) being shallower than the semiconductor substrate (1)-side surfaces of the first small regions (31).

Description

Semiconductor Devices

[0001] This disclosure relates to semiconductor devices.

[0002] Conventionally, a semiconductor device has been proposed that can reduce leakage current by providing a P-layer (FLR) that is provided at a fixed pitch at the edge termination portion and a P-layer that connects the P-layer, and by making the P-layer 10a have a lower impurity concentration than the P layer and a depth smaller than that of the P layer (see, for example, Patent Document 1 below).

[0003] Japanese Patent Application Laid-Open No. 2020-198375

[0004] However, the conventional FLR (Field Limiting Ring) structure has a problem in that the withstand voltage varies greatly due to dimensional variations and edge surface charges.

[0005] In order to solve the problems of the conventional technology described above, the present disclosure aims to provide a semiconductor device with an FLR structure that can reduce fluctuations in breakdown voltage due to dimensional variations and edge surface charges.

[0006] In order to solve the above-mentioned problems and achieve the object of the present disclosure, a semiconductor device according to the present disclosure has the following features: An active region for carrying a main current on a semiconductor substrate of a first conductivity type, and a termination region surrounding the active region, The active region includes a first semiconductor layer of the first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate, and a second semiconductor region of a second conductivity type provided on a surface of the first semiconductor layer opposite to the semiconductor substrate. The termination region comprises the first semiconductor layer and a first semiconductor region of a second conductivity type including a plurality of first small regions of a second conductivity type spaced apart in a surface layer of the first semiconductor layer; and within the first semiconductor layer, from an end of the second semiconductor region to a predetermined number of the first small regions, a third semiconductor region of the second conductivity type having a lower concentration than the first small regions and having a surface facing the semiconductor substrate shallower than the surfaces of the first small regions facing the semiconductor substrate, the third semiconductor region being located between the second semiconductor region and the first small regions closest to the active region and between the first small regions; and within the first semiconductor layer, a fourth semiconductor region of the first conductivity type between the surface of the first semiconductor layer and the third semiconductor region.

[0007] According to the above disclosure, by providing an inter-FLR low-concentration p-type layer (a third semiconductor region of the second conductivity type) in a form that connects the FLRs (first small regions of the second conductivity type), sufficient surface charge resistance can be ensured even if the dimensions of each FLR in the FLR structure vary, and edge breakdown voltage can be stabilized. Furthermore, a stable breakdown voltage can be ensured without performing SiC etching or high-acceleration ion implantation in the edge termination region, and by not using SiC etching or high-acceleration ion implantation, manufacturing costs can be reduced.

[0008] The semiconductor device according to the present disclosure has an effect of reducing fluctuations in breakdown voltage due to dimensional variations and edge surface charges in the FLR structure.

[0009] FIG. 1 is a cross-sectional view showing an edge termination structure of a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view showing an active structure of the silicon carbide semiconductor device according to an embodiment. FIG. 3 is a graph showing a concentration distribution in the depth direction of a p-type layer of a silicon carbide semiconductor device according to an embodiment. FIG. 4 is a graph showing a change in edge breakdown voltage due to FLR size variations and edge surface charges in a conventional silicon carbide semiconductor device. FIG. 5 is a graph showing a change in edge breakdown voltage due to FLR size variations and edge surface charges in a silicon carbide semiconductor device according to an embodiment. FIG. 6 is a cross-sectional view showing an electric field distribution in a conventional silicon carbide semiconductor device. FIG. 7 is a graph showing an electric field distribution in a conventional silicon carbide semiconductor device. FIG. 8 is a cross-sectional view showing a location where breakdown occurs in a conventional silicon carbide semiconductor device. FIG. 9 is a cross-sectional view showing an electric field distribution in a silicon carbide semiconductor device according to an embodiment. FIG. 10 is a graph showing an electric field distribution in a silicon carbide semiconductor device according to an embodiment. FIG. 11 is a cross-sectional view showing a location where breakdown occurs in a silicon carbide semiconductor device according to an embodiment. FIG. 12 is a graph showing electric field distributions in the conventional silicon carbide semiconductor devices and the silicon carbide semiconductor devices according to the embodiment.

[0010] <Outline of Embodiments of the Present Disclosure> In order to solve the above-described problems and achieve the object of the present disclosure, a semiconductor device according to the present disclosure has the following features: An active region for carrying a main current on a semiconductor substrate of a first conductivity type, and a termination region surrounding the periphery of the active region, The active region includes: a first semiconductor layer of the first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate, and a first semiconductor region of a second conductivity type provided on a surface of the first semiconductor layer opposite to the semiconductor substrate. The termination region comprises the first semiconductor layer, a second semiconductor region of a second conductivity type including a plurality of first small regions of a second conductivity type spaced apart on a surface layer of the first semiconductor layer, and a third semiconductor region of a second conductivity type within the first semiconductor layer, the third semiconductor region having a lower concentration than the first small regions and having a surface facing the semiconductor substrate closer to the surface of the first semiconductor layer than the surfaces of the first small regions facing the semiconductor substrate, and a fourth semiconductor region of a first conductivity type within the first semiconductor layer, between the surface of the first semiconductor layer and the third semiconductor region, and each of the first small regions is connected by the third semiconductor region and the fourth semiconductor region.

[0011] According to the above disclosure, by providing an inter-FLR low-concentration p-type layer (a third semiconductor region of the second conductivity type) in a form that connects the FLRs (first small regions of the second conductivity type), sufficient surface charge resistance can be ensured even if the dimensions of each FLR in the FLR structure vary, and edge breakdown voltage can be stabilized. Furthermore, a stable breakdown voltage can be ensured without performing SiC etching or high-acceleration ion implantation in the edge termination region, and by not using SiC etching or high-acceleration ion implantation, manufacturing costs can be reduced.

[0012] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the first small region has a central region having a second small region with a high impurity concentration on the surface side of the first semiconductor layer and a third small region with a low impurity concentration on the semiconductor substrate side of the second small region, an inner region located closer to the active region than the central region, and an outer region located opposite the inner region across the central region, and the inner region and outer region have lower impurity concentrations than the second small region.

[0013] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the fourth semiconductor region is provided from the surface of the first semiconductor layer to the surface of the third semiconductor region on the surface side of the first semiconductor layer, and the thickness of the fourth semiconductor region is equal to or smaller than the distance from the surface of the third semiconductor region on the semiconductor substrate side to the surface of the first small region on the semiconductor substrate side.

[0014] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the fourth semiconductor region is provided from the surface of the first semiconductor layer to the surface of the third semiconductor region on the surface side of the first semiconductor layer, and the thickness of the fourth semiconductor region is smaller than the thickness of the second sub-region of the first sub-region.

[0015] In addition, in the semiconductor device according to the present disclosure, the first small region has an impurity concentration of 5×10 in the second small region of the central region. 19 cm -3 That's it, 2 x 10 20 cm -3 In the third small region of the central region, the impurity concentration is 1×10 16 cm -3 That's it, 5 x 10 19 cm -3 The impurity concentration in the inner region and the outer region is 1×10 or less. 16 cm -3 That's it, 5 x 10 19 cm -3 The present invention is characterized by the following:

[0016] In addition, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the first small region has a width in the central region that is wider than the width of the inner region or the outer region in a direction parallel to the surface of the first semiconductor layer.

[0017] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the width of the inner region and the width of the outer region of the first small region are 3% or more and 20% or less of the width of the first small region located closest to the active region.

[0018] Furthermore, in the semiconductor device according to the present disclosure, the surface of the first semiconductor region and the surface of the second semiconductor region are the same as the surface of the first semiconductor layer.

[0019] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the width of the multiple first small regions narrows and the spacing between the first small regions widens from the active region side toward the chip edge, the width of the first small regions at the surface of the first semiconductor layer is 6.0 μm or more at the side closest to the active region and 2.0 μm or less at the side closest to the chip edge, the width of the first small regions is less than the width of the first small regions adjacent to the active region side, the spacing between the first small regions at the surface of the first semiconductor layer is 2.0 μm or less at the side closest to the active region and 3.0 μm or more at the side closest to the chip edge, the spacing between the first small regions is greater than the spacing between adjacent first small regions on the active region side, and there are 10 or more first small regions.

[0020] Further, in the semiconductor device according to the present disclosure, in the above disclosure, the impurity concentration of the third semiconductor region takes a maximum value on the semiconductor substrate side from the surface side of the first semiconductor layer, and the maximum value is higher than the impurity concentration of the first semiconductor layer and is 2×10 17 cm -3 The impurity concentration of the third semiconductor region is lower than that of the first small region in a region deeper than the position where the first small region has the maximum impurity concentration.

[0021] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above-mentioned disclosure, the end of the third semiconductor region on the chip end side is closer to the chip end side than the first part from the active region side where the spacing between the first small regions becomes 1.5 μm or more or the width of the first small regions becomes 3.0 μm or less.

[0022] <Findings underlying the present disclosure> First, the problems of conventional semiconductor devices will be described. In semiconductor devices, an edge termination region having a breakdown voltage structure is provided, surrounding the periphery of an active region through which current flows when the device is on. In power semiconductor devices, the breakdown voltage structure is fabricated by forming a p-type structure on the surface of an n-type substrate. Semiconductor elements using silicon carbide (SiC) as the semiconductor material (hereinafter referred to as silicon carbide semiconductor devices) mainly use a spatially modulated JTE (Junction Termination Extension) structure, an FLR structure, or a structure combining these.

[0023] The edge termination region's breakdown voltage structure serves to make the edge breakdown voltage equal to or greater than that of the active region by mitigating electric field concentration at the edge of the active region. This reduces the risk of thermal breakdown of the chip by causing breakdown in the active region, which has a larger area than the edge termination region, and also stabilizes the breakdown voltage by reducing the effect of charge accumulation on the surface of the edge termination region.

[0024] The spatially modulated JTE structure uses a patterned p-type region (JTE) to form a structural concentration distribution and prevent electric field concentration. The FLR structure disperses the electric field by arranging the p-type region in a ring shape when viewed from the surface, thereby achieving a high breakdown voltage. Furthermore, a structure in which an FLR is placed closer to the active region and a JTE is combined to cover it is also possible.

[0025] While the spatially modulated JTE structure can reduce the effects of dimensional variations and surface charges in the edge termination region, it requires multiple ion implantations in addition to the active region formation process, resulting in high manufacturing costs. Furthermore, in SiC, where impurities do not easily diffuse, etching of the surface SiC or ion implantation with high acceleration energy is required to ensure a depth equivalent to that of the active region, which also increases manufacturing costs. Furthermore, the FLR structure requires only a single ion implantation and can be formed simultaneously with the p-type region of the active region, resulting in relatively low manufacturing costs, but suffers from significant fluctuations in breakdown voltage due to dimensional variations and edge surface charges. A structure combining an FLR and a JTE formed simultaneously with the active region can stabilize breakdown voltage while limiting the ion implantation to a single step, but the high cost required to ensure depth remains an issue.

[0026] As described above, conventional breakdown voltage structures have been unable to achieve both low manufacturing costs and low breakdown voltage fluctuations. In order to solve the above-mentioned problems, the present disclosure provides a semiconductor device that employs an FLR structure, requires only one ion implantation step, and can be formed simultaneously with the p-type region of the active region, resulting in relatively low manufacturing costs, and further reduces fluctuations in breakdown voltage due to dimensional variations and edge surface charges.

[0027] Preferred embodiments of the semiconductor device according to the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate higher and lower impurity concentrations than layers and regions without these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted. Furthermore, descriptions of "same" or "equivalent" should preferably include variations within 5% in consideration of variations in manufacturing.

[0028] (Embodiment) A semiconductor device according to the present disclosure is configured using a wide bandgap semiconductor. In the embodiment, a silicon carbide semiconductor device fabricated using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as an example. Figure 1 is a cross-sectional view showing a structure from an edge termination region to an active region of a silicon carbide semiconductor device according to an embodiment. Figure 2 is a cross-sectional view showing a structure of an active region of a silicon carbide semiconductor device according to an embodiment.

[0029] As shown in FIGS. 1 and 2 , a silicon carbide semiconductor device 70 according to an embodiment includes an active region 50 and an edge termination region 60 surrounding the active region 50 in a semiconductor substrate made of silicon carbide (hereinafter referred to as a silicon carbide substrate (semiconductor chip)) . The active region 50 is a region through which current flows in the on-state. The edge termination region 60 is a region that relieves the electric field on the front surface side of the substrate in the drift region and maintains a breakdown voltage.

[0030] The silicon carbide substrate is made of silicon carbide. + Mold support substrate (n + A silicon carbide n-type substrate (first conductivity type semiconductor substrate) 1 is provided on the front surface thereof. - a first conductivity type drift region (first semiconductor layer) 2; and - n-type drift region 2 +and a p-type base region 5 made of silicon carbide on the surface opposite to the n-type silicon carbide substrate 1 side. + The n-type silicon carbide substrate 1 functions as a drain region. - type drift region 2 and n + Between the silicon carbide substrate 1 and the n-type silicon carbide substrate 2, for example, + A buffer layer or the like may be provided to reduce the growth of crystal defects from silicon carbide substrate 1 .

[0031] n + The silicon carbide substrate 1 is a silicon carbide single crystal substrate. - The n-type drift region 2 + The impurity concentration is lower than that of the n-type silicon carbide substrate 1. - The drift region 2 reaches the p-type base region 5 and is connected to the p-type base region 5 and the p-type base region 5 described later. + The gate insulating film 11 is in contact with the gate insulating film 11. - The impurity concentration of the drift region 2 is, for example, 5×10 16 cm -3 Below, the thickness is 5.0 μm or more.

[0032] Also, n - An n-type high concentration region (not shown) may be provided between the n-type drift region 2 and the p-type base region 5. When an n-type high concentration region is provided, the n-type high concentration region is formed between adjacent p-type regions as described later. + The n-type high concentration region is in contact with the p-type base region 5 at its upper surface and in contact with the n-type base region 4 at its lower surface. - The n-type high concentration region is in contact with the n-type drift region 2. + lower than that of the silicon carbide substrate 1 - It is higher than the type drift region 2.

[0033] n + A drain electrode 17 serving as a back surface electrode is provided on the second main surface (back surface, i.e., the back surface of the silicon carbide base) of the silicon carbide substrate 1. A drain electrode pad (not shown) is provided on the surface of the drain electrode 17.

[0034] A trench structure is formed on the first main surface side (p-type base region 5 side) of the silicon carbide substrate. Specifically, the trench 25 is formed on the n-type + The n-type silicon carbide substrate 1 is connected to the surface of the silicon carbide substrate 1 opposite to the first main surface side through the p-type base region 5. - The n-type impurity reaches the n-type drift region 2 (or the n-type high concentration region, if provided).

[0035] A gate insulating film 11 is formed along the inner wall of the trench 25, on the bottom and side walls of the trench 25, and a gate electrode 13 is formed inside the gate insulating film 11 in the trench 25. The gate electrode 13 is formed by the gate insulating film 11. - The gate electrode 13 is insulated from the p-type drift region 2 and the p-type base region 5. A part of the gate electrode 13 may protrude from above the trench 25 (the side where the source electrode 16, which will be described later, is provided) toward the source electrode 16.

[0036] n - n-type drift region 2 + The surface layer on the side opposite to the silicon carbide substrate 1 (the first main surface side of the silicon carbide substrate) is provided with an upper p + The upper p + The mold portion region 4a is provided between the trenches 25, for example. - In the drift region 2, an upper p + The lower part p that contacts the bottom of the mold part region 4a + The trench 25 has a bottom formed with a p + A p region 26 is provided in contact with the bottom of the trench 25. + The mold region 26 is provided at a position facing the bottom of the trench 25 in the depth direction (the direction from the source electrode 16 to the back surface electrode). + The mold part region 4a and the lower part p + The mold part region 4b is p + This becomes the mold part region 4.

[0037] p + The width of the mold region 26 is equal to or wider than the width of the trench 25.+ The width of the mold part region 4b is + The width of the trench 25 is equal to or wider than the width of the mold portion region 4a. + The p-type base region 5 and the p-type region 26 may be connected. + n sandwiched between mold regions 26 - It may be located within the mold drift region 2 .

[0038] Inside the p-type base region 5, an n-type ++ type source region 7 and p ++ A contact region 6 is selectively provided. ++ type source region 7 and p ++ The mold contact regions 6 abut each other.

[0039] Also, as shown in FIG. + Mold partial region 4b, upper part p + Mold part regions 4a and p ++ The contact region 6 extends to the edge of the active region 50. At the edge of the active region 50, the lower p + The end of the mold part region 4b is the upper p + Mold subregions 4a and p ++ It is preferable that the contact region 6 is located at least 3.0 μm away from the edge of the contact region 6 toward the active region 50 .

[0040] The interlayer insulating film 14 is provided on the entire first main surface side of the silicon carbide substrate so as to cover the gate electrode 13 embedded in the trench 25. The source electrode 16 is connected to the n-type silicon nitride film 14 through a contact hole opened in the interlayer insulating film 14. ++ type source region 7 and p ++The source electrode 16 is in contact with the contact region 6. The source electrode 16 is electrically insulated from the gate electrode 13 by the interlayer insulating film 14. A source electrode pad (not shown) is provided on the source electrode 16. A barrier metal 15 may be provided between the source electrode 16 and the interlayer insulating film 14, for example, to prevent diffusion of metal atoms from the source electrode 16 toward the gate electrode 13. A polyimide (not shown) that functions as a protective film is provided on the surface of the silicon carbide semiconductor device 70. Although FIG. 1 shows only two MOS gate structures (insulated gates made of a metal-oxide-semiconductor) in the active region 50, more MOS gate structures may be arranged in parallel.

[0041] In the edge termination region 60, n + The n-type silicon carbide substrate 1 is formed on the front surface thereof. - A mold drift region 2 is provided.

[0042] The edge termination region 60 is provided with an FLR structure (second semiconductor region of the second conductivity type) 30. The n-type semiconductor region 30 is located outside the FLR structure 30 (on the chip edge side). - The surface of the n-type drift region 2 functions as a channel stopper. ++ Type (p ++ A channel stopper region (not shown) is provided. - A high breakdown voltage in the lateral direction is maintained by the pn junction with the type drift region 2. The edge termination region 60 is covered with a field oxide film (not shown), and an HTO film (not shown) and an interlayer insulating film (not shown) are deposited in this order on the field oxide film.

[0043] In the silicon carbide semiconductor device according to the embodiment, an FLR structure 30 has a plurality of p-type FLRs (first small regions of a second conductivity type) 31 arranged on the first main surface side of the silicon carbide substrate. A high-concentration p-type FLR region 32, which is a shallow, highly concentrated region, is provided in the center of the surface side of the FLR 31. On the surface side of the FLR 31, a high-concentration p-type FLR region 32 is provided between the side surface of the FLR 31 and the side surface of the FLR 31, and between the n-type FLR region 32 and the n-type FLR 31. + The region on the silicon carbide substrate 1 side is a low-concentration p-type FLR region 33 having a lower impurity concentration than the high-concentration p-type FLR region 32.++ The high-concentration p-type FLR region 32 may have the same depth and impurity concentration as the high-concentration p-type contact region 6. The impurity concentration of the high-concentration p-type FLR region 32 is, for example, 5×10 19 cm -3 2x10 or more 20 cm -3 The depth of the lower surface of the low concentration p-type FLR region 33 is equal to or less than the upper p + The impurity concentration of the low concentration p-type FLR region 33 may be the same as the depth of the lower surface of the upper p-type partial region 4a. + The impurity concentration may be the same as that of the mold portion region 4a.

[0044] On the surface side of the FLR 31, the width between the side surface of the FLR 31 and the side surface of the high-concentration p-type FLR region 32 is preferably narrower than the width of the high-concentration p-type FLR region 32. More preferably, in order to suppress the electric field strength at the pn junction near the high-concentration p-type FLR region 32, the n-type FLR 31 closest to the active region 50 - It is preferable that the width is 3% or more of the width of the outermost surface of the mold drift region 2, and is also preferable that the width is 20% or less in order to suppress fluctuations in breakdown voltage due to surface charges.

[0045] The lower surface depth of the FLR 31 and the upper surface p + Mold subregions 4a and p ++ The bottom depth of the region including the mold contact region 6 is + The width of each FLR 31 narrows and the spacing between them widens from the active region 50 side toward the chip edge. For example, when up to 14 FLRs 31 (F1 to F14) are arranged as shown in FIG. 2, the width of each FLR 31, the width between each FLR 31 (W2 to W14), and the distance between the FLR 31 (F1) closest to the active region 50 and p ++ The width W1 of the mold contact region 6 is as shown in Table 1 below.

[0046]

[0047] As shown in Table 1, n of each FLR31 - The width of the outermost surface of the drift region 2 is 6.0 μm or more at the side closest to the active region 50 and 2.0 μm or less at the chip edge side. Furthermore, the width of the FLR 31 is equal to or less than the width of the FLR 31 adjacent to the active region 50 side. -The spacing at the outermost surface of the mold drift region 2 is 2.0 μm or less on the side closest to the active region 50 and 3.0 μm or less on the chip edge side. The spacing between the FLRs 31 is equal to or greater than the spacing between adjacent FLRs 31 on the active region 50 side, and it is preferable that 10 or more FLRs 31 are provided.

[0048] In the embodiment, the p ++ An inter-FLR low-concentration p-type layer (a third semiconductor region of the second conductivity type) 34 having a lower concentration than the low-concentration p-type FLR region 33 and shallower than the low-concentration p-type FLR region 33 is provided from the end of the contact region 6 to a predetermined number (e.g., the eighth) of FLRs 31 from the active region 50 side. The inter-FLR low-concentration p-type layer 34 is provided in a region deeper than the first main surface of the silicon carbide substrate, and for example, the front surface (n + The surface opposite to the silicon carbide substrate 1) is located closer to the first main surface of the silicon carbide substrate than the lower surfaces of the high-concentration p-type FLR regions 32. + The surface facing the silicon carbide substrate 1 is located between the lower surface of the high-concentration p-type FLR region 32 and the lower surface of the low-concentration p-type FLR region 33 .

[0049] Further, between the first main surface of the semiconductor substrate and the front surface of the inter-FLR low-concentration p-type layer 34, - Mold region 35 (n - The n-type drift region 2 and the n-type fourth semiconductor region are provided. - The thickness of the p-type region 35 is preferably equal to or less than the distance between the bottom surface of the inter-FLR low concentration p-type layer 34 and the bottom surface of the FLR 31. - From the viewpoint of suppressing the electric field strength at the pn junction with the p-type drift layer 2 , it is preferable that the thickness be smaller than the thickness of the high-concentration p-type FLR region 32 .

[0050] As shown in FIG. 2, the end of the inter-FLR low-concentration p-type layer 34 on the active region 50 side is + Mold part region 4a or p ++It is preferable that the end of the inter-FLR low-concentration p-type layer 34 on the chip end side is connected to the end of the contact region 6, and that the end of the inter-FLR low-concentration p-type layer 34 on the chip end side is located closer to the chip end side than the portion from the active region 50 side where the spacing between the FLRs 31 becomes 1.5 μm or more or the width of the FLRs 31 becomes 3.0 μm or less.

[0051] Here, the lower p + In the edge termination structure 60 using the FLR 31 shallower than the type portion region 4b, the electric field is dispersed to the maximum extent in the FLR region 30, and then the lower p + However, if positive charges are accumulated on the surface of the edge termination structure 60, the upper p + The electric field at the end of the mold portion region 4a and the FLR 31 becomes large, and dielectric breakdown occurs at a lower voltage. + The electric field can be alleviated by narrowing the distance between the ends of the mold portion region 4a and the FLRs 31. However, even if the distance is narrowed to the extent possible in the process, there is a problem that the required breakdown voltage cannot be ensured when the spread due to process variations is taken into consideration.

[0052] In the embodiment, when a low-concentration, shallow inter-FLR low-concentration p-type layer 34 is provided between the FLRs 31, the inter-FLR low-concentration p-type layer 34 becomes depleted during device operation, connecting the side surfaces of the FLRs 31 through the depleted p-type region. This reduces the pn junction area of ​​the high-concentration p-type region where the electric field tends to concentrate, and the electric field is more likely to be dispersed to the FLRs 31 closer to the chip edge, even when the spacing increases due to process variations. Therefore, by providing the inter-FLR low-concentration p-type layer 34 in a manner that connects the FLRs 31, sufficient surface charge resistance can be ensured and edge breakdown voltage can be stabilized even if the dimensions of each FLR 31 in the FLR structure 30 vary. Furthermore, a stable breakdown voltage can be ensured without performing SiC etching or high-acceleration ion implantation in the edge termination region 60. By avoiding the use of SiC etching or high-acceleration ion implantation, manufacturing costs can be reduced.

[0053] 3 is a graph showing the concentration distribution in the depth direction of the p-type layer of the silicon carbide semiconductor device according to the embodiment. In FIG. 3, the vertical axis shows the concentration of impurities, here aluminum (Al), in each p-type layer, and the unit is cm -3 The horizontal axis is n - The unit of the distance is μm. - The impurity concentration of the type drift region 2 is, for example, 1×10 16 cm -3 is illustrated.

[0054] In FIG. 3, the region in the center of each FLR 31 is a region where the high concentration p-type FLR region 32 and the low concentration p-type FLR region 33 are combined, and the upper p + Mold subregions 4a and p ++ The impurity concentration of the region including the contact region 6 is indicated by a thin line. - In the region from the surface of the mold drift region 2 to a depth of 0.5 μm, 19 cm -3 2x10 or more 20 cm -3 In addition, in the region of depth 0.5 μm or more to 1.0 μm, the maximum value is 5×10 17 cm -3 2x10 or more 18 cm -3 In these regions, the impurity concentration monotonically decreases in the region of depth 1.0 μm or more, and decreases to n - The impurity concentration of the high-concentration p-type FLR region 32 is the same as that of the high-concentration p-type drift region 2. The impurity concentration of the high-concentration p-type FLR region 32 is, for example, 5×10 19 cm -3 2x10 or more 20 cm -3 The low concentration p-type FLR region 33 is n - The impurity concentration of the type drift region 2 is higher than that of the type drift region 2, and is 5×10 19 cm -3 The following is fine.

[0055] As shown in FIG. 3, the impurity concentration of the inter-FLR low-concentration p-type layer 34 (thick line in FIG. 3) is n -The maximum value is reached only in a region from the surface of the p-type drift region 2 to a depth of 1.0 μm, and in a region deeper than the depth at which the impurity concentration of the high-concentration p-type FLR region 32 is at its maximum. - The impurity concentration of the type drift region 2 is higher than that of the type drift region 2 and is 2×10 17 cm -3 The impurity concentration of the inter-FLR low-concentration p-type layer 34 is lower than the impurity concentration of the FLR 31 in a region deeper than the position where the FLR 31 has the maximum impurity concentration at a depth of 0.5 μm or more and 1.0 μm or less.

[0056] Also, as shown in FIG. + The impurity concentration of the mold portion region 4b (dotted line in FIG. 3) reaches a maximum value in a region having a depth of 1.0 μm or more. + The maximum value of the impurity concentration of the type partial region 4b is higher than the maximum value of the impurity concentration of the FLR 31 at a depth of 0.5 μm or more and 1.0 μm or less. - The FLR 31 in the region at a depth of 0.5 μm from the surface of the mold drift region 2 has the maximum impurity concentration. + In the region up to the position where the impurity concentration of the mold portion region 4b is maximum, the upper p + Mold subregions 4a and p ++ The contact region 6 and the lower p + The impurity concentration of the n-type partial region 4b is always - The impurity concentration is higher than that of the type drift region 2.

[0057] Fig. 4 is a graph showing variations in FLR dimensions of a conventional silicon carbide semiconductor device and changes in edge breakdown voltage due to edge surface charges. Fig. 5 is a graph showing variations in FLR dimensions of a silicon carbide semiconductor device according to an embodiment and changes in edge breakdown voltage due to edge surface charges. In Figs. 4 and 5, the vertical axis represents breakdown voltage in V. The horizontal axis represents n - indicates the charge density on the surface of the drift region 2, and is expressed in cm -2 is.

[0058] Figures 4 and 5 show the simulation results for the solid line ● where the FLR width and FLR spacing are formed according to the dimensions in Table 1, the dotted line ◇ where the FLR width is 0.3 μm wider and the FLR spacing is 0.3 μm narrower, and the dashed line □ where the FLR width is 0.3 μm narrower and the FLR spacing is 0.3 μm wider.

[0059] In the case of the conventional FLR structure 30 alone, the FLR width is narrowed by 0.3 μm and the FLR interval is widened by 0.3 μm due to process variations, and the edge surface is -2 On the other hand, in the embodiment in which the inter-FLR low-concentration p-type layer 34 is provided, the breakdown voltage remains almost unchanged even when both the process variation and the magnitude of the edge surface charge reach their maximums.

[0060] In a conventional silicon carbide semiconductor device, when the FLR width is narrowed by 0.3 μm and the FLR spacing is widened by 0.3 μm as shown by the dashed square in FIG. 4, the electric field distribution and the location of breakdown are as follows: FIG. 6 is a cross-sectional view showing the electric field distribution of a conventional silicon carbide semiconductor device; FIG. 7 is a graph showing the electric field distribution of a conventional silicon carbide semiconductor device; FIG. 8 is a cross-sectional view showing the location of breakdown in a conventional silicon carbide semiconductor device; FIG. 7 shows the electric field distribution at the bottom of the FLR (dotted line T in FIG. 6). The vertical axis shows the electric field strength in MV / cm; the horizontal axis shows the electric field strength at the bottom p + A1 indicates the distance from the mold part region 104b, and the unit is μm. + B1 is the electric field strength at the edge of the mold portion region 104a, and B2 is the electric field strength at the bottom of the FLR 131 closest to the active region.

[0061] Furthermore, in the silicon carbide semiconductor device according to the embodiment, when the FLR width is narrower by 0.3 μm and the FLR spacing is wider by 0.3 μm as shown by the dashed line square in FIG. 5 , the electric field distribution and the location of breakdown are as follows: FIG. 9 is a cross-sectional view showing the electric field distribution of the silicon carbide semiconductor device according to the embodiment; FIG. 10 is a graph showing the electric field distribution of the silicon carbide semiconductor device according to the embodiment; FIG. 11 is a cross-sectional view showing the location of breakdown of the silicon carbide semiconductor device according to the embodiment; FIG. 10 shows the electric field distribution at the bottom of the FLR (dotted line T in FIG. 9 ). The vertical axis indicates the electric field strength in MV / cm; the horizontal axis indicates the lower p + A1 indicates the distance from the mold part region 4b, and the unit is μm. + B1 is the electric field strength at the bottom of the FLR 31 closest to the active region 50;

[0062] 12 is a graph showing electric field distributions in the conventional silicon carbide semiconductor device and the silicon carbide semiconductor device according to the embodiment. Fig. 12 is a combination of Fig. 7 and Fig. 10. In Fig. 12, A1 denotes the upper p + 12, the embodiment using the low concentration p-type layer 34 between FLRs can disperse the electric field outward more than the conventional embodiment, and therefore the upper p-type layer 34 of the active region 50 can be dispersed more outward than the conventional embodiment. + Therefore, the electric field concentration at the end of the molded portion region 4a and the corner of the FLR 31 is reduced. Therefore, the location where the dielectric breakdown occurs is the p-type portion of the active region as shown in FIG. ++ In the embodiment, the lower p of the active region 50 is formed as shown in FIG. + This forms the end S1 of the mold portion region 4b. As a result, the silicon carbide semiconductor device according to the embodiment can prevent a decrease in breakdown voltage even under the most severe conditions of dimensional variations and surface charges.

[0063] In addition, in the method for manufacturing a semiconductor device according to the embodiment, for example, -The source electrode 16 of the active region 50 and the p-type region (lower p + p-type region (upper p + By implanting ions under the same conditions as those for forming the n-type partial region 4a), the FLR structure 30 can be formed in the edge termination region 60. - It can be formed by ion implantation into the inside of the type drift region 2. Other structures can be fabricated in the same manner as in fabricating a MOSFET with a breakdown voltage of, for example, 1200V.

[0064] As described above, according to the embodiment, by providing an inter-FLR low-concentration p-type layer in a form that connects the FLRs, sufficient surface charge resistance can be ensured even if the dimensions of each FLR in the FLR structure vary, and edge breakdown voltage can be stabilized. Furthermore, a stable breakdown voltage can be ensured without performing SiC etching or high-acceleration ion implantation in the edge termination region, and by not using SiC etching or high-acceleration ion implantation, manufacturing costs can be reduced.

[0065] The present disclosure can be modified in various ways without departing from the spirit and scope of the present disclosure. In each of the above-described embodiments, for example, the dimensions of each component and the impurity concentration are set in various ways according to the required specifications. Furthermore, while each of the above-described embodiments has been described using silicon carbide as the wide bandgap semiconductor, the present disclosure can also be applied to wide bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). Furthermore, while each of the embodiments describes the first conductivity type as n-type and the second conductivity type as p-type, the present disclosure is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type.

[0066] As described above, the semiconductor device according to the present disclosure is useful as a power semiconductor device used in power conversion devices such as inverters, power supply devices for various industrial machines, and igniters for automobiles.

[0067] 1n + Silicon carbide substrate 2n - Type drift region 4p +Mold partial area 4a, 104a upper part p + Mold partial area 4b, 104b lower part p + Type partial region 5 P type base region 6, 106 p ++ Type contact region 7 n ++ 8 n-type source region 11 gate insulating film 13 gate electrode 14 interlayer insulating film 15 barrier metal 16 source electrode 17 drain electrode 25 trench 26 p + Type region 30 FLR structure 31, 131 FLR 32 High concentration p-type FLR region 33 Low concentration p-type FLR region 34 Low concentration p-type layer between FLRs 35 n - Mold region 50 Active region 60 Edge termination region 70 Silicon carbide semiconductor device

Claims

1. A semiconductor device comprising an active region through which a main current flows and a termination region surrounding the periphery of the active region on a semiconductor substrate of a first conductivity type. The active region has a first semiconductor layer of the first conductivity type provided on the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate, and a first semiconductor region of a second conductivity type provided on a surface side opposite to the semiconductor substrate side of the first semiconductor layer. The termination region has the first semiconductor layer, and a second semiconductor region of the second conductivity type including a plurality of first small regions of the second conductivity type provided separately on the surface of the first semiconductor layer. In the first semiconductor layer, a third semiconductor region of the second conductivity type having a lower concentration than the first small regions is provided between each of a predetermined number of the first small regions from an end of the first semiconductor region, and a surface on the semiconductor substrate side is provided on the surface side of the first semiconductor layer with respect to the surface on the semiconductor substrate side of the first small regions. In the first semiconductor layer, a fourth semiconductor region of the first conductivity type is provided between the surface of the first semiconductor layer and the third semiconductor region. Each interval is connected by the third semiconductor region and the fourth semiconductor region.

2. The first small region has a central region having a second small region with a high impurity concentration on the surface side of the first semiconductor layer and a third small region with a low impurity concentration on the semiconductor substrate side of the second small region, an inner region provided closer to the active region than the central region, and an outer region provided at a position facing the inner region with the central region interposed therebetween. The inner region and the outer region have an impurity concentration lower than that of the second small region. The semiconductor device according to claim 1.

3. The fourth semiconductor region is provided from the surface of the first semiconductor layer to a surface on the surface side of the first semiconductor layer of the third semiconductor region. The thickness of the fourth semiconductor region is equal to or smaller than the distance from the surface on the semiconductor substrate side of the third semiconductor region to the surface on the semiconductor substrate side of the first small region. The semiconductor device according to claim 1 or 2.

4. The fourth semiconductor region is provided from the surface of the first semiconductor layer to a surface on the surface side of the first semiconductor layer of the third semiconductor region. The thickness of the fourth semiconductor region is smaller than the thickness of the second small region of the first small region. The semiconductor device according to claim 2.

5. The first small region has an impurity concentration of 5×10 19 cm -3 or more and 2×10 20 cm -3 or less in the second small region. In the third small region of the central region, the impurity concentration is 1×10 16 cm -3 or more and 5×10 19 cm -3 or less. In the inner region and the outer region, the impurity concentration is 1×10 16 cm -3 or more and 5×10 19 cm -3 or less. The semiconductor device according to claim 2, characterized in that.

6. The semiconductor device according to claim 2, wherein in a direction parallel to the surface of the first semiconductor layer, the width of the central region is wider than the width of the inner region or the outer region in the first small region.

7. The semiconductor device according to claim 2, wherein the width of the inner region and the width of the outer region of the first small region are 3% or more and 20% or less of the width of the first small region provided closest to the active region side.

8. The semiconductor device according to claim 1, wherein the surface of the first semiconductor region and the surface of the second semiconductor region are the same as the surface of the first semiconductor layer.

9. The plurality of first small regions have a width that narrows from the active region side toward the chip end, and the interval between the first small regions widens. The width of the first small region on the surface of the first semiconductor layer is 6.0 μm or more on the active region side and 2.0 μm or less on the chip end side. The width of the first small region is equal to or less than the width of the first small region adjacent to the active region side. The interval of the first small region on the surface of the first semiconductor layer is 2.0 μm or less on the active region side and 3.0 μm or more on the chip end side. The interval between the first small regions is equal to or more than the interval between the first small regions adjacent to the active region side. The semiconductor device according to claim 1, wherein 10 or more first small regions are provided.

10. The impurity concentration of the third semiconductor region takes a maximum value on the semiconductor substrate side from the surface side of the first semiconductor layer, the maximum value is higher than the impurity concentration of the first semiconductor layer, and is 2×10 17 cm -3 or less. The semiconductor device according to claim 1, wherein the impurity concentration of the third semiconductor region is lower than the impurity concentration of the first small region in a region deeper than the depth position where the first small region takes the maximum value of the impurity concentration.

11. The semiconductor device according to claim 1, wherein the end on the chip end side of the third semiconductor region is on the chip end side of the portion where the interval between the first small regions becomes 1.5 μm or more or the width of the first small region becomes 3.0 μm or less for the first time from the active region side.