Silicon carbide semiconductor device

Abstract

First and second p+-type regions (21, 22) for electric field relaxation, and an n-type current diffusion region (23), are each selectively provided, at positions deeper than the bottom surfaces of trenches, between a p-type base region (3) and an n–-type drift region (2). Between the second p+-type region (22) and the n–-type drift region (2) between adjacent trenches, an n––-type region (24) is selectively provided in contact with these regions. The n-type current diffusion region (23) selectively surrounds the lower surface of the second p+-type region (22) between adjacent trenches, and surrounds the periphery of the n––-type region (24) in plan view. The built-in voltage of a p-n junction immediately below a source ring surrounding the periphery of an active region is lower than the built-in voltage (Vb1) of the p-n junction between the second p+-type region (22) and the n-type current diffusion region (23), and is higher than the built-in voltage (Vb3) of a p-n junction between the second p+-type region (22) and the n––-type region. This makes it possible to improve breakage resistance.

Description

Silicon carbide semiconductor device

[0001] This disclosure relates to silicon carbide semiconductor devices.

[0002] In Patent Document 1, the following is described: + The first p-type drain region side and the second p-type drain region side are provided between the adjacent trenches, respectively, for alleviating the electric field near the bottom of the trench. + Base region, second p + A base region is provided, and the impurity concentration of the n-type current diffusion layer is set to a second p + By making only the portion directly below the base region higher than the other portions, the first p + The breakdown voltage directly below the base region is + A similar technique is described in Japanese Patent Application Laid-Open No. 2003-222299, which discloses a technique for increasing the breakdown voltage of the silicon nitride film to a value higher than that directly below the silicon nitride film.

[0003] Japanese Patent No. 6617657 Japanese Patent Application Laid-Open No. 2020-136416

[0004] When the power is turned on, part of the inrush current is concentrated in a part of the electrode of the MOSFET, and the surge current I FSM There is a risk that the breakdown resistance against the

[0005] An object of the present disclosure is to provide a silicon carbide semiconductor device that can improve breakdown resistance.

[0006] A semiconductor device according to one aspect of the present disclosure is as follows: An active region is provided in a semiconductor substrate. A first semiconductor region of a first conductivity type is provided within the semiconductor substrate. A second semiconductor region of a second conductivity type is provided in the active region between a first major surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of the first conductivity type is selectively provided between the first major surface and the second semiconductor region. A trench penetrates the third semiconductor region and the second semiconductor region in the depth direction. A gate electrode is provided within the trench via a gate insulating film.

[0007] A second conductivity type region is selectively provided between the second semiconductor region and the first semiconductor region. The second conductivity type region reaches a position deeper than the bottom surface of the trench toward the second main surface of the semiconductor substrate and contacts the first semiconductor region. A first electrode is provided on the first main surface in the active region and is electrically connected to the third semiconductor region, the second semiconductor region, and the second conductivity type region. A second electrode is provided on the second main surface. A fourth semiconductor region of the second conductivity type is provided between the first main surface and the first semiconductor region. The fourth semiconductor region surrounds the periphery of the active region.

[0008] The fourth semiconductor region reaches a position deeper than the bottom surface of the trench toward the second major surface and contacts the first semiconductor region. A first wiring layer is provided on the first major surface, surrounds the periphery of the active region, is connected to a portion of the first electrode, and faces the fourth semiconductor region in the depth direction and is electrically connected to the fourth semiconductor region. The second conductivity type region has a first second conductivity type region provided away from the trench and in contact with the second semiconductor region. The first semiconductor region selectively has a first first conductivity type region with a different impurity concentration in a portion that contacts the surface of the first second conductivity type region on the second major surface side.

[0009] The silicon carbide semiconductor device according to the present disclosure has an effect of improving breakdown resistance.

[0010] FIG. 1 is a plan view showing a layout of a silicon carbide semiconductor device according to an embodiment, as viewed from the front surface side of a semiconductor substrate. FIG. 2 is a plan view showing a layout of a cell structure of an active region of FIG. 1, as viewed from the front surface side of the semiconductor substrate. FIG. 3 is a cross-sectional view showing a cross-sectional structure taken along line A1-A1' in FIG. 2. FIG. 4 is a cross-sectional view showing a cross-sectional structure taken along line A2-A2' in FIG. 2. FIG. 5 is a cross-sectional view showing a cross-sectional structure taken along line A3-A3' in FIG. 2. FIG. 6 is a cross-sectional view showing a cross-sectional structure taken along line B-B' in FIG. 2. FIG. 7 is a cross-sectional view showing a cross-sectional structure taken along line C-C' in FIG. 1. FIG. 8 is a cross-sectional view showing a cross-sectional structure taken along line D1-D1' in FIG. 1. FIG. 9 is a cross-sectional view showing a cross-sectional structure taken along line D2-D2' in FIG. 1. FIG. 10 is a plan view showing a layout of a silicon carbide semiconductor device according to a reference example, as viewed from the front surface side of a semiconductor substrate. Fig. 11 is a plan view showing the layout of the cell structure of the active region of Fig. 10 as viewed from the front surface side of the semiconductor substrate. Fig. 12 is a cross-sectional view showing the cross-sectional structure taken along line AA-AA' in Fig. 11. Fig. 13 is a cross-sectional view showing the cross-sectional structure taken along line BB-BB' in Fig. 11. Fig. 14 is a cross-sectional view showing the cross-sectional structure taken along line CC-CC' in Fig. 10. Fig. 15 is a plan view schematically showing dielectric breakdown due to current concentration at the connection end between the source ring and the source electrode in Fig. 10.

[0011] <Outline of Embodiments of the Present Disclosure> (1) A silicon carbide semiconductor device according to one aspect of the present disclosure is as follows: An active region is provided in a semiconductor substrate. A first semiconductor region of a first conductivity type is provided within the semiconductor substrate. A second semiconductor region of a second conductivity type is provided in the active region between a first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of the first conductivity type is selectively provided between the first main surface and the second semiconductor region. A trench penetrates the third semiconductor region and the second semiconductor region in a depth direction. A gate electrode is provided within the trench via a gate insulating film.

[0012] A second conductivity type region is selectively provided between the second semiconductor region and the first semiconductor region. The second conductivity type region reaches a position deeper than the bottom surface of the trench toward the second main surface of the semiconductor substrate and contacts the first semiconductor region. A first electrode is provided on the first main surface in the active region and is electrically connected to the third semiconductor region, the second semiconductor region, and the second conductivity type region. A second electrode is provided on the second main surface. A fourth semiconductor region of the second conductivity type is provided between the first main surface and the first semiconductor region. The fourth semiconductor region surrounds the periphery of the active region.

[0013] The fourth semiconductor region reaches a position deeper than the bottom surface of the trench toward the second major surface and contacts the first semiconductor region. A first wiring layer is provided on the first major surface, surrounds the periphery of the active region, is connected to a portion of the first electrode, and faces the fourth semiconductor region in the depth direction and is electrically connected to the fourth semiconductor region. The second conductivity type region has a first second conductivity type region provided away from the trench and in contact with the second semiconductor region. The first semiconductor region selectively has a first first conductivity type region with a different impurity concentration in a portion that contacts the surface of the first second conductivity type region on the second major surface side.

[0014] According to the above disclosure, the built-in voltage of the pn junction (main junction of the MOSFET) between the second conductivity type region of the active region and the first semiconductor region can be partially set equal to or lower than the built-in voltage of the pn junction between the fourth semiconductor region directly below the first wiring layer and the first semiconductor region. As a result, when an inrush current flows through the MOSFET, a forward current flows preferentially through a portion of the body diode in the active region, or a forward current flows simultaneously through the body diode directly below the source ring (first wiring layer) and a portion of the body diode in the active region, thereby reducing the carrier density in the first semiconductor region directly below the source ring. This makes it possible to suppress current concentration in the source ring when an inrush current flows through the MOSFET, improving the surge current resistance and thereby improving the breakdown resistance of the MOSFET.

[0015] (2) Furthermore, in the silicon carbide semiconductor device according to the present disclosure, in the above-mentioned (1), the impurity concentration of the first first conductivity type region may be higher than the impurity concentration of a second first conductivity type region of the first semiconductor region excluding the first first conductivity type region.

[0016] According to the above disclosure, it is possible to make the avalanche breakdown more likely to occur in the active region, and to improve the avalanche resistance.

[0017] (3) Furthermore, in the silicon carbide semiconductor device according to this disclosure, in the above-described (2), the first first-conductivity type region may be provided between the second semiconductor region and the second first-conductivity type region, reach a position deeper toward the second main surface than the first second-conductivity type region, and selectively surround a surface of the first second-conductivity type region toward the second main surface.

[0018] According to the above disclosure, it is possible to make the active region more susceptible to avalanche breakdown, thereby improving the avalanche resistance.

[0019] (4) Furthermore, in the silicon carbide semiconductor device according to this disclosure, in the above-mentioned (2), the first semiconductor region may selectively have a third first conductivity type region adjacent to the first first conductivity type region and having a lower impurity concentration than the second first conductivity type region, between the first second conductivity type region and the second first conductivity type region.

[0020] According to the above disclosure, when an inrush current flows in the MOSFET, the forward current of the body diode flows preferentially through the third first-conductivity-type region to the active region, thereby further reducing the carrier density in the first semiconductor region directly below the source ring.

[0021] (5) Furthermore, in the silicon carbide semiconductor device according to the present disclosure, in the above-mentioned (1), the impurity concentration of the first first conductivity type region may be lower than the impurity concentration of a second first conductivity type region of the first semiconductor region excluding the first first conductivity type region.

[0022] According to the above disclosure, when an inrush current flows in the MOSFET, the forward current of the body diode flows preferentially through the first first-conductivity-type region to the active region, thereby further reducing the carrier density in the first semiconductor region immediately below the source ring.

[0023] (6) Furthermore, in the silicon carbide semiconductor device according to this disclosure, in the above-mentioned (5), the first first conductivity type region may be provided between the first second conductivity type region and the second first conductivity type region.

[0024] According to the above disclosure, when an inrush current flows in the MOSFET, the forward current of the body diode flows preferentially through the first first-conductivity-type region to the active region, thereby further reducing the carrier density in the first semiconductor region immediately below the source ring.

[0025] (7) Furthermore, in the silicon carbide semiconductor device according to this disclosure, in the above-described (2), the trenches may extend linearly in a first direction parallel to the front surface of the semiconductor substrate. The first second conductivity type regions may be scattered at predetermined intervals in the first direction. The first first conductivity type region may surround the periphery of the first second conductivity type region and extend to a position deeper toward the second main surface than the first second conductivity type region, selectively surrounding a surface of the first second conductivity type region facing the second main surface.

[0026] According to the above disclosure, it is possible to effectively separate a portion through which an avalanche current flows when an avalanche breakdown occurs from a portion through which a surge current flows when an inrush current flows in a MOSFET.

[0027] (8) In the silicon carbide semiconductor device according to the present disclosure, in the above-described (5), the trenches may extend linearly in a first direction parallel to the front surface of the semiconductor substrate, the first second conductivity type regions may be scattered at predetermined intervals in the first direction, and the first first conductivity type regions may be arranged in an island shape adjacent to different first second conductivity type regions in a depth direction.

[0028] According to the above disclosure, it is possible to effectively separate a portion through which an avalanche current flows when an avalanche breakdown occurs from a portion through which a surge current flows when an inrush current flows in a MOSFET.

[0029] (9) In the silicon carbide semiconductor device according to the present disclosure, in the above-described (7) or (8), the second conductivity type region may include a second second conductivity type region facing a bottom surface of the trench, and the second second conductivity type region may extend linearly in the first direction.

[0030] According to the above disclosure, even if the first second conductivity type regions are arranged in a scattered manner, the electric field applied near the bottom surface of the trench can be alleviated.

[0031] <Findings underlying the present disclosure> First, the structure of a silicon carbide semiconductor device of a reference example will be described. Fig. 10 is a plan view showing the layout of a silicon carbide semiconductor device of a reference example as viewed from the front surface side of a semiconductor substrate. Fig. 11 is a plan view showing the layout of the cell structure of the active region of Fig. 10 as viewed from the front surface side of the semiconductor substrate. Figs. 12 and 13 are cross-sectional views showing cross-sectional structures taken along line AA-AA' and line BB-BB' in Fig. 11, respectively. Fig. 14 is a cross-sectional view showing the cross-sectional structure taken along line CC-CC' in Fig. 10. Fig. 15 is a plan view schematically showing dielectric breakdown (burn marks on the insulating layer) due to current concentration at the connection end between the source ring and the source electrode in Fig. 10.

[0032] The silicon carbide semiconductor device 110 of the reference example shown in FIGS. 10 to 14 is a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor having an insulated gate consisting of a three-layer structure of metal-oxide film-semiconductor) having a trench gate structure, which is provided with a gate runner 114 and a source ring 115 surrounding the periphery of an active region 131 in a boundary region 132 between an active region 131 and an edge termination region 133 of a semiconductor substrate (semiconductor chip) 140 using silicon carbide (SiC) as a semiconductor material.

[0033] As shown in FIG. 10 , the active region 131 has a substantially rectangular planar shape and is located approximately in the center (chip center) of the semiconductor substrate 140. MOSFET cells (functional units of an element) are arranged in an effective region (hereinafter referred to as the active effective region) 131a of the active region 131. No MOSFET cells are arranged in an inactive ineffective region 131b of the active region 131 excluding the active effective region 131a. The boundary region 132 is adjacent to the outside (chip edge side) of the active region 131 and surrounds the periphery of the active region 131. The edge termination region 133 is a region between the boundary region 132 and the edge (chip edge) of the semiconductor substrate 140.

[0034] A source pad 111a (source electrode 111), a gate pad 112, a measurement pad 113, a gate runner 114, and a source ring 115 are arranged on the front surface of the semiconductor substrate 140. The source electrode 111 is provided in the active effective region 131a and covers substantially the entire active effective region 131a. The portion of the source electrode 111 exposed in the opening 120a of the passivation film 120 functions as the source pad 111a (hatched portion). The gate pad 112, the measurement pad 113, and a gate resistor (not shown) are arranged in the active inactive region 131b. The measurement pad 113 is an electrode pad for measuring gate resistance.

[0035] The gate runner 114 is arranged in the active inactive region 131b and the boundary region 132. The gate runner 114 and the source ring 115 are arranged apart from each other in the boundary region 132 and have a ring-like planar shape that concentrically surrounds the periphery of the active region 131. The gate runner 114 surrounds the periphery of the active region 131 in a substantially rectangular shape with a partial opening in the boundary region 132. The gate runner 114 is electrically connected to the gate pad 112 via a gate resistor. The gate electrodes 108 (see FIG. 12) of all cells of the MOSFET are electrically connected to the gate runner 114.

[0036] The source ring 115 is disposed outside the gate runner 114 in the boundary region 132, and surrounds the periphery of the active region 131 in a substantially rectangular shape. The source ring 115 is connected to a p-type peripheral region 150, which will be described later, and is connected to the source electrode 111 at a partially opened portion 114a of the gate runner 114, and is fixed to the potential of the source electrode 111. The source ring 115 is connected to the n-type peripheral region 150 outside the active region 131 when the MOSFET is off. - When holes in the type drift region 102 are drawn to the source electrode 111, the gate runner 114 has a function of suppressing the concentration of hole current in the insulating layer directly below the gate runner 114 (on the semiconductor substrate 140 side).

[0037] As shown in FIGS. 11 to 13, the semiconductor substrate 140 is an n-type semiconductor substrate using SiC as a semiconductor material. + On the front surface of the starting mold substrate 141, - The semiconductor substrate 140 is formed by laminating epitaxial layers 142 to 144 in this order, which will become the n-type drift region 102, the n-type current diffusion region 123, and the p-type base region 103. The semiconductor substrate 140 has a main surface on the side of the p-type epitaxial layer 144 as the front surface, and an n-type epitaxial layer 144 as the rear surface. + The main surface on the mold starting substrate 141 side is referred to as the back surface. + The starting substrate 141 is n + The active effective region 131a is a n-type drain region 101. - Between the silicon nitride layer 102 and the silicon nitride layer 104, a trench gate structure of the MOSFET is provided.

[0038] The trench gate structure includes a p-type base region 103, an n + type source region 104, p ++ The p-type base region 103 is formed by the n-type contact region 105, the trench 106, the gate insulating film 107, and the gate electrode 108. The p-type base region 103 is connected to the front surface of the semiconductor substrate 140 over the entire area of ​​the active region 131 and the boundary region 132. - The n-type drift region 102 is provided between the n-type drift region 102 and the n-type drift region 102. + type source region 104 and p ++ The contact regions 105 are selectively provided between the front surface of the semiconductor substrate 140 and the p-type base region 103 in contact with the p-type base region 103 .

[0039] p-type base region 103 and n + The source region 104 extends linearly between adjacent trenches 106 in the longitudinal direction of the trenches 106 (first direction X). ++ The mold contact regions 105 are disposed between adjacent trenches 106 at a distance from the trenches 106 and are scattered in the longitudinal direction of the trenches 106. The trenches 106 extend linearly in a first direction X parallel to the front surface of the semiconductor substrate 140, and a plurality of the trenches 106 are disposed adjacent to each other in a second direction Y parallel to the front surface of the semiconductor substrate 140 and perpendicular to the first direction X, forming a stripe shape when viewed from the front surface side of the semiconductor substrate 140 (in a plan view) (see FIG. 11 ).

[0040] The trench 106 has a depth of n in the Z direction. + The n-type current diffusion region 123 is formed by passing through the p-type source region 104 and the p-type base region 103. - Between the n-type drift region 102 and the bottom surface of the trench 106, + A first p-type impurity ion (P-type impurity ion) for electric field relaxation is formed at a deep position on the side of the drain region 101. + Mold region 121, second p + A first p-type region 122 and an n-type current diffusion region 123 are selectively provided. + Mold region 121, second p + In the active region 131a, the p-type region 122 extends linearly in the longitudinal direction of the trench 106 with substantially the same length as the longitudinal direction of the trench 106 and contacts a p-type peripheral region 150 described later.

[0041] 1st p. + The second p-type region 121 is provided apart from the p-type base region 103 and faces the bottom surface of the trench 106 in the depth direction Z. + The first p-type region 122 is formed between the adjacent trenches 106. + The second p is provided apart from the mold region 121 and the trench 106. + The mold region 122 has an upper surface (n + The second p-type source region 104 faces the p-type base region 103. +The p-type region 122 is connected to the p-type base region 103 in the depth direction Z. ++ The second p + The mold region 122 has a first p + It is partially connected to the mold area 121 .

[0042] The n-type current diffusion region 123 is a first p + Mold region 121, second p + adjacent to the mold region 122, + Mold region 121, second p + n than the mold region 122 + The n-type drain region 101 is - The n-type current diffusion region 123 is in contact with the first p-type drift region 102. + Mold region 121, second p + The lower surface of the mold region 122 (n + The n-type current diffusion region 123 surrounds the entire surface of the active region 131 (the surface facing the n-type drain region 101). The n-type current diffusion region 123 is provided over the entire active region 131 and extends into the boundary region 132. The n-type current diffusion region 123 faces the entire surfaces of the source electrode 111, the gate pad 112, the measurement pad 113, the gate runner 114, and the gate resistor (not shown) in the depth direction Z.

[0043] The gate electrode 108 is provided inside the trench 106 via a gate insulating film 107. The interlayer insulating film 109 is provided on the entire front surface of the semiconductor substrate 140 and covers the gate electrode 108. The source electrode 111 is formed in contact holes 109a and 109b of the interlayer insulating film 109. + type source region 104 and p ++ ohmic contact with the p-type contact region 105, + type source region 104 and p ++ The back surface (n + A drain electrode 116 is provided on the entire surface of the starting substrate 141 (the rear surface of the starting substrate 141).

[0044] As shown in FIG. 14, the front surface of the semiconductor substrate 140 and the n-type semiconductor substrate 140 are in contact with each other over substantially the entire boundary region 132. -A p-type peripheral region 150 (151 to 153) is provided between the active region 131 and the source ring 115. The p-type peripheral region 150 is connected to the source electrode 111 and the source ring 115 and is fixed to the potential of the source electrode 111. The p-type peripheral region 150 surrounds the periphery of the active region 131 in the boundary region 132 and extends over the entire area of ​​the inactive ineffective region 131b. The p-type peripheral region 150 faces the entire surfaces of the gate pad 112, the measurement pad 113, the gate runner 114, the gate resistor, and the source ring 115 in the depth direction Z.

[0045] Directly below the gate runner 114 (n + p-type peripheral region 150 and n-type drain region 101 - An n-type current diffusion region 123 extends from the active region 131 to the entire area between the active region 131 and the p-type drift region 102. The n-type current diffusion region 123 terminates inside the source ring 115 (towards the chip center) in the boundary region 132 and does not face the source ring 115 in the depth direction Z. That is, the bottom surface of the p-type peripheral region 150 in the boundary region 132 contacts the n-type current diffusion region 123 only directly below the gate runner 114, and does not face the n-type current diffusion region 123 in the portion outside the gate runner 114 (including directly below the source ring 115). - It contacts the mold drift region 102 .

[0046] The front surface of the semiconductor body 140 in the edge termination region 133 has an n - type epitaxial layer 142 (n - The edge termination region 133 is formed by a front surface of the semiconductor body 140 and an n-type drift region 102. - A predetermined breakdown voltage structure is provided between the active ineffective region 131b and the p-type drift region 102. The entire front surface of the semiconductor substrate 140 in the active ineffective region 131b, boundary region 132, and edge termination region 133 is covered with an insulating layer made of a field oxide film and interlayer insulating film 109. The p-type peripheral region 150 in the active ineffective region 131b and boundary region 132, and the breakdown voltage structure in the edge termination region 133 are covered with this insulating layer.

[0047] The gate runner 114 is provided on the field oxide film between the source electrode 111 and the source ring 115. The source electrode 111 and the source ring 115 are respectively connected to the p-type semiconductor layer 109 via contact holes 109b and 109d in the insulating layer (field oxide film and interlayer insulating film 109). ++ The source electrode 111 is in ohmic contact with the p-type peripheral contact region 153 and is electrically connected to the p-type peripheral region 150 (151 to 153). A portion 111b of the source electrode 111 (hereinafter referred to as the convex portion) extends outward in a convex shape on the interlayer insulating film 109 at a partially opened portion 114a of the gate runner 114 and is connected to the source ring 115 (FIGS. 10 and 14).

[0048] In the silicon carbide semiconductor device 110 (MOSFET) of the reference example described above, when an inrush current flows in the MOSFET (when an inrush current flows when the power is turned on), a surge current I FSM When this occurs, a surge current I flows through the insulating layer directly below the gate runner 114. FSM is concentrated, and a leakage current I GSS Therefore, the source ring 115 is arranged outside the gate runner 114 to prevent the surge current I FSM By passing the current, dielectric breakdown directly below the gate runner 114 is suppressed.

[0049] However, the connection point between the source electrode 111 and the source ring 115 has a planar shape in which an end 181 (the portion surrounded by a circular frame 180 in FIGS. 10 and 15, hereinafter referred to as the connection end) of the elongated metal layer (source ring 115) is connected to the side surface of the metal layer (the convex portion 111b of the source electrode 111 and the source ring 115) which is approximately rectangular in plan view. In FIG. 15, the outline of the source electrode 111 and the outline of the source ring 115 are respectively indicated by dashed lines. For this reason, the surge current I that flows into the source ring 115 FSM flows through the source ring 115 toward the source electrode 111 and concentrates at the connection end 181 between the source electrode 111 and the source ring 115 .

[0050] A surge current I flows through the connection end 181 between the source electrode 111 and the source ring 115. FSM The reason why the surge current I generated when an inrush current flows through the MOSFET is concentrated is that the n-type current diffusion region 123 is provided in the active region 131. FSM It is presumed that this is because the current flows more easily directly below the source ring 115 than in the active region 131. The built-in voltage (contact potential difference generated at the pn junction surface) V b2 is the built-in voltage V of the first body diode 171 formed in the active region 131. b1 Since the surge current I FSM is playing.

[0051] The first body diode 171 is p ++ the p-type contact region 105, the p-type base region 103, and the first p + Mold region 121, second p + n-type region 122, n-type current diffusion region 123 and n - The second body diode 172 is formed by a pn junction between the p-type peripheral region 150 and the n-type drift region 102. - The pn junction is formed with the type drift region 102. As shown in the following formula (1), the built-in voltage V bi is the acceptor density N A and donor density N d The higher the value, the higher the value. B is the Boltzmann constant. When the temperature T is room temperature (300 K), k B T is 25.9 meV. q is the charge of the electron. n i is the intrinsic carrier density.

[0052]

[0053] The built-in voltage V of the first body diode 171 b1 is the first page + Mold region 121, second p +The built-in voltage V of the second body diode 172 is determined by the impurity concentration of the n-type region 122 and the impurity concentration of the n-type current diffusion region 123. b2 is p + The impurity concentration and n - It is determined by the impurity concentration of the type drift region 102. + The mold outer peripheral region 151 is the first p + Mold region 121, second p + The first p + Mold region 121, second p + The first body diode 171 and the second body diode 172 have the same impurity concentration as the first body diode 171. Therefore, both the first body diode 171 and the second body diode 172 have a built-in voltage V b1 , V b2 The acceptor density N that determines A is the same.

[0054] The built-in voltage V of the second body diode 172 b2 Determine the donor density N d The n-type current diffusion region 123 is provided in the active region 131, so that the built-in voltage V b1 Determine the donor density N d Therefore, the built-in voltage V of the second body diode 172 b2 is the built-in voltage V of the first body diode 171 b1 When the body diode of the MOSFET is conducting, the second body diode 172 conducts in the forward direction before the first body diode 171 conducts in the forward direction, and the second body diode 172 has priority in passing the forward current I F begins to flow.

[0055] When the body diode of the MOSFET is conducting, the forward current I F flows, and n of the active region 131 - The n of the boundary region 132 is larger than that of the drift region 102. - Carriers (holes and electrons) tend to accumulate in the type drift region 102. Therefore, when the body diode of the MOSFET is energized, a surge current I FSM occurs, n in the boundary region 132- The carrier density in the n-type drift region 102 further increases. When the MOSFET transitions from this state to the off state, the n-type drift region 132 - The amount of hole current flowing from the type drift region 102 to the source ring 115 increases.

[0056] The hole current that has flowed into the source ring 115 flows through the source ring 115 toward the source electrode 111 and is concentrated at the connection end 181 between the source electrode 111 and the source ring 115. - This phenomenon becomes more pronounced as the impurity concentration in the type drift region 102 becomes lower (i.e., as the silicon carbide semiconductor device 110 has a higher breakdown voltage, for example, 3.3 kV or higher). As a result, as shown in FIG. 15 , a surge current I FSM The resistance to the surge current I FSM The heat is concentrated and the insulating layer is burned.

[0057] The problem to be improved in this embodiment is the breakdown resistance of a MOSFET (silicon carbide semiconductor device), in particular, the surge current I that flows between the source and drain when an inrush current flows in the MOSFET. FSM The purpose of this invention is to improve the tolerance to

[0058] Preferred embodiments of a silicon carbide semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols appended to n or p indicate higher and lower impurity concentrations than layers and regions not prefixed with these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0059] (Details of the embodiment) Silicon carbide semiconductor devices according to embodiments that solve the above-mentioned problems will be described below. FIG. 1 is a plan view showing a layout of a silicon carbide semiconductor device according to an embodiment, as viewed from the front surface side of a semiconductor substrate. FIG. 2 is a plan view showing a layout of a cell structure of the active region of FIG. 1, as viewed from the front surface side of the semiconductor substrate. FIGS. 3 to 6 are cross-sectional views showing cross-sectional structures taken along cut lines A1-A1', A2-A2', A3-A3', and B-B' in FIG. 2, respectively. FIGS. 7 to 9 are cross-sectional views showing cross-sectional structures taken along cut lines C-C', D1-D1', and D2-D2' in FIG. 1, respectively.

[0060] 1 to 9 is a vertical MOSFET with a trench gate structure (insulated gate structure: element structure consisting of a three-layer structure of metal-oxide film-semiconductor) that includes a gate runner 14 and a source ring 15 surrounding an active region 31 in a boundary region 32 between an active region 31 and an edge termination region 33 of a semiconductor substrate (semiconductor chip) 40 that uses silicon carbide (SiC) as a semiconductor material. The active region 31 is a region through which a main current (drift current) flows when the MOSFET (silicon carbide semiconductor device 10) is on, and occupies most of the area (surface area) of the semiconductor substrate 40.

[0061] 1, the active region 31 has, for example, a substantially rectangular planar shape and is disposed approximately at the center (chip center) of the semiconductor substrate 40. In the effective region (active effective region) 31a of the active region 31, multiple MOSFET cells of the same structure are disposed adjacent to each other and function as a MOSFET. The ineffective region (active ineffective region) 31b of the active region 31 is the region of the active region 31 excluding the active effective region 31a, in which no MOSFET cells are disposed and which does not function as a MOSFET. The boundary region 32 is adjacent to the outside of the active region 31 (toward the chip edge) and surrounds the periphery of the active region 31 in a substantially rectangular shape.

[0062] The edge termination region 33 is a region between the boundary region 32 and the edge (chip edge) of the semiconductor substrate 40, and is adjacent to the outside of the boundary region 32, surrounding the periphery of the boundary region 32 in a substantially rectangular shape. The edge termination region 33 has the function of alleviating the electric field on the front surface side of the semiconductor substrate 40 to maintain a breakdown voltage. The breakdown voltage is the limit voltage at which the element does not malfunction or break down. A predetermined breakdown voltage structure (not shown), such as a guard ring structure, a field limiting ring (FLR) structure, or a junction termination extension (JTE) structure, is disposed in the edge termination region 33.

[0063] A source pad 11a (source electrode (first electrode) 11), a gate pad 12, a measurement pad 13, a gate runner 14, and a source ring (first wiring layer) 15 are arranged on the front surface of the semiconductor substrate 40. The source electrode 11, the gate pad 12, the measurement pad 13, the gate metal wiring layer 63 (described later) of the gate runner 14, and the source ring 15 are metal layers formed on the same level. The source electrode 11 is provided in the active effective region 31a and covers substantially the entire active effective region 31a. The portion of the source electrode 11 exposed in the opening 20a of the passivation film 20 functions as the source pad 11a (hatched portion).

[0064] A portion (convex portion) 11b of the source electrode 11 is connected to the source ring 15 at a partially opened portion 14a of the gate runner 14. The source electrode 11 may be divided into two or more portions. For example, active effective regions 31a are arranged in line symmetry with respect to an active inactive region 31b (gate runner 14) that extends linearly through the center of the chip, and a source electrode 11 is arranged in each of these two active effective regions 31a. The convex portions 11b of all the source electrodes 11 are connected at the partially opened portion 14a of the gate runner 14. A plurality of cells are arranged in each active effective region 31a, for example, in line symmetry with respect to the gate runner 14.

[0065] The gate pad 12, measurement pad 13, and gate resistor (not shown) are arranged in the active inactive region 31b. The measurement pad 13 is an electrode pad for measuring gate resistance and is connected to the gate runner 14. The gate resistor and measurement pad 13 are arranged relatively close to the gate pad 12. The gate runner 14 and source ring 15 are arranged apart from each other in the boundary region 32, and have a ring-like planar shape that concentrically surrounds the periphery of the active region 31. The gate runner 14 is arranged in the boundary region 32. The gate runner 14 surrounds the periphery of the active region 31 in a substantially rectangular shape with a partial opening.

[0066] The gate runner 14 is electrically connected to the gate pad 12 via the gate resistor. The gate electrodes 8 (see FIGS. 3 and 4) of all cells of the MOSFET are electrically connected to the gate runner 14. The gate runner 14 may also be arranged in the active inactive region 31b. FIG. 1 shows a case in which the gate runner 14 extends linearly through the center of the chip in a direction parallel to the front surface of the semiconductor substrate 40. The gate resistor, gate electrode 8, and conductive layers made of polysilicon (poly-Si), such as the gate polysilicon wiring layer 62 (described later), are formed, for example, by ion-implanting n-type impurities into the polysilicon.

[0067] The source ring 15 is disposed outside the gate runner 14 in the boundary region 32, and surrounds the periphery of the active region 31 in a substantially rectangular shape. The source ring 15 is connected to a p-type peripheral region (fourth semiconductor region) 50 (described later), and is connected to the protruding portion 11b of the source electrode 11 at a partially opened portion 14a of the gate runner 14, and is fixed to the potential of the source electrode 11. The source ring 15 is connected to the n-type peripheral region 50 outside the active region 31 when the MOSFET is off. - When holes in the type drift region 2 are extracted to the source electrode 11, this has the function of suppressing the concentration of hole current in the insulating layer 64 directly below the gate runner 14 (on the semiconductor substrate 40 side).

[0068] As shown in FIGS. 2 to 6, the semiconductor substrate 40 is a n-type semiconductor substrate using SiC as a semiconductor material. + On the front surface of the starting mold substrate 41, -The semiconductor substrate 40 is formed by laminating epitaxial layers 42 to 44 in this order, which will become the p-type drift region (second first conductivity type region) 2, the n-type current diffusion region 23, and the p-type base region 3. The semiconductor substrate 40 has a first main surface on the p-type epitaxial layer 44 side as the front surface, and an n-type base region 3 on the n-type epitaxial layer 44 side as the rear surface. + The second main surface on the mold starting substrate 41 side is referred to as the back surface. + The starting substrate 41 is n + In the active effective region 31a, the front surface of the semiconductor substrate 40 and the n-type drain region 1 are - Between the source and drain regions 2, a trench gate structure of the MOSFET is provided.

[0069] The trench gate structure has a p-type base region (second semiconductor region) 3, an n + type source region (third semiconductor region) 4, p ++ The p-type base region 3 is formed of an n-type contact region 5, a trench 6, a gate insulating film 7, and a gate electrode 8. The p-type base region 3 is connected to the front surface of the semiconductor substrate 40 over the entire area of ​​the active region 31 and the boundary region 32. - The n-type drift region 2 is provided between the n-type drift region 2 and the n-type drift region 3. + type source region 4 and p ++ The n-type contact region 5 is a diffusion region formed in the surface region of the p-type epitaxial layer 44 by ion implantation. + type source region 4 and p ++ The contact regions 5 are selectively provided between the front surface of the semiconductor substrate 40 and the p-type base region 3 in contact with the p-type base region 3 .

[0070] The p-type epitaxial layer 44 + type source region 4, p ++ type contact region 5 and p ++ The portion excluding the peripheral contact region 53 is the p-type base region 3. + The n-type source region 4 and the n-type current diffusion region 23 described later extend linearly in the longitudinal direction of the trench 6 (first direction X) between the adjacent trenches 6, and contact a p-type peripheral region 50 described later at their ends in the first direction X. +The n-type source region 4 and an n-type current diffusion region 23 (described later) are adjacent to the sidewall of the trench 6 and face the gate electrode 8 on the sidewall of the trench 6 via the gate insulating film 7 .

[0071] p ++ The contact regions 5 are disposed between the adjacent trenches 6 and spaced apart from the trenches 6. ++ It is preferable that a plurality of the contact regions 5 are disposed in a scattered manner in the longitudinal direction of the trench 6. When viewed from the front surface side of the semiconductor substrate 40 (in a plan view), each p ++ The periphery of the contact region 5 is + The p-type source region 4 is surrounded by ++ The p-type contact region 5 may not be provided. ++ Instead of the p-type contact region 5, the p-type base region 3 reaches the front surface of the semiconductor substrate 40 (not shown). + n-type drain region 1 side + The source region 4 is not provided (see FIGS. 8 and 9 described later).

[0072] The trench 6 extends from the front surface of the semiconductor substrate 40 to the n-th direction in the depth direction Z. + The trenches 6 extend linearly in a first direction X (longitudinal direction) parallel to the front surface of the semiconductor substrate 40, and are arranged adjacent to each other in a second direction Y (transverse direction) parallel to the front surface of the semiconductor substrate 40 and perpendicular to the first direction X, forming a stripe shape when viewed from the front surface of the semiconductor substrate 40 (see FIG. 2 ). A gate electrode 8 is provided within the trench 6 with a gate insulating film 7 interposed therebetween.

[0073] p-type base region 3 and n - Between the n-type drift region 2 and the bottom surface of the trench 6 + A first p + Mold region 21, second p + a first conductivity type region 22 (second conductivity type region), an n-type current diffusion region (first first conductivity type region) 23, and an n-type --The first p-type region (first first-conductivity type region or third first-conductivity type region) 24 is selectively provided. + Type region 21 and n -- The type region 24 is n - The second p epitaxial layer (first semiconductor region) 42 is a diffusion region formed by ion implantation in the surface region thereof. + The n-type region 22 and the n-type current diffusion region 23 are formed in the depth direction Z from the n-type epitaxial layer (first semiconductor region) 43 to the n-type epitaxial layer (first semiconductor region) 43. - The n-type epitaxial layer 43 is a diffusion region formed by ion implantation so as to be disposed over the surface region of the n-type epitaxial layer 42. If the n-type epitaxial layer 43 has the same impurity concentration as the n-type current diffusion region 23, ion implantation into the n-type epitaxial layer 43 to form the n-type current diffusion region 23 may not be performed.

[0074] 1st p. + Mold region 21, second p + The n-type region 22 is fixed to the potential of the source electrode 11, and has the function of depleting when the MOSFET is turned off (or depleting the n-type current diffusion region 23, or both), thereby mitigating the electric field near the bottom of the trench 6. + The first p-type region (second second conductivity type region) 21 is provided apart from the p-type base region 3 and faces the bottom surface of the trench 6 in the depth direction Z. + The mold region 21 may be in contact with the gate insulating film 7 at the bottom of the trench 6, or may be separated from the trench 6. + The mold region 21 extends linearly in the longitudinal direction (first direction X) of the trench 6 with a length substantially equal to the length of the trench 6 in the longitudinal direction, and has a p + It contacts the outer periphery region 51 of the mold.

[0075] 2nd p. + The first second conductivity type region (first second conductivity type region) 22 is formed between the trenches 6 adjacent to each other. + The mold area 21 is provided apart from the upper surface (n + The second p-type source region 4 faces the p-type base region 3. + The p-type region 22 is connected to the p-type base region 3 in the depth direction Z. ++The second p + The type region 22 is n - A lower portion (n) formed in the surface region of the n-type epitaxial layer 42 + the upper portion (n) formed on the n-type epitaxial layer 43 + The second p + The lower part of the mold region 22 is the first p + It may be formed at the same time as the mold region 21 .

[0076] 2nd p. + It is preferable that a plurality of mold regions 22 are provided scattered in the longitudinal direction (first direction X) of the trench 6. + The second p-type regions 22 are surrounded by n-type current diffusion regions 23. + The p-type region 22 is formed in the depth direction Z through the p-type base region 3. ++ It is sufficient that the second p + The mold regions 22 are spaced apart at intervals of p ++ The intervals at which the second p contact regions 5 are scattered in the first direction X may be different from the intervals at which the second p contact regions 5 are scattered. + A second p portion of the mold region 22 + The mold region 22 is the first p + The second p adjacent to each other in the first direction X may be connected to the mold region 21. + The distance w between the mold regions 22 is preferably, for example, about 1 μm or less.

[0077] The second p adjacent to each other in the first direction X + When the distance w between the first and second body regions 22 exceeds the upper limit, an avalanche current I AS When flowing, n + If a parasitic npn bipolar transistor, which has the p-type source region 4 as an emitter, the p-type base region 3 as a base, and the n-type current diffusion region 23 as a collector, is turned on, current flows more easily, causing a secondary breakdown of the parasitic npn bipolar transistor, which reduces the breakdown voltage of the MOSFET and may lead to destruction of the MOSFET. +The inventors have confirmed through experiments that the breakdown voltage of the MOSFET can be maintained by setting the distance w between the mold regions 22 within the above range.

[0078] The n-type current diffusion region 23 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers (holes and electrons). + Mold region 21, second p + Between the mold regions 22, the first p + Mold region 21, second p + Type region 22 and n -- The n-type current diffusion region 23 is provided adjacent to the p-type region 24 and is in contact with the p-type base region 3 at the top surface. The n-type current diffusion region 23 is disposed between the p-type base region 3 and the first p-type region 24 in the second direction Y. + The n-type current spreading region 23 extends between the first p-type region 21 and the trench 6. + Mold region 21, second p + than the mold region 22 + The bottom surface (n + n type drain region 1 side) - It contacts the mold drift region 2.

[0079] The n-type current diffusion region 23 is a first p + The n-type current diffusion region 23 surrounds the entire lower surface of the second p-type region 21. + The lower surface of the mold area 22 is selectively surrounded. + When the n-type regions 22 are scattered in the first direction X, the n-type current diffusion regions 23 are arranged in a plurality of second p + A second p portion of the mold region 22 + The second p + The second p-type region 22 whose lower surface is not surrounded by the n-type current diffusion region 23 + The entire lower surface of the mold area 22 is -- The n-type current spreading region 23 is surrounded by the n-type region 24 in the active region 31. -- The second p + The n-type regions 22 are respectively connected to n-type current spreading regions 23 or n-type --The entire lower surface is surrounded by a mold region 24 .

[0080] The n-type current diffusion region 23 extends from the active region 31 to the boundary region 32 and terminates in the boundary region 32 on the inner side (toward the center of the chip) than the source ring 15. The n-type current diffusion region 23 is p-type in the active ineffective region 31b. + The entire lower surface of the mold outer peripheral region 51 is surrounded by the boundary region 32. + The n-type current diffusion region 23 surrounds the lower surface of the portion of the mold periphery region 51 directly below the gate runner 14. Therefore, the n-type current diffusion region 23 faces the source electrode 11, gate pad 12, measurement pad 13, gate runner 14, and gate resistor in the depth direction Z, but does not face the source ring 15 in the depth direction Z. The n-type current diffusion region 23 - The lower portion formed in the surface region of the n-type epitaxial layer 42 and the upper portion formed in the n-type epitaxial layer 43 are connected in the depth direction Z.

[0081] The n-type current diffusion region 23 reduces the resistance of the main current path of the MOSFET, thereby reducing the on-resistance of the MOSFET. + n than the mold outer peripheral region 51 + By extending the n-type current diffusion region 23 deep into the first body diode 71, it is possible to easily cause avalanche breakdown in the active region 31 that occupies most of the area of ​​the semiconductor substrate 40. In addition, the n-type current diffusion region 23 reduces the forward current I F The resistance of the path is reduced, and the current (hereinafter referred to as the avalanche current) I generated by the rapid increase of carriers due to the avalanche breakdown in the active region 31 AS This makes it easier for current to flow through the first body diode 71. Therefore, the avalanche resistance can be improved.

[0082] The first body diode 71 is p ++ the p-type contact region 5, the p-type base region 3 and the first p + Mold region 21, second p + n-type region 22, n-type current diffusion region 23 and n - The parasitic pn diode formed at the pn junction of the junction drift region 2 and the avalanche current IAS The avalanche current I AS is the source electrode 11 to p ++ Therefore, as described above, the p ++ The second p + The mold region 22 is arranged in the first direction X. ++ type contact region 5 and the second p + By dotting the shaped regions 22, the avalanche current I AS and a region where a surge current I (described later) easily flows (region where the first body diode 71 is formed). FSM This can effectively separate the region where the current flows easily (the region where the third body diode 73 is formed).

[0083] n -- The mold region 24 is a second p + Mold region 22 and n - The n-type drift region 2 is provided between the n-type drift region 2 and the n-type drift region 3 in an island shape in contact with these regions. -- The second p-type regions 24 are surrounded by n-type current diffusion regions 23. + When the mold regions 22 are scattered in the first direction X, each n -- The mold region 24 has a second p + Adjacent to the mold area 22. -- The p-type region 24 forms a third body diode 73 adjacent to the first body diode 71 in the active effective region 31a. ++ the p-type contact region 5, the p-type base region 3 and the second p + Mold region 22 and n -- The mold region 24 and n - The third body diode 73 is a parasitic pn diode formed by the pn junction between the first body diode 71 and the second body diode 72. ... second body diode 71 and the second body diode 72. The third body diode 73 is a parasitic pn diode formed by the pn junction between the first body diode 71 and the second body diode 72. The third body diode 73 is a parasitic pn diode formed by the pn junction between the second body diode 71 and the second body diode 72. The third body diode 73 is a parasitic pn diode formed by the pn junction between the second body diode 71 FSM This is the route.

[0084] The built-in voltage V of the third body diode 73 b3 is the built-in voltage V of the first body diode 71b1 lower than (V b3 <V b1 As mentioned above, the built-in voltage of the pn junction, V bi is the acceptor density N A and donor density N d This is because the higher the built-in voltage V b1 , V b3 The acceptor density N that determines A (p ++ a p-type contact region 5, a p-type base region 3, and a second p + The third body diode 73 has a built-in voltage V b3 Determine the donor density N d (n -- The impurity concentration of the first body diode 71 is determined by the built-in voltage V b1 Determine the donor density N d (the impurity concentration of the n-type current diffusion region 23).

[0085] Also, n -- The type region 24 is a built-in voltage V bi The n-type impurity concentration in the vicinity of the pn junction interface is adjusted so that the n-type impurity concentration in the active effective region 31a is equal to or higher than the boundary region 32. -- The built-in voltage V of the third body diode 73 is b3 is the built-in voltage V of the second body diode 72 (described later) in the boundary region 32. b2 It is adjusted so that: b3 ≦V b2 The main junction of the MOSFET is a p-type region (first p-type region) fixed to the potential of the source electrode 11. + Mold region 21, second p + Mold region 22, p + n-type peripheral region 51), n-type current diffusion region 23, - type drift region 2 and n -- The n-type region 24 forms a pn junction with the n-type region 24 .

[0086] n -- The impurity concentration of the n-type region 24 is - The impurity concentration of the n-type drift region 2 may be approximately the same as that of the n-type drift region 3. In this case, the n-type impurity is implanted by ion implantation. - When forming the lower portion of the n-type current diffusion region 23 in the n-type epitaxial layer 42, -- The portion corresponding to the region where the mold region 24 is formed is covered with an ion implantation mask to prevent ion implantation from being performed on that portion, thereby -- A mold region 24 can be formed. -- The impurity concentration of the n-type region 24 is - When the impurity concentration of the third body diode 73 is approximately the same as that of the third body diode 73, the built-in voltage V b3 is the built-in voltage V of the second body diode 72 b2 It is the same as n -- A mold area 24 can be formed.

[0087] The built-in voltage V of the third body diode 73 b3 is the built-in voltage V of the second body diode 72 b2 If it is the same as (V b3 =V b2 <V b1 ), when the second body diode 72 in the boundary region 32 conducts in the forward direction, the third body diode 73 in the active effective region 31a also conducts in the forward direction. By the third body diode 73 conducting in the forward direction, the n-channel MOSFET in the boundary region 32 conducts more electricity than in the reference example (see FIGS. 10 to 14) when an inrush current flows through the MOSFET. - The carrier density in the type drift region 2 can be reduced. This reduces the surge current I when an inrush current flows through the MOSFET. FSM Even if a surge current I occurs, the amount of hole current flowing into the source ring 15 when an inrush current flows through the MOSFET is reduced compared to the reference example, and current concentration in the source ring 15 can be suppressed. FSM The tolerance to

[0088] Preferably, the built-in voltage V of the third body diode 73 b3is the built-in voltage V of the second body diode 72 b2 It is preferable that the value is lower than (V b3 <V b2 <V b1 ). Therefore, n -- The impurity concentration of the n-type region 24 is - The impurity concentration of the n-type drift region 2 is preferably lower than that of the p-type drift region 2. In this case, the n-type impurity is implanted by ion implantation of p-type impurities. - The n-type epitaxial layer 42 -- By lowering the n-type impurity concentration in the portion corresponding to the region where the n-type region 24 is formed to a degree that does not cause the n-type impurity concentration to be inverted to p-type, -- The n-type impurity ion implantation for forming the lower portion of the n-type current diffusion region 23 is performed by n -- This may be done in a state where the area corresponding to the region where the mold region 24 is to be formed is covered with an ion implantation mask.

[0089] The built-in voltage V of the third body diode 73 b3 is the built-in voltage V of the second body diode 72 b2 When the inrush current flows through the MOSFET, the third body diode 73 conducts forward before the second body diode 72 conducts forward, and the third body diode 73 has priority over the forward current I F As a result, when an inrush current flows through the MOSFET, the n - The carrier density in the type drift region 2 is further reduced, and the amount of hole current flowing into the source ring 15 when the MOSFET is turned off is further reduced, so that the surge current I FSM The resistance to heat is further improved.

[0090] The built-in voltage V of the third body diode 73 b3 is the built-in voltage V of the second body diode 72. b2 If the voltage is lower than b1 is the built-in voltage V of the second body diode 72 b2 Even if it is approximately the same as (V b3 <V b2 =V b1 ), surge current I FSMTherefore, the resistance to n -- By providing the die region 24, the built-in voltage V b3 is the built-in voltage V of the second body diode 72. b2 If the n-type current diffusion region 23 is lower than the n-type current diffusion region 23, for example, the p-type peripheral region 50 and the n-type peripheral region 50 may be disposed so as to face the source ring 15 in the depth direction. - The n-type current diffusion region 23 is extended between the first body diode 71 and the second body diode 72, and the built-in voltage V b1 , V b2 may be the same.

[0091] When the n-type current diffusion region 23 is not provided, the n-type current diffusion region 23 is replaced with - The first p-type drift regions 2 are adjacent to each other. + Mold region 21, second p + The first p-type region 22 extends to the p-type base region 3. + The second p + The first p-type base region 3 and the second p-type base region 22 are selectively surrounded by the second p-type base region 3 in the second direction Y. + The region extends between the mold region 21 and the trench 6. Although not particularly limited, the dimensions and impurity concentrations of each portion have the following values, for example: n - The impurity concentration of the type drift region 2 is, for example, 3×10 15 / cm 3 The impurity concentration of the n-type current diffusion region 23 is, for example, 1×10 17 / cm 3 The thickness of the n-type current diffusion region 23 to the bottom surface is about 0.5 μm. -- The impurity concentration of the mold region 24 is, for example, 1×10 15 / cm 3 3x10 or more 15 / cm 3 It is about the following.

[0092] n -- The mold region 24 has a second p + through the p-type region 22 and the p-type base region 3 ++The contact region 5 is disposed in a position facing the contact region 5. The surge current I generated when an inrush current flows through the MOSFET FSM is the source electrode 11 to p ++ Since it easily flows into the n-type contact region 5, -- The mold region 24 is p ++ Even if the contact is disposed at a position other than directly under the contact region 5, the surge current I FSM It is estimated that the effect of improving tolerance to -- If at least one mold region 24 is arranged, the surge current I FSM The effect of improving the tolerance to n -- The mold region 24 is a second p + It is preferable that the entire lower surface of the mold area 22 is surrounded.

[0093] n -- The mold regions 24 may be scattered in the first direction X between the adjacent trenches 6. In this case, the mold regions 24 may be scattered in the depth direction Z. -- The n-type regions 24 and the n-type current diffusion regions 23 may be alternately and repeatedly arranged at predetermined intervals in the first direction X. -- The n-type regions 24 and the n-type current diffusion regions 23 are alternately and repeatedly arranged in the first direction X at intervals of p ++ The intervals at which the mold contact regions 5 are scattered in the first direction X may be different from the intervals at which the mold contact regions 5 are scattered in the first direction X. -- The depth position of the lower surface of the n-type region 24 is preferably approximately the same as the depth position of the lower surface of the n-type current diffusion region 23. -- Effect of the mold region 24 (surge current I FSM The improvement in tolerance to -- The depth position of the lower surface of the n-type region 24 is set n deeper than the depth position of the lower surface of the n-type current diffusion region 23. + It is presumed that there will be no change even if the thickness is made deeper on the side of the type drain region 1.

[0094] n - The first p-type epitaxial layer 42 + Mold region 21, second p + n-type region 22, n-type current diffusion region 23, n -- The mold region 24 and the p + The outer peripheral region 51, the breakdown voltage structure (not shown) (for example, a p-type region such as a guard ring or FLR, or an n+ Type or p + The part excluding the channel stopper region of the type is n - n-type drift region 2. - The n-type drift region 2 is provided from the active region 31 to the boundary region 32 and the edge termination region 33, and is exposed at the chip edge (the side surface of the semiconductor substrate 40). - A p-type peripheral region 50 , which will be described later, extends from boundary region 32 to the entire region between boundary region 32 and p-type drift region 2 .

[0095] In addition, the active ineffective region 31b includes a p-type peripheral region 50 (p + Mold outer peripheral region 51) and n - The n-type current diffusion region 23 extends from the active effective region 31a to the entire region between the active effective region 31a and the n-type drift region 2, forming a first body diode 71. + The mold peripheral region 51 and n - Between the n-type drift region 2 and the n-type drift region 3, -- The n-type region 24 may be selectively provided. That is, the n-type region 24 may also be provided immediately below the gate pad 12, the measurement pad 13, the gate runner 14, and the gate resistor. -- The active ineffective region 31b may have an n-type region 24 arranged in an island shape. -- The n-type region 24 is also surrounded by the n-type current diffusion region 23 .

[0096] The active ineffective region 31b also has n -- By disposing the mold region 24, n -- The area occupied by the mold region 24 increases, and the surge current I FSM The surge current I at the connection point between the source electrode 11 and the source ring 15 (the partially opened portion 14 a of the gate runner 14 ) is further improved. FSM 1) at a location away from the connection point between the source electrode 11 and the source ring 15 (for example, directly below the gate pad 12 or directly below the measurement pad 13 in FIG. 1). FSM In this way, the surge current I FSM In places where there is a risk of a decrease in resistance to --By arranging the mold region 24, the surge current I FSM It is possible to suppress the decrease in tolerance to the

[0097] The gate electrode 8 is provided inside the trench 6 via the gate insulating film 7. The interlayer insulating film 9 is provided on the entire front surface of the semiconductor substrate 40 and covers the gate electrode 8. The source electrode 11 is provided in contact holes 9a and 9b of the interlayer insulating film 9. + type source region 4 and p ++ ohmic contact with the p-type contact region 5, + type source region 4 and p ++ The back surface (n + On the entire surface of the mold starting substrate 41 (the back surface), + Type drain region 1 (n + A drain electrode (second electrode) 16 is provided in contact with the starting substrate 41 .

[0098] As shown in FIGS. 7 to 9, the front surface of the semiconductor substrate 40 and the n-type semiconductor substrate 40 are in contact with each other over substantially the entire boundary region 32. - A p-type peripheral region 50 is provided between the n-type drift region 2 and the boundary region 32 of the active region 31. The p-type peripheral region 50 surrounds the periphery of the active region 31 in the boundary region 32 and is in contact with the front surface of the semiconductor substrate 40 in the inactive ineffective region 31b. - The p-type peripheral region 50 extends over the entire area between the n-type drift region 2 and the n-type peripheral region 50, surrounding the active effective region 31a. The p-type peripheral region 50 is fixed to the potential of the source electrode 11, and when the MOSFET is turned off, the n-type peripheral region 50 is connected to the n-type edge termination region 33. - It has the function of extracting holes in the type drift region 2 to the source electrode 11 or source ring 15 .

[0099] The p-type peripheral region 50 faces the entire surfaces of the gate pad 12, the measurement pad 13, the gate runner 14, the gate resistor, and the source ring 15 in the depth direction Z. -The n-type current diffusion region 23 extends from the active region 31 to the entire area between the active region 31 and the n-type drift region 2 (FIG. 8). Therefore, a first body diode 71 is formed directly below the gate runner 14 in the boundary region 32, similar to the active ineffective region 31b. -- The third body diode 73 may be formed by providing the mold region 24 in an island shape (FIG. 9).

[0100] In the boundary region 32, the n-type current diffusion region 23 terminates inside the source ring 15 (towards the chip center) and does not face the source ring 15 in the depth direction Z. That is, the lower surface of the p-type peripheral region 50 in the boundary region 32 contacts the n-type current diffusion region 23 only directly below the gate runner 14, and does not face the n-type current diffusion region 23 in the portion outside the gate runner 14 (including directly below the source ring 15). - Since the n-type current diffusion region 23 is not disposed directly below the source ring 15, the built-in voltage V b2 is the built-in voltage V of the first body diode 71 in the active effective region 31a. b1 Lower than.

[0101] The second body diode 72 is connected to the p-type peripheral region 50 and the n-type - The second body diode 72 is a parasitic pn diode formed at the pn junction with the second drift region 2. Therefore, the built-in voltage V b2 is the built-in voltage V of the third body diode 73 described above. b3 As described above, when an inrush current flows through the MOSFET, the second body diode 72 and the third body diode 73 conduct forward at approximately the same time, or the third body diode 73 conducts forward before the second body diode 72. Therefore, compared to the reference example, current concentration in the source ring 15 can be suppressed when the MOSFET is turned off, and the surge current I FSM The resistance to the above can be improved.

[0102] The p-type peripheral region 50 is +From the drain region 1 side, p + p-type peripheral region 51, p-type peripheral base region 52, and p-type ++ The mold periphery contact regions 53 are adjacent to each other in the depth direction. + p-type peripheral region 51, p-type peripheral base region 52, and p-type ++ The layout of the p-type peripheral contact region 53 is substantially the same (i.e., substantially the same as that of the p-type peripheral region 50). + The outer peripheral region 51 is formed from the n-type epitaxial layer 43 in the depth direction Z. - The p-type epitaxial layer 42 is a diffusion region formed by ion implantation and disposed over the surface region of the p-type epitaxial layer 42. + The mold peripheral region 51 is in contact with the front surface of the semiconductor substrate 40. - Between the n-type drift region 2, - The n-type drift region 2 and the n-type current diffusion region 23 are provided in contact with each other.

[0103] p + The impurity concentration and the depth position of the bottom surface of the mold outer peripheral region 51 are respectively + The impurity concentration and depth position of the lower surface of the mold region 21 are preferably the same. + The mold outer peripheral region 51 is, for example, a first p + It may be formed simultaneously with the mold region 21. + The p-type peripheral region 51 may extend toward the active effective region 31a and reach the sidewall of the outermost trench 6. The p-type peripheral base region 52 is an extension (p-type epitaxial layer 44) of the p-type base region 3 to the boundary region 32. The p-type peripheral base region 52 is formed between the front surface of the semiconductor substrate 40 and the p + In the entire area between the mold outer peripheral region 51 and the mold outer peripheral region 52, p + The p-type peripheral base region 52 is provided in contact with the p-type peripheral region 51. The p-type peripheral base region 52 reaches the sidewall of the outermost trench 6.

[0104] p ++ The p-type peripheral contact region 53 is a diffusion region formed in the surface region of the p-type epitaxial layer 44 by ion implantation. ++ The p-type peripheral contact region 53 is provided in contact with the p-type peripheral base region 52 over the entire area between the front surface of the semiconductor substrate 40 and the p-type peripheral base region 52.++ The outer peripheral contact region 53 may extend toward the active effective region 31 a and reach the sidewall of the outermost trench 6. ++ The peripheral contact region 53 is p ++ The contact region 5 may be formed at the same time. ++ The mold peripheral contact region 53 may not be provided. ++ Instead of the p-type periphery contact region 53 , the p-type periphery base region 52 reaches the front surface of the semiconductor substrate 40 .

[0105] An insulating layer 64 made of gate insulating film 7, field oxide film 61, and interlayer insulating film 9 is provided on the entire front surface of semiconductor substrate 40 in active ineffective region 31b, boundary region 32, and edge termination region 33. This insulating layer 64 covers active ineffective region 31b, p-type peripheral region 50 in boundary region 32, and the breakdown voltage structure in edge termination region 33. In edge termination region 33, the front surface of semiconductor substrate 40 is covered with n-type insulating film 64. - type epitaxial layer 42 (n - The edge termination region 33 has a breakdown voltage structure that is connected to the front surface of the semiconductor substrate 40 and the n-type drift region 2 (not shown). - It is provided between the mold drift region 2.

[0106] A gate polysilicon wiring layer 62 and a gate resistor (not shown) are provided between the field oxide film 61 and the interlayer insulating film 9 in the active inactive region 31b. The gate polysilicon wiring layer 62 is electrically connected to the gate pad 12 via the gate resistor. The gate electrode 8 extends onto the front surface of the semiconductor substrate 40 via the gate insulating film 7 and is connected to the gate polysilicon wiring layer 62. A p-type peripheral region 50 is disposed across an insulating layer 64 in the entire area directly below a connection portion 14b between the gate electrode 8 and the gate runner 14 (an extension portion of the gate electrode 8).

[0107] The gate metal wiring layer 63 is provided on the gate polysilicon wiring layer 62 and is connected to the gate polysilicon wiring layer 62 via a contact hole 9c in the interlayer insulating film 9. The gate polysilicon wiring layer 62 and the gate metal wiring layer 63 form a gate runner 14. A gate polysilicon wiring layer (not shown) is disposed directly below the gate pad 12 via the interlayer insulating film 9. The gate polysilicon wiring layer directly below the gate pad 12 is electrically connected to the gate polysilicon wiring layer 62 via a gate resistor. If a gate resistor is not built in, the gate pad 12 and the gate polysilicon wiring layer directly below the gate pad 12 may be in direct contact with each other.

[0108] The insulating layer 64 has p ++ Contact holes 9b and 9d are provided to expose the peripheral contact region 53. The source electrode 11 is ++ ohmic contact with the outer peripheral contact region 53, ++ p-type peripheral contact region 53, p-type peripheral base region 52 and p-type + The source ring 15 is electrically connected to the outer peripheral region 51 of the mold and extends outward on the interlayer insulating film 9 to be connected to the source ring 15. The source ring 15 is connected to the p ++ ohmic contact with the outer peripheral contact region 53, ++ p-type peripheral contact region 53, p-type peripheral base region 52 and p-type + It is electrically connected to the mold outer peripheral region 51 .

[0109] The p-type peripheral region 50 and the n-type peripheral region 51 are formed directly under the convex portion 11b of the source electrode 11. - The n-type current diffusion region 23 extends from the active region 31 to the entire area between the active region 31 and the n-type drift region 2. --No mold region 24 is arranged (FIG. 7). Therefore, a first body diode 71 is formed directly below the convex portion 11b of the source electrode 11, similar to the active inactive region 31b. The passivation film 20 is a surface protection film that covers substantially the entire outermost surface of the front surface of the semiconductor substrate 40 (i.e., the surface of the interlayer insulating film 9) and protects the front surface of the semiconductor substrate 40. The source pad 11a, gate pad 12, and measurement pad 13 are exposed through different openings in the passivation film 20, respectively.

[0110] The operation of the silicon carbide semiconductor device 10 (MOSFET) according to the embodiment will be described. When a voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 8 while a positive voltage relative to the source electrode 11 is applied to the drain electrode 16, the n-type base region 3 is + A channel (n-type inversion layer) is formed along the sidewall of the trench 6 in the region between the n-type source region 4 and the n-type current diffusion region 23. ++ From the n-type drain region 1, - through the n-type drift region 2, the n-type current diffusion region 23 and the channel; + A drift current (main current) flows toward the source region 4, turning the MOSFET on.

[0111] On the other hand, when a voltage positive with respect to the source electrode 11 is applied to the drain electrode 16 and the voltage applied to the gate electrode 8 is less than the gate threshold voltage, the p-type base region 3 and the first p + Mold region 21, second p + type region 22, n-type current diffusion region 23 and n - The MOSFET remains in the off state because the pn junction (main junction) with the type drift region 2 is reverse biased. A depletion layer spreads from the pn junction to the source electrode 11 side and the drain electrode 16 side within the active effective region 31 a, and also spreads laterally from the active effective region 31 a toward the active inactive region 31 b, the boundary region 32, and the edge termination region 33, thereby ensuring a predetermined breakdown voltage.

[0112] During the period when the MOSFET is transitioning from on to off, the p-type base region 3, the first p + Mold region 21, second p +The p-type region 22 and the p-type peripheral region 50, the n-type current diffusion region 23, -- The mold region 24 and n - The parasitic pn junction diode (body diode) formed by the pn junction with the type drift region 2 conducts in the forward direction, - Carriers are injected into and accumulated in the type drift region 2. At this time, the third body diode 73 in the active region 31 becomes forward conductive before the second body diode 72 in the boundary region 32 becomes forward conductive or approximately at the same time as the second body diode 72 in the boundary region 32 becomes forward conductive.

[0113] Therefore, when an inrush current flows through the MOSFET, the surge current I FSM occurs, the n in the boundary region 32 and the edge termination region 33 - The carrier density in the n-type drift region 2 can be reduced. When the MOSFET transitions from this state to the off state (reverse recovery of the body diode), - The holes in the n-type drift region 2 are discharged to the source electrode 11 or the source ring 15, and the MOSFET is turned off. - Since the carrier density in the type drift region 2 is reduced, the amount of hole current flowing into the source ring 15 when an inrush current flows in the MOSFET is reduced, thereby suppressing current concentration in the source ring 15.

[0114] As described above, according to the embodiment, the second p + Type region and n - Between the n-type drift region -- The mold region is selectively disposed, and the second p +The n-type impurity concentration in the portion in contact with the lower surface of the n-type region is partially different. This allows the built-in voltage of the pn junction (main junction of the MOSFET) in the active effective region to be partially lower than the built-in voltage of the pn junction directly below the source ring. Therefore, when an inrush current flows through the MOSFET, a forward current flows preferentially through a part of the body diode in the active effective region (third body diode), or a forward current flows simultaneously through the body diode directly below the source ring and the third body diode in the active effective region, and the n-type impurity concentration directly below the source ring is lowered. - The carrier density in the type drift region is reduced, which makes it possible to suppress current concentration in the source pad and source ring when the MOSFET is turned off, and improves the breakdown resistance of the MOSFET by improving the surge current resistance.

[0115] In the above, the present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the present disclosure. In addition, although the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, the present disclosure is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type.

[0116] INDUSTRIAL APPLICABILITY As described above, silicon carbide semiconductor devices according to the present disclosure are useful for power semiconductor devices used in power conversion devices, power supply devices for various industrial machines, and the like.

[0117] 1,101 n + Type drain region 2,102 n - n-type drift region 3,103 p-type base region 4,104 + Type source region 5,105 p ++1. Type contact region 6, 106 Trench 7, 107 Gate insulating film 8, 108 Gate electrode 9, 109 Interlayer insulating film 9a, 9b, 9c, 9d, 109a, 109b, 109d Contact hole 10, 110 Silicon carbide semiconductor device 11, 111 Source electrode 11a, 111a Source pad 11b, 111b Convex portion of source electrode 12, 112 Gate pad 13, 113 Measurement pad 14, 114 Gate runner 14a, 114a Partially opened portion of gate runner 14b Connection portion of gate runner with gate electrode 8 15, 115 Source ring 16, 116 Drain electrode 20, 120 Passivation film 20a, 120a Opening in passivation film 21, 22, 121, 122 p + n-type region 23, 123 n-type current diffusion region 24 -- Mold region 31, 131 Active region 31a, 131a Active effective region 31b, 131b Active ineffective region 32, 132 Boundary region 33, 133 Edge termination region 40, 140 Semiconductor body 41, 141 n + Starting substrate 42-44, 142-144 Epitaxial layer 50, 150 P-type peripheral region 51, 151 p + p-type peripheral region 52, 152 p-type peripheral base region 53, 153 ++ REFERENCE SIGNS LIST: outer peripheral contact region 61: field oxide film 62: gate polysilicon wiring layer 63: gate metal wiring layer 71 to 73, 171, 172: body diode X: first direction parallel to the front surface of the semiconductor substrate Y: second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction X Z: depth direction

Claims

1. An active region provided in a semiconductor substrate, a first semiconductor region of a first conductivity type provided inside the semiconductor substrate, a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region in the active region, a third semiconductor region of the first conductivity type selectively provided between the first main surface and the second semiconductor region, a trench penetrating the third semiconductor region and the second semiconductor region in the depth direction, a gate electrode provided inside the trench via a gate insulating film, a second conductivity type region selectively provided between the second semiconductor region and the first semiconductor region, reaching a position deeper than the bottom surface of the trench on the second main surface side of the semiconductor substrate, and contacting the first semiconductor region, a first electrode provided on the first main surface in the active region and electrically connected to the third semiconductor region, the second semiconductor region, and the second conductivity type region, a second electrode provided on the second main surface, a fourth semiconductor region of the second conductivity type provided between the first main surface and the first semiconductor region, surrounding the periphery of the active region, reaching a position deeper than the bottom surface of the trench on the second main surface side, and contacting the first semiconductor region, and a first wiring layer provided on the first main surface, surrounding the periphery of the active region, connected to a part of the first electrode, and electrically connected to the fourth semiconductor region facing the fourth semiconductor region in the depth direction. The second conductivity type region has a first second conductivity type region provided away from the trench and contacting the second semiconductor region. The first semiconductor region selectively has a first first conductivity type region with a different impurity concentration at a portion contacting the surface of the first second conductivity type region on the second main surface side. A silicon carbide semiconductor device characterized by this.

2. The silicon carbide semiconductor device according to claim 1, wherein the impurity concentration of the first first conductivity type region is higher than the impurity concentration of the second first conductivity type region of the first semiconductor region excluding the first first conductivity type region.

3. The silicon carbide semiconductor device according to claim 2, wherein the first first conductivity type region is provided between the second semiconductor region and the second first conductivity type region, reaches a position deeper than the first second conductivity type region on the second main surface side, and selectively surrounds the surface of the first second conductivity type region on the second main surface side.

4. The silicon carbide semiconductor device according to claim 2, wherein the first semiconductor region selectively has a third first conductivity type region having an impurity concentration lower than that of the second first conductivity type region, adjacent to the first first conductivity type region, between the first second conductivity type region and the second first conductivity type region.

5. The silicon carbide semiconductor device according to claim 1, wherein the impurity concentration of the first first conductivity type region is lower than the impurity concentration of the second first conductivity type region of the first semiconductor region excluding the first first conductivity type region.

6. The silicon carbide semiconductor device according to claim 5, wherein the first first conductivity type region is provided between the first second conductivity type region and the second first conductivity type region.

7. The trench extends linearly in a first direction parallel to the front surface of the semiconductor substrate, the first second conductivity type regions are distributed at a plurality of points at a predetermined interval in the first direction, the first first conductivity type region surrounds the periphery of the first second conductivity type region, reaches a position deeper than the first second conductivity type region on the second main surface side, and selectively surrounds the surface of the first second conductivity type region on the second main surface side. The silicon carbide semiconductor device according to claim 2, characterized in that.

8. The trench extends linearly in a first direction parallel to the front surface of the semiconductor substrate, the first second conductivity type regions are distributed at a plurality of points at a predetermined interval in the first direction, and the first first conductivity type region is arranged in an island shape adjacent to the first second conductivity type regions having different depths. The silicon carbide semiconductor device according to claim 5, characterized in that.

9. The silicon carbide semiconductor device according to claim 7 or 8, wherein the predetermined interval is 1 μm or less.

10. The second conductivity type region has a second second conductivity type region facing the bottom surface of the trench, and the second second conductivity type region extends linearly in the first direction. The silicon carbide semiconductor device according to claim 7 or 8, characterized in that.