Silicon carbide semiconductor device and power conversion device

Abstract

A silicon carbide semiconductor device (100) comprises: a silicon carbide epitaxial substrate (1) which includes a silicon carbide substrate (10) that has a first conductivity type, a buffer layer (12) that is provided on the silicon carbide substrate (10) and has the first conductivity type, and a drift layer (13) that is provided on the buffer layer (12) and has the first conductivity type; an active region (14), which is a region where a semiconductor element is formed in the silicon carbide epitaxial substrate (1); and a termination region (15), which is a region on the outer side of the active region (14) in the silicon carbide epitaxial substrate (1). The silicon carbide substrate (10) has a back-side trench (11) on the lower surface thereof. The depth of the back-side trench (11) does not reach to the drift layer (13). The bottom edge on the inner peripheral side of the back-side trench (11) is positioned in the active region (14), and the bottom edge on the outer peripheral side of the back-side trench (11) is positioned in the termination region (15).

Description

Silicon carbide semiconductor device and power conversion device

[0001] The present disclosure relates to silicon carbide semiconductor devices and power conversion devices.

[0002] It is known that a continuous flow of forward current, i.e., bipolar current, through a PN diode made of silicon carbide (SiC) can cause stacking faults in the SiC crystal, resulting in high resistance of the device, which is a reliability issue. This occurs because the recombination energy generated when minority carriers injected through the PN diode recombine with majority carriers causes stacking faults, which are planar defects, to expand, starting from basal plane dislocations present in the silicon carbide substrate and blocking current flow. The expansion of stacking faults reduces the effective device area, increasing device resistance and causing a decrease in the reliability of the semiconductor device.

[0003] This increase in forward voltage also occurs in vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) made of silicon carbide. Vertical MOSFETs have a parasitic PN diode (body diode) between the source and drain, and when a forward current flows through this body diode, the vertical MOSFET also experiences a decrease in reliability similar to that of a PN diode. This decrease in reliability is particularly problematic when the body diode is used as a freewheeling diode for the MOSFET.

[0004] As a method for solving the above problem, Non-Patent Document 1 describes a SiC epitaxial growth method in which basal plane dislocations carried over from the SiC substrate to the epitaxial growth layer are converted into threading edge dislocations, thereby preventing the expansion of stacking faults. Also, Non-Patent Document 2 describes a method in which a buffer layer with a high impurity concentration is formed on the SiC substrate, promoting the recombination of holes and electrons in the buffer layer and reducing the number of holes that reach the SiC substrate, thereby preventing the generation of stacking faults from basal plane dislocations present in the SiC substrate.

[0005] Patent Document 1 discloses a PN diode and MOSFET structure having a trench dug from the back side to the front side of a SiC substrate. With this structure, the SiC substrate is partially thinned, thereby ensuring chip strength and reducing the resistance of the device.

[0006] Japanese Patent Application Laid-Open No. 2013-201413

[0007] "Demonstration of High Quality 4H-SiC Epitaxial Growth with Extremely Low Basal Plane Dislocation Density", Materials Science Forum, Vol.778-780, pp. 91-94, 2014"Short minority carrier lifetimes in highly nitrogen-doped 4H-SiC epilayers for suppression of the stacking fault formation in PiN diodes", Journal of Applied Physics, Vol.120, 115101, 2016

[0008] The techniques of Non-Patent Documents 1 and 2 have a certain effect in suppressing deterioration of the characteristics of MOSFETs made of silicon carbide, but there is a concern that productivity may decrease because a thick buffer layer needs to be formed in order to pass a large current through the body diode.

[0009] The present disclosure has been made to solve the above-described problems, and aims to suppress characteristic variations caused by a forward current flowing through a body diode of a silicon carbide semiconductor device while suppressing a decrease in productivity.

[0010] A silicon carbide semiconductor device according to the present disclosure comprises: a silicon carbide epitaxial substrate including a silicon carbide substrate of a first conductivity type, a buffer layer of the first conductivity type provided on the silicon carbide substrate, and a drift layer of the first conductivity type provided on the buffer layer; an active region which is a region in the silicon carbide epitaxial substrate in which a semiconductor element is formed; and a termination region which is a region outside the active region in the silicon carbide epitaxial substrate, wherein the semiconductor element formed in the active region has a first well region of a second conductivity type provided in a surface layer portion of the drift layer, a source region of the first conductivity type provided in a surface layer portion of the first well region, and a gate electrode facing the source region with a gate insulating film interposed therebetween, and the termination region includes a second well region of the second conductivity type provided in a surface layer portion of the drift layer, and a JTE (Junction Termination) of the second conductivity type provided outside the second well region. and a silicon carbide substrate (SCC) having a back surface trench on a lower surface thereof, the back surface trench having a depth not reaching the drift layer, an inner bottom end of the back surface trench being located in the active region, and an outer bottom end of the back surface trench being located in the termination region.

[0011] According to the present disclosure, with a silicon carbide semiconductor device, it is possible to suppress a decrease in productivity and to suppress characteristic fluctuations caused by a forward current flowing through a body diode of the silicon carbide semiconductor device.

[0012] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0013] FIG. 1 is a plan view schematically showing the configuration of a silicon carbide semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view schematically showing the configuration of a silicon carbide semiconductor device according to a modification of the first embodiment. FIG. 3 is a diagram showing simulation results of a hole density ratio to a central portion of an active region when the width of a back surface trench is changed in a silicon carbide semiconductor device according to the first embodiment. FIG. 4 is a diagram showing simulation results of a maximum hole density ratio in the vicinity of a termination region to a central portion of an active region for each trench inner wall point position and back surface trench width in a silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view schematically showing the configuration of a silicon carbide semiconductor device according to a second embodiment. FIG. 6 is a block diagram showing the configuration of a power conversion system to which a power conversion device according to a third embodiment is applied.

[0014] In the following embodiments, the first conductivity type will be described as N-type and the second conductivity type as P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. The impurity concentration of each region is defined by its peak concentration. In other words, a region with a high (or low) impurity concentration means a region with a high (or low) peak impurity concentration.

[0015] First Embodiment In a first embodiment, a MOSFET (SiC-MOSFET) using a silicon carbide substrate as a base material is shown as a silicon carbide semiconductor device. Figures 1 and 2 are diagrams schematically showing a configuration of a silicon carbide semiconductor device 100 according to the first embodiment. Figure 1 is a top view of silicon carbide semiconductor device 100, and Figure 2 is a cross-sectional view taken along line a1-a2 shown in Figure 1.

[0016] Silicon carbide semiconductor device 100 is formed on a SiC epitaxial substrate 1, and as shown in FIG. 1, is provided at the center of the upper surface with a gate pad 2 to which a gate voltage is applied from an external control circuit, and a source pad 3.

[0017] As shown in FIG. 2 , the SiC epitaxial substrate 1 includes a first conductivity type (N-type) SiC substrate 10 and an epitaxial growth layer formed on the upper surface (front surface) of the SiC substrate 10, the epitaxial growth layer including a first conductivity type buffer layer 12 and a drift layer 13.

[0018] The buffer layer 12 is provided on the SiC substrate 10. The buffer layer 12 has the effect of recombining holes injected from the upper surface side of the SiC epitaxial substrate 1, thereby reducing the density of holes reaching the SiC substrate 10. The buffer layer 12 may also have the effect of converting basal plane dislocations present in the SiC substrate 10 into edge dislocations. The buffer layer 12 may also have a two-layer structure consisting of two layers with different impurity concentrations. The higher the impurity concentration of the buffer layer 12, the higher the ability to suppress the expansion of stacking faults due to current flow. Therefore, the impurity concentration and film thickness of the buffer layer 12 are set according to the density of the current flowing through the silicon carbide semiconductor device 100. For example, the impurity concentration of the buffer layer 12 is 1.0×10 １８ / cm ３ From 2.0 x 10 １９ / cm ３ is preferred.

[0019] Drift layer 13 is provided on buffer layer 12. The impurity concentration of drift layer 13 is lower than the impurity concentrations of SiC substrate 10 and buffer layer 12. The impurity concentration and thickness of drift layer 13 are set according to the breakdown voltage required for silicon carbide semiconductor device 100. For example, the impurity concentration of drift layer 13 is 1.0×10 １４ / cm ３ or more, and 1.0 x 10 １７ / cm ３ More preferably, it is 5.0 × 10 or less. １６ / cm ３ The thickness of the drift layer 13 is, for example, not less than 5 μm and not more than several hundred μm.

[0020] A back surface trench 11 is formed in a part of the lower surface (back surface) of the SiC substrate 10. The depth of the back surface trench 11 is a depth that does not reach the drift layer 13, i.e., a depth that is smaller than the thickness of the SiC substrate 10.

[0021] In the present disclosure, the sidewall on the inner periphery side of the back surface trench 11 (i.e., the active region 14 side) is referred to as the "inner wall," and the sidewall on the outer periphery side of the back surface trench 11 (i.e., the termination region 15 side) is referred to as the "outer wall." The bottom end on the inner periphery side of the back surface trench 11, i.e., the intersection point between the inner wall and the bottom side of the back surface trench 11, is defined as the "trench inner wall point 81." The bottom end on the outer periphery side of the back surface trench 11, i.e., the intersection point between the outer wall and the bottom side of the back surface trench 11, is defined as the "trench outer wall point 82." In FIG. 1 , a line consisting of a set of trench inner wall points 81 and a line consisting of a set of trench outer wall points 82 are shown by dotted lines.

[0022] A back surface electrode 71 is provided on the lower surface of the SiC substrate 10 except for the portion of the back surface trench 11. The back surface electrode 71 is connected to the lower surface of the SiC substrate 10 via an ohmic contact layer 72.

[0023] 2 , the SiC epitaxial substrate 1 is divided into an active region 14 in which a device structure of a MOSFET, which is a semiconductor device, is formed, and a termination region 15 outside the active region 14. The buffer layer 12, the drift layer 13, the back surface electrode 71, and the ohmic contact layer 72 are formed across both the active region 14 and the termination region 15.

[0024] The configuration of the active region 14 will be described. In the active region 14, a first well region 31 of a second conductivity type (P type) is selectively formed in a surface layer portion of the drift layer 13. Furthermore, a source region 21 of the first conductivity type and a first well contact region 33 of the second conductivity type, which has a higher impurity concentration than the first well region 31, are selectively formed in a surface layer portion of the first well region 31. In a plan view, the first well contact region 33 is surrounded by the first well region 31.

[0025] A gate insulating film 41 is formed on the SiC epitaxial substrate 1 so as to straddle the source regions 21 of adjacent cells. That is, the gate insulating film 41 is formed from one of the source regions 21 of the two adjacent cells to the other.

[0026] A gate electrode 42 is formed on the gate insulating film 41. The gate insulating film 41 faces the first well region 31 via the gate insulating film 41. The gate electrode 42 is covered with an interlayer insulating film 43, and the source pad 3 is formed on the interlayer insulating film 43. The source pad 3 and the gate electrode 42 are electrically insulated by the interlayer insulating film 43. Contact holes reaching the source region 21 and the first well contact region 33 are formed in the interlayer insulating film 43, and the source pad 3 is connected to the source region 21 and the first well contact region 33 through the contact holes. The source pad 3 is made of a metal such as an aluminum electrode.

[0027] Next, the configuration of termination region 15 will be described. In termination region 15, a second well region 32 of the second conductivity type is selectively formed in the surface layer portion of drift layer 13 so as to surround active region 14. In the surface layer portion of second well region 32, a second well contact region 34 of the second conductivity type, which has a higher impurity concentration than second well region 32, is provided in order to reduce contact resistance with metal electrodes such as source pad 3.

[0028] A second conductivity type JTE (Junction Termination Extension) region 35 is provided on the outer periphery of second well region 32 to maintain the breakdown voltage of silicon carbide semiconductor device 100. JTE region 35 may have, for example, a so-called FLR (Field Limiting Ring) structure formed in a ring shape along the outer periphery of the semiconductor device. JTE region 35 is provided such that its innermost portion contacts second well region 32 or second well contact region 34.

[0029] Here, boundary A between active region 14 and termination region 15 is defined as a position corresponding to either the innermost end of second well region 32 or the innermost end of JTE region 35, whichever is closer to the center of active region 14 (which is located more inward). As shown in Figure 2, part of gate insulating film 41, part of gate electrode 42, part of interlayer insulating film 43, and part of source pad 3 extend from active region 14 to termination region 15, straddling boundary A between active region 14 and termination region 15.

[0030] A field insulating film 51 is formed on the SiC epitaxial substrate 1 in the termination region 15. The field insulating film 51 covers a part of the second well region 32 and the entire JTE region 35. The field insulating film 51 is not provided in the active region 14. In other words, the field insulating film 51 has an opening that encompasses the active region 14.

[0031] The source pad 3 extended to the termination region 15 is connected to the second well contact region 34 through a contact hole formed in the interlayer insulating film 43. The gate electrode 42 extended to the termination region 15 is disposed on the field insulating film 51. The gate pad 2 extended to the termination region 15 is connected to the gate electrode 42 on the field insulating film 51 through a contact hole provided in the interlayer insulating film 43.

[0032] The back surface trench 11 provided on the lower surface of the SiC substrate 10 is arranged so as to straddle the boundary A between the active region 14 and the termination region 15. That is, a trench inner wall point 81 of the back surface trench 11 is located in the active region 14, and a trench outer wall point 82 of the back surface trench 11 is located in the termination region 15. The back surface trench 11 may be formed by selective dry etching using a photolithography technique, for example, or by laser processing.

[0033] Next, a method for manufacturing silicon carbide semiconductor device 100 according to the first embodiment will be described.

[0034] First, a low-resistance SiC substrate 10 of first conductivity type (N type) having a 4H polytype and a (0001) plane orientation at the top surface with an off-axis angle is prepared. The SiC substrate 10 used has an off-axis angle of 2 to 8 degrees in the 11-20 direction. Next, a 1.0×10 １８ / cm ３ to 1.0 x 10 １９ / cm ３ An N-type buffer layer 12 having an impurity concentration of 1.0×10 is epitaxially grown on the SiC substrate 10. The thickness of the buffer layer 12 is, for example, 5 μm. １４ / cm ３ to 1.0 x 10 １７ / cm ３ An N-type drift layer 13 having an impurity concentration of 100 μm is epitaxially grown on the buffer layer 12. The thickness of the buffer layer 12 is, for example, 5 μm to 100 μm. In this way, the SiC epitaxial substrate 1 is obtained.

[0035] Next, a photolithography step of forming a resist mask and an ion implantation step using the resist mask as an implantation mask are repeated to form a first well region 31, a first well contact region 33, a second well region 32, a second well contact region 34, a JTE region 35, and a source region 21 in the surface layer portion of the drift layer 13. In the ion implantation step, N (nitrogen) or the like is used as the N-type impurity, and Al, B, or the like is used as the P-type impurity.

[0036] The depth of the first well region 31 and the second well region 32 is set to about 0.3 μm to 3 μm, which does not exceed the thickness of the drift layer 13. The impurity concentration of the first well region 31 and the second well region 32 is set to 1.0×10 １７ / cm ３ to 1.0 x 10 １９ / cm ３and is higher than the impurity concentration of the drift layer 13. The first well region 31 and the second well region 32 may be formed collectively in the same ion implantation process. The first well contact region 33 and the second well contact region 34 may be formed collectively in the same ion implantation process.

[0037] The impurity concentration of the source region 21 is in a range higher than the impurity concentration of the first well region 31, for example, 1.0×10 １９ / cm ３ or more, and 1.0 x 10 ２１ / cm ３ The dose of the first well contact region 33 and the dose of the JTE region 35 are 0.5×10 １３ / cm ２ or more, and 5.0 x 10 １３ / cm ２ It is preferable that the value is equal to or less than 1.0 × 10 １３ / cm ２ The implantation energy when forming the first well region 31 and the second well region 32 is, for example, 100 keV or more and 700 keV or less. In this case, the impurity concentration of the JTE region 35 converted from the dose is 1.0×10 １７ / cm ３ or more, and 1.0 x 10 １９ / cm ３ The implantation energy when forming the source region 21 is set to, for example, 20 keV or more and 300 keV or less.

[0038] Thereafter, a heat treatment device is used to perform annealing at a temperature of 1500° C. or higher, thereby activating the impurities added by ion implantation.

[0039] Next, for example, a CVD method is used to form a SiO layer having a thickness of, for example, 0.5 μm or more and 2 μm or less on the upper surface of the SiC epitaxial substrate 1. ２ Then, the SiO film is formed by a photolithography process and an etching process. ２The film is patterned to form a field insulating film 51. At this time, the field insulating film 51 is patterned so as to cover a part of the second well region 32 and extend beyond the end of the second well region 32 to the outer periphery of the second well region 32. The field insulating film 51 may also cover a part of the second well contact region 34.

[0040] Next, the upper surface of the drift layer 13 that is not covered with the field insulating film 51 is thermally oxidized to form SiO ２ A gate insulating film 41 made of a film is formed. Then, a conductive polycrystalline silicon film is formed on the gate insulating film 41 by low-pressure CVD, and the polycrystalline silicon film is patterned by photolithography and etching processes to form a gate electrode 42. In this case, the gate electrode 42 may be formed so as to extend over the upper surface of the field insulating film 51.

[0041] Then, SiO ２ An interlayer insulating film 43 made of a film is formed to cover the gate electrode 42. Then, photolithography and etching processes are performed to form contact holes that penetrate the gate insulating film 41 and the interlayer insulating film 43 and reach the first well contact region 33, the source region 21, and the second well contact region 34. In this process, contact holes are formed in the termination region 15 on the field insulating film 51 to reach the gate electrode 42. The interlayer insulating film 43 on the outer edge of the chip is also removed.

[0042] Next, a surface electrode layer that will become the source pad 3 and the gate pad 2 is formed on the upper surface of the SiC epitaxial substrate 1 by sputtering, vapor deposition, or the like. The surface electrode may be made of a metal containing one or more of Ti, Ni, Al, Cu, and Au, or an Al alloy such as Al—Si. Note that a silicide film may be formed in advance by heat treatment on the portion of the SiC epitaxial substrate 1 that will be in contact with the surface electrode.

[0043] Next, the surface electrode is patterned by photolithography and etching processes to separate the surface electrode into the source pad 3 and the gate pad 2. At this time, the surface electrode is patterned into a shape such that, in a plan view, the outer circumferential edge of the surface electrode at the corners of the termination region 15 is located more inward than the outer circumferential edge of the surface electrode at the linear portions of the termination region 15, with the position of the outer circumferential edge of the second well region 32 as the reference. In other words, the surface electrode is patterned into a shape such that the outer circumferential edge of the surface electrode at the corners is not located more outward than the outer circumferential edge of the surface electrode at the linear portions.

[0044] A surface protection film may be formed so as to cover the outer peripheral edge of the surface electrode and at least a portion of the upper surface of SiC epitaxial substrate 1 in termination region 15. The surface protection film is processed into a desired shape by, for example, applying and exposing photosensitive polyimide.

[0045] Next, a layer of a material for the back electrode 71 is formed by sputtering, vapor deposition, or the like on the lower surface of the SiC epitaxial substrate 1. The material for the back electrode 71 may be, for example, a metal containing one or more of Ti, Ni, Al, Cu, and Au.

[0046] Before forming back surface electrode 71, SiC epitaxial substrate 1 may be thinned to reduce the electrical resistivity during operation of silicon carbide semiconductor device 100. Thinning is achieved by grinding and / or polishing the underside of SiC substrate 10 until SiC epitaxial substrate 1 has a desired thickness. The thickness of SiC epitaxial substrate 1 after thinning is, for example, about 100 μm, and can be set to be not less than 50 μm and not more than 200 μm.

[0047] Next, a silicide layer is formed by reacting the back electrode 71 with the SiC substrate 10. By forming the silicide layer, ohmic contact is established between the back electrode 71 and the SiC substrate 10. This silicide layer becomes the ohmic contact layer 72 in FIG. 2. The ohmic contact layer 72 can be formed by irradiation with a focused laser beam or by annealing.

[0048] Thereafter, a laser processing device is used to form a back surface trench 11 on the lower surface of the SiC substrate 10. The shape of the back surface trench 11 may have a taper angle as shown in FIG. 3. The bottom side of the back surface trench 11 does not necessarily have to be parallel to the SiC substrate 10.

[0049] In the procedure of forming the back surface electrode 71 after forming the ohmic contact layer 72 of a silicide layer on the lower surface of the SiC substrate 10, the timing of forming the back surface trench 11 may be after the formation of the ohmic contact layer 72 and before the formation of the back surface electrode 71. In that case, the back surface electrode 71 may also be formed on the inner surface of the back surface trench 11, or may be removed from inside the back surface trench 11.

[0050] Although FIG. 2 shows a planar type transistor as an example of the MOSFET included in silicon carbide semiconductor device 100, the MOSFET may be a trench gate type transistor.

[0051] 1, gate pad 2 is provided near the center of one side of the chip of silicon carbide semiconductor device 100 in plan view, but there are no restrictions on the position and shape of gate pad 2. For example, gate pad 2 may be arranged at a corner of the chip, or may be arranged so as to traverse the center of the chip.

[0052] Research by the inventors of the technology disclosed herein has shown that the current density in the body diode of a SiC-MOSFET is 500 A / cm ２ It has been found that when such a large current is applied, a region is generated at the boundary between active region 14 and termination region 15 where the hole current density is at most twice as high as that at the center of the active region, and stacking faults occur preferentially in the boundary region between active region 14 and termination region 15. Furthermore, it has been confirmed that this phenomenon becomes more pronounced as the current density applied to the center of active region 14 increases, and that a current relatively larger than that at the center of active region 14 is concentrated in the vicinity of the boundary between active region 14 and termination region 15.

[0053] If a large current flows even in a part near the boundary between the SiC substrate 10 and the buffer layer 12, the buffer layer 12 must be designed to be suitable for that maximum current. ２ Even if a current of 1000 A / cm is passed through the body diode, in order to suppress the deterioration of the device characteristics, ２ This is undesirable from the viewpoint of productivity.

[0054] Silicon carbide semiconductor device 100 according to the first embodiment is provided with backside trench 11 on the underside of SiC substrate 10, thereby improving the concentration of hole current that occurs near the boundary between active region 14 and termination region 15 without significantly impairing the characteristics of the body diode. This makes it possible to suppress stacking faults that occur in SiC substrate 10 near the boundary between active region 14 and termination region 15. This prevents characteristic fluctuations when a large current is applied to the body diode, thereby improving the reliability of the device. Furthermore, since the thickness of buffer layer 12 that suppresses the occurrence of stacking faults can be reduced, a decrease in productivity is suppressed.

[0055] 4 is a diagram showing the results of a simulation of hole density distribution when the active region 14 of the silicon carbide semiconductor device 100 is replaced with a PN diode, the thickness of the SiC substrate 10 is 100 μm, the depth of the back surface trench 11 provided on the underside of the SiC substrate 10 is 50 μm, and the position of the trench inner wall point 81 is 50 μm toward the active region 14 from the boundary A. It has been confirmed that the results of the hole density distribution show the same tendency when the active region 14 is a MOSFET and when it is a PN diode. In this simulation, the applied current is 1000 A / cm ２In this simulation, the width of the back surface trench 11 was varied to 50 μm, 100 μm, 150 μm, 200 μm, 350 μm, 550 μm, and 650 μm. The graph labeled "Ref." in FIG. 4 represents the hole distribution when the back surface trench 11 is not present. In FIG. 4, the vertical axis represents the ratio of the hole density at the chip end (near the boundary A between the active region 14 and the termination region 15) to the hole density at the chip center (the center of the termination region 15). The horizontal axis represents the distance from the boundary A between the active region 14 and the termination region 15, with the positive value indicating the chip periphery (to the right in FIG. 2). The hole density is a value measured 2 μm from the outermost surface of the SiC substrate 10 toward the buffer layer 12.

[0056] 4 shows that as the width of the back surface trench 11 increases, the concentration of hole density, i.e., hole current, generated at the boundary A between the active region 14 and the termination region 15 is alleviated. In particular, if the width of the back surface trench 11 is 150 μm or more, it can be seen that the maximum hole density near the boundary A between the active region 14 and the termination region 15 is the same as or lower than the hole density in the central part of the active region 14. This is due to the combined effect of high electrical resistance only in one part due to the absence of the ohmic contact layer 72 on the bottom surface of the back surface trench 11 and a change in the potential distribution of the SiC substrate 10 due to the formation of the back surface trench 11.

[0057] FIG. 5 shows the maximum hole density at the chip end (near the boundary A between the active region 14 and the termination region 15) normalized by the hole density at the chip center for each width of the backside trench 11 shown in FIG. 4 . In FIG. 5 , the vertical axis represents the ratio of the maximum hole density at the chip end to the hole density at the chip center, with 100% representing that the hole density at the chip center and the maximum hole density at the chip end are equal. The horizontal axis represents the backside trench width. When the trench inner wall point 81 is greater than 0 μm (+50 μm, +100 μm), i.e., when the trench inner wall point 81 is closer to the termination region 15 than the boundary A, it can be seen that even if the width of the backside trench 11 is significantly increased, the maximum hole density near the boundary A does not become smaller than the hole density at the chip center. In other words, the effect of alleviating hole concentration near the boundary A is achieved when the trench inner wall point 81 is located closer to the active region 14 than the boundary A. Furthermore, if the bottom of the back surface trench 11 reaches the drift layer 13, the depletion layers extending from the first well region 31 and the second well region 32 reach the bottom of the back surface trench 11 when the device is off, making it impossible to achieve the desired device breakdown voltage.

[0058] From the above results, it can be understood that by providing a back surface trench 11 on the underside of SiC substrate 10, in which trench inner wall point 81 is located closer to active region 14 than boundary A and the bottom surface does not reach the drift layer, the concentration of hole current generated at boundary A between active region 14 and termination region 15 can be alleviated without significantly impairing the characteristics of the body diode and MOSFET.

[0059] Second Embodiment FIG. 6 is a cross-sectional view schematically showing the configuration of a silicon carbide semiconductor device 100 according to a second embodiment, and corresponds to the cross section taken along line a1-a2 shown in FIG.

[0060] In silicon carbide semiconductor device 100 according to the second embodiment, insulator 16 is buried inside back surface trench 11. Other configurations may be similar to those of the first embodiment.

[0061] The insulating material 16 embedded in the back surface trench 11 is, for example, SiO ２ SiO ２is preferably formed using SOG (spin-on glass). For example, after forming an ohmic contact layer 72, which is a silicide layer, on the lower surface of the SiC substrate 10, a back surface trench 11 is formed and the back surface trench 11 is filled with SOG, thereby forming the insulator 16. Thereafter, unnecessary SOG is removed with dilute hydrofluoric acid or the like, and the back surface electrode 71 is formed on the lower surface of the SiC epitaxial substrate 1, including on the insulator 16.

[0062] According to silicon carbide semiconductor device 100 of the second embodiment, it is possible to prevent a decrease in strength of the chip due to the provision of back surface trench 11 by burying insulator 16 in back surface trench 11. Therefore, it is possible to eliminate current concentration near the end portion of the chip while maintaining the bonding strength when the module is mounted.

[0063] Third Embodiment In this embodiment, silicon carbide semiconductor device 100 according to the above-described first and second embodiments is applied to a power conversion device. The application of silicon carbide semiconductor device 100 according to the first and second embodiments is not limited to a specific power conversion device, but hereinafter, as the third embodiment, a case will be described in which silicon carbide semiconductor device 100 according to the first and second embodiments is applied to a three-phase inverter.

[0064] FIG. 7 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0065] The power conversion system shown in Fig. 7 is composed of a power supply 1000, a power conversion device 2000, and a load 3000. The power supply 1000 is a DC power supply and supplies DC power to the power conversion device 2000. The power supply 1000 can be composed of various components, such as a DC system, a solar cell, or a storage battery, or it can be composed of a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 1000 can also be composed of a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0066] The power conversion device 2000 is a three-phase inverter connected between the power supply 1000 and the load 3000, and converts DC power supplied from the power supply 1000 into AC power and supplies the AC power to the load 3000. As shown in Fig. 7 , the power conversion device 2000 includes a main conversion circuit 2001 that converts DC power into AC power and outputs it, a drive circuit 2002 that outputs drive signals that drive each switching element of the main conversion circuit 2001, and a control circuit 2003 that outputs a control signal to the drive circuit 2002 to control the drive circuit 2002.

[0067] The load 3000 is a three-phase electric motor driven by AC power supplied from the power conversion device 2000. The load 3000 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0068] Details of power conversion device 2000 will be described below. Main conversion circuit 2001 includes switching elements and freewheel diodes (not shown). By switching the switching elements, DC power supplied from power supply 1000 is converted into AC power and supplied to load 3000. There are various specific circuit configurations for main conversion circuit 2001, but main conversion circuit 2001 according to this embodiment is a two-level, three-phase full-bridge circuit that can be configured with six switching elements and six freewheel diodes connected in anti-parallel to each switching element. The silicon carbide semiconductor device 100 according to the first or second embodiment described above is applied to each switching element of main conversion circuit 2001. Two of the six switching elements are connected in series to form upper and lower arms, and each upper and lower arm constitutes one phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of main conversion circuit 2001, are connected to load 3000.

[0069] Drive circuit 2002 generates drive signals for driving the switching elements of main conversion circuit 2001 and supplies them to the control electrodes of the switching elements of main conversion circuit 2001. Specifically, in accordance with control signals from control circuit 2003 (described later), drive signals for turning the switching elements on and drive signals for turning the switching elements off are output to the control electrodes of each switching element. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0070] The control circuit 2003 controls the switching elements of the main conversion circuit 2001 so that the desired power is supplied to the load 3000. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 2001 should be in the on state based on the power to be supplied to the load 3000. For example, the main conversion circuit 2001 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 2003 then outputs a control command (control signal) to the drive circuit 2002 so that an on signal is output to the switching element that should be in the on state at each point in time, and an off signal is output to the switching element that should be in the off state at each point in time. In accordance with this control signal, the drive circuit 2002 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0071] In the power conversion device according to the present embodiment, silicon carbide semiconductor device 100 according to the first or second embodiment is used as a switching element in main conversion circuit 2001, and therefore improved reliability can be achieved.

[0072] In the present embodiment, an example has been described in which silicon carbide semiconductor device 100 according to embodiment 1 or 2 is applied to a two-level three-phase inverter, but the application of silicon carbide semiconductor device 100 according to embodiments 1 and 2 is not limited to this, and it can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used, and when power is supplied to a single-phase load, silicon carbide semiconductor device 100 according to embodiment 1 or 2 may be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, silicon carbide semiconductor device 100 according to embodiment 1 or 2 can also be applied to a DC / DC converter or an AC / DC converter.

[0073] Furthermore, a power conversion device employing silicon carbide semiconductor device 100 according to embodiment 1 or 2 is not limited to the case where the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0074] It is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate.

[0075] The above description is illustrative in all respects, and it is understood that countless variations not illustrated can be envisioned.

[0076] REFERENCE SIGNS LIST 1 SiC epitaxial substrate, 2 Gate pad, 3 Source pad, 10 SiC substrate, 11 Back surface trench, 12 Buffer layer, 13 Drift layer, 14 Active region, 15 Termination region, 16 Insulator, 21 Source region, 30 SiC epitaxial substrate, 31 First well region, 32 Second well region, 33 First well contact region, 34 Second well contact region, 35 JTE region, 41 Gate insulating film, 42 Gate electrode, 43 Interlayer insulating film, 51 Field insulating film, 71 Back surface electrode, 72 Ohmic contact layer, 81 Trench inner wall point, 82 Trench outer wall point, 100 Silicon carbide semiconductor device, 1000 Power supply, 2000 Power conversion device, 2001 Main conversion circuit, 2002 Drive circuit, 2003 Control circuit, 3000 Load.

Claims

1. A silicon carbide epitaxial substrate comprising a silicon carbide substrate of a first conductivity type, a buffer layer of the first conductivity type provided on the silicon carbide substrate, and a drift layer of the first conductivity type provided on the buffer layer, The silicon carbide epitaxial substrate has an active region in which a semiconductor element is formed, The terminal region, which is the region outside the active region in the silicon carbide epitaxial substrate, Equipped with, The semiconductor element formed in the active region is A first well region of a second conductivity type is provided on the surface of the drift layer, The first conductivity type source region provided on the surface of the first well region, A gate electrode facing the source region via a gate insulating film, It has, The aforementioned termination region is The second well region of the second conductivity type provided on the surface of the drift layer, The second conductivity type JTE (Junction Termination Extension) region provided outside the second well region, Includes, The silicon carbide substrate has a back surface trench on its lower surface. The depth of the aforementioned back trench is such that it does not reach the drift layer. The bottom end on the inner circumference side of the aforementioned back trench is located in the active region, The bottom end on the outer circumference side of the aforementioned back trench is located in the terminal region. Silicon carbide semiconductor device.

2. No silicide layer is formed on the bottom surface of the aforementioned back trench. The silicon carbide semiconductor device according to claim 1.

3. The width of the trench on the back surface is 150 μm or more. A silicon carbide semiconductor device according to claim 1 or claim 2.

4. The insulator is further embedded in the trench on the back surface, A silicon carbide semiconductor device according to claim 1 or claim 2.

5. The impurity concentration of the buffer layer is 1.0 × 10⁻⁶ １８ / cm ３ from 1.0 x 10 １９ / cm ３ It is within the range of, A silicon carbide semiconductor device according to claim 1 or claim 2.

6. The impurity concentration of the drift layer is 5.0 × 10 １６ / cm ３ The following is: A silicon carbide semiconductor device according to claim 1 or claim 2.

7. A silicon carbide semiconductor device according to claim 1 or claim 2, comprising a main conversion circuit that converts and outputs input power, A drive circuit that outputs a drive signal to the silicon carbide semiconductor device to drive the silicon carbide semiconductor device, A control circuit that outputs a control signal to the drive circuit to control the drive circuit, A power conversion device equipped with this device.