Semiconductor device

Abstract

Provided is a semiconductor device in which the cooling performance of a central part of a semiconductor element is improved. The semiconductor device includes a joining region and the semiconductor element. The joining region is provided to a circuit pattern. The semiconductor element is joined to the joining region. The joining region includes a first region and a second region surrounding the first region. The semiconductor element is joined to the joining region so as to cover the first region and the second region. The area of the upper surface of the first region is smaller than the area of the upper surface of the second region. The first region is formed of a material having a better thermal conduction characteristic than that of the second region, and has the shape of a cylindrical column, a polygonal column, a cone, or a polygonal pyramid.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Semiconductor devices used to control large currents are becoming larger to ensure the amount of current per element, and are becoming thinner to further improve their performance. In such semiconductor devices, the semiconductor elements are prone to warping in an upwardly convex shape. Patent Document 1 proposes a technology for suppressing warping of semiconductor elements using a pressing member.

[0003] Japanese Patent No. 7006706 Japanese Patent Application Laid-Open No. 2015-095561 Japanese Patent Application Laid-Open No. 2004-296723

[0004] When bonding a semiconductor element that is warped upward in a convex shape to a circuit pattern, the thickness of the bonding material directly below the center of the semiconductor element becomes thick. If there is a distribution in the thickness of the bonding material, a temperature distribution occurs when the bonding material cools. Therefore, voids are likely to occur in the thick parts of the bonding material due to differences in the degree of volumetric shrinkage during cooling.

[0005] During inverter operation of a semiconductor device, the center of the semiconductor element becomes the hottest, and such voids hinder heat dissipation, ie, cooling, of the center of the semiconductor element.

[0006] In order to solve the above-mentioned problems, an object of the present disclosure is to provide a semiconductor device that improves the cooling performance of the central portion of a semiconductor element.

[0007] The semiconductor device according to the present disclosure includes a bonding region and a semiconductor element. The bonding region is provided on a circuit pattern. The semiconductor element is bonded to the bonding region. The bonding region includes a first region and a second region surrounding the first region. The semiconductor element is bonded to the bonding region while covering the first region and the second region. The area of ​​the top surface of the first region is smaller than the area of ​​the top surface of the second region. The first region is formed of a material with better thermal conductivity than the second region, and has one of the following shapes: a cylinder, a polygonal prism, a cone, and a polygonal pyramid.

[0008] According to the present disclosure, a semiconductor device is provided in which the cooling performance of the central portion of the semiconductor element is improved.

[0009] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0010] 1 is a partial cross-sectional view showing only a portion of the configuration of a semiconductor device according to a first embodiment, the portion comprising a semiconductor element; FIG. 2 is a top view showing the configuration of a semiconductor device; FIG. 3 is a diagram showing an example of materials forming a first region and a second region of a bonding region; FIG. 4 is a diagram showing the relationship between the area of ​​the first region, the area of ​​the second region, the thermal conductivity of the first region, and the thermal conductivity of the second region; FIG. 5 is a partial cross-sectional view showing only a portion of the configuration of a semiconductor device according to a fourth embodiment, the portion comprising a semiconductor element; FIG. 6 is a top view showing the configuration of a semiconductor device; FIG. 7 is a partial cross-sectional view showing only a portion of a semiconductor device according to a fifth embodiment, the portion comprising a semiconductor element; FIG. 8 is a diagram showing the relationship between the height of a protrusion, the amount of warping of a semiconductor element, and the thickness of a bonding material at an end of a semiconductor element.

[0011] <First Embodiment> Fig. 1 is a partial cross-sectional view showing only a portion including a semiconductor element 5 in the configuration of a semiconductor device 101 according to a first embodiment. The semiconductor device 101 includes an insulating substrate 1, a circuit pattern 2, a bonding region 3, a bonding material 4, and a semiconductor element 5. Fig. 2 is a top view showing the configuration of the semiconductor device 101. In Fig. 2, the bonding material 4 and the semiconductor element 5 are omitted from illustration.

[0012] The insulating substrate 1 is made of, for example, ceramic. The circuit pattern 2 is provided on the upper surface of the insulating substrate 1. The circuit pattern 2 is made of a conductive material such as metal.

[0013] The bonding regions 3 for bonding the semiconductor element 5 are provided at predetermined positions on the circuit pattern 2. The surfaces of the bonding regions 3 are plated with a metal material such as Ni. The plating process has the function of improving the bond between the semiconductor element 5 and the circuit pattern 2.

[0014] The bonding region 3 includes a first region 3A and a second region 3B. The first region 3A includes the center of the bonding region 3. The second region 3B surrounds the first region 3A. The area of ​​the upper surface of the first region 3A is smaller than the area of ​​the upper surface of the second region 3B.

[0015] The first region 3A is formed of a different material than the second region 3B and is formed of a material with better thermal conductivity than the second region 3B. The material of the second region 3B may be the same as the material of the circuit pattern 2 excluding the first region 3A. That is, the second region 3B may be a part of the circuit pattern 2 excluding the first region 3A. The top surface shape of the first region 3A shown in FIG. 2 is circular, but it may also be polygonal. The first region 3A penetrates the circuit pattern 2 as shown in FIG. 1. The first region 3A has the shape of a cylinder or polygonal prism. The first region 3A may have the shape of a cone or a polygonal pyramid with inclined side surfaces.

[0016] The semiconductor element 5 is warped in an upwardly convex shape relative to the circuit pattern 2. The semiconductor element 5 is bonded to the bonding region 3 via a bonding material 4. The bonding material 4 is a conductive material such as solder. The semiconductor element 5 is bonded to the bonding region 3, covering the first region 3A and the second region 3B.

[0017] The semiconductor element 5 is formed of a semiconductor such as Si. The semiconductor may be SiC, GaN, Ga ２ O ３ , GeO ２ Preferably, the semiconductor element 5 is a so-called wide bandgap semiconductor such as diamond. The semiconductor element 5 is a power semiconductor element, a control IC (Integrated Circuit) for controlling the power semiconductor element, or the like. The semiconductor element 5 includes, for example, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a Schottky barrier diode, or the like. Alternatively, the semiconductor element 5 may include a reverse-conducting IGBT (RC-IGBT) in which an IGBT and a free wheel diode are formed within a single semiconductor substrate.

[0018] In such a semiconductor device 101, the first region 3A has good thermal conductivity, and therefore the cooling performance of the central portion of the semiconductor element 5 is improved.

[0019] In summary, the semiconductor device 101 in the first embodiment includes a bonding region 3 and a semiconductor element 5. The bonding region 3 is provided in the circuit pattern 2. The semiconductor element 5 is bonded to the bonding region 3. The bonding region 3 includes a first region 3A and a second region 3B surrounding the first region 3A. The semiconductor element 5 is bonded to the bonding region 3 while covering the first region 3A and the second region 3B. The area of ​​the top surface of the first region 3A is smaller than the area of ​​the top surface of the second region 3B. The first region 3A is formed of a material with better thermal conductivity than the second region 3B, and has any one of the following shapes: a cylinder, a polygonal prism, a cone, and a polygonal pyramid.

[0020] During the manufacturing process of the semiconductor device 101, the molten bonding material 4 cools and solidifies while in contact with the semiconductor element 5 and the bonding region 3. Because the first region 3A has better thermal conductivity than the second region 3B, the bonding material 4 directly below the center of the semiconductor element 5 is locally cooled. Even if the semiconductor element 5 is warped upward, causing a distribution in the thickness of the bonding material 4, the temperature distribution during the cooling process of the bonding material 4 is minimized. Therefore, voids are less likely to occur due to differences in the volumetric shrinkage of the bonding material 4 depending on the temperature distribution. In other words, the occurrence of voids is suppressed even when the bonding material 4 is solidified all at once.

[0021] Furthermore, the central portion of the semiconductor element 5, which generates a large amount of heat, is efficiently cooled even during inverter operation of the semiconductor device 101. As a result, the operating characteristics of the semiconductor device 101 are improved.

[0022] Furthermore, when the first region 3A has a conical or polygonal pyramid shape, the heat generated from the semiconductor element 5 is effectively dissipated to the circuit pattern 2 and insulating substrate 1 directly below the semiconductor element 5. This further improves the cooling performance.

[0023] Regarding a technique for suppressing warpage of a semiconductor element 5, Patent Document 2 corrects warpage by sandwiching both sides of the semiconductor element 5 with electrodes having protrusions. The techniques described in Patent Documents 1 and 2 correct warpage of the semiconductor element 5, but stress is generated in the process. Therefore, the semiconductor element 5 is required to be flexible, making it difficult to apply this technique to a thin-film semiconductor element 5. Furthermore, Patent Document 3 proposes a heat dissipation structure for the entire surface directly below the semiconductor element 5, but does not provide any knowledge specific to cooling the center portion.

[0024] Second Preferred Embodiment FIG. 3 is a diagram showing an example of materials forming the first region 3A and the second region 3B of the bonding region 3. As shown in FIG.

[0025] The first region 3A is made of a material having a higher thermal conductivity than the material of the second region 3B. The first region 3A is made of, for example, one of Cu, Ag, and Au. The second region 3B is made of, for example, Al or an Al alloy.

[0026] This configuration improves the cooling performance of the central portion of the semiconductor element 5. Since the temperature distribution in the cooling process of the bonding material 4 is small, the occurrence of voids is suppressed even when the bonding material 4 is hardened all at once.

[0027] Third Embodiment The area SA of the first region 3A has a value obtained by multiplying the ratio of the thermal conductivity λB of the second region 3B to the thermal conductivity λA of the first region 3A by the area SB of the second region 3B. Fig. 4 is a diagram showing the relationship between the area SA of the first region 3A, the area SB of the second region 3B, the thermal conductivity λA of the first region 3A, and the thermal conductivity λB of the second region 3B.

[0028] This configuration improves the cooling performance of the central portion of the semiconductor element 5. Since the temperature distribution in the cooling process of the bonding material 4 is small, the occurrence of voids is suppressed even when the bonding material 4 is hardened all at once.

[0029] <Fourth Embodiment> Fig. 5 is a partial cross-sectional view showing only a portion including a semiconductor element 5 in the configuration of a semiconductor device 104 according to a fourth embodiment. Fig. 6 is a top view showing the configuration of the semiconductor device 104. In Fig. 6, the bonding material 4 and the semiconductor element 5 are omitted. Figs. 5 and 6 correspond to Figs. 1 and 2, and only the differences will be described below.

[0030] The upper surface of the first region 3A includes a protruding portion 3C that is taller than the upper surface of the second region 3B. The protruding portion 3C is disposed in the center of the bonding region 3. The protruding portion 3C is formed of a metal that has a higher thermal conductivity than the circuit pattern 2 surrounding the protruding portion 3C. Furthermore, the protruding portion 3C is formed of a metal that has good wettability with respect to the bonding material 4 provided between the semiconductor element 5 and the bonding region 3.

[0031] During the manufacturing process of the semiconductor device 104, the bonding material 4 melts between the protrusion 3C and the semiconductor element 5, and gas (e.g., air) generated in the molten bonding material 4 is pushed out around the protrusion 3C. Furthermore, by providing the protrusion 3C, the thickness of the bonding material 4 between the protrusion 3C and the semiconductor element 5 becomes thinner than the thickness of the bonding material 4 without the protrusion 3C. This promotes cooling of the bonding material 4 on the protrusion 3C, reducing the temperature distribution during the cooling process. For example, the bonding material 4 on the protrusion 3C hardens more quickly than the bonding material 4 around the protrusion 3C. As a result, the generation of voids directly below the center of the semiconductor element 5 is suppressed.

[0032] In this way, the cooling performance of the central portion of the semiconductor element 5 is improved, and the temperature distribution in the cooling process of the bonding material 4 is reduced. Even when the bonding material 4 is cured all at once, the generation of voids is suppressed.

[0033] 7 corresponds to Fig. 5 and is a partial cross-sectional view showing only a portion of a semiconductor device 105 according to a fifth embodiment, the portion including a semiconductor element 5. Fig. 8 is a diagram showing the relationship between the height of a protrusion 3C, the amount of warpage of the semiconductor element 5, and the thickness of a bonding material 4 at an end of the semiconductor element 5.

[0034] The height D of the protrusion 3C is equal to or greater than the sum of the thickness d2 of the bonding material 4 provided between the end of the semiconductor element 5 and the upper surface of the second region 3B and the amount of warping d1 of the semiconductor element 5. For example, the height of the protrusion 3C is equal to or greater than the sum of the minimum thickness of the bonding material 4 that must be ensured at the end and the amount of warping of the semiconductor element 5.

[0035] During the manufacturing process of the semiconductor device 105, the bonding material 4 melts between the protrusion 3C and the curved semiconductor element 5, and gas (e.g., air) generated in the molten bonding material 4 is pushed out around the protrusion 3C. Furthermore, by providing the protrusion 3C, the thickness of the bonding material 4 between the protrusion 3C and the semiconductor element 5 becomes thinner than the thickness of the bonding material 4 without the protrusion 3C. This promotes cooling of the bonding material 4 on the protrusion 3C, reducing the temperature distribution during the cooling process. For example, the bonding material 4 on the protrusion 3C hardens more quickly than the bonding material 4 around the protrusion 3C. As a result, the generation of voids directly below the center of the semiconductor element 5 is suppressed.

[0036] In the fifth embodiment, the different material embedded in the first region 3A, the area occupied by the first region 3A in the bonding region 3, and the protruding height of the first region 3A are optimized. This improves the cooling performance of the central portion of the semiconductor element 5, and minimizes the temperature distribution in the cooling process of the bonding material 4. Even when the bonding material 4 is cured all at once, the occurrence of voids is suppressed.

[0037] Although this disclosure has been described in detail, the above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned.

[0038] It should be noted that the embodiments can be freely combined, and the embodiments can be modified or omitted as appropriate.

[0039] REFERENCE SIGNS LIST 1 insulating substrate, 2 circuit pattern, 3 bonding area, 3A first area, 3B second area, 3C protrusion, 4 bonding material, 5 semiconductor element, 101 semiconductor device, 104 semiconductor device, 105 semiconductor device.

Claims

1. A junction region provided in the circuit pattern for joining a semiconductor element to the circuit pattern, The semiconductor element is joined to the junction region, The joining region includes a first region and a second region surrounding the first region. The semiconductor element is bonded to the junction region, covering the first region and the second region. The area of ​​the upper surface of the first region is smaller than the area of ​​the upper surface of the second region. The first region is formed of a material having better thermal conductivity than the second region, and has one of the shapes of a cylinder, a polygonal prism, a cone, or a polygonal pyramid, in a semiconductor device.

2. The second region is formed of Al or an Al alloy. The semiconductor device according to claim 1, wherein the first region is formed of any one of Cu, Ag, and Au, which has a higher thermal conductivity than the material forming the second region.

3. The semiconductor device according to claim 1, wherein the area of ​​the first region is the value obtained by multiplying the ratio of the thermal conductivity of the second region to the thermal conductivity of the first region by the area of ​​the second region.

4. The upper surface of the first region includes a projection that is taller than the upper surface of the second region. The semiconductor device according to any one of claims 1 to 3, wherein the protruding portion is formed of a metal that has a higher thermal conductivity than the surrounding area of ​​the protruding portion and has good wettability to a bonding material provided between the semiconductor element and the bonding region.

5. The semiconductor device according to claim 4, wherein the height of the protrusion is greater than or equal to the sum of the thickness of the bonding material provided between the end of the semiconductor element and the upper surface of the second region and the amount of warping of the semiconductor element.

6. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor element is curved in a shape that is convex upward with respect to the circuit pattern.