Semiconductor device, power conversion device, and manufacturing method for semiconductor device

Abstract

Provided is a semiconductor device in which the distance between an inner lead and a semiconductor element is stabilized, thus improving reliability. This semiconductor device includes an insulating substrate, a semiconductor element, an inner lead, and a sealing material. The insulating substrate includes: a first side surface; and a second side surface that extends in a direction different from the first side surface in plan view, and that has a length longer than the length of the first side surface. The semiconductor element is retained by the insulating substrate. The inner lead is electrically connected to the semiconductor element. The sealing material seals a portion of the inner lead and the semiconductor element. The inner lead includes a first extension portion and a second extension portion. The first extension portion extends inward from the outside of the first side surface of the insulating substrate in plan view. In plan view, the second extension portion includes a tip that branches from the first extension portion and extends toward the vicinity of the center of the second side surface of the insulating substrate. In plan view, the tip of the second extension portion is positioned outside the second side surface of the insulating substrate.

Description

Semiconductor device, power conversion device, and method of manufacturing the semiconductor device

[0001] The present disclosure relates to a semiconductor device, a power conversion device, and a method for manufacturing a semiconductor device.

[0002] There are two methods for forming circuits in power semiconductor devices: one is to form the circuit using wire bonding, and the other is to form the circuit by joining leads with a joining material. Patent Document 1 discloses a semiconductor device in which inner leads are joined to a semiconductor element with solder.

[0003] Patent No. 5805029

[0004] Because the tip of the cantilevered inner lead is not supported, the distance between the semiconductor element and the inner lead is unstable during the lead bonding process of the semiconductor device. In other words, it is difficult to form a bond with the desired dimensions, which affects the reliability of the semiconductor device.

[0005] In order to solve the above-mentioned problems, an object of the present disclosure is to provide a semiconductor device in which the distance between the inner lead and the semiconductor element is stable and reliability is improved.

[0006] The semiconductor device according to the present disclosure includes an insulating substrate, a semiconductor element, an inner lead, and an encapsulant. The insulating substrate includes a first side surface and a second side surface that, in a plan view, extends in a different direction from the first side surface and has a length longer than the length of the first side surface. The semiconductor element is held by the insulating substrate. The inner lead is electrically connected to the semiconductor element. The encapsulant encapsulates a portion of the inner lead and the semiconductor element. The inner lead includes a first extension portion and a second extension portion. In a plan view, the first extension portion extends from the outside toward the inside of the first side surface of the insulating substrate. In a plan view, the second extension portion includes a tip that branches from the first extension portion and extends toward the center of the second side surface of the insulating substrate. In a plan view, the tip of the second extension portion is located outside the second side surface of the insulating substrate.

[0007] According to the present disclosure, a semiconductor device is provided in which the distance between the inner lead and the semiconductor element is stable, improving reliability.

[0008] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0009] FIG. 1 is a top view showing the configuration of a semiconductor device according to the first embodiment before tie bar cutting. FIG. 2 is an A-A' cross-sectional view showing the configuration of the semiconductor device after tie bar cutting. FIG. 3 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view showing the configuration of an insulating substrate that holds a semiconductor element. FIG. 5 is a cross-sectional view showing a state in which an inner lead and an insulating substrate are mounted on a lower jig and clamped by an upper jig. FIG. 6 is a cross-sectional view showing the configuration of a completed semiconductor device. FIG. 7 is a graph showing the relationship between the longitudinal position and height of the insulating substrate before heating or after cooling according to the first embodiment. FIG. 8 is a graph showing the relationship between the longitudinal position and height of the insulating substrate during heating according to the first embodiment. FIG. 9 is a cross-sectional view showing the state of a bonding process between an inner lead and a semiconductor element. FIG. 10 is a cross-sectional view showing the state of a bonding process between an inner lead and a semiconductor element. FIG. 11 is a cross-sectional view showing the state of a bonding process in a method for manufacturing a semiconductor device according to the second embodiment. FIG. 12 is a cross-sectional view showing the state of a bonding process in a method for manufacturing a semiconductor device according to the third embodiment. FIG. 13 is a functional block diagram showing the configuration of a power conversion system according to the fourth embodiment.

[0010] First Embodiment FIG. 1 is a top view showing the configuration of a semiconductor device 101 according to a first embodiment before tie bars are cut. FIG. 2 is an A-A' cross-sectional view showing the configuration of the semiconductor device 101 after tie bars are cut. The semiconductor device 101 includes an insulating substrate 1, a semiconductor element 2, inner leads 3, signal terminals 4, metal wires 5, and a sealing material 6. FIG. 1 shows the configuration of the semiconductor device 101 in a process of being manufactured, with the inner leads 3 connected to a lead frame 31 by tie bars 30. FIG. 2 shows the cross-section taken along A-A' in FIG. 1. FIG. 2 shows the semiconductor device 101 in a state in which the tie bars 30 have been cut and the inner leads 3 have been separated from the lead frame 31.

[0011] Insulating substrate 1 includes first side surface 1A and second side surface 1B extending in a different direction from first side surface 1A. Insulating substrate 1 in embodiment 1 has a rectangular shape in a plan view, and second side surface 1B is perpendicular to first side surface 1A. First side surface 1A is a surface extending in the short-side direction (the up-down direction in FIG. 1 ), and second side surface 1B is a surface extending in the long-side direction (the left-right direction in FIG. 1 ).

[0012] The insulating substrate 1 includes an insulating base material 11, an upper conductor layer 12, and a lower conductor layer 13. The insulating base material 11 is made of ceramic. In the first embodiment, the insulating base material 11 is made of silicon nitride (SiN). The upper conductor layer 12 is provided on the upper surface of the insulating base material 11. The lower conductor layer 13 is provided on the lower surface of the insulating base material 11. The upper conductor layer 12 and the lower conductor layer 13 are made of a conductive material such as copper (Cu).

[0013] The semiconductor element 2 is held by the insulating substrate 1. The semiconductor element 2 is bonded to the upper conductor layer 12 of the insulating substrate 1 via a bonding material 7A. The semiconductor element 2 may be a power semiconductor element, a control integrated circuit (IC) for controlling the power semiconductor element, or the like. In the first embodiment, the semiconductor element 2 is a silicon insulated gate bipolar transistor (IGBT) 2A or a silicon diode 2B. The bonding material 7A is a conductive material, such as solder (Sn-3Ag-0.5Cu). The semiconductor device 101 shown in FIG. 1 is a 2-in-1 module and includes two IGBTs 2A and two diodes 2B. In FIG. 1, one IGBT 2A and one diode 2B are provided on the left side, and one IGBT 2A and one diode 2B are also provided on the right side.

[0014] The inner lead 3 is electrically connected to the semiconductor element 2. The inner lead 3 includes a first extending portion 3A, a second extending portion 3B, a terminal portion 3C, and a bonding portion 3D.

[0015] The first extending portion 3A extends from the outside to the inside of the first side surface 1A of the insulating substrate 1 in a plan view.

[0016] The second extending portion 3B includes a tip branching from the first extending portion 3A and extending toward the second side surface 1B of the insulating substrate 1. The second extending portion 3B preferably branches near the center in the longitudinal direction (left-right direction in FIG. 1 ) of the insulating substrate 1. In the first embodiment, the second extending portion 3B branches out on both sides (up-down direction in FIG. 1 ) of the extending direction of the first extending portion 3A. The tip of the second extending portion 3B is located outside the second side surface 1B of the insulating substrate 1 and inside the sealing material 6 in a plan view. The length of the second extending portion 3B extending outside the second side surface 1B of the insulating substrate 1 is equal to or greater than the thickness of the inner lead 3. The width of the second extending portion 3B is equal to or greater than the thickness of the inner lead 3.

[0017] Terminal portion 3C corresponds to an end portion of first extending portion 3A. Terminal portion 3C is provided on the outer side of first side surface 1A of insulating substrate 1 and protrudes from sealing material 6. Terminal portion 3C is configured to be connectable to an external circuit provided outside semiconductor device 101, and is a so-called main terminal.

[0018] The joint 3D is provided on the first extending portion 3A, but not on the second extending portion 3B. The joint 3D is joined to the upper surfaces of the IGBT 2A and the diode 2B via a joint material 7B. The joint material 7B is a conductive material, such as solder (Sn-3Ag-0.5Cu).

[0019] The signal terminal 4 is connected to the IGBT 2A by a metal wire 5. The metal wire 5 is an Al wire. A lead 8 separate from the inner lead 3 is joined to the upper surface conductor layer 12 by a bonding material 7C. The bonding material 7C is a conductive material, such as solder (Sn-3Ag-0.5Cu). The sealing material 6 seals the upper surface of the insulating substrate 1, the semiconductor element 2, and a portion of the inner lead 3. The sealing material 6 is a resin.

[0020] FIG. 3 is a flowchart showing a method for manufacturing the semiconductor device 101 according to the first embodiment.

[0021] In step S1, a semiconductor element 2 is prepared and held on an insulating substrate 1. The semiconductor element 2 is bonded to an upper surface conductor layer 12 of the insulating substrate 1 by a bonding material 7A. Fig. 4 is a cross-sectional view showing the configuration of the insulating substrate 1 holding the semiconductor element 2.

[0022] In step S2, the insulating substrate 1 is mounted on a lower jig 51 (see FIG. 5). The lower jig 51 has a recess at the position where the insulating substrate 1 is to be mounted. The insulating substrate 1 is mounted so as to be accommodated in the recess.

[0023] In step S3, bonding material 7B is placed at the bonding locations with bonding portions 3D of inner leads 3, and then lead frame 31 is mounted on lower jig 51. Lower jig 51 has a recess on its upper surface at the position where lead frame 31 will be mounted. Lead frame 31 is mounted so as to fit into the recess. Figure 5 is a cross-sectional view showing a state in which inner leads 3 and insulating substrate 1 are mounted on lower jig 51 and sandwiched by upper jig 52, which will be described later (corresponding to the left-right direction in Figure 1).

[0024] In step S3, although not shown, the tip of the second extending portion 3B of the inner lead 3 is supported on the upper surface of the lower jig 51. Furthermore, the first extending portion 3A of the inner lead 3 is arranged to extend from the outside toward the inside of the first side surface 1A of the insulating substrate 1 in a plan view. The tip of the second extending portion 3B of the inner lead 3 is arranged to branch from the first extending portion 3A and extend toward the second side surface 1B of the insulating substrate 1 in a plan view, and is positioned outside the second side surface 1B of the insulating substrate 1.

[0025] In step S4, the inner lead 3 is held down by the upper jig 52. Although not shown, the tip of the second extending portion 3B is held down by the upper jig 52 and pressure is applied.

[0026] In step S5, the bonding portions 3D of the inner leads 3 are bonded to the upper surfaces of the IGBT 2A and the diode 2B. By heating the semiconductor device 101, the bonding material 7B melts and the inner leads 3 are bonded to the semiconductor element 2. At this time, a lead 8 separate from the inner leads 3 is bonded to the bonding portions of the upper surface conductor layer 12 via the bonding material 7C. Through steps S2 to S5, the inner leads 3 are electrically connected to the semiconductor element 2.

[0027] In step S6, the signal terminal 4 and the IGBT 2A are connected by the metal wire 5.

[0028] In step S7, the upper surface of the insulating substrate 1, a portion of the inner leads 3, and the semiconductor element 2 are sealed with the sealing material 6. At this time, the tip of the second extending portion 3B is sealed with the sealing material 6 so as to be positioned inside the sealing material 6.

[0029] Thereafter, the tie bars 30 are cut and the inner leads 3 are separated from the lead frame 31 and molded. Through the above steps, the semiconductor device 101 is completed. Figure 6 is a cross-sectional view showing the configuration of the completed semiconductor device 101.

[0030] The cantilevered inner lead described in Patent Document 1 has a bent portion formed by press working. Because metal has an elastic region and a plastic region, the cantilevered inner lead is not perfectly parallel to the lead frame due to the effect of springback during press working. Therefore, the cantilevered inner lead is prone to variations in height.

[0031] In contrast, the semiconductor device 101 of the first embodiment includes, in plan view, second extending portions 3B that branch off from both sides of the first extending portion 3A and protrude outside the insulating substrate 1. In the bonding process of the inner leads 3, the tips of the second extending portions 3B are supported by a lower jig 51. This significantly reduces variations in the height direction of the inner leads 3.

[0032] When the insulating substrate 1 is heated to the soldering temperature, warping of approximately 100 μm to 300 μm occurs due to differences in the pattern shapes of the upper surface conductor layer 12 and the lower surface conductor layer 13. Even when such warping occurs in the insulating substrate 1, the height of the inner leads 3 remains stable, so the distance between the semiconductor element 2 and the bonding portion 3D of the inner leads 3 also remains stable. As a result, the thickness of the bonding material 7B also remains stable, meaning that soldering can be performed at the desired dimensions.

[0033] FIG. 7 is a graph showing the relationship between the longitudinal position and height of the insulating substrate 1 before heating or after cooling. FIG. 8 is a graph showing the relationship between the longitudinal position and height of the insulating substrate 1 during heating. The insulating substrate 1 may have a second side surface 1B that extends in a different direction from the first side surface 1A and has a length longer than the first side surface 1A in a plan view. As shown in FIGS. 7 and 8 , the lower surface of the insulating substrate 1 contacts the lower jig 51 near the longitudinal center of the insulating substrate 1, which is the central portion of the second side surface 1B divided into three parts in a plan view. This makes the insulating substrate less susceptible to temperature rises and falls during soldering. When the inner leads 3 are supported near the longitudinal center of the insulating substrate 1, as the warpage of the insulating substrate 1 decreases due to a temperature drop after solidification, the inner leads 3, which have lower rigidity than the insulating substrate 1, deform, and residual stress is uniformly generated in the bonding material 7B at every joint. On the other hand, if the inner leads 3 are supported at a position other than near the longitudinal center of the insulating substrate 1, deformation of the inner leads 3 due to temperature drop may cause high residual stress to remain in one area depending on the order in which the solder solidifies. Note that, because the order in which the solder solidifies cannot be controlled, there is a concern that this may affect the reliability of the semiconductor device 101.

[0034] If the thickness of the bonding material 7B is excessively large, problems such as an increase in inductance and an insufficient wettable area between the bonding material 7B and the inner lead 3 may occur. On the other hand, if the thickness of the bonding material 7B is too small, problems such as a decrease in reliability and short circuit defects due to the bonding material 7B protruding may occur. The semiconductor device 101 prevents the occurrence of problems caused by the difference in the thickness of the bonding material 7B.

[0035] In the first embodiment, the tip of the second extension portion 3B is contained inside the sealing material 6. In this configuration, compared to a configuration in which the tip of the second extension portion 3B protrudes outside the sealing material 6, it is possible to shorten the creepage distance, thereby realizing a more compact semiconductor device 101. Furthermore, if the tip of the second extension portion 3B protrudes outside the sealing material 6, a complex design regarding the creepage discharge distance and the space discharge distance is required, which increases the number of design steps. On the other hand, in the semiconductor device 101, such a design is easy, making it possible to reduce the number of design steps.

[0036] In summary, the semiconductor device 101 in the first embodiment includes an insulating substrate 1, a semiconductor element 2, and an inner lead 3. The insulating substrate 1 includes a first side surface 1A and a second side surface 1B extending in a different direction from the first side surface 1A. The semiconductor element 2 is held by the insulating substrate 1. The inner lead 3 is electrically connected to the semiconductor element 2. The inner lead 3 includes a first extension portion 3A and a second extension portion 3B. In a plan view, the first extension portion 3A extends from the outside toward the inside of the first side surface 1A of the insulating substrate 1. In a plan view, the second extension portion 3B includes a tip branching from the first extension portion 3A and extending toward the second side surface 1B of the insulating substrate 1. In a plan view, the tip of the second extension portion 3B is located outside the second side surface 1B of the insulating substrate 1.

[0037] Another semiconductor device 101 according to the first embodiment includes an insulating substrate 1, a semiconductor element 2, and an inner lead 3. The insulating substrate 1 includes a first side surface 1A and a second side surface 1B that, in a plan view, extends in a different direction from the first side surface 1A and has a length longer than the first side surface 1A. The semiconductor element 2 is held by the insulating substrate 1. The inner lead 3 is electrically connected to the semiconductor element 2. The inner lead 3 includes a first extension portion 3A and a second extension portion 3B. In a plan view, the first extension portion 3A extends from the outside toward the inside of the first side surface 1A of the insulating substrate 1. In a plan view, the second extension portion 3B includes a tip that branches from the first extension portion 3A and extends toward the center of the second side surface 1B of the insulating substrate 1. The tip of the second extension portion 3B is located outside the second side surface 1B of the insulating substrate 1. The vicinity of the center of the second side surface 1B of the insulating substrate 1 refers to the central portion of the third portion of the second side surface 1B when viewed from above.

[0038] This configuration stabilizes the distance between the inner lead 3 and the semiconductor element 2. This improves the reliability of the semiconductor device 101. It also makes it possible to use an insulating substrate 1 that is prone to warping due to heat, thereby achieving a smaller size and lower thermal resistance of the semiconductor device 101. The semiconductor device 101 is useful, for example, in power generation and transmission technologies, as well as efficient energy utilization and regeneration technologies.

[0039] The insulating substrate 1 may be formed of alumina (Al2O3) or aluminum nitride (AlN). The upper conductor layer 12 and the lower conductor layer 13 may be made of Al with a surface treatment such as Ni. The semiconductor element 2 may be made of Si or a wide-gap semiconductor such as SiC or GaN. The semiconductor element 2 may also be a metal oxide semiconductor field effect transistor (MOSFET). Alternatively, the semiconductor element 2 may be a reverse-conducting IGBT (RC-IGBT) in which an IGBT 2A and a freewheeling diode are formed within a single semiconductor substrate. The composition of the solder used as the bonding materials 7A, 7B, and 7C is not limited to Sn-3Ag-0.5Cu. The bonding material 7A may be a sintered material containing Ag or Cu. The metal wire 5 is not limited to Al and may be made of any wire-bondable metal, such as Cu, Au, or Ag.

[0040] 1, the second extending portion 3B protrudes on both sides of the first extending portion 3A in the extending direction. However, the second extending portion 3B may protrude only on one side. The second extending portion 3B also extends toward the second side surface 1B of the insulating substrate 1. However, when the planar shape of the insulating substrate 1 is close to a square, such as when the ratio of the long side to the short side is 1:1.2 or less, the extending direction of the first extending portion 3A and the extending direction of the second extending portion 3B may be reversed.

[0041] In the manufacturing method of the semiconductor device 101 of the first embodiment, the bonding process between the semiconductor element 2 and the upper surface conductor layer 12 is performed in a step different from the bonding process between the semiconductor element 2 and the inner leads 3. However, these bonding processes may be performed simultaneously by a single heating.

[0042] The semiconductor device 101 may be a 6-in-1 module or an IPM (Intelligent Power Module) having a drive circuit and a self-protection function.

[0043] 9 and 10 are cross-sectional views showing the bonding process between the inner lead 3 and the semiconductor element 2. The insulating substrate 1 is warped due to heating. In FIG. 9, the left and right ends of the insulating substrate 1 are at the same height. As shown in FIG. 10, when the upper surface conductor layer 12 includes an asymmetric pattern, the point where the lower surface of the insulating substrate 1 contacts the lower jig 51 is offset from the center, resulting in a difference in the height of the left end and the right end of the insulating substrate 1. The inner lead 3 and the insulating substrate 1 are not parallel. If cooling is performed in this state, a larger gap will be created at the right end than at the left end, as shown in region B in FIG. 10. During the sealing process, the sealing material 6 will find its way into the back surface conductor layer through the gap, hindering the heat dissipation of the semiconductor device.

[0044] 11 is a cross-sectional view showing a state of a bonding process in the manufacturing method of the semiconductor device 102 in the embodiment 2. In the embodiment 2, the attitude control jig 53 is mounted in step S4 shown in FIG.

[0045] The posture control jig 53 includes a plate 53A and four protrusions 53B each extending downward from the plate 53A. In the second embodiment, the protrusions 53B are supports. The distances from the plate 53A to the tips of the protrusions 53B are the same. The four protrusions 53B are integrated with one another at a position higher than the inner leads 3.

[0046] In step S4, upper jig 52 presses the tip of second extension 3B, and protrusions 53B of attitude control jig 53 press the four corners of insulating substrate 1. In step S5, semiconductor device 102 is heated with attitude control jig 53 pressing insulating substrate 1, and bonding portions 3D of inner leads 3 are bonded to the upper surfaces of IGBT 2A and diode 2B, respectively. The other steps are the same as those in the first embodiment.

[0047] The manufacturing method using the posture control jig 53 as described above maintains the insulating substrate 1 and inner leads 3 in a parallel state during heating. As a result, the sealing material 6 is prevented from wrapping around in step S7. Furthermore, since the height of the inner leads 3 is fixed by the second extending portions 3B, the thicknesses of the bonding materials 7B and 7C can be controlled with high precision at all bonding locations.

[0048] The number of protrusions 53B is not limited to four, but may be any number equal to or greater than three. The upper jig 52 and the attitude control jig 53 may be integrated into one jig.

[0049] Third Preferred Embodiment FIG. 12 is a cross-sectional view showing a state of a bonding process in a manufacturing method of a semiconductor device 103 according to a third preferred embodiment.

[0050] The lower jig 51 includes four support portions 51A provided at the four corners of the surface facing the lower surface of the insulating substrate 1. The support portions 51A are steps formed by cutting. The four support portions 51A support the lower surface of the insulating substrate 1 at four locations other than the center.

[0051] 3, insulating substrate 1 is heated while being supported by support portions 51A at the four corners of lower jig 51. Here, insulating substrate 1 is supported only by support portions 51A. This heating bonds bonding portions 3D of inner leads 3 to the upper surfaces of IGBT 2A and diode 2B, respectively. Other steps are the same as those in the first embodiment.

[0052] The manufacturing method using the lower jig 51 as described above maintains the insulating substrate 1 and inner leads 3 in a parallel state during heating. As a result, the sealing material 6 is prevented from wrapping around in step S7. Furthermore, since the height of the inner leads 3 is fixed by the second extending portions 3B, the thicknesses of the bonding materials 7B and 7C can be controlled with high precision at all bonding locations.

[0053] Taking into consideration warping of the insulating substrate 1, the support portion 51A preferably has a height such that no part other than the support portion 51A comes into contact with the insulating substrate 1. For example, a through hole may be provided in the bottom surface of the lower jig 51, and the support portion 51A may be formed by a step provided on the edge of the through hole.

[0054] The number of support portions 51A is not limited to four, and may be three or more as long as parallelism between the inner leads 3 and the insulating substrate 1 is ensured. In other words, it is sufficient that at least three support portions 51A support the three locations on the lower surface of the insulating substrate 1 other than the central portion.

[0055] Fourth Embodiment FIG. 13 is a functional block diagram showing the configuration of a power conversion system according to a fourth embodiment.

[0056] The power conversion system includes a power source 100 , a power conversion device 200 , and a load 300 .

[0057] The power supply 100 is a DC power supply. The power supply 100 supplies DC power to the power conversion device 200. The power supply 100 is, for example, a DC system, a solar cell, a storage battery, or the like. The power supply 100 may be a DC / DC converter that converts DC power output from a DC system into predetermined power. The power supply 100 may also be a rectifier circuit connected to an AC system, an AC / DC converter, or the like.

[0058] The power conversion device 200 is connected between the power supply 100 and the load 300. The power conversion device 200 in the fourth embodiment is a three-phase inverter. The power conversion device 200 converts DC power supplied from the power supply 100 into AC power. The power conversion device 200 supplies the AC power to the load 300.

[0059] The load 300 is driven by AC power supplied from the power conversion device 200. The load 300 in the fourth embodiment is a three-phase motor. The three-phase motor is not limited to a specific application. The three-phase motor is mounted in various electrical devices. For example, the three-phase motor is mounted in hybrid vehicles, electric vehicles, railroad cars, elevators, air conditioning equipment, and the like.

[0060] The following describes in detail the power conversion device 200. The power conversion device 200 includes a main conversion circuit 201 and a control circuit 203.

[0061] The main conversion circuit 201 includes at least one semiconductor device 202 and a driver circuit (not shown). The semiconductor device 202 corresponds to the semiconductor device shown in any one of the first to third embodiments.

[0062] The semiconductor device 202 forms a two-level three-phase full-bridge circuit (not shown). The three-phase full-bridge circuit includes six switching elements (not shown) and six freewheeling diodes (not shown). At least one of the switching elements and freewheeling diodes corresponds to the semiconductor element 2 shown in any one of the first to third embodiments.

[0063] The three-phase full-bridge circuit includes three upper arms and three lower arms. Each of the upper arms and lower arms includes one switching element and one freewheeling diode connected in anti-parallel to the switching element. The switching element included in one upper arm is connected in series to the switching element included in one lower arm, forming a pair of upper and lower arms. In other words, the three-phase full-bridge circuit includes three pairs of upper and lower arms. The three pairs of upper and lower arms correspond to the U phase, V phase, and W phase of the three-phase full-bridge circuit, respectively. The output terminals of the three pairs of upper and lower arms, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0064] The main conversion circuit 201 converts DC power supplied from the power supply 100 into AC power by the switching operation of the switching elements. The main conversion circuit 201 supplies the AC power to the load 300 via the output terminals.

[0065] The drive circuit may be built into the semiconductor device 202 or may be provided separately from the semiconductor device 202. The drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 in accordance with a control signal output from the control circuit 203. The drive circuit supplies the drive signal to the control electrode of the switching element of the semiconductor device 202.

[0066] The drive signal is a signal for turning on a switching element or a signal for turning off a switching element. More specifically, when a switching element is maintained in an on state, the drive signal is a voltage signal (on signal) that is equal to or greater than the threshold voltage of the switching element. When a switching element is maintained in an off state, the drive signal is a voltage signal (off signal) that is smaller than the threshold voltage of the switching element.

[0067] The control circuit 203 outputs a control signal to the drive circuit for controlling the drive circuit. The control circuit 203 calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300, and generates the control signal. In other words, the control circuit 203 generates a control signal so that the main conversion circuit 201 is PWM-controlled. The control circuit 203 outputs a control signal to the drive circuit so that the drive circuit outputs an on signal to a switching element that should be in the on state, and an off signal to a switching element that should be in the off state. In this way, the control circuit 203 controls the switching elements of the main conversion circuit 201 so that a predetermined power is supplied to the load 300.

[0068] In such a power conversion device 200, the semiconductor device shown in any one of the first to third embodiments is applied to the main conversion circuit 201, thereby achieving improved reliability.

[0069] In the fourth embodiment, an example has been shown in which the power conversion device 200 is a two-level three-phase inverter, but the configuration of the power conversion device 200 is not limited thereto. For example, the power conversion device 200 may be a multi-level power conversion device, such as a three-level power conversion device. Alternatively, the power conversion device 200 may be a single-phase inverter for supplying power to a single-phase load. When the load 300 is a DC load, the power conversion device 200 may be a DC / DC converter or an AC / DC converter. When the load 300 is a solar power generation system, a power storage system, or the like, the power conversion device 200 may be a power conditioner.

[0070] Although the fourth embodiment has been described with reference to an example in which the load 300 is a three-phase motor, the configuration of the load 300 is not limited to this. For example, the load 300 may be an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system.

[0071] Although the present disclosure has been described in detail, the above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned.

[0072] In the present disclosure, the embodiments can be freely combined, and the embodiments can be modified or omitted as appropriate.

[0073] Various aspects of the present disclosure are summarized below as appendices.

[0074] (Supplementary Note 1) A semiconductor device comprising: an insulating substrate including a first side surface and a second side surface, in a plan view, extending in a different direction from the first side surface and having a length longer than a length of the first side surface; a semiconductor element held on the insulating substrate; an inner lead electrically connected to the semiconductor element; and a sealing material that seals a portion of the inner lead and the semiconductor element, wherein the inner lead, in a plan view, includes: a first extension portion that extends from the outside to the inside of the first side surface of the insulating substrate; and a second extension portion that includes a tip that branches from the first extension portion and extends toward the center of the second side surface of the insulating substrate, and the tip of the second extension portion is located outside the second side surface of the insulating substrate in a plan view.

[0075] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the tip of the second extending portion is located inside the sealing material.

[0076] (Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or Supplementary Note 2, wherein a length from the first extending portion to the tip of the second extending portion is equal to or greater than a thickness of the inner lead.

[0077] (Supplementary Note 4) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 3, wherein the width of the second extending portion is equal to or greater than the thickness of the inner lead.

[0078] (Supplementary Note 5) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 4, wherein the vicinity of the center of the second side surface of the insulating substrate is a central portion of one of three parts obtained by dividing the second side surface in a plan view.

[0079] (Supplementary Note 6) A power conversion device including: a main conversion circuit including the semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 5, which converts and outputs power input from a power supply; and a control circuit which outputs a control signal to the main conversion circuit for controlling the main conversion circuit.

[0080] (Appendix 7) A method for manufacturing a semiconductor device, comprising: a step of preparing a semiconductor element held on an insulating substrate including, in a plan view, a first side surface and a second side surface that extends in a different direction from the first side surface and has a length longer than a length of the first side surface; a step of electrically connecting an inner lead including a first extension portion and a second extension portion to the semiconductor element; and a step of encapsulating a portion of the inner lead and the semiconductor element with an encapsulant, wherein in the step of electrically connecting the inner lead to the semiconductor element, the first extension portion of the inner lead is arranged to extend from the outside to the inside of the first side surface of the insulating substrate in a plan view, and a tip of the second extension portion of the inner lead is arranged to branch from the first extension portion and extend toward the center of the second side surface of the insulating substrate in a plan view, and is positioned outside the second side surface of the insulating substrate.

[0081] (Supplementary Note 8) The method for manufacturing a semiconductor device according to Supplementary Note 7, wherein the tip of the second extension portion is located inside the sealing material.

[0082] (Appendix 9) A method for manufacturing a semiconductor device according to Appendix 7 or Appendix 8, wherein the step of electrically connecting the inner lead to the semiconductor element includes the steps of: mounting the insulating substrate on a lower jig; mounting a lead frame including the inner lead on the lower jig so that the tip of the second extension portion is supported by the lower jig; holding the tip of the second extension portion with an upper jig; and joining the joint portion of the inner lead to the top surface of the semiconductor element.

[0083] (Appendix 10) A method for manufacturing a semiconductor device according to Appendix 9, wherein the step of pressing the tip of the second extension portion with the upper jig includes three or more protrusions pressing the insulating substrate, and the three or more protrusions are integrated with each other at a position higher than the inner lead.

[0084] (Appendix 11) A method for manufacturing a semiconductor device according to Appendix 9 or Appendix 10, wherein the step of mounting the insulating substrate on the lower jig includes three or more support portions of the lower jig each supporting three or more locations other than the center of the underside of the insulating substrate, and not supporting the center.

[0085] 1 insulating substrate, 1A first side surface, 1B second side surface, 2 semiconductor element, 2A IGBT, 2B diode, 3 inner lead, 3A first extension portion, 3B second extension portion, 3C terminal portion, 3D bonding portion, 4 signal terminal, 5 metal wire, 6 sealing material, 7A bonding material, 7B bonding material, 7C bonding material, 8 lead, 11 substrate, 12 upper conductor layer, 13 lower conductor layer, 30 tie bar, 31 lead frame, 51 lower jig, 51A support portion, 52 upper jig, 53 attitude control jig, 53A plate material, 53B protrusion portion, 100 power supply, 101 to 103 semiconductor device, 200 power conversion device, 201 main conversion circuit, 202 semiconductor device, 203 control circuit, 300 load.

Claims

1. A semiconductor device comprising: an insulating substrate including a first side surface and a second side surface, in a plan view, extending in a different direction from the first side surface and having a length longer than that of the first side surface; a semiconductor element held by the insulating substrate; an inner lead electrically connected to the semiconductor element; and an encapsulant that encapsulates a portion of the inner lead and the semiconductor element, wherein the inner lead, in a plan view, includes: a first extension portion that extends from the outside to the inside of the first side surface of the insulating substrate; and a second extension portion that includes a tip that branches from the first extension portion and extends toward the center of the second side surface of the insulating substrate, and the tip of the second extension portion is located outside the second side surface of the insulating substrate in a plan view.

2. The semiconductor device according to claim 1, wherein the tip of the second extension portion is located inside the sealing material.

3. The semiconductor device according to claim 1 or 2, wherein the length from said first extending portion to said tip of said second extending portion is equal to or greater than the thickness of said inner lead.

4. The semiconductor device according to any one of claims 1 to 3, wherein the width of said second extending portion is equal to or greater than the thickness of said inner lead.

5. The semiconductor device according to any one of claims 1 to 4, wherein the vicinity of the center of the second side surface of the insulating substrate is a central portion of one of three parts of the second side surface when viewed from above.

6. A power conversion device comprising: a main conversion circuit that includes the semiconductor device according to any one of claims 1 to 5 and converts and outputs power input from a power source; and a control circuit that outputs a control signal to the main conversion circuit for controlling the main conversion circuit.

7. A method for manufacturing a semiconductor device, comprising: a step of preparing a semiconductor element held on an insulating substrate including, in a plan view, a first side surface and a second side surface that extends in a different direction from the first side surface and has a length longer than that of the first side surface; a step of electrically connecting an inner lead including a first extension portion and a second extension portion to the semiconductor element; and a step of encapsulating a portion of the inner lead and the semiconductor element with an encapsulant, wherein in the step of electrically connecting the inner lead to the semiconductor element, the first extension portion of the inner lead is arranged to extend from the outside to the inside of the first side surface of the insulating substrate in a plan view, and the tip of the second extension portion of the inner lead is arranged to branch from the first extension portion and extend toward the center of the second side surface of the insulating substrate in a plan view, and is positioned outside the second side surface of the insulating substrate.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the tip of the second extension portion is located inside the sealing material.

9. A method for manufacturing a semiconductor device as described in claim 7 or claim 8, wherein the step of electrically connecting the inner lead to the semiconductor element includes the steps of: mounting the insulating substrate on a lower jig; mounting a lead frame including the inner lead on the lower jig so that the tip of the second extension portion is supported by the lower jig; holding the tip of the second extension portion with an upper jig; and joining the joint portion of the inner lead to the top surface of the semiconductor element.

10. A method for manufacturing a semiconductor device as described in claim 9, wherein the step of pressing the tip of the second extension portion with the upper jig includes three or more protrusions pressing the insulating substrate, and the three or more protrusions are integrated with each other at a position higher than the inner lead.

11. A method for manufacturing a semiconductor device as described in claim 9 or claim 10, wherein the step of mounting the insulating substrate on the lower jig includes three or more support portions of the lower jig each supporting three or more locations other than the center of the underside of the insulating substrate, and not supporting the center.