Semiconductor device
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Filing Date
- 2025-01-17
- Publication Date
- 2025-09-18
AI Technical Summary
Existing resistive elements for semiconductor modules, such as intelligent power modules, cannot be directly applied as gate resistors due to the inclusion of capacitance, leading to increased mounting area requirements.
A semiconductor device is designed with a resistive layer and a capacitor integrated on a single chip, where the resistive layer is connected in parallel with a lower-layer insulating film acting as a dielectric, allowing for a resistor and capacitor to be integrated into a single chip.
This integration reduces the packaging size of semiconductor modules by combining resistors and capacitors on a single chip, facilitating easy specification changes and reducing the overall module size.
Abstract
Description
Semiconductor Devices
[0001] The present disclosure relates to semiconductor devices.
[0002] Patent Document 1 discloses a resistor element comprising a first external connection electrode provided on the upper surface side of a chip, a second external connection electrode spaced apart from the first external connection electrode and provided in parallel to the first external connection electrode, and a protective film covering the first and second external connection electrodes and having a first opening and a second opening that expose a portion of the upper surfaces of the first and second external connection electrodes, respectively, and further discloses that the resistor element may have a horizontal structure.
[0003] Patent Document 2 discloses a resistance element including: a lower insulating film; a resistance layer provided on the lower insulating film; a resistance layer protection element provided on the lower insulating film in parallel to one sidewall surface of the resistance layer, and having a pn junction formed by an alternating arrangement of n-type bands made of n-type layers and p-type bands made of p-type layers connected in series; an interlayer insulating film provided to cover the resistance layer and the resistance layer protection element; external connection electrodes provided on the interlayer insulating film and electrically connected to one terminal of the resistance layer and one terminal of the resistance layer protection element, respectively; and external connection electrodes provided on the interlayer insulating film and electrically connected to the other terminal of the resistance layer and the other terminal of the resistance layer protection element, respectively; and it is further disclosed that the resistance element may have a horizontal structure.
[0004] JP 2020-98822 A JP 2020-98884 A
[0005] Consider a case where the resistive elements described in Patent Documents 1 and 2 are applied to the gate resistance of a switching element of a semiconductor module such as an intelligent power module (IPM) having a switching element and a control circuit that controls the switching element. In this case, not only a gate resistance but also a capacitance is connected between the gate of the switching element and the control circuit, so the resistive elements described in Patent Documents 1 and 2 cannot be applied as is. Furthermore, if the gate resistance and capacitance are configured as separate chips, there are problems such as an increase in the mounting area.
[0006] In view of the above problems, an object of the present disclosure is to provide a semiconductor device that can realize resistors and capacitors on a single chip.
[0007] One aspect of the present disclosure is summarized as a semiconductor device comprising: a semiconductor substrate; a lower-layer insulating film provided on an upper surface side of the semiconductor substrate; a resistive layer provided on the upper surface side of the lower-layer insulating film; an interlayer insulating film provided on the upper surfaces of the lower-layer insulating film and the resistive layer; a first surface electrode provided on the upper surface side of the interlayer insulating film and electrically connected to one end of the resistive layer; a second surface electrode provided on the upper surface side of the interlayer insulating film and spaced apart from the first surface electrode and electrically connected to the other end of the resistive layer; and a back surface electrode provided on the lower surface side of the semiconductor substrate, wherein a resistance formed by the resistive layer and a first capacitance having the lower-layer insulating film below the resistive layer as a dielectric are connected in parallel to the first surface electrode.
[0008] According to the present disclosure, it is possible to provide a semiconductor device that can realize a resistor and a capacitor on a single chip.
[0009] 9 is a plan view showing an example of a semiconductor device according to a first embodiment. FIG. 10 is a cross-sectional view taken along line A-A' in FIG. 1. FIG. 11 is a circuit diagram showing an equivalent circuit of the semiconductor device according to the first embodiment. FIG. 12 is a circuit diagram showing an application example of the semiconductor device according to the first embodiment. FIG. 13 is a cross-sectional view showing a semiconductor device according to a comparative example. FIG. 14 is a cross-sectional view with an equivalent circuit of the semiconductor device according to the comparative example added. FIG. 15 is a circuit diagram showing an equivalent circuit of the semiconductor device according to the comparative example. FIG. 16 is another circuit diagram showing an equivalent circuit of the semiconductor device according to the comparative example. FIG. 17 is a graph showing the relationship between impedance and frequency. FIG. 18 is a plan view showing an example of a semiconductor device according to a second embodiment. FIG. 19 is a cross-sectional view taken along line A-A' in FIG. 9. FIG. 19 is a cross-sectional view taken along line B-B' in FIG. 9. FIG. 19 is a plan view showing an example of a semiconductor device according to a third embodiment. FIG. 11 is a cross-sectional view taken along line A-A' in FIG. 12. FIG. 12 is a cross-sectional view taken along line B-B' in FIG.
[0010] First to third embodiments will be described below with reference to the drawings. In the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the first to third embodiments described below are intended to exemplify devices and methods for embodying the technical concept of the present disclosure, and the technical concept of the present disclosure does not specify the materials, shapes, structures, arrangements, etc. of the components described below.
[0011] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical idea of the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.
[0012] 1 shows a planar layout of a semiconductor device (semiconductor chip) according to a first embodiment. In this figure, the outlines of a lower insulating film 2 hidden under a protective film (passivation film) 7, a resistive layer 3, a pair of surface electrodes (external connection electrodes) 5 a, 5 b, and contacts (contact plugs) 6 a, 6 b are schematically shown by dashed lines.
[0013] The semiconductor device according to the first embodiment is a semiconductor chip having a substantially rectangular planar pattern with the longitudinal direction being the direction in which the surface electrodes 5 a, the resistive layer 3, and the surface electrodes 5 b are arranged (the horizontal direction in FIG. 1 ) and the lateral direction being the direction perpendicular to the direction in which the surface electrodes 5 a, the resistive layer 3, and the surface electrodes 5 b are arranged (the vertical direction in FIG. 1 ). The chip size of the semiconductor device according to the first embodiment is, for example, about 3.0 mm × 2.5 mm, but is not limited to this.
[0014] The lower insulating film 2 has a rectangular planar pattern whose longitudinal direction is the longitudinal direction of the semiconductor device according to the first embodiment (the left-right direction in FIG. 1 ). The resistive layer 3, which is located above the lower insulating film 2, is provided inside the outer shape of the lower insulating film 2. The resistive layer 3 has a rectangular planar pattern whose longitudinal direction is the longitudinal direction of the lower insulating film 2 (the left-right direction in FIG. 1 ).
[0015] The surface electrodes 5a and 5b, which are located above the resistive layer 3, are provided inside the outer shape of the lower insulating film 2 and sandwich the resistive layer 3. The surface electrodes 5a and 5b have a substantially rectangular planar pattern with the longitudinal direction being the short-side direction of the lower insulating film 2 (the vertical direction in FIG. 1 ). The surface electrode 5a is electrically connected to the resistive layer 3 via a plurality of contacts 6a at a position overlapping one longitudinal end of the resistive layer 3 located below the surface electrode 5a. The number and positions of the contacts 6a are not particularly limited. The surface electrode 5b is electrically connected to the resistive layer 3 via a plurality of contacts 6b at a position overlapping the other longitudinal end of the resistive layer 3 located below the surface electrode 5b. The number and positions of the contacts 6b are not particularly limited.
[0016] Approximately rectangular openings 7a and 7b are provided in the protective film 7. The opening 7a exposes a part of the upper surface of the surface electrode 5a as a pad region (effective connection region) connectable to an external connection means such as a bonding wire. The opening 7b exposes a part of the upper surface of the surface electrode 5b as a pad region (effective connection region) connectable to an external connection means such as a bonding wire.
[0017] Fig. 2 shows a cross section taken along line A-A', which passes through the resistive layer 3 and the surface electrodes 5a and 5b in Fig. 1. As shown in Fig. 2, the semiconductor device according to the first embodiment includes a semiconductor substrate 1, a lower insulating film (first insulating film) 2 provided on the upper surface side of the semiconductor substrate 1, and a resistive layer 3 provided on the upper surface side of the lower insulating film 2.
[0018] The thickness of the semiconductor substrate 1 is, for example, approximately 250 μm or more and 450 μm or less. A low resistivity substrate such as a silicon substrate doped with a high concentration of n-type impurities can be used as the semiconductor substrate 1. However, a silicon substrate doped with a high concentration of p-type impurities or a semiconductor substrate other than silicon may also be used as the semiconductor substrate 1.
[0019] The lower insulating film 2 is a silicon oxide film (SiO ２ film), silicon nitride film (Si ３ N ４In order to increase the capacitance value of a capacitance (also called a "capacitor") that uses the lower insulating film 2 as a dielectric, a Si film can be used as the lower insulating film 2. ３ N ４ SiO films etc. ２ A material having a higher dielectric constant than the film may be used. From the viewpoints of reliability and lifespan, a local oxidation film (LOCOS film) formed by a local oxidation of silicon (LOCOS) method may be used as the lower insulating film 2. An insulating film (TEOS film) formed by a chemical vapor deposition (CVD) method using tetraethoxysilane (TEOS) gas, an organosilicon compound, may be used as the lower insulating film 2.
[0020] The thickness of the lower insulating film 2 may be, for example, about 15 nm to 1000 nm, about 15 nm to 800 nm, about 15 nm to 500 nm, about 15 nm to 300 nm, or about 15 nm to 100 nm. Also, the thickness of the lower insulating film 2 may be about 50 nm to 1000 nm, about 50 nm to 800 nm, about 50 nm to 500 nm, about 50 nm to 300 nm, or about 50 nm to 100 nm.
[0021] The thinner the thickness of the lower insulating film 2, the larger the capacitance value of the capacitor using the lower insulating film 2 as a dielectric. From the viewpoint of increasing the capacitance value of the capacitor, the thickness of the lower insulating film 2 is preferably about 800 nm or less, more preferably about 500 nm or less, more preferably about 300 nm or less, and even more preferably about 100 nm or less. Furthermore, when the semiconductor device according to the first embodiment is applied to the gate resistor of an IGBT, which is a switching element, the thickness of the lower insulating film 2 is preferably about 15 nm or more from the viewpoint of ensuring a gate voltage of about ±15 V of the IGBT. Furthermore, from the viewpoints of reliability and lifespan, when designed similarly to the gate insulating film, the thickness of the lower insulating film 2 is preferably about 50 nm or more.
[0022] The larger the area of the lower insulating film 2 immediately below the resistive layer 3, the larger the capacitance value of the capacitor that uses the lower insulating film 2 as a dielectric. The area of the lower insulating film 2 immediately below the resistive layer 3 should be 1.5 mm to achieve a capacitance value of 1 nF or more. ２ It is preferable that the above amount is used.
[0023] The thickness of the resistive layer 3 is, for example, about 400 nm or more and 600 nm or less. The sheet resistance of the resistive layer 3 is, for example, about 100 Ω / □ or more and 200 Ω / □ or less. The resistance value of the resistive layer 3 can be controlled by adjusting the thickness of the resistive layer 3, the width of the resistive layer 3 in the depth direction in FIG. 2, the length of the resistive layer 3 in the left-right direction in FIG. 2, the material of the resistive layer 3, the connection positions of the resistive layer 3 and the contacts 6 a, 6 b, etc.
[0024] For example, polysilicon doped with n-type or p-type impurities (doped polysilicon) can be used as the resistance layer 3. Doped polysilicon can be formed by ion implanting n-type or p-type impurities into polysilicon, or by adding n-type or p-type impurities during deposition of polysilicon by chemical vapor deposition (CVD). The resistance value of the resistance layer 3 can be controlled by adjusting the dose during ion implantation into the resistance layer 3, the acceleration voltage, the heat treatment temperature, the heat treatment time, etc.
[0025] The resistive layer 3 is not limited to doped polysilicon, but may be made of tantalum nitride (TaN ｘ The resistive layer 3 may be a film of a nitride of a transition metal such as chromium (Cr), nickel (Ni), or manganese (Mn), or a laminated film of high-melting-point metal films laminated in this order. ２ ) may also be used.
[0026] An interlayer insulating film (second insulating film) 4 is provided on the upper surface of the lower insulating film 2 and the resistance layer 3 so as to cover the lower insulating film 2 and the resistance layer 3. The thickness of the interlayer insulating film 4 is, for example, about 1 μm or more and 2 μm or less. The interlayer insulating film 4 is a silicon oxide film (SiO ) that does not contain phosphorus (P) or boron (B), which is called an "NSG film." ２film), silicon oxide film doped with phosphorus (PSG film), silicon oxide film doped with boron (BSG film), silicon oxide film doped with phosphorus and boron (BPSG film), or silicon nitride film (Si ３ N ４ A single layer membrane of the above-mentioned membranes or a composite membrane in which a plurality of types of these membranes are selected and combined can be used.
[0027] A pair of surface electrodes 5a, 5b are provided spaced apart from each other on the upper surface of the interlayer insulating film 4. The surface electrode 5a is located above the lower insulating film 2 and overlaps one longitudinal end of the resistive layer 3 in the depth direction. The surface electrode 5a is electrically connected to one longitudinal end of the resistive layer 3 via a contact 6a embedded in a contact hole provided in the interlayer insulating film 4. The surface electrode 5b is located above the lower insulating film 2 and overlaps the other longitudinal end of the resistive layer 3 in the depth direction. The surface electrode 5b is electrically connected to the other longitudinal end of the resistive layer 3 via a contact 6b embedded in a contact hole provided in the interlayer insulating film 4. The semiconductor device according to the first embodiment forms a resistor with a lateral structure, with a current path passing through the surface electrode 5a, the contact 6a, the resistive layer 3, the contact 6b, and the surface electrode 5b.
[0028] The thickness of the surface electrodes 5a, 5b is, for example, about 1 μm or more and 5 μm or less. The surface electrodes 5a, 5b can be formed, for example, from a laminated film of titanium / titanium nitride (Ti / TiN) as a barrier metal, aluminum-silicon (Al-Si), and TiN / Ti as an anti-reflection film. Instead of Al-Si, Al or an Al alloy such as Al-Si-copper (Cu) or Al-Cu may be used.
[0029] A protective film 7 is disposed on the upper surface side of the interlayer insulating film 4 and the surface electrodes 5a and 5b. The protective film 7 is not particularly limited as long as it is an insulating film. For example, a TEOS film, a Si ３ N ４ The protective film 7 can be made of a composite film in which a polyimide film and a polyimide film are laminated in this order. Openings 7a and 7b are provided in the protective film 7. The portions of the surface electrodes 5a and 5b exposed from the openings 7a and 7b become pad regions (electrode pads) to which bonding wires (not shown) such as aluminum (Al) can be connected.
[0030] A back electrode (third electrode) 9, which is an external connection electrode, is disposed on the underside of the semiconductor substrate 1. The back electrode 9 can be formed, for example, of a single-layer film made of gold (Au) or a metal film laminated in this order of titanium (Ti), nickel (Ni), and gold (Au). The outermost layer of the back electrode 9 can be formed of a solderable material. In the semiconductor device according to the first embodiment, a capacitance is formed with the resistive layer 3 as one electrode, the lower insulating film 2 below (directly below) the resistive layer 3 as a dielectric (insulator), and the semiconductor substrate 1 and the back electrode 9 as the other electrode. In FIG. 2, a resistance R1 formed by the resistive layer 3 and a capacitance C1 with the lower insulating film 2 as a dielectric are schematically shown by circuit symbols.
[0031] Fig. 3 shows an equivalent circuit of the semiconductor device according to the first embodiment shown in Fig. 1 and Fig. 2. One end of a resistor R1 and one end of a capacitor C1 are connected to a terminal T1 corresponding to the front surface electrode 5a shown in Fig. 1 and Fig. 2. The other end of the resistor R1 is connected to a terminal T2 corresponding to the front surface electrode 5b shown in Fig. 1 and Fig. 2. The other end of the capacitor C1 is connected to a terminal T3 corresponding to the back surface electrode 9 shown in Fig. 1 and Fig. 2.
[0032] <Method of Manufacturing Semiconductor Device> Next, an example of a method of manufacturing a semiconductor device according to the first embodiment will be described with reference to Figures 1 and 2. Note that the manufacturing method described below is just one example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be implemented within the scope of the spirit of the claims.
[0033] First, a semiconductor substrate 1 such as a silicon substrate doped with a high concentration of n-type impurities is prepared. Next, a lower insulating film 2 is formed on the upper surface of the semiconductor substrate 1 by a method such as LOCOS. Then, if necessary, a portion of the outer periphery of the lower insulating film 2 is selectively removed by photolithography, dry etching, or the like.
[0034] Next, the resistive layer 3 is formed on the upper surfaces of the semiconductor substrate 1 and the lower insulating film 2 by CVD, ion implantation, etc. Then, a portion of the outer periphery of the resistive layer 3 is selectively removed by photolithography, dry etching, etc.
[0035] Next, the interlayer insulating film 4 is deposited by CVD or the like on the upper surfaces of the lower insulating film 2 and the resistive layer 3. Then, a portion of the interlayer insulating film 4 is selectively removed by photolithography, dry etching, or the like to open a contact hole in the interlayer insulating film 4.
[0036] Next, a metal film is deposited by vacuum deposition, sputtering, or the like so as to fill the contact holes, and then, by photolithography, dry etching, or the like, portions of the metal film are selectively removed to form surface electrodes 5 a and 5 b on the upper surface of the interlayer insulating film 4.
[0037] Next, a protective film 7 is formed on the upper surfaces of the interlayer insulating film 4 and the surface electrodes 5a and 5b. Then, portions of the protective film 7 are selectively removed by photolithography, dry etching, or the like to form openings 7a and 7b in the protective film 7.
[0038] Next, if necessary, the semiconductor substrate 1 is ground from the lower surface side to adjust the thickness of the semiconductor substrate 1. Then, a back surface electrode 9 is formed on the lower surface side of the semiconductor substrate 1 by a vacuum deposition method, a sputtering method, or the like. Note that a large number of chip regions having the same configuration as the semiconductor device according to the first embodiment shown in FIGS. 1 and 2 are formed as a matrix on a single wafer, and these chip regions are separated by dicing into chips of the semiconductor device according to the first embodiment shown in FIGS.
[0039] 4 shows an example in which the semiconductor device according to the first embodiment is applied to a semiconductor module 10 that drives a motor 30. The semiconductor module 10 may be an intelligent power module (IPM). The semiconductor module 10 includes switching elements S1 to S6, a high-voltage integrated circuit (HVIC) 11, and a low-voltage integrated circuit (LVIC) 12 as control circuits (driver ICs) that control (drive) the switching elements S1 to S6. The switching elements S1 to S6 may be, for example, insulated gate bipolar transistors (IGBTs) or metal oxide semiconductor field effect transistors (MOSFETs). The semiconductor module 10 includes a motor 30, a DC power supply V ＤＣ, a current detection resistor Rdet, power supply capacitors CB(U), CB(V), CB(W), a signal power supply Vcc, and a controller 20 are connected.
[0040] The motor 30 is a three-phase motor and is connected to output terminals U, V, and W of three half-bridge circuits. The positive electrode of the DC power supply VDC is connected to the positive DC terminal P of the three half-bridge circuits. The negative electrode of the DC power supply VDC is connected to the negative DC terminals N(U), N(V), and N(W) of the three half-bridge circuits via current detection resistors Rdet. With the above connections, the semiconductor module 10 receives DC power from the DC power supply VDC via the positive DC terminal P and the negative DC terminals N(U), N(V), and N(W), and supplies power to the motor 30 via the output terminals U, V, and W.
[0041] The power supply capacitors CB(U), CB(V), and CB(W) are used as gate drive power supplies for the high-potential side switching elements S1, S2, and S3. One of the pair of terminals of the power supply capacitor CB(U) is connected to the gate power supply terminal V ＢＵ and the other terminal is connected to the reference potential terminal V Ｓ２Ｕ One of the pair of terminals of the power supply capacitor CB(V) is connected to the gate power supply terminal V ＢＶ and the other terminal is connected to the reference potential terminal V Ｓ２Ｖ One of the pair of terminals of the power supply capacitor CB(W) is connected to the gate power supply terminal V ＢＷ and the other terminal is connected to the reference potential terminal V Ｓ２Ｗ is connected to.
[0042] The positive terminal of the signal power supply Vcc is connected to the signal power supply terminal V ＣＣＨ and signal power terminal V ＣＣＬ The negative pole of the signal power supply Vcc is connected to the common terminal COM and the ground terminal GND of the controller 20. ＣＣＨ and the gate power supply terminal V ＢＵ , V ＢＶ , V ＢＷ Each of these refers to the signal power supply terminal V ＣＣＨvia a bootstrap diode (BSD) 13. This allows power from the signal power supply Vcc to charge each of the power supply capacitors CB(U), CB(V), and CB(W).
[0043] The controller 20 is a microprocessing unit (MPU) for pulse width modulation (PWM) control. The controller 20 is connected to a signal input terminal U ＩＮＨ , V ＩＮＨ , W ＩＮＨ , common terminal COM, signal input terminal U ＩＮＬ , V ＩＮＬ , W ＩＮＬ and connected to the current detection terminal IS.
[0044] The controller 20 is connected to a signal input terminal U ＩＮＨ , V ＩＮＨ , W ＩＮＨ and signal input terminal U ＩＮＬ , V ＩＮＬ , W ＩＮＬ The PWM signal input to each of the signal input terminals U is output. ＩＮＨ , V ＩＮＨ , W ＩＮＨ The PWM signal input to the signal input terminal U is input to the HVIC 11. ＩＮＬ , V ＩＮＬ , W ＩＮＬ The PWM signals input to the HVIC 11 and the LVIC 12 are input to the LVIC 12. Based on the input PWM signals, the HVIC 11 and the LVIC 12 output signals to the output terminals U1 and U2 that change the gate potentials of the corresponding switching elements S1 to S6. ＯＵＴ , V ＯＵＴ , W ＯＵＴ As a result, the switching elements S1 to S6 are switched on and off based on the PWM signal from the controller 20.
[0045] The semiconductor module 10 detects the current flowing through each phase of the three half-bridge circuits based on the resistance value of the current detection resistor Rdet, and protects the semiconductor module 10 from damage when an overcurrent occurs. A current level signal corresponding to a change in the resistance value of the current detection resistor Rdet is input to the LVIC 12 via the current detection terminal IS and also to the controller 20. The LVIC 12 determines whether an overcurrent has occurred based on the result of comparing the current level signal with a reference value, and if an overcurrent has occurred, shuts off the current in the LVIC 12. The controller 20 also determines whether an overcurrent has occurred based on the result of comparing the current level signal with the reference value, and if an overcurrent has occurred, shuts off the current in the HVIC 11.
[0046] HVIC11 output terminal U ＯＵＴ A resistor R11 is connected between the output terminal U of the HVIC 11 and the gate of the switching element S1. ＯＵＴ A capacitor C11 is connected between one end of the resistor R11 and the output terminal U. The resistor R11 and the capacitor C11 are configured on one semiconductor chip 41 corresponding to the semiconductor device according to the first embodiment shown in FIGS. 1 and 2. The resistor R11 functions as a gate resistor, for example, to suppress oscillation when the switching element S1 is short-circuited. Resistors R12 to R16, which will be described later, have the same function as the resistor R11. The capacitor C11 has the function of protecting the gate voltage of the switching element S1 from jumping up and the function of controlling the turn-on time. The capacitors C12 to C16, which will be described later, have the same function as the capacitor C11.
[0047] HVIC11 output terminal V ＯＵＴ A resistor R12 is connected between the output terminal V of the HVIC 11 and the gate of the switching element S2. ＯＵＴ A capacitor C12 is connected between one end of the resistor R12 and the output terminal V. The resistor R12 and the capacitor C12 are configured on one semiconductor chip 42 corresponding to the semiconductor device according to the first embodiment shown in FIGS.
[0048] HVIC11 output terminal W ＯＵＴA resistor R13 is connected between the output terminal W of the HVIC 11 and the gate of the switching element S3. ＯＵＴ A capacitor C13 is connected between one end of the resistor R13 and the output terminal W. The resistor R13 and the capacitor C13 are configured on one semiconductor chip 43 corresponding to the semiconductor device according to the first embodiment shown in FIGS.
[0049] LVIC12 output terminal U ＯＵＴ A resistor R14 is connected between the output terminal U of the LVIC 12 and the gate of the switching element S4. ＯＵＴ A capacitor C14 is connected between one end of the resistor R14 and the negative DC terminal N(U). The resistor R14 and the capacitor C14 are configured on one semiconductor chip 44 corresponding to the semiconductor device according to the first embodiment shown in FIGS.
[0050] LVIC12 output terminal V ＯＵＴ A resistor R15 is connected between the output terminal V of the LVIC 12 and the gate of the switching element S5. ＯＵＴ A capacitor C15 is connected between one end of the resistor R15 and the negative DC terminal N(V). The resistor R15 and the capacitor C15 are configured on one semiconductor chip 45 corresponding to the semiconductor device according to the first embodiment shown in FIGS.
[0051] LVIC12 output terminal W ＯＵＴ A resistor R16 is connected between the output terminal W of the LVIC 12 and the gate of the switching element S6. ＯＵＴ A capacitor C16 is connected between one end of the resistor R16 and the negative DC terminal N(W). The resistor R16 and the capacitor C16 are configured on one semiconductor chip 46 corresponding to the semiconductor device according to the first embodiment shown in FIGS.
[0052] <Comparative Example> Next, a vertically structured resistor element will be described as a semiconductor device according to a comparative example. The semiconductor device according to the comparative example is applied to a gate resistor for suppressing oscillation of a large-capacity IGBT module. As shown in FIG. 5 , the semiconductor device according to the comparative example includes a semiconductor substrate 101, lower insulating films 102a and 102b provided on the upper surface of the semiconductor substrate 101, and resistive layers 103a and 103b provided on the upper surfaces of the lower insulating films 102a and 102b. An interlayer insulating film 104 is provided on the upper surfaces of the lower insulating films 102a and 102b and the resistive layers 103a and 103b.
[0053] Surface electrodes 105a and 105b and relay wiring 105c are provided on the upper surface side of the interlayer insulating film 104. The surface electrode 105a is connected to the resistive layer 103a via contact 106a. The surface electrode 105b is connected to the resistive layer 103b via contact 106c. The relay wiring 105c is connected to the resistive layer 103a via contact 106b, to the resistive layer 103b via contact 106d, and to the semiconductor substrate 1 via contact 106e. A guard ring 105d is provided on the upper surface side of the interlayer insulating film 104, closer to the outer periphery than the surface electrodes 105a and 105b. The guard ring 105d is connected to the semiconductor substrate 1 via contacts 106f and 106g.
[0054] A protective film 107 is provided on the upper surfaces of the surface electrodes 105a, 105b and the relay wiring 105c. Openings 107a, 107b are provided in the protective film 107. The openings 107a, 107b expose portions of the surface electrodes 105a, 105b as pad regions. A back surface electrode 109 is provided on the lower surface of the semiconductor substrate 101. In the semiconductor device according to the comparative example, a current path is formed from the surface electrodes 105a, 105b to the back surface electrode 109 via the resistive layers 103a, 103b, the relay wiring 105c, and the semiconductor substrate 101.
[0055] 6 shows an equivalent circuit superimposed on the left cross-sectional structure of the semiconductor device according to the comparative example shown in FIG. 5. A terminal T101 is connected to the front surface electrode 105a, and a terminal T102 is connected to the rear surface electrode 109. A parasitic capacitance C ｐａｄ A parasitic capacitance C is formed under the resistive layer 103a with the lower insulating film 102a as a dielectric. ｐｏｌｙ A parasitic capacitance C between the end of the surface electrode 105a and the end of the relay wiring 105c, with the protective film 107 as a dielectric layer, is formed. ｐｍｍ is small and can be ignored.
[0056] 7A shows the equivalent circuit shown in FIG. 6. The parasitic capacitance C ｐｏｌｙ is the resistance R of the resistive layer 103a ｐｏｌｙ In FIG. 7B, the parasitic capacitance C ｐａｄ and parasitic capacitance C ｐｏｌｙ The combined parasitic capacitance C ｐａｒａ The current I flowing from the terminal T101 to the terminal T102 is ＰＡＤ is the chip resistance R ｐｏｌｙ The current I Ｒ and parasitic capacitance C ｐａｒａ The current I Ｃ It is decomposed into the following: Parasitic capacitance C ｐａｒａ The impedance of the chip resistor R ｐｏｌｙ If it is lower, the parasitic capacitance C ｐａｒａ The current I Ｃ becomes dominant and oscillation occurs.
[0057] FIG. 8 shows the parasitic capacitance C ｐａｒａ The relationship between the impedance and frequency of the ｐａｒａ The impedance of the parasitic capacitance C ｐａｒａ The smaller the capacitance value of ｐａｒａ Therefore, in the semiconductor device according to the comparative example, the impedance of the parasitic capacitance C ｐａｒａ In order to avoid a drop in the impedance of ｐａｒａ It is necessary to reduce the capacitance value of the lower insulating film 102, and therefore the thickness of the lower insulating film 102 must be increased.
[0058] Here, consider a case where the semiconductor device according to the comparative example is applied not as a gate resistor for suppressing oscillation of a large-capacity IGBT module, but to a semiconductor module 10 having HVIC11 and LVIC12, which are control circuits (driver ICs) shown in Fig. 4. In this case, not only are gate resistors R11 to R16 connected to the HVIC11 and LVIC12, but capacitors C11 to C16 are also connected, so the semiconductor device according to the comparative example cannot be applied as is.
[0059] In contrast, in the semiconductor device according to the first embodiment, as shown in FIGS. 1 to 3, the resistor R1 and the capacitor C1 are integrated into a single chip, and the resistor R1 and the capacitor C1 are connected in parallel to the terminal T1 corresponding to the surface electrode 5a. As a result, when applied to a semiconductor module 10 including the control circuits (driver ICs) HVIC11 and LVIC12 shown in FIG. 4, the gate resistors R11 to R16 and the capacitors C11 to C16 connected to the HVIC11 and LVIC12 can be configured on a single chip, i.e., the semiconductor chips 41 to 46 corresponding to the semiconductor device according to the first embodiment. Therefore, the packaging size of the semiconductor module 10 can be reduced compared to when the gate resistors R11 to R16 and the capacitors C11 to C16 are configured on separate chips. Furthermore, if the specifications of the switching elements S1 to S6 change, simply changing the semiconductor chips 41 to 46 that configure the gate resistors R11 to R16 and the capacitors C11 to C16 facilitates this change.
[0060] Second Embodiment Fig. 9 is a plan view showing an example of a semiconductor device according to a second embodiment. In Fig. 9, the lower insulating film 2, resistive layer 3, conductive layer 3x, surface electrodes 5a, 5b, and contacts (contact plugs) 6a to 6c hidden under a protective film 7 are schematically shown by dashed lines. As shown in Fig. 9, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment shown in Figs. 1 and 2 in that it further includes a conductive layer 3x that is provided around the resistive layer 3 and is located in the same layer as the resistive layer 3.
[0061] As shown in FIG. 9 , the conductive layer 3x is located inside the outer shape of the lower insulating film 2 and has a ring-shaped (frame-shaped) planar pattern surrounding the resistance layer 3. The conductive layer 3x is not limited to a ring-shaped (frame-shaped) planar pattern, and may have, for example, a U-shaped planar pattern in which a portion of the ring-shaped (frame-shaped) pattern is separated. Alternatively, the conductive layer 3x may have a planar pattern divided into multiple rectangular or other regions. A portion of the conductive layer 3x overlaps a portion of the surface electrodes 5a and 5b located above the conductive layer 3x. The conductive layer 3x is electrically connected to the surface electrode 5a via a contact 6c at the position where it overlaps with the surface electrode 5a. The number and arrangement of the contacts 6c are not particularly limited.
[0062] 10 shows a cross section taken along line A-A' in FIG. 9, which passes through the resistive layer 3, the conductive layer 3x, and the surface electrodes 5a and 5b, and FIG. 11 shows a cross section taken along line B-B' in FIG. 9, which passes through the conductive layer 3x and the surface electrodes 5a and 5b but does not pass through the resistive layer 3. As shown in FIGS. 10 and 11, the conductive layer 3x is provided on the upper surface side of the lower insulating film 2, spaced apart from the resistive layer 3. The conductive layer 3x is located below the surface electrodes 5a and 5b. The conductive layer 3x is made of the same material as the resistive layer 3 and has the same thickness as the resistive layer 3. The conductive layer 3x can be formed in the same process as the process for forming the resistive layer 3.
[0063] In the semiconductor device according to the second embodiment, a capacitance C1 is formed, with the resistive layer 3 as one electrode, the lower insulating film 2 located below (directly below) the resistive layer 3 as a dielectric (insulator), and the semiconductor substrate 1 and backside electrode 9 as the other electrode. Furthermore, a capacitance C2 is formed, with the conductive layer 3x as one electrode, the lower insulating film 2 located below (directly below) the conductive layer 3x as a dielectric, and the semiconductor substrate 1 and backside electrode 9 as the other electrode. A resistance R1 and capacitances C1 and C2 are connected in parallel to the front side electrode 5a. The other configuration of the semiconductor device according to the second embodiment is similar to that of the semiconductor device according to the first embodiment shown in FIGS. 1 and 2 , so a duplicated description will be omitted.
[0064] According to the semiconductor device of the second embodiment, the resistor R1 and the capacitors C1 and C2 connected in parallel to the surface electrode 5 a can be realized on a single chip. Furthermore, since the capacitor C2, which uses the lower insulating film 2 located directly below the conductive layer 3 x as a dielectric, is connected in parallel to the capacitor C1, the capacitance value can be made larger than that of the semiconductor device of the first embodiment.
[0065] Third Embodiment FIG. 12 is a plan view showing an example of a semiconductor device according to a third embodiment. In FIG. 12, the outlines of the lower insulating film 2, the resistive layer 3, the conductive layer 3x, the surface electrodes 5a and 5b, the contacts 6a to 6c, and the trench 8, which are hidden under the protective film 7, are schematically shown by dashed lines. As shown in FIG. 12, the semiconductor device according to the third embodiment is similar to the semiconductor device according to the second embodiment shown in FIGS. 9 to 11 in that it further includes a conductive layer 3x provided around the resistive layer 3. However, the semiconductor device according to the third embodiment differs from the semiconductor device according to the second embodiment shown in FIGS. 9 to 11 in that it further includes a trench 8 provided at a position below the conductive layer 3x.
[0066] As shown in Figure 12, the trenches 8 are located inside the outer shape of the conductive layer 3x. The trenches 8 are spaced apart from one another and are provided in a planar pattern of multiple stripes extending parallel to the longitudinal direction of the surface electrodes 5a, 5b (the vertical direction in Figure 12). The pitch and width of the trenches 8 and their positions inside the outer shape of the conductive layer 3x are not particularly limited. The trenches 8 may be provided in a planar pattern of multiple stripes extending parallel to the short direction of the surface electrodes 5a, 5b (the horizontal direction in Figure 12), or may be provided in a planar pattern of dots instead of stripes.
[0067] In the longitudinal direction of the surface electrodes 5a, 5b (the vertical direction in FIG. 12), the trenches 8 are provided opposite each other, dividing the electrodes 5a, 5b so as to sandwich the resistive layer 3. In FIG. 12, the trenches 8 are not provided around the contact 6c, but they may be provided around the contact 6c.
[0068] Fig. 13 shows a cross section taken along line A-A', which passes through the resistive layer 3, the conductive layer 3x, and the surface electrodes 5a and 5b in Fig. 12, and Fig. 14 shows a cross section taken along line B-B', which passes through the conductive layer 3x and the surface electrodes 5a and 5b but does not pass through the resistive layer 3 in Fig. 12. As shown in Figs. 13 and 14, a trench 8 is provided on the upper surface side of the semiconductor substrate 1, dug in the depth direction from the upper surface of the semiconductor substrate 1. A part of the lower insulating film 2 is provided inside the trench 8.
[0069] The thickness of the lower insulating film 2 located on the upper surface side of the semiconductor substrate 1 is thicker than the thickness of the lower insulating film 2 located inside the trench 8. The thickness of the lower insulating film 2 located on the upper surface side of the semiconductor substrate 1 may be substantially the same as the thickness of the lower insulating film 2 located inside the trench 8. The lower insulating film 2 located inside the trench 8 can be formed of the same material and to the same or greater thickness as the gate insulating film of the switching element in the semiconductor module in which the semiconductor device according to the first embodiment is mounted, thereby ensuring a sufficient dielectric strength voltage.
[0070] A buried layer (conductive layer) 3y is buried inside the trench 8 via the lower insulating film 2. The upper surface of the buried layer 3y is in contact with the lower surface of the conductive layer 3x. The material of the buried layer 3y may be the same as or a different conductive material from the resistive layer 3 and the conductive layer 3x. The buried layer 3y can be formed integrally with the conductive layer 3x in the same process as the process of forming the resistive layer 3 and the conductive layer 3x.
[0071] In the semiconductor device according to the third embodiment, a capacitance C1 is formed using the lower insulating film 2 located immediately below the resistive layer 3 as a dielectric, and a capacitance C2 is formed using the lower insulating film 2 located immediately below the conductive layer 3x as a dielectric. Furthermore, a capacitance C3 is connected in parallel to the capacitances C1 and C2, using the buried layer 3y buried in the trench 8 as one electrode, the lower insulating film 2 inside the trench 8 as a dielectric (insulator), and the semiconductor substrate 1 and the back surface electrode 9 as the other electrode. The other configuration of the semiconductor device according to the third embodiment is similar to that of the semiconductor device according to the first embodiment shown in FIGS. 1 and 2 and the semiconductor device according to the second embodiment shown in FIGS. 9 to 11, so a duplicated description will be omitted.
[0072] According to the semiconductor device of the third embodiment, the resistor R1 and the capacitors C1 to C3 connected in parallel to the surface electrode 5a can be realized on a single chip. Furthermore, the capacitor C2, which uses the lower insulating film 2 immediately below the conductive layer 3x as a dielectric, and the capacitor C3, which uses the lower insulating film 2 inside the trench 8 as a dielectric, are connected in parallel to the capacitor C1, so that the capacitance value can be increased.
[0073] As described above, the present disclosure has been described with reference to the first to third embodiments, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present disclosure. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.
[0074] For example, the semiconductor device according to the first to third embodiments is illustrated as being applied to the semiconductor module 10 shown in FIG. 4, but it can also be applied to various integrated circuits (ICs) having resistance and capacitance other than the semiconductor module 10.
[0075] Furthermore, the configurations disclosed in the first to third embodiments can be combined as appropriate within the scope of not causing any contradictions. As such, the present disclosure naturally includes various embodiments not described here. Therefore, the technical scope of the present disclosure is defined only by the invention-specifying matters according to the scope of the claims that are appropriate from the above description.
[0076] DESCRIPTION OF SYMBOLS 1, 101...Semiconductor substrate 2, 102a, 102b...Lower layer insulating film 3, 103a, 103b...Resistance layer 3x...Conductive layer 3y...Buried layer 4, 104...Interlayer insulating film 5a, 5b, 105a, 105b...Surface electrodes 6a to 6c, 106a to 106g...Contacts 7, 107...Protective film 7a, 7b, 107a, 107b...Openings 8...Trench 9, 109...Back electrode 10...Semiconductor module 11...HVIC 12...LVIC 13...BSD 20...Controller 30...Motor 41 to 46...Semiconductor chip 105c...Relay wiring 105d...Guard ring
Claims
a first surface electrode provided on the upper surface of the interlayer insulating film and electrically connected to one end of the resistive layer; a second surface electrode provided on the upper surface of the interlayer insulating film and spaced apart from the first surface electrode, and electrically connected to the other end of the resistive layer; and a back surface electrode provided on the lower surface of the semiconductor substrate, wherein a resistance formed by the resistive layer and a first capacitance having the lower insulating film below the resistive layer as a dielectric are connected in parallel to the first surface electrode.
2. The semiconductor device according to claim 1, wherein the thickness of the lower insulating film is 1000 nm or less.
3. The semiconductor device according to claim 1 or 2, further comprising a conductive layer provided on the upper surface of the lower insulating film at a distance from the resistive layer and electrically connected to the first surface electrode, wherein a second capacitor having the lower insulating film below the conductive layer as its dielectric is connected in parallel to the first capacitor.
4. The semiconductor device according to claim 3, wherein the conductive layer has a planar pattern surrounding the periphery of the resistive layer.
5. The semiconductor device according to claim 3, further comprising a buried layer in contact with the conductive layer, the buried layer being provided in a trench provided on the upper surface side of the semiconductor substrate via a part of the lower insulating film, and a third capacitor located inside the trench and using the lower insulating film as a dielectric, the third capacitor being connected in parallel to the first capacitor and the second capacitor.
6. The semiconductor device according to claim 5, wherein the trenches have a planar pattern of a plurality of stripes extending in one direction.
7. The semiconductor device according to claim 6, wherein the trench has a planar pattern divided by the resistive layer.
8. The semiconductor device according to claim 5, wherein the thickness of the lower insulating film located on the upper surface side of the semiconductor substrate is thicker than the thickness of the lower insulating film located inside the trench.