Semiconductor device

Abstract

The present invention mitigates a decrease in thermal conductivity by reducing stress between a board and a cooling module.　A semiconductor device (1) includes: an insulating circuit board (20) including a metal plate (22) as the lowermost layer; a stress relief layer (24) formed on the underside of the metal plate (22) and having a higher coefficient of linear expansion than the metal plate (22); and a cooling module (3) including a placement surface (3a) on which the underside of the stress relief layer (24) is provided via a bonding member (4) that is a thermally conductive adhesive. Since the stress relief layer (24) has a higher coefficient of linear expansion than the metal plate (22), the difference in the coefficients of linear expansion between the metal plate (22) (insulating circuit board (20)) and the placement surface (3a) of the cooling module (3) is reduced gradually and stress is reduced.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] The semiconductor device includes a semiconductor module and a cooling module in which the semiconductor module is arranged, and a metal plate, a buffer layer, a bonding layer, and an insulating plate are sandwiched between the semiconductor module and the cooling module (see, for example, Patent Documents 1 to 4).

[0003] International Publication No. 2016 / 121159 JP 2013-138267 A JP 2015-185688 A JP 2015-018833 A

[0004] An object of the present invention is to provide a semiconductor device in which the stress between the substrate and the cooling module is reduced, thereby preventing a decrease in thermal conductivity.

[0005] According to one aspect of the present invention, there is provided a semiconductor device having an insulating circuit board including a metal plate as a bottom layer, a stress relief layer formed on the underside of the metal plate and having a linear expansion coefficient greater than that of the metal plate, and a cooling module including an arrangement surface on which the underside of the stress relief layer is provided via a thermally conductive adhesive.

[0006] The stress relaxation layer may include aluminum. The bonding temperature of the thermally conductive adhesive may be 200° C. or less. The thermally conductive adhesive may include an epoxy resin and a filler contained in the epoxy resin.

[0007] The filler may be electrically conductive. The placement surface of the cooling module may be made of at least one of copper and aluminum.

[0008] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions.

[0009] According to the disclosed technology, the stress between the substrate and the cooling module is reduced, thereby suppressing the decrease in thermal conductivity. The above and other objects, features, and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings, which illustrate preferred embodiments of the present invention by way of example.

[0010] FIG. 1 is a side cross-sectional view of a semiconductor device according to an embodiment. FIG. 2 is a back view of a semiconductor device according to an embodiment. FIG. 3 is a flowchart showing a manufacturing method of a semiconductor device according to an embodiment. FIG. 4 is a diagram (part 1) for explaining a semiconductor module assembly process according to an embodiment. FIG. 5 is a diagram (part 2) for explaining a semiconductor module assembly process according to an embodiment. FIG. 6 is a diagram (part 3) for explaining a semiconductor module assembly process according to an embodiment. FIG. 7 is a side cross-sectional view of a semiconductor module according to an embodiment. FIG. 8 is a side cross-sectional view of a semiconductor device of a reference example. FIG. 9 is a graph showing the amount of warpage and tensile stress according to the thickness of a stress relaxation layer.

[0011] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "top surface" refer to the X-Y plane facing upward (+Z direction) in the semiconductor device 1 of FIG. 1. Similarly, "top" refers to the upward direction (+Z direction) in the semiconductor device 1 of FIG. 1. The terms "back surface" and "bottom surface" refer to the X-Y plane facing downward (-Z direction) in the semiconductor device 1 of FIG. 1. Similarly, "bottom" refers to the downward direction (-Z direction) in the semiconductor device 1 of FIG. 1. As necessary, the same orientations as above will be used in all other drawings. The terms "higher" and "upper" refer to the upper position (+Z direction) in the semiconductor device 1 of FIG. 1. Similarly, the terms "lower" and "lower" refer to the lower position (-Z direction) in the semiconductor device 1 of FIG. 1. The terms "front surface," "top surface," "top," "back surface," "bottom surface," "bottom," and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. In the following description, "main component" refers to a component containing 80 vol% or more. "Approximately the same" means that the difference is within a range of ±10%. "Perpendicular," "orthogonal," and "parallel" mean that the difference is within a range of ±10°.

[0012] [Embodiment] A semiconductor device 1 according to an embodiment will be described with reference to Figures 1 and 2. Figure 1 is a side cross-sectional view of the semiconductor device according to the embodiment. Figure 2 is a rear view of the semiconductor device according to the embodiment. Note that Figure 2 is a cross-sectional view of the semiconductor device 1 in Figure 1 taken along the II plane indicated by the dashed dotted line. That is, Figure 2 is a plan view of the placement surface 3a on which the joining members 4 of the cooling module 3 are provided. Figure 1 is a cross-section taken along the dashed dotted line II in Figure 2, viewed in the +Y direction.

[0013] The semiconductor device 1 includes a semiconductor module 2, a cooling module 3, and a joining member 4 that joins the semiconductor module 2 and the cooling module 3. The semiconductor device 1 may include other necessary components in addition to these.

[0014] The semiconductor module 2 includes semiconductor chips 10a, 10b, 10d, and 10e, an insulating circuit board 20, a printed circuit board 30, and a stress relief layer 24, as well as a sealing member 35 that seals these components. The semiconductor chips 10a, 10b, 10d, and 10e may be power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) primarily composed of silicon carbide. The body diode of the power MOSFET may function as a free-wheeling diode (FWD). Each of the semiconductor chips 10a, 10b, 10d, and 10e includes, for example, an input electrode (drain electrode) as a main electrode on the back surface and an output electrode (source electrode) and a control electrode (gate electrode) as main electrodes on the front surface. The control electrode may be located at the center of one edge of the front surface of the semiconductor chips 10a, 10b, 10d, and 10e or offset from the center along the edge.

[0015] The semiconductor chips 10a, 10b, 10d, and 10e may also include a switching element primarily made of silicon. The switching element is, for example, an RC (Reverse-Conducting)-IGBT (Insulated Gate Bipolar Transistor). The RC-IGBT is a semiconductor element in which an IGBT and an FWD are arranged in anti-parallel within a single chip.

[0016] Each of the semiconductor chips 10a, 10b, 10d, and 10e has an input electrode (collector electrode) as a main electrode on its back surface, and an output electrode (emitter electrode) and a control electrode (gate electrode) as main electrodes on its front surface. As in the case of a power MOSFET, the control electrode may be provided at the center of one side of the front surface of each of the semiconductor chips 10a, 10b, 10d, and 10e or offset from the center along the side.

[0017] Furthermore, for example, the semiconductor chips 10a, 10b, 10d, and 10e may be semiconductor chips mainly composed of silicon and each including a pair of switching elements and diode elements. Specifically, the semiconductor chips 10a and 10d may be switching elements, and the semiconductor chips 10b and 10e may be diode elements. The switching elements may be, for example, power MOSFETs or IGBTs. The semiconductor chips including the switching elements may have, for example, an input electrode (a drain electrode in a power MOSFET or a collector electrode in an IGBT) as a main electrode on the back surface, and a gate electrode (a control electrode) and an output electrode (a source electrode in a power MOSFET or an emitter electrode in an IGBT) as a main electrode on the front surface. Furthermore, for example, a Schottky Barrier Diode (SBD) or a P-intrinsic-N (PiN) diode may be used as the FWD for the diode elements. A semiconductor chip including a diode element has an output electrode (cathode electrode) as a main electrode on the back surface and an input electrode (anode electrode) as a main electrode on the front surface.

[0018] The semiconductor chips 10a, 10b and the semiconductor chips 10d, 10e may be joined to the conductive circuit patterns 23a, 23b (described later) with solder 12, respectively. The solder 12 is composed of solder components. The solder components are materials constituting the solder 12 and include lead-free solder primarily composed of a predetermined alloy. The predetermined alloy includes tin. Such alloys include, for example, at least one of a tin-silver alloy, a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, a tin-silver-indium-bismuth alloy, and a tin-antimony alloy. Furthermore, such solder components may include additives. Examples of additives include nickel, germanium, cobalt, or silicon. Therefore, examples of the solder components include tin and at least one of silver, zinc, copper, bismuth, indium, and antimony. Furthermore, the solder components may include, for example, at least one of nickel, germanium, cobalt, and silicon. A sintered body may be used instead of the solder 12. The sintered material when joining with a sintered body is, for example, a powder of silver, iron, copper, aluminum, titanium, nickel, tungsten, or molybdenum.

[0019] The insulating circuit board 20 includes an insulating plate 21, a metal plate 22, and conductive circuit patterns 23a and 23b. The insulating plate 21 and the metal plate 22 are rectangular in plan view. The corners of the insulating plate 21 and the metal plate 22 may be round-chamfered or C-chamfered. The size of the metal plate 22 is smaller than the size of the insulating plate 21 in plan view, and is formed inside the insulating plate 21.

[0020] The insulating plate 21 may be, for example, a ceramic substrate. The ceramic substrate is made of ceramic with good thermal conductivity. The ceramic is made of a material containing, for example, aluminum oxide, aluminum nitride, or silicon nitride as its main component. The insulating plate 21 has a rectangular shape in plan view. Examples of the insulating circuit board 20 including the insulating plate 21 having such a configuration include a DCB (Direct Copper Bonding) substrate and an AMB (Active Metal Brazed) substrate.

[0021] Alternatively, the insulating plate 21 may be made of a resin. The resin may be a material with low thermal resistance and high insulating properties. An example of such a resin is a thermosetting resin. The thermosetting resin may further contain a filler. By controlling the material and content of the filler in the insulating plate 21, the thermal resistance of the insulating plate 21 can be further reduced.

[0022] Examples of such thermosetting resins include at least one of epoxy resin, cyanate resin, polyimide resin, benzoxazine resin, unsaturated polyester resin, phenol resin, melamine resin, silicone resin, and maleimide resin. The filler is composed of at least one of an oxide and a nitride. Examples of oxides include silicon oxide and aluminum oxide. Examples of nitrides include silicon nitride, aluminum nitride, and boron nitride. Furthermore, the filler may be hexagonal boron nitride.

[0023] The thickness of the insulating plate 21 depends on the rated voltage of the semiconductor device 1. That is, the higher the rated voltage of the semiconductor device 1, the thicker the insulating plate 21 needs to be. On the other hand, it is necessary to make the insulating plate 21 as thin as possible to reduce thermal resistance.

[0024] The metal plate 22 is made of a metal with excellent thermal conductivity. Examples of such metals include copper, aluminum, or an alloy containing at least one of these. In this example, copper is included. Furthermore, to improve corrosion resistance, the surface of the metal plate 22 may be plated. In this case, the plating material includes nickel. Examples of such plating materials include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0025] The semiconductor chips 10a, 10b and the semiconductor chips 10d, 10e are disposed on the conductive circuit patterns 23a, 23b, respectively. The conductive circuit patterns 23a, 23b are formed over the entire surface of the insulating plate 21 except for the edges. Preferably, in a plan view, the ends of the conductive circuit patterns 23a, 23b facing the outer periphery of the insulating plate 21 overlap the ends of the metal plate 22 on the outer periphery. This maintains a stress balance between the insulating circuit board 20 and the metal plate 22 on the back surface of the insulating plate 21. This further suppresses damage to the insulating plate 21, such as excessive warping and cracking.

[0026] The conductive circuit patterns 23a, 23b are made of a material with excellent conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. The conductive circuit patterns 23a, 23b can also be plated with a material with excellent corrosion resistance. Examples of such materials include nickel, nickel-phosphorus alloy, and nickel-boron alloy. The conductive circuit patterns 23a, 23b for the insulating plate 21 are obtained by forming a metal plate on the front surface of the insulating plate 21 and then etching or other processes on the metal plate. Alternatively, the conductive circuit patterns 23a, 23b may be cut out from a metal plate in advance and bonded to the front surface of the insulating plate 21. The conductive circuit patterns 23a, 23b included in the semiconductor device 1 of this embodiment are merely an example. The number, shape, size, and other factors of the conductive circuit patterns may be appropriately selected as needed.

[0027] The printed circuit board 30 includes an insulating layer and multiple upper circuit pattern layers formed on the front surface of the insulating layer. The printed circuit board 30 may also include multiple lower circuit pattern layers on the back surface of the insulating layer. Such a printed circuit board 30 faces the front surface of the insulating circuit board 20 in plan and side views. The printed circuit board 30 is electrically connected to the output electrodes, input electrodes, and control electrodes of the semiconductor chips 10a, 10b, 10d, and 10e. Note that the conductive posts 31a, 31b, 31d, and 31e shown in FIG. 1 are merely examples, and the printed circuit board 30 may also include conductive posts not shown in FIG. 1. The upper portions of the conductive posts 31a, 31b, 31d, and 31e, along with the conductive posts not shown, are electrically connected to the upper and lower circuit pattern layers of the printed circuit board 30. The lower portions are connected to the output and control electrodes of the semiconductor chips 10a, 10b, 10d, and 10e by solder 32. The solder components of the solder 32 are also the same as those of the solder 12. The solder 32 may be replaced with the sintered body described above.

[0028] For example, the printed circuit board 30 is electrically connected to the output electrodes on the front surfaces of the semiconductor chips 10a and 10b through conductive posts 31a and 31b, and to the output electrodes on the front surfaces of the semiconductor chips 10d and 10e through conductive posts 31d and 31e.

[0029] The printed circuit board 30 is electrically connected to the input electrodes on the rear surfaces of the semiconductor chips 10a and 10b via the conductive posts 31c and the conductive circuit patterns 23a, and is also electrically connected to the input electrodes on the rear surfaces of the semiconductor chips 10d and 10e via the conductive posts 31f and the conductive circuit patterns 23b.

[0030] The printed circuit board 30 is electrically connected to the control electrodes on the front surfaces of the semiconductor chips 10a and 10b via conductive posts (not shown) and to the control electrodes on the front surfaces of the semiconductor chips 10d and 10e via conductive posts (not shown).

[0031] The stress relaxation layer 24 is provided on the entire lower surface of the metal plate 22 of the insulating circuit board 20. The stress relaxation layer 24 is made of a material with a higher linear expansion coefficient than the metal plate 22 of the insulating circuit board 20. Furthermore, a material with high thermal conductivity is preferable. An example of such a material is aluminum. The stress relaxation layer 24 includes a heat dissipation surface 24a on its lower surface. This heat dissipation surface 24a may be substantially flat. The heat dissipation surface 24a also forms part of the lower surface of the semiconductor module 2. The heat dissipation surface 24a of the stress relaxation layer 24 is exposed from a sealing lower surface 35a of a sealing member 35, which will be described later. In this case, the heat dissipation surface 24a of the stress relaxation layer 24 may protrude outward from the sealing lower surface 35a of the sealing member 35, or may be flush with the sealing lower surface 35a of the sealing member 35. In this embodiment, the heat dissipation surface 24a of the stress relaxation layer 24 is flush with the sealing lower surface 35a of the sealing member 35.

[0032] The sealing member 35 seals the entire insulating circuit board 20, the semiconductor chips 10a, 10b, 10d, and 10e, the printed circuit board 30, and the stress relaxation layer 24. If necessary, various terminals, for example, for input, output, and control, may protrude from the upper surface of the sealing member 35. The sealing member 35 may be, for example, a rectangular parallelepiped, and includes a flat sealing lower surface 35a. The heat dissipation surface 24a of the stress relaxation layer 24 is exposed from the sealing lower surface 35a of the sealing member 35.

[0033] Such a sealing member 35 may be a thermosetting resin containing a filler. That is, the sealing member 35 is composed mainly of an insulating filler (described later) and a resin (thermosetting resin). In this case, the thermosetting resin is, for example, an epoxy resin, a phenolic resin, a maleimide resin, or a polyester resin. The filler may be mainly composed of an insulating ceramic having high thermal conductivity. Such a filler is, for example, silicon oxide, aluminum oxide, boron nitride, or aluminum nitride.

[0034] The cooling module 3 has an upper surface, a mounting surface 3a, on which the heat dissipation surface 24a of the semiconductor module 2 is disposed. The mounting surface 3a is wider and generally flat than the lower sealing surface 35a, which is the rear surface of the semiconductor module 2. The cooling module 3 may be, for example, a heat dissipation base equipped with heat dissipation fins or a cooling device in which a refrigerant circulates inside. At least the portion of the cooling module 3, including the mounting surface 3a on which the semiconductor module 2 is disposed, is made of a metal with excellent thermal conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. In this example, copper is included. Furthermore, to improve corrosion resistance, the surface of the mounting surface 3a of the cooling module 3 may be plated. In this case, the plating material includes nickel. Examples of such plating materials include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0035] The bonding member 4 is provided between the heat dissipation surface 24a of the stress relaxation layer 24 of the semiconductor module 2 and the placement surface 3a of the cooling module 3. The shape and size of the bonding member 4 in a plan view in the -Z direction substantially match the shape and size of the bottom surface of the semiconductor module 2. In other words, the bonding member 4 is in contact with the heat dissipation surface 24a of the stress relaxation layer 24 of the semiconductor module 2 and the surrounding sealing bottom surface 35a.

[0036] Such a bonding member 4 may be a thermally conductive adhesive and may be made of a material having thermal conductivity, insulation, and adhesive properties. The thermal conductivity may be, for example, 10 W / (m·K) or more. A material may be selected that achieves a thermal conductivity within this range. The adhesive strength may be, for example, 10 MPa or more. Note that the adhesive strength here refers to tensile adhesive strength. Furthermore, the bonding temperature may be 200°C or less. Such a bonding member 4 may be primarily composed of a resin and may contain a filler. The resin may be, for example, an epoxy-based resin. The filler may be primarily composed of ceramics or metal. Ceramics have high thermal conductivity, such as silicon oxide, aluminum oxide, boron nitride, or aluminum nitride. When the filler is ceramic, the bonding member 4 containing such a filler can ensure thermal conductivity in addition to adhesive properties. The metal has high thermal conductivity and electrical conductivity, such as silver, copper, gold, nickel, chromium, aluminum, or an alloy containing at least one of these. When the filler is metal, the bonding member 4 containing such a filler ensures thermal conductivity and electrical conductivity in addition to adhesiveness. The electrical conductivity of the bonding member 4 allows the stress relief layer 24 and the cooling module 3 (described later) to have the same potential, preventing discharge between the semiconductor module 2 (stress relief layer 24) and the cooling module 3. The outer corners of the bonding member 4 may be rounded. This prevents stress concentration at the corners. This prevents peeling of the bonding member 4 from the heat dissipation surface 24a and the placement surface 3a.

[0037] Next, a method for manufacturing such a semiconductor device 1 will be described with reference to FIG. 3 . FIG. 3 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment. First, a preparation step is performed to prepare components of the semiconductor device 1 (step P1). Examples of the components prepared here include the semiconductor chips 10a, 10b, 10d, and 10e that constitute the semiconductor module 2, the insulating circuit board 20, the printed circuit board 30 provided with conductive posts 31a, 31b, 31c, 31d, 31e, and 31f, the sealing member 35, the bonding member 4, and the raw materials for the stress relaxation layer 24. Also included is the cooling module 3.

[0038] Components not listed here may be prepared as necessary for manufacturing the semiconductor device 1. Also, manufacturing equipment used for manufacturing the semiconductor device 1 may be prepared. Examples of the manufacturing equipment include an application device that applies solder and a molding device that seals with a sealing member.

[0039] Next, a semiconductor module assembly process is performed to assemble the semiconductor module 2 (process P2). The semiconductor module assembly process further includes the following processes. First, a stress relief layer 24 is formed on the insulating circuit board 20 (process P2a). This process P2a will be described with reference to FIG. 4. FIG. 4 is a diagram for explaining the semiconductor module assembly process according to the embodiment.

[0040] Metal powder is sprayed onto the rear surface of the metal plate 22 of the insulating circuit board 20. For example, this spraying is performed by cold spraying, in which the metal powder is accelerated to a supersonic speed range and sprayed in a solid state, forming a stress relief layer 24 on the rear surface of the metal plate 22. The cold spraying method can be performed at a lower temperature than other thermal spraying methods. This prevents oxidation of the metal plate 22 and suppresses the effects of heat on the insulating circuit board 20. By this type of spraying, the stress relief layer 24 is formed on the rear surface of the metal plate 22 of the insulating circuit board 20, as shown in FIG. 4 .

[0041] Alternatively, the insulating circuit board 20 having the stress relief layer 24 formed thereon can also be formed by the following method. For example, in the preparation step of step P1, a clad material is prepared in which a metal plate made of the same material as the metal plate 22 and a layer made of the same material as the stress relief layer 24 are formed on the back surface of the metal plate. This clad material is manufactured by roll-bonding the previously described layers to the previously described metal plate and then heat treating it. Such a clad material is cut to a desired size to obtain a member in which the metal plate 22 and the stress relief layer 24 are laminated. The insulating plate 21 is formed on the front surface of the metal plate 22 of this member, and conductive circuit patterns 23 a, 23 b are formed on the front surface of the insulating plate 21, thereby obtaining the insulating circuit board 20 having the stress relief layer 24 formed thereon, as shown in FIG. 4 .

[0042] Thereafter, semiconductor chips 10a, 10b, 10d, and 10e are bonded to insulating circuit board 20 (step P2b). This step P2b will be described with reference to FIG. 5. FIG. 5 is a diagram for explaining the semiconductor module assembly step of the embodiment. Semiconductor chips 10a, 10b, 10d, and 10e are bonded to conductive circuit patterns 23a and 23b of insulating circuit board 20 via solder 12. The bonding at this time is performed by conventional solder bonding. As a result, a structure is obtained in which semiconductor chips 10a and 10b are bonded to conductive circuit pattern 23a of insulating circuit board 20 via solder 12, and semiconductor chips 10d and 10e are bonded to conductive circuit pattern 23b via solder 12, as shown in FIG. 5.

[0043] Thereafter, conductive posts 31a, 31b, 31c, 31d, 31e, and 31f of printed circuit board 30 are bonded to semiconductor chips 10a and 10b, conductive circuit pattern 23a of insulating circuit board 20, semiconductor chips 10d and 10e, and conductive circuit pattern 23b of insulating circuit board 20 (step P2c). This step P2c will be described with reference to FIG. 6. FIG. 6 is a diagram for explaining the semiconductor module assembly process according to this embodiment.

[0044] Conductive posts 31a, 31b, 31c, 31d, 31e, and 31f are provided in advance on printed circuit board 30. These conductive posts 31a, 31b, 31c, 31d, 31e, and 31f are joined with solder 32 using conventional soldering. As a result, a structure is obtained in which printed circuit board 30 is attached to insulating circuit board 20 to which semiconductor chips 10a, 10b, 10d, and 10e are joined, as shown in FIG.

[0045] The final step of process P2 is sealing with a sealing member 35 (process P2d). This process P2d will be described with reference to FIGS. 7 and 2. FIG. 7 is a side cross-sectional view of the semiconductor module according to the embodiment. FIG. 2 is a view of the rear surface (heat dissipation surface 24a and sealing lower surface 35a) of the semiconductor module 2 in FIG. 7 as viewed in the +Z direction, and is a plan view of the heat dissipation surface 24a and sealing lower surface 35a of the semiconductor module 2.

[0046] The structure obtained in process P2c is set, for example, in a predetermined mold. The mold is filled with a sealing member 35 to seal the structure. The mold is then removed to obtain the semiconductor module 2 shown in FIG. 7. In the semiconductor module 2, as shown in FIG. 2, the heat dissipation surface 24a of the stress relaxation layer 24 is exposed from the sealing lower surface 35a of the sealing member 35. The sealing lower surface 35a of the sealing member 35 and the heat dissipation surface 24a of the stress relaxation layer 24 form the same plane. The back surface of the semiconductor module 2 is composed of the sealing lower surface 35a of the sealing member 35 and the heat dissipation surface 24a of the stress relaxation layer 24.

[0047] Next, a coating step of coating the bonding material 4 is performed (step P3). The bonding material 4 may be applied to either the rear surface (heat dissipation surface 24a and sealing lower surface 35a) of the semiconductor module 2 or the mounting surface 3a of the cooling module 3.

[0048] Next, an attachment process is performed in which the heat dissipation surface 24a and the sealing lower surface 35a of the stress relaxation layer 24 of the semiconductor module 2 are attached to the mounting surface 3a of the cooling module 3 via the bonding material 4 (process P4). First, the cooling module 3 with the bonding material 4 applied to the mounting surface 3a is fixed to a predetermined fixing base, and the semiconductor module 2 is set against the bonding material 4 applied to the cooling module 3 from the sealing lower surface 35a side.

[0049] Then, the structure including the cooling module 3 and the semiconductor module 2 arranged on the arrangement surface 3a of the cooling module 3 via the bonding member 4 is heated. The heating temperature at this time is, for example, 200°C or less. Because this heating temperature is lower than the melting temperature of the solders 12, 32, remelting of the solders 12, 32 in the semiconductor module 2 is suppressed. In addition, at this time, the semiconductor module 2 is pressed against the cooling module 3 side with a constant pressure. This makes it possible to control the thickness of the bonding member 4. By heating in this manner, the bonding member 4 hardens, and the semiconductor module 2 and the cooling module 3 are bonded together. In this manner, the semiconductor device 1 shown in FIGS. 1 and 2 is obtained.

[0050] Here, a semiconductor device 100 of a reference example will be described with reference to Fig. 8. Fig. 8 is a side cross-sectional view of the semiconductor device of the reference example. The semiconductor module 2 of the semiconductor device 100 of the reference example is a case where the semiconductor module 2 of the semiconductor device 1 does not include the stress relaxation layer 24. In other words, the semiconductor device 100 has the same configuration as the semiconductor device 1 except for the stress relaxation layer 24.

[0051] The joining member 400 may be a thermal interface material (hereinafter referred to as TIM), but is different from the joining member 4 of the embodiment. The TIM used here is an insulating material such as thermally conductive grease, elastomer sheet, RTV (Room Temperature Vulcanization) rubber, gel, or phase change material. The joining member 400 contacts the entire heat dissipation surface 22 a and the sealing lower surface 35 a of the metal plate 22 of the semiconductor module 2, joining the semiconductor module 2 and the cooling module 3.

[0052] The components included in the semiconductor module 2 included in such a semiconductor device 100 have different linear expansion coefficients. Therefore, the semiconductor module 2 and the cooling module 3 are warped and deformed when heated and cooled during the manufacturing process of the semiconductor module 2 and when subjected to thermal cycles during use of the semiconductor device 100. This applies stress to the bonding member 400 between the semiconductor module 2 and the cooling module 3. If the bonding member 400 is grease-like, it is subjected to stress and pushed out from between the semiconductor module 2 and the cooling module 3 every time the semiconductor module 2 and the cooling module 3 deform. If the bonding member 400 is sheet-like, peeling occurs between the semiconductor module 2 and the cooling module 3. If the bonding member 400 is an adhesive, cracks occur and peeling occurs between the semiconductor module 2 and the cooling module 3. Therefore, when stress is applied to the bonding member 400, the thermal conductivity between the semiconductor module 2 and the cooling module 3 decreases, and the heat dissipation performance for the semiconductor module 2 decreases.

[0053] The semiconductor device 1 includes an insulating circuit board 20 having a metal plate 22 as its bottom layer, a stress relief layer 24 formed on the underside of the metal plate 22 and having a linear expansion coefficient greater than that of the metal plate 22, and a cooling module 3 having a mounting surface 3a on the underside of the stress relief layer 24 via a bonding member 4 made of a thermally conductive adhesive. Because the stress relief layer 24 has a linear expansion coefficient greater than that of the metal plate 22, the difference in linear expansion coefficient between the metal plate 22 (insulating circuit board 20) and the mounting surface 3a of the cooling module 3 is gradually reduced. This reduces the overall amount of warping of the semiconductor module 2, thereby reducing stress on the bonding member 4. Furthermore, the bonding member 4 has adhesive properties and thus secures the cooling module 3 to the semiconductor module 2. As a result, the decrease in thermal conductivity between the semiconductor module 2 and the cooling module 3 is reduced, preventing a decrease in the heat dissipation performance of the semiconductor module 2.

[0054] Here, the amount of warpage and tensile stress of the insulating circuit board 20 depending on the thickness of the bonding member 4 will be described with reference to FIG. 9 . FIG. 9 is a graph showing the amount of warpage and tensile stress depending on the thickness of the stress relaxation layer. FIG. 9A shows the amount of warpage of the insulating circuit board 20 depending on the thickness of the bonding member 4. The horizontal axis of FIG. 9A represents the thickness [mm] of the bonding member 4, and the vertical axis of FIG. 9A represents the amount of warpage [%]. In this case, the amount of warpage refers to, for example, when the upper surface (the conductive circuit patterns 23 a and 23 b side) of the insulating circuit board 20 is facing up and upwardly convex warpage occurs, the distance from the lower surface of the insulating circuit board 20 before warpage occurs to the apex of the upwardly convex upper surface of the insulating circuit board 20 after warpage occurs. FIG. 9A also shows the amount of warpage when the temperature during bonding with the bonding member 4 is 175°C and then cooled to room temperature (25°C).

[0055] 9(B) shows the tensile stress on the insulating circuit board 20 according to the thickness of the bonding member 4. The horizontal axis of Fig. 9(B) represents the thickness [mm] of the bonding member 4, and the vertical axis of Fig. 9(B) represents the tensile stress [%].

[0056] 9A and 9B, the case where the stress relaxation layer 24 is not provided is represented by "None" at the leftmost position on the horizontal axis. The amount of warpage and tensile stress of the insulating circuit board 20 when the stress relaxation layer 24 is not provided are each set to 100%.

[0057] 9A, when the thickness of the bonding members 4 is increased to 0.05 mm, the amount of warpage of the insulating circuit board 20 is reduced to approximately 60%. Even when the thickness of the bonding members 4 is increased to 0.2 mm, the amount of warpage does not decrease significantly further and remains approximately constant.

[0058] 9(B) , when the thickness of the bonding members 4 is increased to 0.25 mm, the tensile stress on the insulating circuit board 20 is reduced to approximately 57%. When the thickness of the bonding members 4 is further increased to 0.05 mm, the tensile stress on the insulating circuit board 20 is reduced to 40%. On the other hand, when the thickness of the bonding members 4 is increased to 0.2 mm, the tensile stress does not decrease significantly further and remains approximately constant.

[0059] In this way, in semiconductor device 1, by providing stress relaxation layer 24, which has a linear expansion coefficient greater than that of metal plate 22, between insulating circuit board 20 and cooling module 3, it is possible to reduce the amount of warping of insulating circuit board 20 and the tensile stress on insulating circuit board 20 even when thermal changes occur. In particular, the thickness of stress relaxation layer 24 is preferably 0.25 mm or more and 0.2 mm or less, and more preferably 0.05 mm or more.

[0060] The foregoing merely illustrates the principles of the present invention. Further, since numerous modifications and changes will be apparent to those skilled in the art, the present invention is not limited to the exact construction and application shown and described above, and all corresponding modifications and equivalents are deemed to be within the scope of the present invention as defined by the appended claims and their equivalents.

[0061] REFERENCE SIGNS LIST 1 semiconductor device 2 semiconductor module 3 cooling module 3a mounting surface 4 bonding member 10a, 10b, 10d, 10e semiconductor chip 12 solder 20 insulating circuit board 21 insulating plate 22 metal plate 22a heat dissipation surface 23a, 23b conductive circuit pattern 24 stress relaxation layer 24a heat dissipation surface 30 printed circuit board 31a, 31b, 31c, 31d, 31e, 31f conductive post 32 solder 35 sealing member 35a sealing lower surface 35b groove

Claims

1. A semiconductor device comprising: an insulating circuit board including a metal plate as its bottom layer; a stress relief layer formed on the underside of the metal plate and having a linear expansion coefficient greater than that of the metal plate; and a cooling module including a mounting surface on which the underside of the stress relief layer is provided via a thermally conductive adhesive.

2. The semiconductor device according to claim 1, wherein the stress relaxation layer contains aluminum.

3. The semiconductor device according to claim 1, wherein the bonding temperature of the thermally conductive adhesive is 200°C or less.

4. The semiconductor device according to claim 1, wherein the thermally conductive adhesive contains an epoxy resin and a filler contained in the epoxy resin.

5. The semiconductor device according to claim 4, wherein the filling material is conductive.

6. The semiconductor device according to claim 1, wherein the mounting surface of the cooling module is made of at least one of copper and aluminum.

Images