Semiconductor device

Abstract

Provided is a semiconductor device in which a significant change in positional relationship between a pin terminal and an electrode of a semiconductor chip is suppressed. This semiconductor device is provided with: an insulating circuit board (1); a semiconductor chip (3) that is mounted on the insulating circuit board (1) using a solder and has an electrode (30) on the upper surface thereof; a printed circuit board (6) that is disposed above the semiconductor chip (3); pin terminals (51, 52) that are inserted into the printed circuit board (6) and are joined to the electrode (30) by a solder; and a solder resist (71) and a solder resist (72) that are provided on the upper surface side of the insulating circuit board (1) and are spaced apart along a first direction. The semiconductor chip (3) is positioned between the solder resist (71) and the solder resist (72) along the first direction.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device (semiconductor module) equipped with a power semiconductor chip.

[0002] Semiconductor devices equipped with power semiconductor chips (hereinafter simply referred to as "semiconductor chips") are primarily used for variable speed drives such as motors and inverters, and for power conversion. Laser light is sometimes irradiated onto the metal layer of a substrate on which the semiconductor chip is mounted, forming a resist on the top surface of the metal layer.

[0003] Patent Document 1 describes a technique for providing a liquid-repellent portion formed by laser irradiation on a circuit board of a ceramic circuit substrate, and also describes a technique for providing the liquid-repellent portion between areas where a semiconductor chip and a contact component are respectively arranged.

[0004] Patent Document 2 describes an oxide film provided around a solder joint on the upper surface of a metal circuit pattern, and describes a technique in which the oxide film is provided outside an area that is 0.5 mm or less away from a semiconductor element in a plan view.

[0005] Patent document 3 describes a technology in which a low-wettability portion with low wettability to solder is formed on an electrode pad of a semiconductor chip, solder paste containing flux is printed so as to cover the top of the low-wettability portion, and the solder paste is reflowed to form a solder bump that is conductive to the electrode pad, and gas generated from the flux comes into contact with and remains on the top of the low-wettability portion, forming a void in the solder bump.

[0006] Patent Document 4 describes a technology in which a nickel (Ni) plating layer is formed on the surface of a circuit layer of a circuit board for a semiconductor device, and a solder joint portion where a semiconductor element is to be soldered and a portion that has been altered by laser irradiation are arranged adjacent to each other in the planar direction on the formed nickel plating layer.

[0007] Patent Document 5 describes a technology in which a substrate is joined to one main surface of a heat sink with a solder layer, a semiconductor element is joined to one main surface of the substrate with a solder layer, a case is adhered to one main surface of the heat sink so as to surround the substrate, the inner periphery of the case includes an internal electrode that is electrically connected to the semiconductor element, and the adhesive surface of one main surface of the heat sink that is bonded to the case has a first region where a resist layer is formed and a second region where no resist layer is formed, and the second region is formed to include a region that overlaps with the internal electrode in a planar view.

[0008] Patent Document 6 describes a technology in which a cell unit is formed by soldering a semiconductor chip to one side of an insulating circuit board having conductive patterns on both sides, and a metal-based cell unit that dissipates heat generated by the semiconductor chip is formed by bonding an insulating inorganic layer using a metal mask to the unsoldered portion.The cell unit is then soldered to the metal base and encapsulated with insulating resin.Patent Document 7 describes a semiconductor device whose internal wiring is made of a printed circuit board with pins.

[0009] JP 2021-118350 A JP 2022-137686 A JP 2015-76429 A JP 2014-167983 A JP 2019-197831 A JP 2008-172066 A JP 2012-119618 A

[0010] In some cases, electrodes of a semiconductor chip are connected to an external device via a printed circuit board with pin terminals. Also, the semiconductor chip may move during reflow, which melts the solder.

[0011] In view of the above problems, an object of the present invention is to provide a semiconductor device in which the positional relationship between pin terminals and electrodes of a semiconductor chip is prevented from changing significantly.

[0012] One aspect of the present invention is a semiconductor device comprising: (a) an insulating circuit board; (b) a semiconductor chip mounted on the insulating circuit board using solder and having electrodes on its upper surface; (c) a printed circuit board arranged above the semiconductor chip; (d) pin terminals inserted into the printed circuit board and joined to the electrodes via solder; and (e) a first solder resist and a second solder resist provided on the upper surface of the insulating circuit board and spaced apart along a first direction; and (f) the semiconductor chip is located between the first solder resist and the second solder resist along the first direction.

[0013] Furthermore, if the distance between the first solder resist and the second solder resist along the first direction is L1, the width of the semiconductor chip is L2, the width of the electrode is w1, and the width of the area occupied by the pin terminal relative to the electrode is d1, the relationship (L1-L2)<(w1-d1) may be satisfied.

[0014] The insulating circuit board may also include a third solder resist and a fourth solder resist provided on the upper surface thereof and spaced apart along a second direction intersecting the first direction, and the semiconductor chip may be positioned between the third solder resist and the fourth solder resist along the second direction.

[0015] Furthermore, if the distance between the third solder resist and the fourth solder resist along the second direction is L3, the width of the semiconductor chip is L4, the width of the electrode is w2, and the width of the area occupied by the pin terminal relative to the electrode is d2, the relationship (L3-L4)<(w2-d2) may be satisfied.

[0016] Furthermore, the first solder resist, the second solder resist, the third solder resist, and the fourth solder resist may be connected to form one ring.

[0017] At least a portion of the first solder resist, the second solder resist, the third solder resist, and the fourth solder resist may have a slit.

[0018] Furthermore, at least a portion of the first solder resist, the second solder resist, the third solder resist, and the fourth solder resist may be provided in duplicate.

[0019] Alternatively, one of the first solder resist and the second solder resist may extend in the second direction, and the other may be in the form of dots.

[0020] In addition, one of the first solder resist and the second solder resist may extend along the second direction and the other may be dot-shaped, and one of the third solder resist and the fourth solder resist may extend along the first direction and the other may be dot-shaped.

[0021] Alternatively, the first solder resist may be bonded to only one of the third solder resist and the fourth solder resist, and the second solder resist may be bonded to only the other of the third solder resist and the fourth solder resist.

[0022] Furthermore, each of the first solder resist, the second solder resist, the third solder resist, and the fourth solder resist may be made up of a plurality of dot-shaped solder resists.

[0023] Furthermore, a plurality of semiconductor chips may be arranged side by side, and the plurality of semiconductor chips may share at least a portion of the first solder resist, the second solder resist, the third solder resist, and the fourth solder resist.

[0024] Furthermore, each of the first solder resist, the second solder resist, the third solder resist, and the fourth solder resist may be a laser resist provided by irradiating the upper surface of the insulating circuit board with laser light.

[0025] The electrode may also be a gate electrode or a source electrode.

[0026] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions.

[0027] According to the present invention, it is possible to provide a semiconductor device in which the positional relationship between the pin terminals and the electrodes of the semiconductor chip is prevented from changing significantly.

[0028] 1 is a cross-sectional view of a semiconductor device according to a first embodiment; FIG. 2 is a plan view of a printed circuit board included in the semiconductor device according to the first embodiment; FIG. 3 is an enlarged plan view showing a positional relationship between a solder resist and a semiconductor chip included in the semiconductor device according to the first embodiment before reflow; FIG. 4 is an enlarged plan view showing a positional relationship between a solder resist and a semiconductor chip included in the semiconductor device according to the first embodiment after reflow; FIG. 5 is an enlarged plan view showing a solder resist and a semiconductor chip included in the semiconductor device according to the first embodiment; FIG. 6 is an enlarged plan view showing a semiconductor chip of a semiconductor device according to a comparative example; FIG. 7 is an enlarged plan view showing a solder resist and a semiconductor chip included in a semiconductor device according to a first modification of the first embodiment; FIG. 8 is an enlarged plan view showing a solder resist and a semiconductor chip included in a semiconductor device according to a second modification of the first embodiment; FIG. 9 is an enlarged plan view showing a solder resist and a semiconductor chip included in a semiconductor device according to a third modification of the first embodiment; FIG. 10 is an enlarged plan view showing a solder resist and a semiconductor chip included in a semiconductor device according to a fourth modification of the first embodiment; FIG. 11 is an enlarged plan view showing a solder resist and a semiconductor chip included in a semiconductor device according to a fifth modification of the first embodiment; and FIG. 12 is an enlarged plan view showing a solder resist and a semiconductor chip included in a semiconductor device according to a sixth modification of the first embodiment. 10A and 10B are enlarged plan views showing a solder resist and a semiconductor chip included in a semiconductor device according to a seventh modification of the first embodiment, and an enlarged plan view showing a solder resist and a semiconductor chip included in a semiconductor device according to an eighth modification of the first embodiment.

[0029] The first embodiment and its modifications will be described below with reference to the drawings. In the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant description will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the first embodiment and its modifications shown below are examples of devices and methods for embodying the technical concept of the present invention, and the technical concept of the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components described below.

[0030] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical concept of the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if it is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0031] 1, the semiconductor device according to the first embodiment includes an insulating circuit board 1, semiconductor chips (semiconductor elements) 3a, 3b, and 3c mounted on the insulating circuit board 1 via solders 2a, 2b, and 2c, and a printed circuit board 6 disposed above and spaced apart from the semiconductor chips 3a, 3b, and 3c. The peripheries of the semiconductor chips 3a, 3b, and 3c and the printed circuit board 6 are sealed with a sealing member 8, and are electrically insulated from the surroundings.

[0032] The insulating circuit board 1 comprises an insulating substrate 11, upper conductor layers 12a and 12b arranged on the upper surface of the insulating substrate 11, which is the circuit side, and a lower conductor layer 13 arranged on the lower surface of the insulating substrate 11, which is the cooling side.

[0033] The insulating circuit board 1 may be, for example, a direct copper bond (DCB) board or an active matrix brazing (AMB) board. The insulating substrate 11 may be, for example, an aluminum oxide (Al ２ O ３ ), aluminum nitride (AlN), silicon nitride (Si ３ N ４ The upper conductor layers 12a, 12b and the lower conductor layer 13 are made of a ceramic substrate made of a material such as copper (Cu) or aluminum (Al), or a resin insulating substrate made of a polymer material. The upper conductor layers 12a, 12b and the lower conductor layer 13 are made of a conductive foil or conductive plate made of, for example, copper (Cu) or aluminum (Al). A nickel (Ni) plating layer may be formed on the upper surfaces of the upper conductor layers 12a, 12b. The upper conductor layers 12a, 12b form a predetermined circuit pattern. A solder resist 7 is provided on the upper surface of the upper conductor layers 12a, 12b. The solder resist 7 is a laser resist.

[0034] The semiconductor chips 3a, 3b, and 3c are bonded to the upper conductor layers 12a and 12b via solders 2a, 2b, and 2c, respectively. The solders 2a, 2b, and 2c are bonding materials. Examples of the solder that can be used include tin-antimony (SnSb)-based and tin-silver (SnAg)-based solders.

[0035] The semiconductor chips 3a, 3b, and 3c may be of different types depending on the application, but may include, for example, power semiconductor elements such as insulated gate bipolar transistors (IGBTs), reverse conducting IGBTs (RC-IGBTs), field effect transistors (FETs), static induction (SI) thyristors, and gate turn-off (GTO) thyristors, and rectifying elements such as free wheel diodes (FWDs). The semiconductor chips 3a, 3b, and 3c may be formed of, for example, a silicon (Si) substrate, or may be formed of silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga ２ O ３ The semiconductor chip 3 may be, for example, a power semiconductor chip.

[0036] For example, if the semiconductor chip 3 is a field-effect transistor, the semiconductor chip 3 has a control electrode (gate electrode) and a first main electrode (source electrode) on the upper surface side, and a second main electrode (drain electrode) on the lower surface side. If the semiconductor chip 3 is an IGBT or RC-IGBT, the semiconductor chip 3 has a control electrode (gate electrode) and a first main electrode (emitter electrode) on the upper surface side, and a second main electrode (collector electrode) on the lower surface side. If the semiconductor chip 3 is a static induction thyristor, gate turn-off thyristor, or freewheeling diode, the semiconductor chip 3 has a first main electrode (e.g., an anode electrode) on the upper surface side, and a second electrode (e.g., a cathode electrode) on the lower surface side. Of the first and second main electrodes, the first main electrode is the main electrode that is joined to a pin terminal (described later) via solder. In this embodiment, the semiconductor chip 3 is described as a field-effect transistor.

[0037] Although FIG. 1 illustrates three semiconductor chips 3a, 3b, and 3c, the number of semiconductor chips is not particularly limited. For example, the insulating circuit substrate 1 may include only one semiconductor chip, or four or more semiconductor chips. For example, as shown in FIG. 2, semiconductor chips (semiconductor elements) 3d, 3e, 3f, and 3g may also be mounted on the insulating circuit substrate 1 via solder (not shown). In the example shown in FIG. 2, the lower arm LO includes four semiconductor chips, namely, semiconductor chips 3a, 3b, 3d, and 3e, and the upper arm UP includes three semiconductor chips, namely, semiconductor chips 3c, 3f, and 3g. Note that the lower arm LO may include only three semiconductor chips. Furthermore, like the other semiconductor chips, the semiconductor chips 3b and 3c may be mounted on the insulating circuit substrate 1 with their gate electrodes located on the right side of the page and their source electrodes located on the left side of the page. When the semiconductor chips 3a, 3b, 3c, 3d, 3e, 3f, and 3g are not to be distinguished from one another, they may simply be referred to as semiconductor chips 3.

[0038] 1, a printed circuit board 6 is disposed above the semiconductor chips 3a, 3b, and 3c. The printed circuit board 6 includes an insulating layer 61, an upper wiring layer (not shown) disposed on the upper surface of the insulating layer 61, and a lower wiring layer (not shown) disposed on the lower surface of the insulating layer 61. The upper wiring layer and the lower wiring layer form a predetermined circuit pattern.

[0039] The insulating layer 61 is made of, for example, aluminum oxide (Al ２ O ３ ), aluminum nitride (AlN), silicon nitride (Si ３ N ４ The upper wiring layer 61 is made of an insulating material such as ceramics or resin mainly composed of copper (Cu) or aluminum (Al). The insulating layer 61 may be a resin substrate made of a combination of glass fiber and epoxy resin. The upper wiring layer and the lower wiring layer are made of conductive foil made of copper (Cu), aluminum (Al), or the like.

[0040] 2, the printed circuit board 6 is provided with a plurality of through holes (via holes) 6x penetrating an insulating layer 61, an upper wiring layer, and a lower wiring layer. A plurality of pin terminals (post electrodes) 51 to 59 are inserted (press-fitted) into the plurality of through holes 6x of the printed circuit board 6 and fixed therein. The printed circuit board 6 and the pin terminals 51 to 59 constitute an implant substrate (6, 51 to 59). A conductive layer (not shown) that electrically connects the upper wiring layer and the lower wiring layer may be formed on the inner surface of some of the through holes 6x, and the conductive layer on the inner surface may be electrically connected to the inserted pin terminal, thereby causing the upper wiring layer and the lower wiring layer to have the same potential.

[0041] The pin terminals 51 to 59 are, for example, rod-shaped (pin-shaped) or columnar, and specifically may be in the form of a polygonal prism such as a circular cylinder, an elliptical cylinder, a triangular prism, or a square prism. Conductive materials such as copper (Cu) can be used as the material for the pin terminals 51 to 59. The number of pin terminals is not limited to the examples shown in FIGS. 1 and 2 . The number of pin terminals is not particularly limited.

[0042] The drain electrode on the underside of the semiconductor chip 3 is soldered to the upper conductor layers 12a and 12b of the insulating circuit board 1 shown in FIG. 1 . The control electrode (gate electrode) of the semiconductor chip 3 is bonded to a pin terminal 51. The source electrode of the semiconductor chip 3 is bonded to a pin terminal 52. To distinguish the pin terminals 51 and 52 connected to the semiconductor chip 3a, the pin terminals 51 and 52 connected to the semiconductor chip 3b, and the pin terminals 51 and 52 connected to the semiconductor chip 3c, the pin terminals connected to the semiconductor chip 3a are referred to as pin terminals 51a and 52a, the pin terminals connected to the semiconductor chip 3b are referred to as pin terminals 51b and 52b, and the pin terminals connected to the semiconductor chip 3c are referred to as pin terminals 51c and 52c. When there is no need to distinguish between the pin terminals 51a and 52a, the pin terminals 51b and 52b, and the pin terminals 51c and 52c, they may be simply referred to as pin terminals 51 and 52.

[0043] As shown in FIG. 2 , one pin terminal 51 is provided for each semiconductor chip 3. Two pin terminals 52 are provided for each semiconductor chip 3. For example, the two pin terminals 52a provided for the semiconductor chip 3a may be referred to as pin terminals 52a1 and 52a2 to distinguish them from one another. Furthermore, for example, the two pin terminals 52e provided for the semiconductor chip 3e may be referred to as pin terminals 52e1 and 52e2 to distinguish them from one another. When the pin terminals 52a1 and 52a2 are not distinguished from one another, they are simply referred to as pin terminals 52a. When the pin terminals 52e1 and 52e2 are not distinguished from one another, they are simply referred to as pin terminals 52e. The number of pin terminals 52 provided for each semiconductor chip 3 is not limited to two. For example, one pin terminal 52 or three or more pin terminals 52 may be provided for each semiconductor chip 3.

[0044] As shown in FIG. 1 , the lower ends of pin terminals 51a and 52a are bonded to the upper surface of semiconductor chip 3a via solders 41a and 42a, respectively. Solder 41a and 42a are bonding materials. Examples of suitable solder include tin-antimony (SnSb) and tin-silver (SnAg) solders. The lower ends of pin terminals 51b and 52b are bonded to the upper surface of semiconductor chip 3b via solders 41b and 42b, respectively. The lower ends of pin terminals 51c and 52c are bonded to the upper surface of semiconductor chip 3c via solders 41c and 42c, respectively. The lower ends of pin terminals 54, 58, and 59 are bonded to the upper surfaces of upper conductor layers 12a and 12b of insulating circuit board 1 via solders 44, 48, and 49, respectively. The lower end of pin terminal 56 is inserted (press-fitted) into hole 12x provided in upper conductor layer 12b and fixed therein. The pin terminal 56 is a positioning pin used to fix the relative positional relationship between the insulating circuit board 1 and the printed circuit board 6. The pin terminals 53, 55, and 57 are not connected to the insulating circuit board 1.

[0045] 1 are external terminals. Pin terminal 59 is an anode side (P side) terminal, and pin terminal 53 is a cathode side (N side) terminal. At least one of pin terminals 55 and 57 is an output terminal. Pin terminals 53, 55, 57, and 59 protrude from sealing member 8 and are connected to an external circuit.

[0046] For example, if the semiconductor chip 3 is a field-effect transistor, the pin terminal 59 may supply current to the drain electrode of the semiconductor chip 3 in the upper arm UP via the upper conductor layer 12b, etc. The source electrode of the semiconductor chip 3 in the upper arm UP may supply current to the drain electrode of the semiconductor chip 3 in the lower arm LO via the pin terminal 52, a circuit configured on the printed circuit board 6, the pin terminal 54, the upper conductor layer 12a, etc. The source electrode of the semiconductor chip 3 in the lower arm LO may output to an external circuit via the pin terminal 52, the circuit configured on the printed circuit board 6, and the pin terminal 53. A control signal for controlling the on / off of the semiconductor chip 3 may be supplied to the gate electrode of the semiconductor chip 3 via an external terminal (not shown), a circuit configured on the printed circuit board 6, the pin terminal 51, etc. At least one of the pin terminals 55 and 57 may be connected as an output terminal between the upper arm UP and the lower arm LO.

[0047] <Solder Resist> The semiconductor chip 3 and the solder resist 7 provided around the semiconductor chip 3 will be described below with reference to FIGS. 3 to 5. The solder resist 7 may be provided for each semiconductor chip 3. FIGS. 3 to 5 show a semiconductor chip 3a as an example of the semiconductor chip 3. The semiconductor chips 3 other than the semiconductor chip 3a have the same configuration as the semiconductor chip 3a, and therefore will not be described here. Furthermore, one of the X direction and the Y direction is defined as a first direction, and the other as a second direction. In this embodiment, the X direction is defined as the first direction and the Y direction is defined as the second direction. However, the Y direction may be defined as the first direction and the X direction as the second direction. The X direction and the Y direction intersect with each other. In this embodiment, the X direction and the Y direction are orthogonal to each other. Furthermore, in FIG. 5 and subsequent drawings, the solders 41a and 42a are not shown.

[0048] FIG. 3 shows an example of a semiconductor chip 3a before reflow (heat treatment), which is one of the manufacturing processes, and FIG. 4 shows an example of the semiconductor chip 3a after reflow. When reflow is performed, as shown in FIG. 4, the solder 2a melts and spreads, which may cause the semiconductor chip 3a to move. As already explained, the relative positional relationship between the pin terminals 51a, 52a1, and 52a2 and the insulating circuit board 1 is less likely to change due to the presence of the pin terminals 56, which serve as positioning pins. In order to bond the pin terminals 51a, 52a1, and 52a2 to the electrodes of the semiconductor chip 3a, it is desirable to prevent the semiconductor chip 3a from moving excessively. In this technology, by providing solder resist 7 on the upper surfaces of the upper conductor layers 12a and 12b, excessive spreading of the solder 2a is suppressed, thereby preventing the semiconductor chip 3a from moving excessively. Therefore, the pin terminals 51a, 52a1, and 52a2 are bonded to the electrodes of the semiconductor chip 3a after reflow.

[0049] As shown in FIG. 3 , a gate electrode 31 and a source electrode 32 are provided as electrodes on the top surface of the semiconductor chip 3a. When the gate electrode 31 and the source electrode 32 are not distinguished from each other, they are simply referred to as electrodes 30. The lower end of a pin terminal 51a is joined to the gate electrode 31 via solder 41a, and the lower end of a pin terminal 52a is joined to the source electrode 32 via solder 42a. The solder resist 7 includes solder resists 71 and 72 spaced apart along the X direction, and solder resists 73 and 74 spaced apart along the Y direction. The solder resist 71 faces the solder resist 72, and the solder resist 73 faces the solder resist 74. The solder resists 71, 72, 73, and 74 are connected to form a ring. The semiconductor chip 3a is located between solder resist 71 and solder resist 72, and movement of the semiconductor chip 3a in the X direction is restricted by solder resist 71 and solder resist 72. The semiconductor chip 3a is located between solder resist 73 and solder resist 74, and movement of the semiconductor chip 3a in the Y direction is restricted by solder resist 73 and solder resist 74. The dimensions of the solder resists 71 and 72 in the X direction (short-side dimensions) and the dimensions of the solder resists 73 and 74 in the Y direction (short-side dimensions) are, for example, approximately 150 μm or more and 1000 μm or less.

[0050] The distance between the solder resists 71 and 72 along the X direction is defined as L1, and the width of the semiconductor chip 3a is defined as L2. The width of the gate electrode 31 along the X direction is defined as w1, and the width of the region occupied by the lower end of the pin terminal 51a relative to the gate electrode 31 is defined as d1. Similarly, the width of the source electrode 32 along the X direction is defined as w1, and the width of the region occupied by the lower end of the pin terminal 52a relative to the gate electrode 31 is defined as d1. The width d1 may be the diameter of the pin terminals 51a and 52a. L1, L2, w1, and d1 satisfy the relationship (L1-L2)<(w1-d1). (L1-L2) is the distance allowed for movement of the semiconductor chip 3a along the X direction, i.e., the play of the semiconductor chip 3a along the X direction. (w1-d1) is the distance that the gate electrode 31 and source electrode 32 are allowed to move relative to the pin terminals 51a, 52a along the X direction, i.e., the play along the X direction of the gate electrode 31 and source electrode 32. By making the play of the semiconductor chip 3a smaller than the play of the gate electrode 31 and source electrode 32, even if the semiconductor chip 3a moves along the X direction during reflow, it is possible to prevent the bond between the pin terminal 51a and gate electrode 31 from opening, and it is also possible to prevent the bond between the pin terminal 52a and source electrode 32 from opening.

[0051] As shown in FIG. 5 , the distance between the solder resist 73 and the solder resist 74 in the Y direction is L3, and the width of the semiconductor chip 3a is L4. The width of the gate electrode 31 in the Y direction is w2, and the width of the area occupied by the lower end of the pin terminal 51a relative to the gate electrode 31 is d2. Similarly, the width of the source electrode 32 in the Y direction is w2, and the width of the area occupied by the lower end of the pin terminal 52a relative to the gate electrode 31 is d2. L3, L4, w2, and d2 satisfy the relationship (L3-L4)<(w2-d2). (L3-L4) is the distance allowed for movement of the semiconductor chip 3a in the Y direction, i.e., the play of the semiconductor chip 3a in the Y direction. (w2-d2) is the distance allowed for movement of the gate electrode 31 and the source electrode 32 relative to the pin terminals 51a and 52a in the Y direction, i.e., the play of the gate electrode 31 and the source electrode 32 in the Y direction. By making the play of the semiconductor chip 3a smaller than the play of the gate electrode 31 and the source electrode 32, even if the semiconductor chip 3a moves along the Y direction during reflow, the bond between the pin terminal 51a and the gate electrode 31 can be prevented from opening, and the bond between the pin terminal 52a and the source electrode 32 can be prevented from opening.

[0052] Two pin terminals 52a are provided along the Y direction. In this manner, when a plurality of pin terminals 52a are provided, the width of the region occupied by the lower ends of the plurality of pin terminals 52a relative to the gate electrode 31 is defined as d2. For example, the width d2 may be defined as the distance from a tangent line to a portion of the pin terminal closest to the solder resist 73 of the plurality of pin terminals 52a closest to the solder resist 73 to a tangent line to a portion of the pin terminal closest to the solder resist 74 of the pin terminal closest to the solder resist 74. Similarly, when a plurality of pin terminals 52a are provided along the X direction, the width of the region occupied by the lower ends of the plurality of pin terminals 52a relative to the gate electrode 31 may be defined as d1. The widths d1 and d2 of the region occupied by the lower ends of the pin terminals 51a, 52a, etc. relative to the electrode 30 are set smaller than the widths w1 and w2 of the electrode 30.

[0053] Two electrodes, a gate electrode 31 and a source electrode 32, are provided on the top surface of the semiconductor chip 3a. The widths w1 and w2 and areas of the gate electrode 31 and the source electrode 32 may be determined, for example, according to the number of pin terminals to be joined. Generally, since a single pin terminal is connected to the gate electrode 31, the area of ​​the gate electrode 31 is often set smaller than the area of ​​the source electrode 32. Furthermore, when the widths L2 and L4 of the semiconductor chip 3a are reduced, the widths w1 and w2 and areas of the gate electrode 31 and the source electrode 32 may also be reduced.

[0054] <Method for Manufacturing Solder Resist> The method for manufacturing the solder resist 7 will be described below. As shown in FIG. 1 , the solder resist 7 is a laser resist formed by irradiating the upper surfaces of the upper conductor layers 12a and 12b with laser light. Two examples of the wavelength, power, and frequency of the laser, and the scanning conditions of the laser light, are shown below. The manufacturing conditions of the solder resist 7 may be changed depending on the material of the upper surfaces of the upper conductor layers 12a and 12b. The solder resists 71, 72, 73, and 74 are configured by arranging multiple lines formed by laser irradiation, for example, along the longitudinal direction. Condition Example 1: Wavelength: 1064 (nm) Power: 5 (W) Frequency: 5 (kHz) Scanning Speed: 8 (mm / s) Line Pitch: 100 (μm) Condition Example 2: Wavelength: 532 (nm) Power: 4.8 (W) Frequency: 30 (kHz) Scanning Speed: 300 (mm / s) Line Pitch: 10 (μm)

[0055] When the upper surfaces of the upper conductor layers 12a and 12b are irradiated with laser light, irregularities are formed on the upper surfaces of the upper conductor layers 12a and 12b, reducing the solder wettability. In addition, an oxide film is formed on the upper surfaces of the upper conductor layers 12a and 12b, reducing the solder wettability.

[0056] Comparative Example A comparative example shown in FIG. 6 will now be described. In the semiconductor device according to the comparative example, solder resist 7 is not formed on the upper surfaces of the upper conductor layers 12a and 12b. During reflow, if the flux components in the solder gasify, bubbles may form or the solder may be ejected to the outside. The semiconductor chip 3a may move due to the influence of the gasified flux components. Furthermore, if the solder wettability of the upper conductor layers 12a and 12b is uneven, the solder may move toward the wetter side, causing the semiconductor chip 3a to move along with the solder. If the semiconductor chip 3a moves too much during reflow, the solder may solidify without maintaining the relative positional relationship between the pin terminals and the electrodes. This may result in an open bond between the pin terminal 51a and the gate electrode 31, or an open bond between the pin terminal 52a and the source electrode 32. In particular, when the semiconductor chip 3a is constructed using a compound semiconductor substrate such as SiC, the chip dimensions may be smaller than those of a silicon chip, for example, to prevent crystal defects. As the chip dimensions become smaller, there is a possibility that the widths w1 and w2 and area of ​​the gate electrode 31 and source electrode 32, the amount of play of the electrode 30, etc. will be affected. Furthermore, when the gate electrode 31 and source electrode 32 are connected by pin terminals, the amount of play of the electrode 30 is more limited than when the gate electrode 31 and source electrode 32 are connected by wire bonding. When the wiring connection is made by wire bonding, even if the positions of the gate electrode 31 and source electrode 32 are slightly misaligned, the positions can be recognized by a camera or the like, so the margin for the amount of play of the electrode 30 is larger than when pin terminals are used.

[0057] In contrast, according to the semiconductor device according to the first embodiment of the present technology, as shown in Figures 3 and 5, the solder resist 7 is provided on the upper surfaces of the upper conductor layers 12a and 12b, so that excessive movement of the semiconductor chip 3a during reflow can be restricted. This makes it possible to prevent a large change in the positional relationship between the pin terminals 51a and 52a and the gate electrode 31 and the source electrode 32. This also makes it possible to prevent the junction between the pin terminal 51a and the gate electrode 31 from becoming open, and to prevent the junction between the pin terminal 52a and the source electrode 32 from becoming open.

[0058] Furthermore, according to the semiconductor device of the first embodiment of the present technology, the play of the semiconductor chip 3 a is set smaller than the play of the gate electrode 31 and the source electrode 32, so that the junction between the pin terminal 51 a and the gate electrode 31 can be prevented from becoming open, and the junction between the pin terminal 52 a and the source electrode 32 can be prevented from becoming open.

[0059] Furthermore, according to the semiconductor device according to the first embodiment of the present technology, a single ring is formed by connecting the solder resists 71, 72, 73, and 74. The solder resist 7 surrounds the semiconductor chip 3a without any gaps, which can suppress the amount of solder 2a that wets and spreads from the periphery of the semiconductor chip 3a, preventing the solder 2a from becoming too thin and suppressing deterioration of its shape.

[0060] Furthermore, according to the semiconductor device according to the first embodiment of the present technology, the solder resists 71, 72, 73, and 74 are laser resists. The laser resist has an uneven surface, which can improve the adhesion between the sealing member 8 and the upper conductor layers 12 a and 12 b.

[0061] Furthermore, according to the semiconductor device of the first embodiment of the present technology, the solder resists 71, 72, 73, and 74 are formed using laser light, so that if the layout of the solder resist needs to be changed, it can be accommodated by changing the numerical data, thereby preventing a significant increase in production costs.

[0062] 7, the semiconductor device according to the first modification of the first embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 1 in that the solder resist 7 includes solder resists 71 and 72 provided along the X direction and solder resists 73 and 74 provided along the Y direction, but only includes solder resists 71 and 72 provided along the X direction. The other configurations of the semiconductor device according to the first modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore redundant description will be omitted.

[0063] According to the semiconductor device of the first modification of the first embodiment, excessive movement of the semiconductor chip 3a in the X direction during reflow can be restricted, thereby preventing a large change in the positional relationship in the X direction between the pin terminals 51a, 52a and the gate electrode 31 and source electrode 32. The solder resist 7 may include only the solder resists 73, 74.

[0064] <Second Modification of First Embodiment> As shown in FIG. 8 , a semiconductor device according to a second modification of the first embodiment differs from the semiconductor device according to the first modification of the first embodiment shown in FIG. 7 in that one of the solder resists 71, 72 is linear and extends along the Y direction, and the other is dot-shaped. In FIG. 8 , the solder resist 71 is linear and extends along the Y direction, and the solder resist 72 is dot-shaped. The solder resists 71, 72 face each other. Other configurations of the semiconductor device according to the second modification of the first embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore, redundant description will be omitted. The semiconductor device according to the second modification of the first embodiment also has the same effects as the semiconductor device according to the first modification of the first embodiment.

[0065] <Third Modification of First Embodiment> As shown in FIG. 9 , a semiconductor device according to a third modification of the first embodiment differs from the semiconductor device according to the second modification of the first embodiment shown in FIG. 8 in that it includes solder resists 73 and 74, one of which is linear and extends along the X-direction, while the other is dot-shaped. Other configurations of the semiconductor device according to the third modification of the first embodiment are similar to those of the semiconductor device according to the second modification of the first embodiment, and therefore redundant description will be omitted. Furthermore, in the drawings from FIG. 9 onward, various dimensions are similar to those of the first embodiment, and therefore will not be described. In FIG. 9 , the solder resist 74 is linear and extends along the X-direction, and the solder resist 73 is dot-shaped. The solder resists 73 and 74 face each other.

[0066] The semiconductor chip 3a has corners 33 and 34 along the diagonal direction. The solder resists 71 and 74 are not connected to each other and are arranged along the sides that form the corner 33. The solder resists 72 and 73 are not connected to each other and are arranged near the corner 34. The semiconductor device according to the third modification of the first embodiment can prevent the semiconductor chip 3a from moving too far in the X and Y directions during reflow. This can prevent the positional relationships between the pin terminals 51a and 52a and the gate electrode 31 and source electrode 32 from changing significantly. This can prevent the junction between the pin terminal 51a and the gate electrode 31 from becoming open, and the junction between the pin terminal 52a and the source electrode 32 from becoming open.

[0067] <Fourth Modification of First Embodiment> As shown in FIG. 10 , a semiconductor device according to a fourth modification of the first embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 3 in that solder resist 71 is bonded (connected) to only one of solder resists 73 and 74, and solder resist 72 is bonded (connected) to only the other of solder resists 73 and 74. In FIG. 10 , solder resist 71 is bonded to solder resist 74, and solder resist 72 is bonded to solder resist 73. Other configurations of the semiconductor device according to the fourth modification of the first embodiment are similar to those of the semiconductor device according to the first embodiment, so redundant description will be omitted. Note that solder resists 71 and 72 do not necessarily have to face each other. The distance L1 between solder resists 71 and 72 along the X direction can be determined by using a line extending from the sides of solder resists 71 and 72 closest to semiconductor chip 3a. Similarly, solder resists 73 and 74 do not necessarily have to face each other.

[0068] In the semiconductor device according to the fourth modification of the first embodiment, the solder resists 71 and 74 prevent the corners 33 of the semiconductor chip 3a from moving too far, and the solder resists 72 and 73 prevent the corners 34 of the semiconductor chip 3a from moving too far. This prevents a large change in the positional relationship between the pin terminals 51a and 52a and the gate electrode 31 and the source electrode 32. This prevents the junction between the pin terminal 51a and the gate electrode 31 from opening, and prevents the junction between the pin terminal 52a and the source electrode 32 from opening.

[0069] 11, a semiconductor device according to a fifth modification of the first embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 3 in that it includes a plurality of semiconductor chips 3 arranged side by side, and that the plurality of semiconductor chips 3 share at least a portion of solder resists 71, 72, 73, and 74. FIG. 11 shows semiconductor chips 3a and 3e arranged side by side. The other configuration of the semiconductor device according to the fifth modification of the first embodiment is the same as that of the semiconductor device according to the first embodiment, and therefore a duplicated description will be omitted.

[0070] The semiconductor chips 3a and 3e are arranged side by side along the Y direction. The solder resists 71 and 72 provided for the semiconductor chips 3a and 3e are connected together along the Y direction and are shared by the multiple semiconductor chips 3a and 3e. A single solder resist 75 extending along the X direction is provided between the semiconductor chip 3a and the semiconductor chip 3e. The solder resist 75 is shared by the multiple semiconductor chips 3a and 3e. The solder resist 75 functions as a solder resist 74 for the semiconductor chip 3a and as a solder resist 73 for the semiconductor chip 3e.

[0071] The semiconductor device according to the fifth modification of the first embodiment has the same effects as the semiconductor device according to the first embodiment. Note that a solder resist 73 may be provided on the underside of the semiconductor chip 3a. Also, a solder resist 74 may be provided on the upper side of the semiconductor chip 3e.

[0072] 12, the semiconductor device according to the sixth modification of the first embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 3 in that at least some of the solder resists 71, 72, 73, and 74 are interrupted by slits, and at least some of the solder resists 71, 72, 73, and 74 are provided in duplicate. The other configurations of the semiconductor device according to the sixth modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore redundant explanations will be omitted.

[0073] Solder resists 71, 72, 73, and 74 are provided in two layers. The inner portions of the two layers are called solder resists 71, 72, 73, and 74, and the outer portions are called solder resists 71A, 72A, 73A, and 74A. Solder resists 71, 72, 73, and 74 are partially interrupted. The interrupted portions of solder resists 71, 72, 73, and 74 are called slits 9. Similarly, solder resists 71A, 72A, 73A, and 74A are partially interrupted. The interrupted portions of solder resists 71A, 72A, 73A, and 74A are called slits 9A. Solder resists 71A, 72A, 73A, and 74A are arranged to face slit 9. Solder resists 71, 72, 73, and 74 are arranged to face slit 9A.

[0074] The semiconductor device according to the sixth modification of the first embodiment has the same effects as the semiconductor device according to the first embodiment. Furthermore, according to the semiconductor device according to the sixth modification of the first embodiment, the solder resists 71, 72, 73, and 74 are provided in two layers, so that even if the slits 9 and 9A are present, the solder 2a and 2e can be prevented from spreading too much. This prevents the thickness of the solder 2a and 2e from becoming too thin, and prevents deterioration of the shape.

[0075] <Seventh Modification of First Embodiment> As shown in FIG. 13 , the semiconductor device according to the seventh modification of the first embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 3 in that each of the solder resists 71, 72, 73, and 74 is configured by connecting a plurality of dot-shaped solder resists in a line. The solder resists 71, 72, 73, and 74 are connected to form a ring. Other configurations of the semiconductor device according to the seventh modification of the first embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore redundant description will be omitted. The semiconductor device according to the seventh modification of the first embodiment also has the same effects as the semiconductor device according to the first embodiment.

[0076] Eighth Modification of First Embodiment The semiconductor device according to the eighth modification of the first embodiment differs from the semiconductor device according to the sixth modification of the first embodiment shown in FIG. 12 in that, as shown in FIG. 14 , each of the solder resists 71, 72, 73, and 74 is configured by arranging multiple dot-shaped solder resists in a line. The gaps between the dot-shaped solder resists correspond to slits 9 and 9A. Other configurations of the semiconductor device according to the eighth modification of the first embodiment are similar to those of the semiconductor device according to the sixth modification of the first embodiment, and therefore redundant description will be omitted. The semiconductor device according to the eighth modification of the first embodiment has the same effects as the semiconductor device according to the sixth modification of the first embodiment. The solder resists 71A, 72A, 73A, and 74A do not necessarily have to face the slit 9. The solder resists 71, 72, 73, and 74 do not necessarily have to face the slit 9A.

[0077] As described above, the present invention has been described by the first embodiment and its modifications, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0078] For example, the configurations disclosed in the first embodiment and its modifications can be combined as appropriate within the scope of not causing any contradiction. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description.

[0079] 1 Insulated circuit board 3, 3a, 3b, 3c, 3d, 3e, 3f, 3g Semiconductor chip 6 Printed circuit board 7, 71, 71A, 72, 72A, 73, 73A, 74, 74A, 75 Solder resist 9, 9A Slit 30 Electrode 31 Gate electrode 32 Source electrode 51, 51a, 51b, 51c, 52, 52a, 52a1, 52a2 Pin terminal d1, d2, L2, L4, w1, w2 Width L1, L3 Spacing

Claims

1. A semiconductor device comprising: an insulated circuit board; a semiconductor chip mounted on the insulated circuit board using solder and having electrodes on its upper surface; a printed circuit board arranged above the semiconductor chip; pin terminals inserted into the printed circuit board and joined to the electrodes via solder; and first and second solder resists provided on the upper surface of the insulated circuit board and spaced apart along a first direction, wherein the semiconductor chip is located between the first solder resist and the second solder resist along the first direction.

2. The semiconductor device according to claim 1, wherein, when the distance between the first solder resist and the second solder resist along the first direction is L1, the width of the semiconductor chip is L2, the width of the electrode is w1, and the width of the area occupied by the pin terminal relative to the electrode is d1, the relationship (L1-L2)<(w1-d1) is satisfied.

3. The semiconductor device according to claim 1 or 2, further comprising: a third solder resist and a fourth solder resist provided on the upper surface of the insulating circuit board and spaced apart along a second direction intersecting the first direction; and the semiconductor chip is located between the third solder resist and the fourth solder resist along the second direction.

4. The semiconductor device according to claim 3, wherein, when the distance between the third solder resist and the fourth solder resist along the second direction is L3, the width of the semiconductor chip is L4, the width of the electrode is w2, and the width of the area occupied by the pin terminal relative to the electrode is d2, the relationship (L3 - L4) < (w2 - d2) is satisfied.

5. The semiconductor device according to claim 3, wherein the first solder resist, the second solder resist, the third solder resist, and the fourth solder resist are connected to form a ring.

6. The semiconductor device according to claim 5, wherein at least a portion of the first solder resist, the second solder resist, the third solder resist, and the fourth solder resist has a slit.

7. The semiconductor device according to claim 6, wherein at least a portion of the first solder resist, the second solder resist, the third solder resist, and the fourth solder resist is provided in duplicate.

8. The semiconductor device according to claim 1 or 2, wherein one of the first solder resist and the second solder resist extends in the second direction, and the other is in a dot shape.

9. The semiconductor device according to claim 3, wherein one of the first solder resist and the second solder resist extends along the second direction and the other is in a dot shape, and one of the third solder resist and the fourth solder resist extends along the first direction and the other is in a dot shape.

10. The semiconductor device according to claim 3, wherein the first solder resist is bonded to only one of the third solder resist and the fourth solder resist, and the second solder resist is bonded to only the other of the third solder resist and the fourth solder resist.

11. The semiconductor device according to claim 3, wherein each of the first solder resist, the second solder resist, the third solder resist, and the fourth solder resist is composed of a plurality of dot-shaped solder resists.

12. The semiconductor device according to claim 3, comprising a plurality of the semiconductor chips arranged side by side, the plurality of semiconductor chips sharing at least a portion of the first solder resist, the second solder resist, the third solder resist, and the fourth solder resist.

13. The semiconductor device according to claim 3, wherein each of the first solder resist, the second solder resist, the third solder resist, and the fourth solder resist is a laser resist formed by irradiating the upper surface of the insulating circuit board with laser light.

14. The semiconductor device according to claim 1 or 2, wherein the electrode is a gate electrode or a source electrode.