Silicon carbide semiconductor device
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Filing Date
- 2026-04-01
- Publication Date
- 2026-07-03
AI Technical Summary
Conventional silicon carbide semiconductor devices face challenges in achieving low resistance and high breakdown voltage due to complex structures that hinder the reduction of cell pitch, leading to issues like electric field concentration and increased switching loss.
A silicon carbide semiconductor device with a parallel pn region and trench structure, featuring a shallower p-type region and deeper p-type connection regions, along with a high-concentration n-type drift region, reduces cell pitch and drift resistance, enhancing breakdown voltage and reducing switching loss.
The proposed structure allows for shorter cell pitch, achieving high breakdown voltage and low resistance while minimizing switching loss and electric field concentration.
Abstract
Description
Silicon carbide semiconductor device
[0001] This disclosure relates to silicon carbide semiconductor devices.
[0002] A known semiconductor device includes a carrier transport layer of a first conductivity type, an injection control region of a second conductivity type provided on the upper surface of the carrier transport layer, an upper buried region of the second conductivity type in contact with the lower surface of the injection control region, and a lower buried region of the second conductivity type in contact with the lower surface of the upper buried region and the bottom surface of the trench, the lower buried regions being separated from each other between the trenches via the carrier transport layer (see, for example, Patent Document 1 listed below). Also known is a super-junction silicon carbide semiconductor device in which a lower p-type column region and an upper p-type column region are arranged to intersect, thereby eliminating fluctuations in on-resistance even when pattern misalignment occurs, thereby suppressing performance variations (see, for example, Patent Document 2 listed below).
[0003] International Publication No. 2022 / 137789 Patent No. 7293750
[0004] However, in conventional semiconductor devices, the structure of each cell is complex, making it difficult to shorten the cell pitch. This makes it difficult to achieve low resistance, especially in SiC, which has low channel mobility. Furthermore, the complex structure narrows the p-type region of the pn junction, making it more susceptible to electric field concentration and resulting in a decrease in breakdown voltage.
[0005] The present disclosure aims to provide a silicon carbide semiconductor device that can reduce the cell pitch, achieve high breakdown voltage and low resistance, and reduce drift resistance in order to solve the problems of the prior art described above.
[0006] In order to solve the above-described problems and achieve the object of the present disclosure, a silicon carbide semiconductor device according to this disclosure has the following features: a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on a front surface of a silicon carbide semiconductor substrate of a first conductivity type; a parallel pn region in which first column regions of a first conductivity type and second column regions of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface is provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; a second semiconductor layer of a second conductivity type is provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; a first semiconductor region of a first conductivity type is selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate; and a second semiconductor region of a second conductivity type is selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate, in contact with the first semiconductor region and the second semiconductor layer. A trench is provided that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer. A gate electrode is provided within the trench with a gate insulating film interposed therebetween. A high-concentration region of a second conductivity type is provided within the first semiconductor layer at a position facing the trench in the depth direction. A connection region of a second conductivity type is selectively provided within the first semiconductor layer, on the second semiconductor layer side of the high-concentration region and on the silicon carbide semiconductor substrate side of the second semiconductor layer, in contact with the high-concentration region and the second semiconductor layer. First electrodes are provided on surfaces of the first semiconductor region and the second semiconductor region. A second electrode is provided on a back surface of the silicon carbide semiconductor substrate. The second semiconductor regions are periodically arranged in the longitudinal direction of the trench, and the connection regions are periodically arranged in the longitudinal direction of the trench in regions that do not overlap with the second semiconductor region in a plan view.
[0007] According to the above disclosure, the p + The p-type region (high concentration region) is shallower than the p-type region and deeper than the p-type base region (second semiconductor layer). + A type connection region (connection region) is provided. + Type domain and p ++The area of connection with the contact region can be increased, the fluctuation of the feedback capacitance can be suppressed, and the SW loss can be reduced. + The p-type connection region reduces the area of the p-type base region exposed to the drain electrode, making it difficult for a high voltage to be applied to the p-type base region, and making it possible to increase the breakdown voltage. + A pn parallel region with an SJ structure is formed under the type region. - The n-type drift region (first semiconductor layer) is doped with a high impurity concentration. - This allows the thickness of the mold drift region to be reduced, thereby reducing the drift resistance.
[0008] According to the silicon carbide semiconductor device according to the present disclosure, the cell pitch can be shortened to achieve high breakdown voltage and low resistance, and drift resistance can be reduced.
[0009] FIG. 1 is a perspective view showing a structure of a silicon carbide semiconductor device according to a first embodiment. FIG. 2A is a cross-sectional view taken along line A-A' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2B is a cross-sectional view taken along line B-B' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2C is a cross-sectional view taken along line C-C' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2D is a cross-sectional view taken along line C-C' of FIG. 1 showing another structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3A is a surface D plan view of FIGS. 2A to 2C showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3B is a depth E plan view of FIGS. 2A to 2C showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3C is a depth F plan view of FIGS. 2A to 2C showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3D is a depth G plan view of FIGS. 2A to 2C showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 4 is a perspective view showing the structure of a silicon carbide semiconductor device according to a second embodiment. FIG. 5 is an A-A' cross-sectional view of FIG. 4 showing the structure of a silicon carbide semiconductor device according to a second embodiment. FIG. 6 is a B-B' plan view of FIG. 5 showing the structure of a silicon carbide semiconductor device according to the second embodiment. FIG. 7 is a perspective view showing the structure of a silicon carbide semiconductor device according to a third embodiment. FIG. 8 is an A-A' cross-sectional view of FIG. 7 showing the structure of a silicon carbide semiconductor device according to the third embodiment. FIG. 9 is a B-B' plan view of FIG. 8 showing the structure of a silicon carbide semiconductor device according to the third embodiment. FIG. 10 is a perspective view showing the structure of a silicon carbide semiconductor device according to a fourth embodiment. FIG. 11 is an A-A' cross-sectional view of FIG. 10 showing the structure of a silicon carbide semiconductor device according to the fourth embodiment. FIG. 12 is a B-B' cross-sectional view of FIG. 10 showing the structure of a silicon carbide semiconductor device according to the fourth embodiment. FIG. 13 is a CC' plan view of FIGS. 11 and 12 showing the structure of a silicon carbide semiconductor device according to the fourth embodiment. FIG. 14 is an A-A' cross-sectional view of FIG. 16 showing the structure of a silicon carbide semiconductor device of a comparative example. Fig. 15 is a cross-sectional view taken along line BB' of Fig. 16 showing the structure of a silicon carbide semiconductor device of a comparative example. Fig. 16 is a perspective view showing the structure of a silicon carbide semiconductor device of a comparative example. Fig. 17 is a characteristic diagram showing the relationship between cell pitch and on-resistance of the silicon carbide semiconductor device according to the first embodiment.
[0010] Overview of Embodiments of the Present Disclosure In order to solve the above-described problems and achieve the object of the present disclosure, a silicon carbide semiconductor device according to the present disclosure has the following features. A first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on a front surface of a silicon carbide semiconductor substrate of a first conductivity type. A parallel pn region is provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate, in which first column regions of a first conductivity type and second column regions of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface. A second semiconductor layer of a second conductivity type is provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. A first semiconductor region of a first conductivity type is selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. A second semiconductor region of a second conductivity type is selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate, in contact with the first semiconductor region and the second semiconductor layer. A trench is provided that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer. A gate electrode is provided within the trench with a gate insulating film interposed therebetween. A high-concentration region of a second conductivity type is provided within the first semiconductor layer at a position facing the trench in the depth direction. A connection region of a second conductivity type is selectively provided within the first semiconductor layer, on the second semiconductor layer side of the high-concentration region and on the silicon carbide semiconductor substrate side of the second semiconductor layer, in contact with the high-concentration region and the second semiconductor layer. First electrodes are provided on surfaces of the first semiconductor region and the second semiconductor region. A second electrode is provided on a back surface of the silicon carbide semiconductor substrate. The second semiconductor regions are periodically arranged in the longitudinal direction of the trench, and the connection regions are periodically arranged in the longitudinal direction of the trench in regions that do not overlap with the second semiconductor region in a plan view.
[0011] According to the above disclosure, the p + The p-type region (high concentration region) is shallower than the p-type region and deeper than the p-type base region (second semiconductor layer). + A type connection region (connection region) is provided. + Type domain and p ++The area of connection with the contact region can be increased, the fluctuation of the feedback capacitance can be suppressed, and the SW loss can be reduced. + The p-type connection region reduces the area of the p-type base region exposed to the drain electrode, making it difficult for a high voltage to be applied to the p-type base region, and making it possible to increase the breakdown voltage. + A pn parallel region with an SJ structure is formed under the type region. - The n-type drift region (first semiconductor layer) is doped with a high impurity concentration. - This allows the thickness of the mold drift region to be reduced, thereby reducing the drift resistance.
[0012] Moreover, the silicon carbide semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the second column region is in contact with a surface of the high concentration region facing the silicon carbide semiconductor substrate, and is provided on the silicon carbide semiconductor substrate side of the high concentration region.
[0013] Moreover, the silicon carbide semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the second column region is in contact with the surface of the connection region facing the silicon carbide semiconductor substrate, and is provided on the silicon carbide semiconductor substrate side of the connection region.
[0014] Moreover, the silicon carbide semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the second column region is in contact with the surface of the second semiconductor region facing the silicon carbide semiconductor substrate, and is provided on the silicon carbide semiconductor substrate side of the second semiconductor region.
[0015] Furthermore, the silicon carbide semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the second column region is in contact with surfaces of the high concentration region and the connection region facing the silicon carbide semiconductor substrate, and is provided on the silicon carbide semiconductor substrate side of the high concentration region and the connection region.
[0016] Moreover, in the silicon carbide semiconductor device according to the present disclosure, in the above disclosure, the width of the second column region is the same as the width of a region where the second column region contacts the surface opposite to the silicon carbide semiconductor substrate.
[0017] Moreover, in the silicon carbide semiconductor device according to the present disclosure, in the above disclosure, the width of the second column region is narrower than the width of a region where the second column region contacts the surface opposite to the silicon carbide semiconductor substrate.
[0018] Furthermore, in the silicon carbide semiconductor device disclosed above, the first column regions and the second column regions have a periodic repeat pitch of 1.8 μm to 2.2 μm.
[0019] <Findings underlying the present disclosure> First, the problems with the semiconductor device of the comparative example will be described. Silicon carbide (SiC) is expected to be a next-generation semiconductor material to replace silicon (Si). A semiconductor element using silicon carbide as a semiconductor material (hereinafter referred to as a silicon carbide semiconductor device) has various advantages compared to conventional semiconductor elements using silicon as a semiconductor material, such as the ability to reduce the resistance of the element in the on-state to one-hundredth of that of conventional semiconductor elements using silicon as a semiconductor material, and the ability to be used in higher temperature environments (200°C or higher). This is due to the characteristics of the material itself, namely, the band gap of silicon is about three times larger than that of silicon, and the dielectric breakdown field strength is nearly one order of magnitude greater than that of silicon.
[0020] To date, commercially available silicon carbide semiconductor devices include Schottky barrier diodes (SBDs) and vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) having a planar gate structure or a trench gate structure.
[0021] The planar gate structure is a MOS gate structure in which a flat MOS gate is provided on the front surface of a semiconductor substrate. The trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on the front surface of a semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed along the sidewall of the trench in a direction perpendicular to the front surface of the semiconductor substrate. This allows for a higher density of unit cells (element constituent units) per unit area and a higher current density per unit area compared to a planar gate structure in which a channel is formed along the front surface of the semiconductor substrate, which is advantageous in terms of cost.
[0022] FIG. 14 is a cross-sectional view taken along line AA' in FIG. 16 showing the structure of a silicon carbide semiconductor device of a comparative example. FIG. 15 is a cross-sectional view taken along line BB' in FIG. 16 showing the structure of a silicon carbide semiconductor device of a comparative example. FIG. 16 is a perspective view showing the structure of a silicon carbide semiconductor device of a comparative example. A semiconductor device 110 of a comparative example shown in FIGS. 14 to 16 is a vertical MOSFET having a trench gate structure in a semiconductor substrate (semiconductor chip) 140 made of silicon carbide. In FIGS. 14 to 16, only the active region is shown, and the edge termination region is omitted.
[0023] The semiconductor substrate 140 is made of silicon carbide. + On the front surface of the starting substrate 141, - n-type drift region 112 - The semiconductor substrate 140 is formed by epitaxially growing an n-type silicon carbide layer 142. - The main surface on the side of the silicon carbide layer 142 is the front surface, and + The main surface on the mold starting substrate 141 side is referred to as the back surface. + A drain electrode 145 is provided over the entire area of the back surface of the starting substrate 141. + The starting substrate 141 is n + The doped drain region 111 is a doped region.
[0024] n - n type drift region 112 +An n-type current diffusion region 120 is provided on the surface opposite to the silicon carbide substrate 111. In addition, a p-type current diffusion region 120 is provided in the n-type current diffusion region 120 at a position facing the bottom of the trench 116 in the depth direction. + The MOS gate of the trench gate structure has a p-type base region 113, an n-type base region 121, and a n-type base region 122. + type source region 114, p ++ The semiconductor device is composed of a contact region 115, a trench 116, a gate insulating film 117, and a gate electrode 118. ++ The p-type contact region 115 + A mold area 122 is optionally provided.
[0025] An interlayer insulating film 119 is provided on the gate electrode 118, and an n-type insulating film is formed in an opening of the interlayer insulating film 119. + type source region 114 and p ++ An ohmic electrode 143 is provided in contact with the type contact region 115. A barrier metal 138 that prevents diffusion of metal atoms toward the gate electrode 118 is provided on the ohmic electrode 143 and the interlayer insulating film 119. A source electrode 144 is provided on the barrier metal 138.
[0026] p + The n-type regions 121 and 122 are fixed to the potential of the source electrode 144, and have the function of depleting (or depleting the n-type current diffusion region 120, or both) when the MOSFET (silicon carbide semiconductor device 110) is turned off, thereby mitigating the electric field applied to the gate insulating film 117. + The p-type region 121 is provided apart from the p-type base region 113 and faces the bottom surface of the trench 116 in the depth direction. + The mold region 121 is p + The p-type region 122 is partially connected to the source electrode 144. + 15 shows a cross section of a portion where the mold region 122 is not provided. + A mold region 122 is provided, and p + The mold region 122 and p + 1 shows a cross section of the portion where the mold region 121 is connected.
[0027] In this way, p+ The p between the trenches 116 provided at the same depth as the mold region 121 + The type region is eliminated, and the JFET structure per cell (the structure of the portion where the current flows between the trenches 116) is unified. + Type region 121 and p ++ The connection to the contact region 115 is made by a deep p-type contact in the center between the trenches 116. + This is achieved by creating a mold area 122 .
[0028] This simplifies the structure per cell, thereby shortening the cell pitch, and shortening the cell pitch makes it possible to reduce the resistance of a SiC MOSFET with low channel mobility. + The width of the mold region 121 can be increased, and the flat portion of the pn junction becomes wider, thereby alleviating electric field concentration and increasing the breakdown voltage.
[0029] However, in this structure, the p + Type region 121 and p ++ p under the contact region 115 + The connection portion of the p-type region 122 becomes thinner. Therefore, when a high voltage is applied to the drain electrode 145 and the depletion region expands, + Type region 121 and p + The neutral region of the type region 122 separates, and p + The p-type region 121 is electrically floating, causing a sudden change in feedback capacitance, which in turn increases switching loss. + The electrically floating of the p-type region 121 causes problems such as application of a high voltage to the gate insulating film 117. In addition, since the area of the p-type base region 113, which is the channel region, exposed to the drain electrode 145 is large, a high voltage is applied to the channel, causing a problem of a decrease in breakdown voltage.
[0030] Preferred embodiments of the silicon carbide semiconductor device according to the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate higher and lower impurity concentrations than layers and regions not prefixed with these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted. It is preferable that the terms "same" or "equivalent" be used to include variations within 5% in consideration of variations in manufacturing.
[0031] First Embodiment A structure of a silicon carbide semiconductor device according to a first embodiment will be described. FIG. 1 is a perspective view showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2A is a cross-sectional view taken along line A-A' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2B is a cross-sectional view taken along line B-B' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2C is a cross-sectional view taken along line C-C' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2D is a cross-sectional view taken along line C-C' of FIG. 1 showing another structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3A is a plan view at a depth D of FIGS. 2A to 2C showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3B is a plan view at a depth E of FIGS. 2A to 2C showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3C is a plan view at a depth F of FIGS. 2A to 2C showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3D is a plan view at a depth G of FIGS. 2A to 2C showing the structure of the silicon carbide semiconductor device according to the first embodiment. A silicon carbide semiconductor device 10 according to the first embodiment shown in FIGS. 1 to 3D is a vertical MOSFET having a trench gate structure on a semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC).
[0032] 1 to 3D show only the active region through which current flows in the on-state, and omit the edge termination region, which is surrounded by a substantially rectangular shape around the active region and has a breakdown voltage structure. The breakdown voltage structure functions to maintain a breakdown voltage by mitigating the electric field near the boundary between the active region and the edge termination region. The breakdown voltage is the limit voltage at which breakdown does not occur even if an avalanche breakdown occurs at the pn junction and the drain-source current increases.
[0033] A plurality of unit cells (functional units of an element) of the same structure (element structure) of the MOSFET are arranged adjacent to each other in parallel on the semiconductor substrate 40. The semiconductor substrate 40 is made of n-type silicon carbide. + On the front surface of a starting substrate (a silicon carbide semiconductor substrate of a first conductivity type) 41, - n-type drift region (first semiconductor layer of the first conductivity type) 12 - The semiconductor substrate 40 is formed by epitaxially growing an n-type silicon carbide layer 42. - The main surface on the silicon carbide layer 42 side is the front surface (first main surface), and + The main surface on the mold starting substrate 41 side is referred to as the back surface (second main surface).
[0034] n + The starting substrate 41 is n + The semiconductor substrate 40 is formed with n-type drain regions 11 to form the active regions. + On the starting substrate 41, - n-type drift region 12 - The n-type silicon carbide layer 42 is epitaxially grown in multiple stages. - The n-type drift region 12 - This is a portion of the silicon carbide layer 42 where no diffusion region is formed by ion implantation and the impurity concentration remains the same as during epitaxial growth. - The n-type drift region 12 + The substrate 41 is in contact with the active region and extends from the edge of the chip. - The silicon carbide layer 42 is formed by one-stage epitaxial growth, and the p-type base region 13 and the n-type + type source region 14, p ++ type contact region 15, n-type current diffusion region 20, p + Type region 21 and p+ The mold connection region 23 may be formed by ion implantation.
[0035] The active region of the first embodiment is provided with a trench gate structure. The trench gate structure includes a p-type base region (second semiconductor layer of the second conductivity type) 13, an n + p-type source region (first semiconductor region of the first conductivity type) 14, ++ The p-type base region 13, the n-type contact region 15, the n-type semiconductor region 16, the n-type gate insulating film 17, and the n-type gate electrode 18 are formed. + type source region 14 and p ++ The n-type contact region 15 - The p-type base region 13 is a diffusion region formed by ion implantation inside the n-type silicon carbide layer 42. - It is provided over the entire area between the mold drift region 12 and the substrate.
[0036] n + type source region 14 and p ++ The n-type contact regions 15 are selectively provided between the front surface of the semiconductor substrate 40 and the p-type base region 13, and are in contact with the p-type base region 13 at their bottoms (lower surfaces: rear surface side edges of the semiconductor substrate 40). + The source region 14 is p ++ The n-type contact region 15 is provided in contact with the n-type contact region 15. + type source region 14 and p ++ The mold contact region 15 is in ohmic contact with the ohmic electrode 43 on the upper surface (the end portion on the front surface side of the semiconductor substrate 40 ).
[0037] n - Between the n-type drift region 12 and the p-type base region 13, + The n-type current diffusion region 20 and the p-type current diffusion region 21 are formed at a deep position on the side of the n-type drain region 11 (the back surface side of the semiconductor substrate 40). + A p-type region (high concentration region of the second conductivity type) 21 is selectively provided on the p-type base region 13 side of the bottom surface of the trench 16. + The n-type current diffusion region 20, the p-type connection region (second conductivity type connection region) 23 are selectively provided. + Type region 21 and p+ The n-type connection region 23 - The n-type current diffusion region 20 is a diffusion region formed by ion implantation inside the p-type silicon carbide layer 42. + n than the mold region 21 + It is preferable that the ion implantation reaches a deep position on the side of the mold drain region 11 .
[0038] The n-type current diffusion region 20 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. + Type region 21 and p + The n-type current diffusion region 20 contacts the p-type base region 13 at the top and the n-type current diffusion region 21 at the bottom. - It contacts the mold drift region 12 .
[0039] The n-type current diffusion region 20 may not be provided. When the n-type current diffusion region 20 is not provided, the n-type current diffusion region 20 may be replaced by - The p-type drift region 12 reaches the p-type base region 13, + Type region 21 and p + The n - The mold drift region 12 contacts the gate insulating film 17 on a part of the sidewall of the trench 16 .
[0040] p + Type region 21 and p + The n-type connection region 23 is fixed to the potential of the source electrode 44 described later, and has the function of depleting (or depleting the n-type current diffusion region 20, or both) when the MOSFET (silicon carbide semiconductor device 10) is turned off, thereby mitigating the electric field applied to the gate insulating film 17. + The p-type region 21 is provided apart from the p-type base region 13 and faces the bottom surface of the trench 16 in the depth direction. + The type region 21 is p + The p-type connection region 23 is partially connected to the source electrode 44. +A type connection region 23 is provided, and p + Type region 21 and p + 2B and 2C show cross sections of the portion where the p + 1 shows a cross section of a portion where the mold connection region 23 is not provided.
[0041] p + The mold region 21 may be in contact with the gate insulating film 17 at the bottom of the trench 16, or may be spaced apart from the bottom of the trench 16. + The width of the mold region 21 is the same as or wider than the width of the trench 16. For example, p + The width of the mold region 21 is preferably at least twice as wide as the width of the trench 16. + By making the width of the mold region 21 wider than the width of the trench 16, p + The mold region 21 also faces the bottom corner portion (boundary between the sidewall and the bottom) of the trench 16 in the depth direction. + The effect of the type region 21 in alleviating the electric field near the bottom of the trench 16 is further enhanced. + The mold regions 21 are arranged in a stripe pattern in the longitudinal direction of the trench 16 in a plan view.
[0042] p + As shown in FIG. 2A, the type connection region 23 is + The p-type region 21 and the p-type base region 13 are connected to each other. + shallower than the p-type base region 21 (on the p-type base region 13 side), and deeper than the p-type base region 13 (on the n-type base region 13 side). + As shown in FIG. 3B, + The mold connection regions 23 are arranged in a stripe pattern between the trenches 16 in a direction perpendicular to the longitudinal direction of the trenches 16 (the short direction of the trenches 16) in a plan view, and are in contact with the trenches 16. By arranging the mold connection regions 23 in a stripe pattern between the trenches 16, p + The p-type connection region 23 and the p-type connection region 24 under the trench 16 + The area of contact with the mold region 21 increases, and the breakdown voltage can be improved. ++The mold contact regions 15 are periodically arranged in a dot pattern between the trenches 16 in the longitudinal direction of the trenches 16 in a plan view, and are not in contact with the trenches 16. ++ By forming contact region 15 in a dot shape, the characteristics of silicon carbide semiconductor device 10 can be improved.
[0043] Also, as shown in FIGS. 3A and 3B, p + The connecting region 23 is p ++ The contact region 15 is disposed in a region that does not overlap with the contact region 15. + A type connection region 23 is provided, and p ++ The region where the contact region 15 is not provided, as shown in FIG. + The type connection region 23 and p ++ The region where the contact region 15 is not provided, as shown in FIG. ++ A contact region 15 is provided, and p + Regions where no mold connection region 23 is provided are periodically arranged in the longitudinal direction of the trench 16 .
[0044] Also, in plan view, + The width of the mold connection region 23 in the direction perpendicular to the longitudinal direction of the trench 16 is p ++ It is preferable that the width of the contact region 15 is wider than the width of the trench 16 in the direction perpendicular to the longitudinal direction. + The p-type connection region 23 and the p-type connection region 24 under the trench 16 + The area of contact with the mold region 21 increases, and the pressure resistance can be improved.
[0045] In this way, the p + The p-type region 21 is shallower than the p-type base region 13. + By providing the mold connection region 23, + Type region 21 and p ++ The area of connection with the contact region 15 can be increased. This makes it possible to suppress the fluctuation of the feedback capacitance and reduce the SW loss. +The region of the p-type base region 13 exposed to the drain electrode 45 is reduced by the type connection region 23, making it difficult for a high voltage to be applied to the p-type base region 13, and making it possible to increase the breakdown voltage.
[0046] In this way, p + By providing the type connection region 23, the cell pitch can be shortened, and high breakdown voltage and low channel resistance can be achieved, but the drift resistance remains unchanged. A super junction (SJ) structure is known in which the drift layer is a parallel pn layer formed by alternately and repeatedly arranging n-type column regions and p-type column regions adjacent to each other in a direction parallel to the substrate main surface. In the SJ structure, by making the impurity concentrations contained in the p-type column region and the n-type column region approximately equal, a pseudo-non-doped layer is created in the off state, thereby achieving high breakdown voltage.
[0047] Therefore, in the first embodiment, n - The n-type drift region 12 and the n-type current diffusion region 20 are separated into a p-type region (p-type column region 24) and an n-type region (n-type column region sandwiched between the p-type column region 24) that extend in a direction perpendicular to the substrate main surface and have a narrow width in a plane parallel to the substrate main surface. - The SJ structure is a parallel structure (hereinafter referred to as a parallel pn structure 26) in which p-type column regions (second column regions of the second conductivity type) 24 and n-type column regions (first column regions of the first conductivity type) 25 that make up the parallel pn structure 26 are alternately arranged in a plane parallel to the main surface of the substrate. - 1 to 2D, the p-type column region 24 and the n-type column region 25 are regions with a higher impurity concentration corresponding to the n-type drift region 12. + The p-type column region 24 and the n-type column region 25 are formed in a semi-semi-junction structure so as not to reach the surface of the n-type drain region 11. + It may also have a full-SJ structure that reaches the surface of the type drain region 11. FIG.
[0048] As a charge balance of the parallel pn structure 26, the product (amount of impurities) of the width of the p-type column region 24 and the impurity concentration of the p-type column region 24 is approximately equal to the product (amount of impurities) of the width of the n-type column region 25 and the impurity concentration of the n-type column region 25. Specifically, the difference in the amount of impurities between the p-type column region 24 and the n-type column region 25 is set to within ±5%. Therefore, the parallel pn structure 26 can create a pseudo-non-doped layer in the off state to achieve high breakdown voltage, and both low on-resistance and high breakdown voltage characteristics can be obtained simultaneously. As a result, the n - The impurity concentration of the n-type drift region 12 is increased. - The thickness of the mold drift region 12 can be reduced, and the drift resistance can be reduced.
[0049] For the charge balance of the parallel pn structure 26, a p-rich structure in which the amount of p-type impurities is greater than the amount of n-type impurities is preferable. By making it p-rich, it is possible to increase the avalanche resistance. Furthermore, since the activation rate of p-type impurities in the p-type layer is low, a p-rich design in advance makes it easier to achieve charge balance in the parallel pn structure 26.
[0050] As shown in FIGS. 1 to 2C, in the first embodiment, the p-type column region 24 is + p so as to contact with the mold region 21 + 2A to 2C, the p-type column region 24 is formed below the p-type region 21. + The p-type column region 24 has a width similar to that of the p-type region 21. + 2D, the p-type column region 24 is + 1 when the p-type column region 24 is narrower than the p-type region 21. Although not shown, the AA' and BB' cross sections of FIG. 1 are similar. + By making the p-type column region 24 narrower than the p-type region 21, even if the position at which the p-type column region 24 is formed is shifted, the upper surface of the p-type column region 24 will not be + The p-type column region 24 comes into contact with the p-type region 21, and the tolerance to misalignment of the p-type column region 24 can be increased.
[0051] Although not shown, the parallel pn structure 26 is provided over the entire chip. For this reason, the parallel pn structure 26 is also provided in the edge termination region. In the edge termination region, the p-type base region 13 is not provided on the surface, and a guard ring is provided on the n-type column region 25 of the parallel pn structure 26 as a breakdown voltage structure.
[0052] Also, p + The impurity concentration of the p-type connection region 23 is higher than the impurity concentration of the p-type base region 13. + It is preferable that the impurity concentration is lower than that of the impurity concentration of the type region 21. ++ The impurity concentration of the contact region 15 is 1×10 20 / cm 3 Thus, the p-type base region 13, p + the p-type connection region 23, the p-type column region 24, and the p + The impurity concentration of the p-type base region 13 is higher than that of the p-type region 21. + The type connection region 23 and p + The impurity concentration of the mold region 21 is 9.0×10 16 / cm 3 It is preferable that the value is equal to or greater than 1. + The type connection region 23 and p + The mold region 21 has the same impurity concentration and is 1×10 18 / cm 3 The p-type column region 24 is preferably p + The type connection region 23 and p + The impurity concentration is the same as or lower than that of the mold region 21, and is 9.0×10 16 / cm 3 1x10 or more 18 / cm 3 It is preferable that:
[0053] The trench 16 has a depth of n + The n-type current diffusion region 20 (or the n-type current diffusion region 20 if the n-type current diffusion region 20 is not provided) penetrates the p-type source region 14 and the p-type base region 13. - The trench 16 extends to the p-type drift region 12. +The trench 16 may terminate within the mold region 21. The trench 16 extends, for example, in a stripe shape in a direction parallel to the front surface of the semiconductor substrate 40 and reaches the outer periphery (not shown) of the active region. A gate electrode 18 is provided within the trench 16 with a gate insulating film 17 interposed therebetween.
[0054] The interlayer insulating film 19 is provided on the front surface of the semiconductor substrate 40, and in particular covers the gate electrode 18. The ohmic electrode (first electrode) 43 is provided on a portion of the front surface of the semiconductor substrate 40 that is exposed through the contact hole of the interlayer insulating film 19. The ohmic electrode 43 is connected to the n-type ohmic electrode 43 on the front surface of the semiconductor substrate 40 through the contact hole of the interlayer insulating film 19. + type source region 14 and p ++ The ohmic electrode 43 is in ohmic contact with the contact region 15. The ohmic electrode 43 is, for example, a nickel silicide (NixSiy, x and y are any integers) film. + type source region 14 and p ++ The surface of the contact region 15 may be in ohmic contact with the 3C structure, which is cubic 3C-SiC.
[0055] The source electrode (first electrode) 44 is provided over the interlayer insulating film 19 so as to fill the contact hole in the interlayer insulating film 19. The source electrode 44 is provided over substantially the entire area of the center of the active region. The source electrode 44 is connected to the n-type ohmic electrode 43 via the ohmic electrode 43. + type source region 14, p ++ p-type contact region 15, p-type base region 13, p + Type region 21 and p + It is electrically connected to the mold connection region 23 .
[0056] A barrier metal 38 that prevents diffusion of metal atoms toward the gate electrode 18 may be provided on the ohmic electrode 43 and the interlayer insulating film 19. The barrier metal 38 is made of, for example, titanium (Ti) or titanium nitride (TiN). The barrier metal 38 may have a two-layer structure of Ti and TiN, with the Ti layer facing the semiconductor substrate 40. In this case, a source electrode 44 is provided on the barrier metal 38.
[0057] The drain electrode (second electrode) 45 is formed on the rear surface (n + The back surface of the starting substrate 41 is provided with n + type drain region 11 (n + ohmic contact with the starting substrate 41), + The gate electrode 12 is electrically connected to the drain region 11 .
[0058] (Method for manufacturing a silicon carbide semiconductor device according to the first embodiment) Next, a method for manufacturing a silicon carbide semiconductor device according to the first embodiment will be described. The silicon carbide semiconductor device according to the first embodiment is manufactured in the same manner as the method for manufacturing a silicon carbide semiconductor device of the comparative example. For example, it is manufactured as follows. First, n + Starting substrate (n + On the front surface of the mold starting wafer 41, n - The first n-th region that becomes the type drift region 12 - A silicon carbide layer is epitaxially grown.
[0059] Next, n - The n-type drift region 12 is formed from the surface thereof by photolithography and ion implantation of p-type impurities. - The p-type column region 24 is formed in the n-type drift region 12. - The second n-type drift region 12 is formed on the front surface thereof, and the second n-type current diffusion region 20 is formed on the front surface thereof. - Next, a second n-type silicon carbide layer is epitaxially grown. - A second n-type silicon carbide layer is formed on the surface of the silicon carbide layer by photolithography and ion implantation of p-type impurities. - Next, a second n-type column region 24 is formed in the silicon carbide layer by ion implantation of n-type impurities. - The lower part of the n-type current diffusion region 20 is formed in the silicon carbide layer. Here, the p-type column region 24 is formed by ion implantation. - From the surface of the silicon carbide layer - Alternatively, a trench may be formed that reaches the p-type drift region 12 and then filled with p-type impurities by epitaxial growth.
[0060] Next, the 2nth -The third n-type silicon carbide layer is formed on the front surface of the n-type silicon carbide layer. - A third n-type silicon carbide layer is epitaxially grown on the silicon carbide substrate. Then, a third n-type silicon carbide layer is formed on the silicon carbide substrate by photolithography and ion implantation of p-type impurities. - The silicon carbide layer is + Next, a third n-type region 21 is selectively formed by ion implantation of n-type impurities. - A central portion of an n-type current diffusion region 20 is formed in the silicon carbide layer.
[0061] Next, a fourth n-type current diffusion layer is formed on the central portion of the n-type current diffusion region 20. - Next, a fourth n-type silicon carbide layer is epitaxially grown by ion implantation of n-type impurities. - Next, a fourth n-type silicon carbide layer is formed on the upper portion of the n-type current diffusion region 20. - a 5n-th silicon carbide layer on the silicon carbide layer; - The n-type silicon carbide layer is then epitaxially grown. + On the starting substrate 41 - A semiconductor substrate (semiconductor wafer) 40 having a predetermined thickness is completed by laminating the silicon carbide layer 42 thereon.
[0062] Next, photolithography and p-type impurity ion implantation are performed to form a 5n-th - A p-type base region 13 is formed inside the silicon carbide layer. Next, a fifth n-type base region 13 is formed by photolithography and ion implantation of n-type impurities. - The surface region of the silicon carbide layer is + A type source region 14 is selectively formed.
[0063] Next, photolithography and ion implantation of p-type impurities are performed to form a fourth n-type - The silicon carbide layer has a p-type silicon carbide layer on the bottom surface. + The upper surface of the p-type semiconductor layer 11 is in contact with the p-type base region 13. + Next, a fifth n-type connection region 23 is formed by photolithography and ion implantation of p-type impurities. - The surface region of the silicon carbide layer is ++ A mold contact region 15 is selectively formed.
[0064] n -The portion of the silicon carbide layer 42 that is not ion-implanted and remains at the same impurity concentration as during epitaxial growth is n - This forms the n-type drift region 12. - A heat treatment is performed to activate the impurities ion-implanted into the silicon carbide layer 42. The heat treatment for activating the impurities is performed in the first to fifth n-th steps. - This may be done each time impurity ions are implanted into the silicon carbide layer, or may be done all at once. Next, trenches 16, gate insulating films 17 and gate electrodes 18 are formed by a general method.
[0065] Next, an interlayer insulating film 19 is formed on the front surface of the semiconductor substrate 40. Next, a source electrode 44, a gate pad (not shown), a passivation film (surface protection film: not shown), and a drain electrode 45 are formed by a typical method. The portion of the source electrode 44 exposed in the opening of the passivation film becomes the source pad. Thereafter, the semiconductor wafer is diced (cut) into individual chips, thereby completing the silicon carbide semiconductor device 10 shown in FIGS. 1 to 3D.
[0066] As described above, according to the silicon carbide semiconductor device of the first embodiment, the p + shallower than the p-type region and deeper than the p-type base region + A type connection region is provided. + Type domain and p ++ The area of connection with the contact region can be increased, the fluctuation of the feedback capacitance can be suppressed, and the SW loss can be reduced. + The p-type connection region reduces the area of the p-type base region exposed to the drain electrode, making it difficult for a high voltage to be applied to the p-type base region, and making it possible to increase the breakdown voltage. + A pn parallel region with an SJ structure is formed under the type region. - The n-type drift region is made highly doped, - This allows the thickness of the mold drift region to be reduced, thereby reducing the drift resistance.
[0067] For the silicon carbide semiconductor device according to the first embodiment, a simulation of on-resistance was performed by changing the cell pitch. Fig. 17 is a characteristic diagram showing the relationship between the cell pitch and on-resistance of the silicon carbide semiconductor device according to the first embodiment. In Fig. 17, the impurity concentrations of the p-type column region 24 and the n-type column region 25 were set to 9.5 × 10 16 / cm 3 The depth was set to 1.5 μm. The periodic repeat pitch (equivalent to the cell pitch) of the p-type column region 24 and the n-type column region 25 was changed from 1.6 μm to 2.6 μm to study the on-resistance (RonA). The threshold voltage (Vth) was set to 4 V. When the cell pitch was 1.8 μm to 2.2 μm, the on-resistance was 2.54 mΩcm. 2 ~2.56mΩcm 2 In both cases, a breakdown voltage of 1500V or more was obtained, which is sufficient for a device in the 1200V breakdown voltage class.
[0068] Second Embodiment Next, a structure of a silicon carbide semiconductor device according to a second embodiment will be described. Fig. 4 is a perspective view showing the structure of the silicon carbide semiconductor device according to the second embodiment. Fig. 5 is a cross-sectional view taken along line AA' of Fig. 4 showing the structure of the silicon carbide semiconductor device according to the second embodiment. Fig. 6 is a plan view taken along line BB' of Fig. 5 showing the structure of the silicon carbide semiconductor device according to the second embodiment.
[0069] The silicon carbide semiconductor device 10 according to the second embodiment differs from the silicon carbide semiconductor device 10 according to the first embodiment in that the p-type column region 24 is p + The p + 4, the p-type column region 24 is formed under the p-type connection region 23. + The p-type column region 24 has a width (depth direction width of the trench 16) that is approximately the same as that of the p-type connection region 23. + It may be narrower than the mold connection area 23 .
[0070] Also, p + Since no channel is formed where the p-type connection region 23 is provided, the p-type column region 24 is +By providing the p-type column region 24 below the type connection region 23, the p-type column region 24 does not act as a resistance, and the JFET resistance (spreading resistance) can be reduced.
[0071] As described above, according to the silicon carbide semiconductor device of the second embodiment, similarly to the first embodiment, p + As a result, it is possible to suppress the fluctuation of the feedback capacitance, reduce the SW loss, and increase the breakdown voltage, as in the first embodiment. + A pn parallel region that forms an SJ structure is formed under the type connection region. - The n-type drift region is made highly doped, - This allows the thickness of the mold drift region to be reduced, thereby reducing the drift resistance.
[0072] Third Embodiment Next, a structure of a silicon carbide semiconductor device according to a third embodiment will be described. Fig. 7 is a perspective view showing the structure of the silicon carbide semiconductor device according to the third embodiment. Fig. 8 is a cross-sectional view taken along line AA' of Fig. 7 showing the structure of the silicon carbide semiconductor device according to the third embodiment. Fig. 9 is a plan view taken along line BB' of Fig. 8 showing the structure of the silicon carbide semiconductor device according to the third embodiment.
[0073] The silicon carbide semiconductor device 10 according to the third embodiment differs from the silicon carbide semiconductor device 10 according to the first embodiment in that the p-type column region 24 is p ++ The p ++ 7 and 8, the p-type column region 24 is formed under the p-type contact region 15. ++ Although it is narrower than the p-type contact region 15, ++ The p-type contact region 15 is narrowed to form the p-type column region 24. ++ The width may be approximately the same as that of the mold contact region 15 .
[0074] As shown in FIG. ++The p-type contact regions 15 are provided in a distributed manner in the depth direction of the trench 16. Therefore, the p-type column regions 24 are also provided in a distributed manner in the depth direction of the trench 16. This shortens the current path, and the avalanche resistance can be increased.
[0075] As described above, according to the silicon carbide semiconductor device of the third embodiment, similarly to the first embodiment, p + This makes it possible to suppress the fluctuation of the feedback capacitance, reduce the SW loss, and increase the breakdown voltage, as in the first embodiment. ++ A pn parallel region that forms an SJ structure is formed under the contact region. - The n-type drift region is made highly doped, - This allows the thickness of the mold drift region to be reduced, thereby reducing the drift resistance.
[0076] Fourth Embodiment Next, a structure of a silicon carbide semiconductor device according to a fourth embodiment will be described. Fig. 10 is a perspective view showing the structure of the silicon carbide semiconductor device according to the fourth embodiment. Fig. 11 is a cross-sectional view taken along line A-A' of Fig. 10 showing the structure of the silicon carbide semiconductor device according to the fourth embodiment. Fig. 12 is a cross-sectional view taken along line B-B' of Fig. 10 showing the structure of the silicon carbide semiconductor device according to the fourth embodiment. Fig. 13 is a plan view taken along line C-C' of Figs. 11 and 12 showing the structure of the silicon carbide semiconductor device according to the fourth embodiment.
[0077] The silicon carbide semiconductor device 10 according to the fourth embodiment differs from the silicon carbide semiconductor device 10 according to the first embodiment in that the p-type column region 24 is a p + Type region 21 and p + The p-type connection region 23 is in contact with the p-type connection region 23 under the trench. + Type region 21 and p + 10 and 12, the p-type column region 24 is formed under the p-type connection region 23. + The p-type column region 24 has a width similar to that of the p-type region 21. +10, the p-type column region 24 may be narrower than the p-type region 21. + The p-type column region 24 has a width (depth direction width of the trench 16) that is approximately the same as that of the p-type connection region 23. + It may be narrower than the mold connection area 23 .
[0078] 13, in the fourth embodiment, the p-type column region 24 surrounds the n-type column region 25. This makes it possible to increase the impurity concentration of the p-type column region 24, and at the same time, to increase the impurity concentration of the n-type column region 25. This reduces the resistance of the pn parallel region 26, and makes it possible to enhance the effect of the SJ structure more than in the first to third embodiments.
[0079] As described above, according to the silicon carbide semiconductor device of the fourth embodiment, similarly to the first embodiment, + In the fourth embodiment, the p-type column region is provided with a p-type connection region. This makes it possible to suppress fluctuations in feedback capacitance, reduce SW loss, and increase the breakdown voltage, as in the first embodiment. + Type region and p + A pn parallel region that forms an SJ structure is formed under the type connection region. - The n-type drift region is made highly doped, - This allows the thickness of the mold drift region to be reduced, thereby reducing the drift resistance.
[0080] In the fourth embodiment, p + Type region 21 and p + Although the pn parallel region 26 is formed under the type connection region 23, other combinations are also possible. ++ type contact region 15 and p + A pn parallel region 26 may be formed under the type connection region 23. ++ type contact region 15 and p + A pn parallel region 26 may be formed under the type region 21, and further, p ++ type contact region 15, p + The type connection region 23 and p + A pn parallel region 26 may be formed below the mold region 21 .
[0081] The present disclosure can be modified in various ways without departing from the spirit of the present disclosure, and in each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, etc. are variously set according to the required specifications, etc. Furthermore, each of the above-described embodiments has been described using a MOSFET having a trench structure as an example, but the present disclosure can also be applied to other semiconductor devices having a trench structure, such as IGBTs.
[0082] INDUSTRIAL APPLICABILITY As described above, silicon carbide semiconductor devices according to the present disclosure are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, automobile igniters, and the like.
[0083] 10, 110 Silicon carbide semiconductor device 11, 111 n + type drain region (n + Silicon carbide substrate) 12, 112 n - n-type drift region 13, 113 p-type base region 14, 114 + Type source region 15, 115 p ++ 1. N-type contact region 16, 116: trench 17, 117: gate insulating film 18, 118: gate electrode 19, 119: interlayer insulating film 20, 120: n-type current diffusion region 21, 121: p-type current diffusion region under the trench + Mold area 23p + Type connection region 24 p-type column region 25 n-type column region 26 pn parallel region 38, 138 barrier metal 40, 140 semiconductor substrate 41, 141 n + Starting substrate 42, 142 n - Silicon carbide layer 43, 143 Ohmic electrode 44, 144 Source electrode 45, 145 Drain electrode 122 p ++ p under the contact region + type area
Claims
1. A silicon carbide semiconductor substrate of the first conductivity type, A first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on the front surface of the silicon carbide semiconductor substrate, On the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate, there is a pn parallel region in which a first column region of a first conductivity type and a second column region of a second conductivity type are repeatedly and alternately arranged on a plane parallel to the front surface, A second semiconductor layer of a second conductivity type is provided on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, A first semiconductor region of a first conductivity type is selectively provided on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, A second semiconductor region of a second conductivity type is selectively provided on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, in contact with the first semiconductor region and the second semiconductor layer. A trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer, A gate electrode is provided inside the trench via a gate insulating film, A high-concentration region of a second conductivity type is provided inside the first semiconductor layer at a position opposite to the trench in the depth direction, A second conductivity type connection region is selectively provided within the first semiconductor layer, on the side of the second semiconductor layer from the high-concentration region, and on the side of the silicon carbide semiconductor substrate from the second semiconductor layer, in contact with the high-concentration region and the second semiconductor layer. A first electrode provided on the surface of the first semiconductor region and the second semiconductor region, A second electrode provided on the back surface of the silicon carbide semiconductor substrate, Equipped with, The second semiconductor region is periodically arranged in the longitudinal direction of the trench. The silicon carbide semiconductor device is characterized in that the connection region is periodically arranged in the longitudinal direction of the trench in a region that does not overlap with the second semiconductor region in a plan view.
2. The silicon carbide semiconductor device according to claim 1, characterized in that the second column region is in contact with the surface of the silicon carbide semiconductor substrate side of the high-concentration region and is provided on the silicon carbide semiconductor substrate side of the high-concentration region.
3. The silicon carbide semiconductor device according to claim 1, characterized in that the second column region is in contact with the surface of the connection region on the silicon carbide semiconductor substrate side and is provided on the silicon carbide semiconductor substrate side of the connection region.
4. The silicon carbide semiconductor device according to claim 1, characterized in that the second column region is in contact with the surface of the second semiconductor region on the silicon carbide semiconductor substrate side and is provided on the silicon carbide semiconductor substrate side of the second semiconductor region.
5. The silicon carbide semiconductor device according to claim 1, characterized in that the second column region is in contact with the surface of the silicon carbide semiconductor substrate side of the high-concentration region and the connection region, and is provided on the silicon carbide semiconductor substrate side of the high-concentration region and the connection region.
6. The silicon carbide semiconductor device according to any one of claims 2 to 5, characterized in that the width of the second column region is the same as the width of the region in contact with the silicon carbide semiconductor substrate on the surface opposite to the silicon carbide semiconductor substrate side.
7. The silicon carbide semiconductor device according to any one of claims 2 to 5, characterized in that the width of the second column region is narrower than the width of the region in contact with the silicon carbide semiconductor substrate on the surface opposite to the silicon carbide semiconductor substrate side.
8. The silicon carbide semiconductor device according to claim 1, characterized in that the periodic repeating pitch of the first column region and the second column region is 1.8 μm to 2.2 μm.