Semiconductor photodetector, method of manufacturing semiconductor photodetector, optical line terminal, multilevel intensity modulation transmitter / receiver, digital coherent receiver, optical fiber radio system, SPAD sensor system, and lidar device

Abstract

The semiconductor light receiving element (100) of the present disclosure comprises a substrate (1), a first mesa structure (30) having at least n-type semiconductor layers (2, 3) sequentially formed on the substrate (1), a multiplication layer (4), a p-type electric field relaxation layer (5), a light absorption layer (6), and an i-type semiconductor layer (8) having a larger band gap than the light absorption layer (6), a second mesa structure (31) formed on the first mesa structure (30) and having at least a window layer (9) having a larger band gap than the light absorption layer (6), and a terrace portion (40) consisting of an outermost surface of the first mesa structure (30) exposed on the outer periphery of the second mesa structure (31).

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor photodetector, a manufacturing method for a semiconductor photodetector, an optical line terminal, a multilevel intensity modulation transceiver, a digital coherent receiver, an optical fiber radio system, a SPAD sensor system, and a LIDAR device. [Background technology]

[0002] Along with the progress of digital transformation that utilizes digital information, there has been remarkable development of communication networks that communicate digital information with each other and data centers that store and process data. Optical communication is used for communication networks and communication within data centers. In recent years, optical communication has made remarkable progress in increasing speed and capacity. With the progress of optical communication, photodiodes (PD) and avalanche photodiodes (APD), which provide high receiving sensitivity, are required as optical communication receivers.

[0003] Passive Optical Networks (PON) are the main method used in access networks that connect optical communication subscribers. PON systems started with G(E)-PON systems that transmit signals of 1 to 2 Gbps, and are expected to increase in the future with 10G-EPON and XG-PON systems that transmit signals of 10 Gbps.

[0004] Furthermore, the International Telecommunication Union Telecommunication Standardization Sector (ITU-T) is currently studying the 50G-PON system, a next-generation high-speed PON system, and it is expected that 50Gbps-class transmission will also be put to practical use in access networks in the future. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 4609430 [Patent Document 2] Patent No. 4985298 [Patent Document 3] Patent No. 5025330 [Patent Document 4] Japanese Patent Application Publication No. 11-354827 [Patent Document 5] Japanese Patent Application Publication No. 3-050875 [Patent Document 6] JP 2002-324911 A [Non-patent literature]

[0006] [Non-Patent Document 1] Jiyuan Zheng, et al.,“Digital Alloy InAlAs Avalanche Photodiodes”,JOURNAL OF LIGHTWAVE TECHNOLOGY,VOL.36,NO.17,SEPTEMBER 1,pp.3580-3585,2018 Summary of the Invention [Problem to be solved by the invention]

[0007] (1) Issues regarding the multiplication layer in APDs APDs, which are semiconductor photodetectors used in PON systems, have an element structure consisting of a light absorption layer (InGaAs), an electric field buffer layer (InP or InAlAs), and a multiplication layer (InP or InAlAs). A high electric field of about 800 kV / cm is applied to the multiplication layer to multiply, or ionize, the electrons and holes generated in the light absorption layer. The electric field buffer layer functions to weaken the electric field so that the high electric field of the multiplication layer is not applied to the light absorption layer. Incidentally, the ionization rate of electrons is expressed as α, and the ionization rate of holes as β.

[0008] In an APD, the greater the difference between the ionization rates of electrons and holes, the smaller the excess noise generated during multiplication and the higher the receiver sensitivity. Furthermore, the greater the difference between the ionization rates of electrons and holes, the shorter the multiplication time in the multiplication layer, resulting in a wider response band.

[0009] The ionization rate ratio k of electrons and holes is defined as k = β / α. When electrons are injected into the multiplication layer, the smaller the ionization rate ratio k, the better the APD performance. Compound semiconductor materials such as InAlAs or InP are used for the multiplication layer of APDs for optical communications.

[0010] When InAlAs is selected as the material for the multiplication layer, the difference between the ionization rates of electrons and holes is greater than in the case of InP. In InP, the ionization rate of holes is greater than that of electrons, and the ionization rate of holes is about twice that of electrons. On the other hand, when InAlAs is selected as the material for the multiplication layer, the ionization rate of electrons is greater than that of holes, and the ionization rate of electrons is about five times that of holes. Therefore, since the reception sensitivity is higher when InAlAs is used as the multiplication layer, InAlAs is more suitable than InP as the material for the multiplication layer of an APD.

[0011] As mentioned above, PON systems require APDs, which are semiconductor light-receiving elements, to have a wide response band and high reception sensitivity. However, unlike PDs, APDs have a problem in that the time required for multiplication, that is, the multiplication time, increases as the multiplication factor increases, resulting in a decrease in the response band at high multiplication factors.

[0012] Although APDs with a multiplication layer made of InAlAs, which is used in optical communications, have a wider response band than APDs made of other semiconductor materials, the response band remains at approximately 20 GHz when the multiplication factor is 6 or more. In other words, the wide response band of 37.5 GHz or more required for 50G-PON systems is difficult to achieve when conventional APDs are used.

[0013] As described above, APDs, which are semiconductor light receiving elements used in optical communications, are required to operate in an even wider response band. Patent Document 5 describes an APD that uses a superlattice as a multiplication layer, but since the thickness of each layer of the superlattice is 5 to 10 nm, it acts as a quantum well that reflects the band gap of each layer. If the thickness of each layer in the stack is several nm or more, energy unevenness that reflects the band gap of each layer is generated, which hinders the movement of carriers and reduces the traveling speed.

[0014] In a 50G-PON system, the response bands of the semiconductor light emitting element and the semiconductor light receiving element, as well as the optical output of the semiconductor light emitting element and the receiving sensitivity of the semiconductor light receiving element are insufficient. For this reason, it is being considered to provide a digital bandwidth compensation circuit using a digital signal processor (DSP) after the APD in the optical network unit (ONU), that is, the receiving device on the subscriber side.

[0015] Furthermore, in the optical line terminal (OLT), i.e., the receiving equipment on the central office side, a semiconductor optical amplifier (SOA) is required to compensate for the lack of receiving sensitivity of the semiconductor photodetector, and it is also necessary to integrate an SOA into the electro-absorption modulated laser diode (EML) on the transmitting side of the ONU to increase the optical output.

[0016] However, DSPs and SOAs consume a lot of power, which increases costs, and there are fears that the replacement of existing PON systems with 50G-PON systems will not progress.

[0017] In existing PON systems other than the next-generation high-speed PON system, it has been considered to increase the number of splits of the optical signal output from the OLT in order to reduce costs. However, in this case, it is necessary to increase the optical output by integrating an SOA in the EML on the transmitting side of the OLT and ONU, which causes problems such as an increase in the power consumption of the transmitter and an increase in costs.

[0018] As described above, in order to compensate for the limitations of the receiving sensitivity and response bandwidth of semiconductor photodetectors, transceivers have been designed that incorporate expensive, power-hungry DSPs and SOAs into the ONUs and OLTs. However, this brings about problems of increased power consumption and costs.

[0019] In order to solve the problems related to the multiplication layer in the APD as described above, it has been considered to apply a digital alloy structure, in which the ionization rate ratio k is significantly reduced compared to a random alloy structure, to the multiplication layer as described in Non-Patent Document 1. However, there are problems to be solved in order to apply a digital alloy structure multiplication layer to an APD having a highly reliable p-type impurity diffusion structure.

[0020] (2) Issues regarding the formation of p-type impurity regions in APDs with p-type impurity diffusion structures Patent Document 1 and the like disclose an APD having a p-type impurity diffusion structure. In an APD having a p-type impurity diffusion structure, a downwardly convex p-type impurity diffusion region, i.e., a p-type region, is formed, so that an electric field is concentrated in the light receiving region and local multiplication (edge ​​breakdown) at the outer periphery of the light receiving region is suppressed. Since an APD having a p-type impurity diffusion structure does not cause edge breakdown, it has an excellent structure with low dark current and highly reliable element characteristics. In an APD having a p-type impurity diffusion structure, a p-type region is formed in an i-type InP window layer by Zn diffusion, and a pn junction is formed and a reverse bias is applied, so that an electric field is applied to the light absorption layer, the electric field relaxation layer, and the multiplication layer. The applied electric field forms a depletion layer between the deepest part of the p-type region and the n-type semiconductor layer.

[0021] A necessary condition for a wide response band APD is that the transit time of carriers through the depletion layer must be short. The 3 dB bandwidth (ftr), which is determined by the transit time of carriers through the depletion layer in the optical absorption layer, is expressed by the following formula (1). ftr=3.5Vav / (2πW) (1) In formula (1), W is the thickness of the depletion layer formed in the light absorption layer, and Vav is the average saturated transit speed of electrons and holes. The response bandwidth of the entire APD is determined by the time it takes for carriers to transit through the depletion layer formed in the light absorption layer as described above, as well as the RC time constant, the multiplication time, and the time it takes for carriers to diffuse through the p-type region in the light absorption layer. As can be seen from formula (1), ftr is inversely proportional to the thickness of the depletion layer, so in order to achieve a wide response bandwidth, it is necessary to thin the thickness of the depletion layer by making it a p-type region partway through the light absorption layer.

[0022] Therefore, it is necessary to perform thermal diffusion of p-type impurities such as Zn at high temperatures for a long time so that the deepest part of the p-type impurity diffusion region reaches the inside of the light absorption layer. However, if the diffusion time of Zn at high temperatures is long, the dopants contained in the p-type InP field relaxation layer thermally diffuse to each layer in the upper and lower directions, and the required field relaxation amount cannot be obtained. As a result, a high electric field is applied to the light absorption layer, causing a tunnel breakdown, and the multiplication is no longer possible. Alternatively, even if the multiplication occurs, a high dark current flows. In particular, when the multiplication layer has a digital alloy structure, the thermal diffusion of the p-type impurities into the multiplication layer causes the digital alloy structure to become disordered, causing an increase in multiplication noise.

[0023] In this way, if the thermal diffusion of p-type impurities is carried out for a long period of time in order to shorten the transit time of carriers, and the deepest part of the p-type impurity diffusion region is formed inside the light absorption layer, problems such as no multiplication, an increase in dark current, and an increase in multiplication noise may occur.

[0024] The present disclosure has been made to solve the problems described above, and aims to provide a semiconductor photodetector having excellent element characteristics, such as operation over a wide response band, a method for manufacturing the same, and equipment using the semiconductor photodetector. [Means for solving the problem]

[0025] The semiconductor light receiving element according to the present disclosure comprises: A substrate; a first mesa structure having at least an n-type semiconductor layer, a multiplication layer, a p-type electric field buffer layer, a light absorption layer, and an i-type semiconductor layer having a band gap larger than that of the light absorption layer, which are successively formed on the substrate; a second mesa structure formed on the first mesa structure, the second mesa structure having at least a window layer having a band gap larger than that of the light absorption layer, and a ring-shaped p-type contact layer; a terrace portion formed on an outermost surface of the first mesa structure and exposed on an outer periphery side of the second mesa structure; the window layer on the inner periphery side of the ring-shaped p-type contact layer, and a p-type Impurity diffusion and a region.

[0026] A method for manufacturing a semiconductor light receiving element according to the present disclosure includes: epitaxially growing, on a substrate, at least an n-type semiconductor layer, a multiplication layer, a p-type electric field relaxation layer, a light absorption layer, an i-type semiconductor layer having a band gap larger than that of the light absorption layer, a window layer having a band gap larger than that of the light absorption layer, and a p-type contact layer in that order; forming a selective diffusion mask made of an insulating film having a substantially circular opening on a surface of the p-type contact layer; forming a p-type impurity diffusion region having a bottom extending from the opening to at least the inside of the light absorbing layer; removing the selective diffusion mask; processing the p-type contact layer into a ring shape along an outer periphery of a light receiving region; forming a second mesa structure by etching an outer periphery of the light receiving region until the i-type semiconductor layer is exposed at least on the surface; and forming a first mesa structure by etching a portion other than a predetermined region from the outer periphery side of the second mesa structure.

[0027] The optical line terminal according to the present disclosure comprises: The semiconductor light receiving element described above, an optical multiplexer / demultiplexer that inputs an optical signal to the semiconductor light receiving element; an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element; a clock data recovery circuit connected to the amplifier circuit and configured to recover clock data from the amplified electrical signal; and a forward error correction circuit connected to the clock data recovery circuit for correcting an error in the clock data.

[0028] A multi-level intensity modulation transmitting / receiving device according to the present disclosure comprises: The semiconductor light receiving element described above for receiving an optical signal intensity-modulated into multiple values; an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element; an analog / digital conversion circuit connected to the amplifier circuit and converting the amplified electrical signal into a digital signal; A digital signal processing circuit is connected to the analog / digital conversion circuit and processes the digital signal.

[0029] The radio-over-fiber system according to the present disclosure comprises: a light source that emits an analog modulated optical signal; The semiconductor light receiving element described above for receiving the analog-modulated optical signal; a transmission path for transmitting an analog electrical signal output from the semiconductor light receiving element to an antenna; and an antenna connected to the transmission line for emitting the analog electrical signal as a radio wave signal.

[0030] A digital coherent receiving device according to the present disclosure includes: The semiconductor light receiving element described above, a polarization splitter that splits the polarization of the intensity- and phase-modulated polarization multiplexed optical signal; a 90-degree hybrid that splits and combines the optical signals output from the polarization splitter; and a digital signal processing circuit connected to the 90-degree hybrid device for processing a digital signal.

[0031] The SPAD (Single Photon Avalanche Diode) sensor system according to the present disclosure includes: A SPAD sensor constituted by the semiconductor light receiving element described above; a quenching circuit for repeatedly applying a voltage equal to or greater than a breakdown voltage and a voltage equal to or less than the breakdown voltage to the SPAD sensor; and an optoelectronic measurement circuit that measures the electrical signal output from the SPAD sensor.

[0032] The LIDAR device according to the present disclosure comprises: A light source that emits light in a pulsed manner; the semiconductor light receiving element described above for receiving light emitted from the light source and reflected by an object; an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element; and a distance measuring circuit that calculates a distance based on the electrical signal amplified by the amplifier circuit. Effect of the Invention

[0033] According to the semiconductor light receiving element and the method for manufacturing a semiconductor light receiving element according to the present disclosure, since a terrace portion is provided, it is possible to obtain a semiconductor light receiving element and a method for manufacturing a semiconductor light receiving element having excellent element characteristics such as operation over a wide response band.

[0034] The optical line terminal device, multi-level intensity modulation transceiver device, digital coherent receiver device, optical fiber radio system, SPAD sensor system, and LIDAR device according to the present disclosure have the advantage that the semiconductor photodetector element according to the present disclosure is used as the semiconductor photodetector element, thereby providing devices and systems with excellent performance. [Brief description of the drawings]

[0035] [Figure 1] 1 is a cross-sectional view illustrating an element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to a first embodiment. [Diagram 2] 3 is a cross-sectional view after epitaxial crystal growth in a manufacturing method for a back-illuminated APD, which is an example of a semiconductor light-receiving element according to the first embodiment. FIG. [Diagram 3] 3 is a cross-sectional view showing a p-type impurity diffusion step in a manufacturing method for a back illuminated APD, which is an example of a semiconductor light receiving element according to the first embodiment. FIG. [Figure 4] 3 is a cross-sectional view after patterning of a contact layer in a manufacturing method for a back-illuminated APD, which is an example of a semiconductor light-receiving element according to the first embodiment. FIG. [Diagram 5] 3 is a cross-sectional view after patterning of a window layer in a manufacturing method for a back-illuminated APD, which is an example of a semiconductor light-receiving element according to the first embodiment. FIG. [Figure 6] FIG. 6A is a cross-sectional view after patterning a mesa groove in a manufacturing method for a back-illuminated APD that is an example of a semiconductor light-receiving element according to the first embodiment, and FIG. 6B is a top view. [Figure 7] 3 is a cross-sectional view after a surface protection film is formed and patterned in a manufacturing method for a back-illuminated APD, which is an example of a semiconductor light-receiving element according to the first embodiment. FIG. [Figure 8] 3 is a cross-sectional view after a front surface side electrode is formed and patterned in a manufacturing method for a back illuminated APD, which is an example of a semiconductor light receiving element according to the first embodiment. FIG. [Figure 9] 4 is a cross-sectional view illustrating an element structure of a back-illuminated APD that is a comparative example of the first embodiment. FIG. [Figure 10] FIG. 10A is a cross-sectional view after epitaxial crystal growth in a manufacturing method for a back-illuminated APD that is an example of the semiconductor light receiving element according to embodiment 1, and FIG. 10B is a cross-sectional view after epitaxial crystal growth in a manufacturing method for a back-illuminated APD that is a comparative example. [Figure 11] FIG. 11A is a cross-sectional view of a back-illuminated APD as an example of the semiconductor light receiving element according to embodiment 1 after a p-type impurity diffusion step in a manufacturing method thereof, and FIG. 11B is a cross-sectional view of a back-illuminated APD as a comparative example after a p-type impurity diffusion step in a manufacturing method thereof. [Figure 12] 10 is a cross-sectional view illustrating an element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to a second embodiment. [Figure 13] FIG. 13 is a diagram showing the electric field dependence of the electron dead space in an InAlAs multiplication layer. [Figure 14] 14A to 14C are conceptual diagrams showing the ionization rates of electrons and holes. [Figure 15] FIG. 13 is a graph showing the dependence of the ionization rate ratio and the tunnel current on the thickness of the multiplication layer. [Figure 16] Figures 16A to 16D are conceptual diagrams showing the ionization rate in the multiplication layer and electric field relaxation layer, with Figure 16A showing the ionization rate in the case of a random alloy structure multiplication layer, Figure 16B showing the ionization rate in the case of a digital alloy structure multiplication layer, Figure 16C showing the ionization rate in the case of a partially disordered digital alloy structure multiplication layer, and Figure 16D showing the ionization rate in the case of a combination of a thick electric field relaxation layer and a digital alloy structure multiplication layer. [Figure 17] 11 is a cross-sectional view illustrating an element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to a first modification of the second embodiment. FIG. [Figure 18] 11 is a cross-sectional view illustrating an element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Modification 2 of the second embodiment. FIG. [Figure 19] 11 is a cross-sectional view illustrating an element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Modification 3 of the second embodiment. FIG. [Figure 20]11 is a cross-sectional view illustrating an element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Modification 4 of the second embodiment. FIG. [Figure 21] 13 is a cross-sectional view illustrating an element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to a fifth modification of the second embodiment. FIG. [Figure 22] 13 is a cross-sectional view after a second terrace is formed in a process of manufacturing a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Modification 5 of Embodiment 2. FIG. [Figure 23] 11 is a cross-sectional view illustrating a device structure of a front-illuminated APD, which is an example of a semiconductor light-receiving device according to a third embodiment. FIG. [Figure 24] FIG. 11 is a configuration diagram illustrating an optical line terminal (OLT) of a 50G-PON system according to a fourth embodiment. [Diagram 25] FIG. 11 is a configuration diagram showing an optical network unit (ONU) of a 50G-PON system according to a fourth embodiment. [Figure 26] FIG. 1 is a configuration diagram illustrating an optical line terminal (OLT) of a 50G-PON system as a comparative example. [Figure 27] FIG. 13 is a diagram illustrating a configuration of an optical line terminal (OLT) of a 50G-PON system according to a fourth embodiment. [Figure 28] A diagram showing the configuration of an optical network unit (ONU) of a 50G-PON system relating to embodiment 4. [Figure 29] FIG. 13 is a diagram illustrating a configuration of a multilevel intensity modulation transmitting / receiving device according to a fifth embodiment. [Diagram 30] 30A and 30B are conceptual diagrams showing received waveforms of a multilevel intensity modulation transmitting / receiving device according to the fifth embodiment. [Diagram 31] 31A and 31B are conceptual diagrams illustrating the operation of a PD when a high optical input is applied. [Diagram 32] 1 is a conceptual diagram illustrating the operation of an APD when a high optical input is applied. [Diagram 33] FIG. 2 is a diagram showing the residence times of electrons and holes for each material constituting the multiplication layer. [Diagram 34] FIG. 13 is a diagram illustrating a configuration of a radio-on-fiber system according to a sixth embodiment. [Diagram 35] FIG. 1 illustrates a configuration of a radio-on-fiber system as a comparative example. [Diagram 36] FIG. 13 is a diagram illustrating a configuration of a digital coherent receiving device according to a seventh embodiment. [Figure 37] FIG. 37A is a conceptual diagram showing waveforms of a digital coherent receiving device as a comparative example, and FIG. 37B is a conceptual diagram showing waveforms of a digital coherent receiving device according to the seventh embodiment. [Figure 38] FIG. 23 is a diagram illustrating a configuration of a SAPD sensor system according to an eighth embodiment. [Figure 39] FIG. 39A is a conceptual diagram showing the multiplication characteristics of a SAPD sensor system as a comparative example, and FIG. 39B is a conceptual diagram showing the multiplication characteristics of a SAPD sensor system according to embodiment 8. [Diagram 40] FIG. 13 is a diagram showing the calculated difference between the quenching electric field and the Geiger mode electric field for each multiplication layer configuration. [Diagram 41] FIG. 23 is a diagram illustrating the configuration of a LIDAR device according to a ninth embodiment. [Diagram 42] FIG. 42A is a conceptual diagram showing a received waveform of an APD mounted on a LIDAR device that is a comparative example, and FIG. 42B is a conceptual diagram showing a received waveform of an APD mounted on a LIDAR device related to embodiment 9. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] Embodiment 1 1 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element 100 according to embodiment 1. In the following description, the upper side refers to the direction in which semiconductor layers are stacked from the surface of a semiconductor substrate, that is, the stacking direction, and the lower side refers to the direction opposite to the stacking direction, in other words, the direction from the surface side on which the semiconductor layers are formed to the back side of the semiconductor substrate.

[0037] <Element structure of semiconductor photodetector (APD) according to the first embodiment> The back-illuminated APD, which is an example of the semiconductor light-receiving element 100 according to the first embodiment, is composed of an Fe-doped InP substrate 1 and a semiconductor layer having a carrier concentration of 5×10 17 ~8×10 18 cm -3 and an n-type InP conductive layer 2 having a thickness of 0.1 to 1.0 μm and a carrier concentration of 5×10 17 ~8×10 18 cm -3 The n-type InAlAs conductive layer 3 has a thickness of 0.1 to 1.0 μm, the i-type InAlAs multiplication layer 4 has a carrier concentration of 1×10 16 ~5×10 18 cm -3 The semiconductor device includes a first mesa structure 30 having a substantially circular surface shape in a top view, a p-type InAlAs electric field relaxation layer 5 having a thickness of 10 to 100 nm, an i-type InGaAs light absorption layer 6 having a thickness of 0.1 to 2.0 μm, an i-type InAlGaAs graded layer 7 having a thickness of 5 to 100 nm in which the composition wavelength is gradually shortened, and an i-type InAlAs surface protection layer 8 having a thickness of 10 to 200 nm, and an n-type InP conductive layer 2 is exposed on the outer periphery as a semiconductor layer. 17 ~8×10 18 cm -3 and a p-type InP window layer 9 having a layer thickness of 0.1 to 3.0 μm and a carrier concentration of 5×10 17 ~8×10 18 cm -3a p-type InGaAs contact layer 10 having a ring shape along the outer periphery of a light receiving region 60 having a layer thickness of 0.05 to 0.5 μm and being approximately circular in top view; a second mesa structure 31 having a surface having an approximately circular shape in top view; a p-type impurity diffusion region 20 provided in a part of the p-type InP window layer 9 and the i-type InGaAs light absorption layer 6 on the inner periphery side of the ring-shaped p-type InGaAs contact layer 10; a terrace portion 40 consisting of an outermost surface of the first mesa structure 30 exposed on the outer periphery side of the second mesa structure 31 and having a region with a width of 0.5 μm or more in the outer periphery direction; and a surface protection film 11 consisting of an insulating film covering the first mesa structure 30, the side portions of the first mesa structure 30, and the terrace portion 40. the p-type InP window layer 9 corresponding to the inner periphery of the ring-shaped p-type InGaAs contact layer 10, i.e., the surface of the p-type InP window layer 9 corresponding to the approximately circular light-receiving region 60; an n-type electrode 50 formed on the surface of the n-type InP conductive layer 2 exposed as a semiconductor layer on the outer periphery of the first mesa structure 30; a p-type electrode 51 provided on the surface of the ring-shaped p-type InGaAs contact layer 10 and on the surfaces of the front-side antireflection coating 15; a back-side antireflection coating 16 provided on the back side of the Fe-doped InP substrate 1 at a position opposite to the p-type electrode 51; and a back-side electrode 52 provided on the outer periphery of the back-side antireflection coating 16 on the back side of the Fe-doped InP substrate 1.

[0038] In this disclosure, i-type refers to undoped, or a p-type impurity concentration or n-type impurity concentration of 5×10 17 cm -3 This means the following cases:

[0039] As described above, the terrace portion 40 is made up of the outermost surface of the first mesa structure 30 exposed on the outer periphery side of the second mesa structure 31, and has a region with a width of 0.5 μm or more in the outer periphery direction. In the above-mentioned configuration, the outermost surface of the first mesa structure 30 exposed on the outer periphery side is the upper surface of the i-type InAlAs surface protection layer 8. In the following description, the surface exposed as a semiconductor layer in the terrace portion 40 is called the terrace surface 41. For example, in the above-mentioned configuration, the upper surface of the i-type InAlAs surface protection layer 8, that is, the upper surface, is the terrace surface 41. Note that the upper surface refers to, for example, the upper surface of the two surfaces of the i-type InAlAs surface protection layer 8, that is, the surface opposite to the Fe-doped InP substrate 1.

[0040] The p-type electrode 51 also functions as a reflective film that returns, to the i-type InGaAs light absorption layer 6, part of the incident light 90 that is incident from the back surface side of the Fe-doped InP substrate 1 and that has transmitted to the front surface side without being absorbed by the i-type InGaAs light absorption layer 6.

[0041] The p-type InP window layer 9 may be a p-type InAlAs layer, a p-type InAlGaAs layer, or a p-type InGaAsP layer instead of the p-type InP layer. The window layer may be formed of a multi-layer structure in which two or more layers selected from the p-type InP layer, the p-type InAlAs layer, the p-type InAlGaAs layer, and the p-type InGaAsP layer are laminated. The i-type InAlAs surface protective layer 8 also functions as a goodied layer for reducing the band gap step between two layers provided above and below the i-type InAlAs surface protective layer 8.

[0042] An i-type InP layer may be used as the surface protective layer instead of the i-type InAlAs surface protective layer 8. Using the i-type InP layer as the surface protective layer makes it possible to prevent oxidation of the terrace surface 41 of the terrace portion 40, which has the effect of extending the life of the semiconductor light-receiving element.

[0043] When the i-type InP layer is used as the surface protective layer, the window layer can be a p-type InAlAs layer, which makes it easy to form the terrace portion 40 by selective etching. When the i-type InP layer is used as the surface protective layer, an i-type InAlAs layer may be provided between the i-type InAlGaAs graded layer 7 and the i-type InP surface protective layer to reduce the band gap step between the i-type InAlGaAs graded layer 7 and the i-type InP surface protective layer.

[0044] Here, the graded layer is a layer for mitigating the step between the valence band and the conduction band that occurs when semiconductor materials of different materials or different compositions are laminated.Specific examples of the graded layer include a layer made of multiple layers having an intermediate band gap between the two layers to be laminated, a layer of a material composition that forms an intermediate energy step in the valence band and the conduction band even if it is not an intermediate band gap, and a layer in which two layers are alternately laminated with a short period of several nm or less.

[0045] The p-type InAlAs electric field relaxation layer 5 may be constructed with either a random alloy structure or a digital alloy structure. Alternatively, the electric field relaxation layer may be constructed with a p-type InP layer. A graded layer made of an i-type InAlGaAs layer or an i-type InGaAsP layer may be provided between the p-type InAlAs electric field relaxation layer 5 and the i-type InGaAs light absorption layer 6.

[0046] <Method of Manufacturing Semiconductor Light-Receiving Element According to First Embodiment> A method for manufacturing a back illuminated APD, which is an example of the semiconductor light receiving element 100 according to the first embodiment, will be described with reference to FIGS.

[0047] First, an n-type InP conductive layer 2, an n-type InAlAs conductive layer 3, an i-type InAlAs multiplication layer 4, a p-type InAlAs electric field relaxation layer 5, an i-type InGaAs light absorption layer 6, an i-type InAlGaAs graded layer 7, an i-type InAlAs surface protection layer 8, a p-type InP window layer 9, and a p-type InGaAs contact layer 10 are epitaxially grown on an Fe-doped InP substrate 1 in this order from the Fe-doped InP substrate 1 side. Fig. 2 is a cross-sectional view after each epitaxially grown layer in the manufacturing method of the back-illuminated APD according to the first embodiment.

[0048] Examples of epitaxial crystal growth methods include metal organic vapor phase epitaxy (MOVPE) and molecular beam epitaxy (MBE).

[0049] As the n-type impurity (n-type dopant) of the epitaxial crystal growth layer, sulfur (S) or silicon (Si) is preferable. As the p-type impurity (p-type dopant), zinc (Zn), beryllium (Be), carbon (C), cadmium (Cd), and magnesium (Mg) are preferable. The crystal growth temperature during the epitaxial crystal growth is preferably within the range of 450°C to 800°C in the case of MOVPE, and within the range of 500°C to 800°C in the case of MBE.

[0050] The features of the wafer after epitaxial crystal growth of the back-illuminated APD according to the first embodiment include that an i-type InAlAs surface protection layer 8 is provided, and that the InP window layer and InGaAs contact layer are p-type rather than i-type.

[0051] A selective diffusion mask 12 made of an insulating film such as a SiN film or a SiO2 film is formed on the surface of the p-type InGaAs contact layer 10, and an opening is provided in a portion that will become the light receiving region 60. A p-type impurity diffusion region 20 is formed by thermally diffusing p-type impurities such as Zn, Cd, or Mg into the semiconductor layer by gas phase diffusion or solid phase diffusion. The diffusion temperature is set within a range of 400° C. to 800° C. In the thermal diffusion, the thermal diffusion is controlled so that the deepest part in the depth direction of the p-type impurity diffusion region 20 is located inside the i-type InGaAs light absorption layer 6. FIG. 3 is a cross-sectional view after the p-type impurity diffusion step in the manufacturing method of the back-illuminated APD according to the first embodiment.

[0052] The depth of the p-type impurity diffusion into the i-type InGaAs light absorbing layer 6 is controlled to 0.3 μm or less. If the p-type impurity diffusion is too deep into the i-type InGaAs light absorbing layer 6, a problem occurs in that the light receiving sensitivity decreases due to the influence of carrier recombination in the p-type i-type InGaAs light absorbing layer 6. Therefore, the optimum depth of the p-type impurity diffusion into the i-type InGaAs light absorbing layer 6 is within the range of 0.05 to 0.3 μm.

[0053] In the back-illuminated APD according to the first embodiment, the p-type InP window layer 9 and the p-type InGaAs contact layer 10 are doped in advance with p-type impurities such as Zn, Be, C, Cd or Mg during epitaxial crystal growth.

[0054] For example, as shown in FIG. 3, when Zn is, for example, subjected to solid-phase diffusion into a Zn- or Be-doped p-type InGaAs contact layer 10 and a p-type InP window layer 9, the pre-doped Zn or Be starts thermal diffusion toward the lower side, i.e., toward the Fe-doped InP substrate 1, without waiting for the arrival of newly added Zn from the outside, and therefore the p-type impurity is thermally diffused into the i-type InGaAs light absorption layer 6 in a short time.

[0055] In particular, when Zn is thermally diffused into the p-type InGaAs contact layer 10 and the p-type InP window layer 9 that have been doped with Be in advance, inter-diffusion (or mutual diffusion) of Be and Zn occurs, that is, a phenomenon in which Be and Zn replace impurity atoms already present in the semiconductor layer in a short time. This inter-diffusion causes the atoms that serve as the diffusion source, i.e., Zn, to reach the deepest part of the p-type impurity diffusion region 20 in an extremely short time. Since Zn has a higher diffusion rate than Be, Zn inter-diffuses into the i-type InGaAs light absorption layer 6 in a short time, which greatly reduces the diffusion time.

[0056] On the other hand, it is preferable to maintain a thick depletion layer on the outer periphery of the light-receiving region 60, that is, in the region covered with the selective diffusion mask 12, by preventing as much of the p-type impurity as possible from entering the inside of the i-type InGaAs light absorption layer 6. Since vacancies are unlikely to occur in the region covered with the selective diffusion mask 12, the p-type impurity is unlikely to thermally diffuse into the inside of the i-type InGaAs light absorption layer 6.

[0057] In particular, when the pre-doped p-type impurity is Be, the diffusion rate of Be is smaller than that of Zn as described above, and therefore interdiffusion of Be into the i-type InGaAs light absorption layer 6 is less likely to proceed, and the depletion layer can be maintained thick. Therefore, a suitable combination of impurity species is that the p-type impurity doped in the epitaxial crystal growth of the p-type InGaAs contact layer 10 and the p-type InP window layer 9 is Be, and the p-type impurity thermally diffused in the subsequent p-type impurity diffusion step is Zn.

[0058] After the above-mentioned p-type impurity diffusion process, the p-type InGaAs contact layer 10 is processed to have a ring shape when viewed from above. Fig. 4 is a cross-sectional view of the p-type InGaAs contact layer 10 after processing into a ring shape in the manufacturing method of the back-illuminated APD according to the first embodiment. The ring-shaped p-type InGaAs contact layer 10 is processed to have an inner diameter substantially the same as or smaller than the p-type impurity diffusion region 20. On the other hand, the outer diameter of the ring-shaped p-type InGaAs contact layer 10 may be smaller than or larger than the p-type impurity diffusion region 20.

[0059] Next, the p-type InP window layer 9 exposed on the outer peripheral surface of the ring-shaped p-type InGaAs contact layer 10 is removed by etching until it reaches the surface of the i-type InAlAs surface protection layer 8. Figure 5 is a cross-sectional view after patterning the p-type InP window layer 9 in the manufacturing method of the back-illuminated APD according to the first embodiment.

[0060] However, it is not always necessary to etch until the p-type InP window layer 9 is completely removed. In other words, it is sufficient if the p-type InP window layer 9 can be mostly removed by etching, and the p-type window layer 9 may remain on the surface of the i-type InAlAs surface protective layer 8 as long as the p-type window layer 9 has a layer thickness of about 100 nm. The reason for this is that if the partially remaining p-type InP window layer 9 is a thin layer, the remaining p-type InP window layer 9 is also depleted when a voltage is applied to the APD, and functions to alleviate the electric field of the terrace portion 40.

[0061] Furthermore, the etching depth may be set to about 100 nm from the lower surface of the i-type InAlAs surface protective layer 8 so that the etched surface reaches the inside of the i-type InAlGaAs graded layer 7 or the inside of the i-type InGaAs light absorption layer 6. The reason for this is that even if the p-type impurities are thermally diffused downward from the p-type InP window layer 9 during the heat treatment for thermal diffusion, the electric field in the terrace portion 40 is alleviated by removing the region into which the p-type impurities have been thermally diffused in a subsequent process.

[0062] The p-type InP window layer 9 and the i-type InAlAs surface protective layer 8 may both be made of InP layers. Alternatively, the p-type InP window layer 9 may be made of a p-type InAlAs layer, and the i-type InAlAs surface protective layer 8 may be made of an i-type InP layer. In the latter case, the window layers can be easily selectively etched.

[0063] By etching the p-type InP window layer 9 described above, a second mesa structure 31 is formed, which has a substantially circular surface in top view, and which includes the p-type InP window layer 9 and the p-type InGaAs contact layer 10 having a ring shape along the outer periphery of the light-receiving region 60 having a substantially circular shape in top view, which are sequentially formed on the first mesa structure 30 described below.

[0064] A mesa groove 35 is formed by leaving a terrace portion 40 having a width of 1 μm or more in the peripheral direction with the upper surface of the i-type InAlAs surface protection layer 8 as the outermost surface, i.e., the terrace surface 41, on the outer periphery side of the second mesa structure 31 having a substantially circular shape, that is, on the outer periphery side of the p-type InP window layer 9 after etching. The semiconductor layer on the outer periphery side is further etched until the etching surface reaches the n-type InAlAs conductive layer 3 or the n-type InP conductive layer 2. The depth of the mesa groove 35 may be such that the i-type InAlAs multiplication layer 4 is physically separated and the bottom surface of the etching does not reach the Fe-doped InP substrate 1. FIGS. 6A and 6B are a cross-sectional view and a top view, respectively, after the mesa groove 35 whose bottom surface of the etching reaches the n-type InP conductive layer 2 is formed in the manufacturing method of the back-illuminated APD according to the first embodiment.

[0065] The steps from patterning the p-type InGaAs contact layer 10 into a ring shape in Fig. 4 to forming the mesa groove in Fig. 6 may be performed in any order. For example, the p-type InP window layer 9 may be etched into a substantially circular shape in top view so that the etched surface reaches the i-type InAlAs surface protection layer 8, and then the p-type InGaAs contact layer 10 on the inner periphery side is etched away while leaving the outer periphery of the substantially circular p-type InGaAs contact layer 10, thereby patterning the p-type InGaAs contact layer 10 into a ring shape. Alternatively, the mesa groove 35 may be formed first, and then the p-type InP window layer 9 and the p-type InGaAs contact layer 10 may be patterned.

[0066] By etching the semiconductor layer on the outer periphery side of the second mesa structure 31 and the terrace portion 40, a first mesa structure 30 is formed, which has an n-type InP conductive layer 2, an n-type InAlAs conductive layer 3, an i-type InAlAs multiplication layer 4, a p-type InAlAs electric field relaxation layer 5, an i-type InGaAs light absorption layer 6, an i-type InAlGaAs graded layer 7, and an i-type InAlAs surface protection layer 8, which are sequentially formed on the Fe-doped InP substrate 1, with the n-type InP conductive layer 2 exposed on the outer periphery as a semiconductor layer, and has a substantially circular surface as viewed from above. In other words, the outermost surface of the first mesa structure 30 is exposed on the terrace portion 40 as a semiconductor layer.

[0067] On the wafer after the formation of the first mesa structure 30, a surface protection film 11 made of a SiN film and a front-side antireflection film 15 are formed. An opening is provided in the surface protection film 11 formed on the surface of the ring-shaped p-type InGaAs contact layer 10 and on the surface of the n-type InP conductive layer 2 exposed at the bottom of the mesa groove 35 by the above-mentioned etching. Instead of a SiN film, an insulating film made of an organic material such as a SiO2 film, a SiON film, a BCB (benzocyclobutene) film, or a polyimide may be used. FIG. 7 is a cross-sectional view after the surface protection film 11 made of a SiN film and the front-side antireflection film 15 are formed and the opening is patterned in the manufacturing method of the back-illuminated APD according to the first embodiment.

[0068] Next, a p-type electrode 51 is formed on the ring-shaped p-type InGaAs contact layer 10 and on the insulating film made of a SiN film of the light-receiving region 60, and an n-type electrode 50 is formed on the surface of the n-type InP conductive layer 2 exposed on the outer periphery of the first mesa structure 30. Fig. 8 is a cross-sectional view showing the element structure after the p-type electrode 51 and the n-type electrode 50 are formed in the manufacturing method of the back-illuminated APD according to the first embodiment.

[0069] The p-type electrode 51 and the n-type electrode 50 are formed from a combination of multiple metal films, such as Ti / Au, Ti / Pt / Au, Pt / Ti / Pt / Au, and Pt / Ti / Au / Ti / Pt / Au, from the bottom up. When mounting a back-illuminated APD in a junction-down manner, the p-type electrode 51 may be formed from multiple metal films, such as Ti / Au / Ti / Pt / Au, from the bottom up. The reason for inserting Pt into some of the multiple metal films is that Pt functions as a barrier metal that prevents the diffusion of solder material into the back-illuminated APD.

[0070] In the back-illuminated APD, which is an example of the semiconductor light receiving element 100 according to the first embodiment, the Fe-doped InP substrate 1 is used as the semiconductor substrate because the optical absorption loss due to the n-type InP substrate increases slightly when the n-type InP substrate is used in the case of the back-illuminated APD. However, there is no particular problem in the operation of the APD even if the n-type InP substrate is used instead of the Fe-doped InP substrate 1. When the n-type InP substrate is applied to the back-illuminated APD, an n-type electrode may be provided on the back side of the n-type InP substrate, and the back electrode of the back-illuminated APD may be used as the n-type electrode.

[0071] <Function of the semiconductor light receiving element according to the first embodiment> The operation of the back-illuminated APD, which is an example of the semiconductor light-receiving element 100 according to the first embodiment shown in FIG. 1, will be described below.

[0072] In the back-illuminated APD according to the first embodiment, the p-type InGaAs contact layer 10 and the p-type InP window layer 9 are doped with p-type impurities such as Zn and Be in advance during epitaxial crystal growth. For example, when solid-phase or vapor-phase diffusion of Zn is performed from the outside into the p-type InGaAs contact layer 10 and the p-type InP window layer 9, which are semiconductor layers doped with Be, Be, which is already contained as a p-type impurity, starts diffusing downward without waiting for the arrival of Zn by solid-phase or vapor-phase diffusion. Zn reaches the deepest part of the p-type impurity diffusion region 20 in an extremely short time due to the mutual diffusion of Be and Zn. That is, the p-type impurities, i.e., Zn and Be, mutually diffuse into the i-type InGaAs light absorption layer 6 in a short time.

[0073] Diffusion depth is (diffusion time) 0.5 Since the diffusion time is proportional to the diffusion depth, if the depth required for diffusion is halved, the diffusion time becomes 1 / 4, so that the p-type impurity can be thermally diffused into the i-type InGaAs light absorption layer 6 in a short time. By shortening the diffusion time, it is possible to prevent problems such as an increase in dark current caused by the diffusion of the p-type impurity already contained in the p-type InAlAs electric field relaxation layer 5 into the i-type InGaAs light absorption layer 6.

[0074] In the back-illuminated APD according to the first embodiment, the inner circumference side of the ring-shaped p-type InGaAs contact layer 10 functions as a light-receiving region 60. In the light-receiving region 60, electrons generated by light absorbed in the i-type InGaAs light absorption layer 6 travel to the i-type InAlAs multiplication layer 4 side and are multiplied.

[0075] The deepest part of the p-type impurity diffusion region 20 penetrates about 0.2 μm into the i-type InGaAs light absorption layer 6. Since the thickness of the i-type InGaAs light absorption layer 6 is about 0.6 μm in an APD for 50 Gbps, the thickness of the depletion layer inside the i-type InGaAs light absorption layer 6 is about 0.4 μm. As shown in the above formula (1), the response band determined by the time it takes for light to travel through the depletion layer inside the i-type InGaAs light absorption layer 6 is inversely proportional to the thickness of the depletion layer, so that the APD according to the first embodiment has improved reception sensitivity over a wide response band.

[0076] On the other hand, below the p-type InGaAs contact layer 10, the portion below the lower surface of the p-type InP window layer 9 becomes a depletion layer, and the thickness of the depletion layer increases. Since the capacitance of the pn junction of the APD is inversely proportional to the thickness of the depletion layer, the capacitance is reduced, and therefore the response band determined by the RC time constant is improved in the back-illuminated APD according to the first embodiment.

[0077] For example, when the total layer thickness from the lower surface of the p-type InP window layer 9 to the upper surface of the n-type InAlAs conductive layer 3, i.e., DL1 in FIG. 1, is 0.9 μm, and the total layer thickness from the deepest part of the p-type impurity diffusion region 20 to the upper surface of the n-type InAlAs conductive layer 3, i.e., DL2 in FIG. 1, is 0.6 μm, the capacitance per unit area below the p-type InGaAs contact layer 10 is 2 / 3 (=0.6 μm / 0.9 μm) of the capacitance per unit area of ​​the light-receiving region 60.

[0078] A back-illuminated APD according to the first embodiment in which the p-type impurity is thermally diffused only to the inner periphery of the ring-shaped p-type InGaAs contact layer 10 and a back-illuminated APD as a comparative example described below in which the p-type impurity is thermally diffused up to the outer periphery of the p-type InGaAs contact layer 10 are compared when the capacitance of the pn junction is set to that of an APD for 50 Gbps. The capacitance Cpn of the pn junction is expressed by the following equation (2). Cpn=εr ε0 S / Wt (2)

[0079] In equation (2), εr is the relative dielectric constant, ε0 is the dielectric constant of a vacuum (=8.85×10 -18 F / μm), S is the area of ​​the pn junction, and Wt is the thickness of the depletion layer. The relative dielectric constant εr varies depending on the composition of the semiconductor material, but is around 13.5. In reality, the dielectric constant differs slightly for each semiconductor layer, but to simplify the calculations, the relative dielectric constant εr of all semiconductor layers is set to a uniform 13.5.

[0080] In order to reduce capacity in a 50 Gbps APD, the diameter of the light receiving area, i.e., the inner circumference of the ring-shaped contact layer, must be reduced to about 10 μmΦ, and the diameter of the window layer, i.e., the outer circumference of the ring-shaped contact layer, must be reduced to about 16 μmΦ. The surface area of ​​a light receiving area with a diameter of 10 μmΦ is 78.5 μm 2 The surface area of ​​the window layer with a diameter of 16 μm is 201.0 μm 2 The surface area of ​​the window layer excluding the light receiving region, that is, the surface area of ​​the ring-shaped contact layer, is 122.5 μm 2 The pn junction capacitance Cpn of an APD according to a comparative example described later is calculated by the following formula (3). 13.5×8.85×10 -18 F / μm ×201.0μm 2 / 0.6μm=40fF (3)

[0081] On the other hand, the pn junction capacitance Cpn of the back-illuminated APD according to the first embodiment is calculated by the following formula (4). 13.5×8.85×10 -18 F / μm× (78.5μm 2 / 0.6μm+122.5μm 2 / 0.9μm)=32fF (4)

[0082] That is, the pn junction capacitance Cpn of the back-illuminated APD of the comparative example is 40 fF, whereas the pn junction capacitance Cpn of the back-illuminated APD according to the first embodiment is 32 fF, which is reduced by 8 fF. That is, in the back-illuminated APD according to the first embodiment, the pn junction capacitance Cpn can be reduced by 20% compared to the comparative example. Therefore, the bandwidth fcr (=1 / (2πCR)) determined by the capacitance C and the load resistance R is improved by 20%. For example, when the load resistance R is 50Ω, in the back-illuminated APD according to the first embodiment, the bandwidth fcr determined only by the pn junction capacitance Cpn is 100 GHz.

[0083] In addition, the response bandwidth of an APD is affected by factors other than the pn junction capacitance Cpn, such as the transit time and multiplication time of electrons and holes, parasitic capacitance, and element resistance. Therefore, in an APD for 50 Gbps, the response bandwidth determined by the pn junction capacitance Cpn and load resistance R must be approximately 100 GHz, which is about twice the transmission speed.

[0084] As described above, by reducing the thickness of the depletion layer in the light-receiving region through which electrons and holes travel, and by increasing the thickness of the depletion layer below the p-type contact layer in the region through which electrons and holes do not travel, it is possible to reduce the pn junction capacitance Cpn of the APD, and as a result, the response bandwidth is improved.

[0085] The drawback of making the entire window layer p-type is that an electric field applied to the side portion of the first mesa structure 30 increases during APD operation. If a large electric field is applied to each of the side portions of the i-type InAlAs multiplication layer 4, the p-type InAlAs electric field relaxation layer 5, and the i-type InGaAs light absorption layer 6 exposed on the side portion of the first mesa structure 30, the dark current changes over time, which may impair the reliability of the APD.

[0086] In the back-illuminated APD according to the first embodiment, a terrace portion 40 is provided between the side portion of the second mesa structure 31 and the side portion of the first mesa structure 30, thereby increasing the distance between the side portion of the second mesa structure 31 and the side portion of the first mesa structure 30 (hereinafter referred to as terrace width Lt). This reduces the electric field applied to the side portion of the first mesa structure 30, thereby providing a highly reliable back-illuminated APD.

[0087] The lower limit of the terrace width Lt is preferably 1 μm or more, which allows easy processing to form the terrace portion 40 and relaxes the electric field applied to the mesa groove 35. On the other hand, if the terrace width Lt is too long, that is, if the area of ​​the terrace portion 40 is too wide, the areas of the i-type InAlAs multiplication layer 4 and the i-type InGaAs light absorption layer 6 increase, which causes a problem of increasing the dark current. Therefore, the upper limit of the terrace width Lt is preferably 300 μm or less. Furthermore, considering that the device resistance increases as the distance between the light receiving region 60 and the n-type electrode 50 increases, the terrace width Lt is preferably 50 μm or less. In other words, it can be said that the terrace width Lt is preferably within the range of 1 μm to 50 μm.

[0088] <Advantages of the First Embodiment> As described above, according to the semiconductor light receiving element of the first embodiment, a device structure is formed in which a second mesa structure and a terrace portion are provided on the first mesa structure and a p-type impurity region is formed only in the light receiving region. This reduces the pn junction capacitance and suppresses thermal diffusion of the p-type impurity in areas other than the light receiving region, thereby providing an advantageous effect of providing a semiconductor light receiving element that operates over a wide response band and has high reliability.

[0089] As described above, according to the method for manufacturing a semiconductor light receiving element according to the first embodiment, the contact layer and the window layer are doped with p-type impurities in advance in the epitaxial crystal growth process, and the p-type impurities are selectively diffused only in the light receiving region into the light absorption layer in the p-type impurity diffusion process after the epitaxial crystal growth, so that the diffusion time of the p-type impurities can be shortened. Also, the time required for the heat treatment at high temperature during the p-type impurity diffusion can be shortened. As a result, the thermal diffusion of the p-type impurities contained in the electric field relaxation layer into the light absorption layer and the multiplication layer can be prevented, so that the dark current is reduced, and as a result, a semiconductor light receiving element with high reception sensitivity can be easily manufactured.

[0090] Furthermore, an advantage of doping the contact layer and window layer with p-type impurities in advance in the epitaxial crystal growth process, and selectively diffusing the p-type impurities only in the light-receiving region into the light-absorbing layer in the p-type impurity diffusion process after the epitaxial crystal growth, is that the thickness of the depletion layer formed under the ring-shaped p-type InGaAs contact layer can be made thicker than the thickness of the depletion layer formed in the light-receiving region on the inner periphery of the p-type InGaAs contact layer. This advantage makes it possible to reduce the pn junction capacitance, thereby achieving a semiconductor light-receiving element with a wide response band.

[0091] Comparative example of embodiment 1. 9 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor photodetector 200 according to a comparative example of embodiment 1. The semiconductor photodetector 200 according to the comparative example is structurally different from the semiconductor photodetector 100 according to embodiment 1 in that it does not have a second mesa structure, an i-type InAlAs surface protection layer, or a terrace portion, and that the contact layer and window layer are not doped with p-type impurities in advance during the epitaxial crystal growth process.

[0092] <Element structure of semiconductor photodetector (APD) according to a comparative example of the first embodiment> The back-illuminated APD, which is an example of the semiconductor light-receiving element 200 according to the first embodiment, is composed of an Fe-doped InP substrate 1 and a semiconductor layer having a carrier concentration of 5×10 17 ~8×10 18 cm -3 and an n-type InP conductive layer 2 having a thickness of 0.1 to 1.0 μm and a carrier concentration of 5×10 17 ~8×10 18 cm -3 The n-type InAlAs conductive layer 3 has a thickness of 0.1 to 1.0 μm, the i-type InAlAs multiplication layer 4 has a carrier concentration of 1×10 16 ~5×10 18 cm -3The p-type InAlAs field relaxation layer 5 has a thickness of 10 to 100 nm, the i-type InGaAs light absorption layer 6 has a thickness of 0.1 to 2.0 μm, the i-type InAlGaAs graded layer 7 has a thickness of 5 to 100 nm and the composition wavelength is gradually shortened, the i-type InP window layer 9a has a thickness of 0.1 to 3.0 μm and is undoped, and the i-type InP window layer 9b has a thickness of 0.05 to 0.5 μm and is undoped and has a substantially circular shape when viewed from above. a p-type impurity diffusion region 20a provided in a part of the i-type InGaAs light absorption layer 6 and an i-type InP window layer 9a on the outer periphery of the ring-shaped i-type InGaAs contact layer 10a, the p-type impurity diffusion region 20a being provided in a part of the i-type InGaAs light absorption layer 6; and a surface protective film 11 made of an insulating film covering the surface of the i-type InP window layer 9a exposed on the outer periphery of the ring-shaped i-type InGaAs contact layer 10a; a front-side antireflection film 15 made of a SiN film formed on the inner periphery of the ring-shaped i-type InGaAs contact layer 10a, i.e., on the surface of the i-type InP window layer 9a corresponding to the approximately circular light-receiving region 60; an n-type electrode 50 formed on the surface of the n-type InP conductive layer 2 exposed as a semiconductor layer on the outer periphery of the mesa structure 33; a p-type electrode 51 provided on the surface of the ring-shaped i-type InGaAs contact layer 10a and on the surface of the front-side antireflection film 15; a back-side antireflection film 16 provided on the back side of the Fe-doped InP substrate 1 at a position facing the p-type electrode 51; and a back electrode 52 provided on the outer periphery of the back-side antireflection film 16 on the back side of the Fe-doped InP substrate 1.

[0093] FIG. 10A is a cross-sectional view of the semiconductor photodetector 100 according to the first embodiment, i.e., a back-illuminated APD, after epitaxial crystal growth in a manufacturing method thereof, and FIG. 10B is a cross-sectional view of the semiconductor photodetector 100 according to the first embodiment, after epitaxial crystal growth in a manufacturing method thereof in a back-illuminated APD according to a comparative example to the first embodiment.

[0094] As shown in FIG. 10B, in the back-illuminated APD according to the comparative example of the first embodiment, the wafer after epitaxial crystal growth is configured with, on the Fe-doped InP substrate 1, the following semiconductor layers, in this order from the Fe-doped InP substrate 1 side: an n-type InP conductive layer 2, an n-type InAlAs conductive layer 3, an i-type InAlAs multiplication layer 4, a p-type InAlAs electric field relaxation layer 5, an i-type InGaAs light absorption layer 6, an i-type InAlGaAs graded layer 7, an i-type InP window layer 9a, and an i-type InGaAs contact layer 10a.

[0095] 10A and 10B, the back-illuminated APD according to the comparative example of the first embodiment is structurally different from the back-illuminated APD according to the first embodiment in that the stacked structure of semiconductor layers does not include an i-type InAlAs surface protection layer, and the InP window layer 9a and the InGaAs contact layer 10a each have an i-type conductivity type. That is, in the comparative example, the i-type InP window layer 9a and the i-type InGaAs contact layer 10a are i-type regions.

[0096] FIG. 11A is a cross-sectional view of a back-illuminated APD after a p-type impurity diffusion step in a manufacturing method for the back-illuminated APD according to the first embodiment, and FIG. 11B is a cross-sectional view of a back-illuminated APD after a p-type impurity diffusion step in a manufacturing method for the comparative example.

[0097] 11B, it takes a long time for Zn to reach the i-type InGaAs light absorption layer 6 from the outermost surface of the semiconductor layer, so that Be contained in advance as a p-type impurity in the p-type InAlAs electric field relaxation layer 5 thermally diffuses into the i-type InGaAs light absorption layer 6, resulting in a problem of an increase in dark current. In addition, Be also thermally diffuses toward the i-type InAlAs multiplication layer 4, partially turning the multiplication layer into a p-type layer, generating an electric field distribution in the multiplication layer, resulting in problems such as an increase in multiplication noise.

[0098] 11A according to the first embodiment, the diffusion time is short, so that the thermal diffusion of Be contained in advance as a p-type impurity in the p-type InAlAs electric field buffer layer 5 is suppressed, and the p-type impurity in the p-type InAlAs electric field buffer layer 5 does not thermally diffuse. Therefore, problems such as an increase in dark current and a deterioration in multiplication noise in the back-illuminated APD do not occur.

[0099] Embodiment 2 <Features of the semiconductor photodetector (APD) according to the second embodiment> 12 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor photodetector 110 according to embodiment 2. The semiconductor photodetector 110 according to embodiment 2 is structurally different from the semiconductor photodetector 100 according to embodiment 1 in that the multiplication layer of the semiconductor photodetector 100 according to embodiment 1 is an i-type InAlAs layer, i.e., has a random alloy structure, whereas the multiplication layer of the semiconductor photodetector 110 according to embodiment 2 has an i-type InAs / AlAs digital alloy structure. That is, the semiconductor photodetector 110 according to embodiment 2 has an i-type InAs / AlAs digital alloy structure multiplication layer 4a.

[0100] The i-type InAs / AlAs digital alloy structure multiplication layer 4a is, for example, composed of semiconductor layers in which an InAs layer (having a thickness of two atomic layers, approximately 0.6 nm) and an AlAs layer (having a thickness of two atomic layers, approximately 0.6 nm) are alternately laminated in this order.

[0101] However, the thickness of the InAs layer and the AlAs layer may be in the range of 2 to 6 atomic layers, respectively. The reason for 6 atomic layers or less is that it is desirable for the stacked structure of the InAs layer and the AlAs layer not to function as a quantum well structure. In other words, the digital alloy structure has two types of semiconductor layers, each made of a different semiconductor material, stacked alternately at a period of 2 to 6 atomic layers.

[0102] Furthermore, the number of atomic layers of each layer of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is preferably 2 to 4 atomic layers, with 2 atomic layers being optimal. The reason for this is that the thinner the atomic layer thickness of each layer, the greater the effect of reducing the ionization rate ratio k due to the digital alloy structure. Also, when considering not only the performance as a semiconductor light receiving element but also productivity, a layer thickness of 4 to 6 atomic layers, which reduces the number of shutter switching times during crystal growth by the MBE method, is also optimal.

[0103] Considering the above factors, it can be said that the number of atomic layers in each layer of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is preferably in the range of a period of 2 to 6 atomic layers. Similarly, from the viewpoint of productivity, the entire multiplication layer does not have to have an InAs / AlAs digital alloy structure, but a part of the multiplication layer may have an InAs / AlAs digital alloy structure and the rest may have an InAlAs random alloy structure.

[0104] The thickness of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is suitably in the range of 40 nm to 170 nm, but may be 300 nm or less. For example, if the thickness of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is 100 nm, the number of repetitions of the InAs layer (2 atomic layers) / AlAs layer (2 atomic layers) is 85.

[0105] The conductivity type of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is i-type, and the carrier concentration is 1×10 17 cm -3 The following is an example. However, the conductivity type of the InAs / AlAs digital alloy multiplication layer is 5×10 17 cm -3 It may be p-type or n-type as follows:

[0106] In addition to the multiplication layer having an InAs / AlAs digital alloy structure, for example, a digital alloy structure made of InAlAsSb, a material system containing antimony (Sb), can also be applied as the multiplication layer of the semiconductor light receiving element of the present disclosure.

[0107] In the semiconductor light receiving element 110 according to the second embodiment, similarly to the first embodiment, the diffusion depth is (diffusion time) 0.5 Since the diffusion time is proportional to the diffusion time, when the depth required for thermal diffusion is halved, the diffusion time becomes 1 / 4, so that the p-type impurity can be thermally diffused into the i-type InGaAs light absorption layer 6 in a short time. By shortening the diffusion time, it becomes possible to prevent problems such as an increase in dark current due to the thermal diffusion of the p-type impurity already contained in the p-type InAlAs electric field buffer layer 5 into the i-type InGaAs light absorption layer 6, and further, the p-type impurity thermally diffuses from the p-type InAlAs electric field buffer layer 5 to the i-type InAs / AlAs digital alloy structure multiplication layer 4a, causing the digital alloy structure multiplication layer to become disordered and the multiplication noise to deteriorate.

[0108] In the semiconductor light receiving element 110 according to the second embodiment, as in the first embodiment, the p-type impurity diffusion region 20 is provided only in the light receiving region 60 that affects the transit time of carriers to deepen the p-type region, so that the depth of the p-type region formed on the outer periphery side of the second mesa structure 31, i.e., below the terrace portion 40, is formed 0.3 μm shallower than the light receiving region 60. Therefore, even if the terrace width Lt is 0 μm, the distance between the p-type region and the i-type InAs / AlAs digital alloy structure multiplication layer 4a is 0.3 μm larger. As a result, in the back-illuminated APD according to the first embodiment, even if the terrace width Lt is 0 μm, i.e., the terrace portion 40 is not provided, the thickness of the depletion layer below the p-type InGaAs contact layer 10 is 0.3 μm larger than that of the semiconductor light receiving element 200 of the comparative example, and thus the effect of reducing the capacitance is achieved.

[0109] The semiconductor light receiving element 110 according to the second embodiment is characterized in that the multiplication layer has an i-type InAs / AlAs digital alloy structure. The following describes in detail the digital alloy structure multiplication layer, which is one of the structural features of the semiconductor light receiving elements of the present disclosure, including the semiconductor light receiving elements described below.

[0110] If a wideband APD of 37.5 GHz or more can be realized, the next generation high-speed PON system can be realized without using a DSP or SOA. In the case of a PD, which has a relatively easy response bandwidth, the response bandwidth is as follows: (1) RC time constant (R is the element resistance, C is the element capacitance) (2) Carrier transit time (the time it takes for an electron or hole to travel through the depletion layer) In addition, the APD is limited by (3) It is also limited by the multiplication time (the time it takes for electrons and holes to multiply in a chain reaction in the multiplication layer, which increases in proportion to the multiplication factor).

[0111] Although a PD can achieve the above-mentioned 37.5 GHz bandwidth, an APD requires a multiplication time, so if the multiplication factor is increased, it becomes difficult to achieve the desired bandwidth. The multiplication time TM is expressed by the following equations (5) to (7). Multiplication time TM=multiplication rate M / GB product (5) GB product=1 / (2πNkτav) (6) In other words, Multiplication time TM=2πNkMτav (7) It becomes.

[0112] Here, GB product is the product of the multiplication factor and the response bandwidth, k is the ionization rate ratio, N is a coefficient that is loosely dependent on the ionization rate ratio k, and τav is the average time that electrons and holes travel through the multiplication layer. Therefore, it is possible to shorten the multiplication time TM by reducing the ionization rate ratio k. In particular, to realize a high-speed PON system, it is necessary to make the multiplication time TM approach zero, that is, to make the ionization rate ratio k approach zero.

[0113] In order to make the ionization rate ratio k zero, various compound semiconductors have been proposed as materials for the multiplication layer. In addition, in order to reduce the ionization rate ratio k, a digital alloy structure has been proposed in which semiconductor layers with different compositions are alternately stacked in a cycle of 1 to 6 atomic layers. However, it is difficult to make the ionization rate ratio k zero in the digital alloy structure unless the structure is optimized. The digital alloy structure is described in Non-Patent Document 1.

[0114] Therefore, in order to reduce the ionization rate ratio k of the digital alloy structure, the inventors fabricated an APD with a digital alloy structure multiplication layer using a multiplication layer in which two-atom-layered InAs layers and two-atom-layered AlAs layers are alternately stacked, and as a result of analyzing the multiplication characteristics, they discovered that the distance that carriers travel in the multiplication layer until they are ionized is longer than that of an APD with an InAlAs multiplication layer made of normal bulk crystal, that is, an InAlAs random alloy structure multiplication layer. The distance that carriers travel in the multiplication layer until they are ionized is called the dead space.

[0115] Since the length of the dead space (hereinafter referred to as the dead space length) is longer for holes than for electrons, in the case of an InAlAs random alloy structure made of a normal bulk crystal, when the thickness of the multiplication layer is thinned to a level of several tens of nm, the ionization rate ratio k decreases because the holes cannot be ionized. However, when the thickness of the multiplication layer is thinned to a level of several tens of nm, a new problem occurs in that a leak current such as a tunnel current increases because a higher electric field needs to be applied to the multiplication layer in order to obtain a desired multiplication factor. In other words, an increase in the tunnel current increases the noise generated in the APD. On the other hand, the inventors' analysis discovered that the ionization rate ratio k=0 in the digital alloy structure even when the multiplication layer has a thickness of 100 nm or more because the dead space is unusually large in the digital alloy structure compared to the random alloy structure.

[0116] That is, the inventors have found for the first time that it is possible to make the ionization rate ratio k=0 while suppressing the tunnel current by forming the multiplication layer of the APD with a digital alloy structure. Specifically, it has been found that in the multiplication layer having the digital alloy structure of the present disclosure, the ionization rate ratio k drops sharply at a layer thickness of 170 nm or less, and in particular, the dead space effect improves dramatically when the layer thickness of the multiplication layer is in the range of 60 to 130 nm. That is, the inventors have demonstrated that the ionization rate ratio k=0, which was impossible to achieve with a multiplication layer having a random alloy structure or a multiplication layer having a thick digital alloy structure, can be achieved by applying the multiplication layer having the digital alloy structure of the present disclosure. At present, no research institute has reported that the thinning of the multiplication layer of an APD having a digital alloy structure has a higher effect of reducing the ionization rate ratio k than the thinning of the multiplication layer of an APD made of a conventional material.

[0117] The thickness of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is within a range of 40 nm to 1000 nm. However, in order to increase the dead space effect in the i-type InAs / AlAs digital alloy structure multiplication layer 4a, the thickness of the i-type InAs / AlAs digital alloy structure multiplication layer 4a may be within a range of 40 nm to 170 nm. Furthermore, considering the typical degree of variation in layer thickness during fabrication of the semiconductor light receiving element 110 of 20%, the thickness of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is more preferably within a range of 50 nm to 140 nm.

[0118] The operation of an APD having an i-type InAs / AlAs digital alloy structure multiplication layer will be described below. The inventors have found that the use of a digital alloy structure multiplication layer, as in the back-illuminated APD according to the second embodiment, enhances the dead space effect, that is, the effect of reducing the ionization rate ratio k.

[0119] Fig. 13 is a diagram (estimated values) showing the electric field dependence of the electron dead space in an InAlAs multiplication layer. As a result of analyzing the electron multiplication characteristics in a digital alloy structure multiplication layer, the inventors have clarified that the InAs / AlAs digital alloy structure multiplication layer of the present disclosure has a longer dead space than the conventional InAlAs random alloy structure multiplication layer, as shown in the graph of Fig. 17.

[0120] 14A to 14C are conceptual diagrams showing the ionization rates of electrons and holes, respectively, where FIG. 14A shows the case of electron ionization, FIG. 14B shows the case of hole ionization, and FIG. 14C shows the ionization rate when the multiplication layer is thinned. In a conventional InAlAs random alloy structure multiplication layer, as shown in the graph of FIG. 13, the dead space length is about 45 nm, so the layer thickness of the multiplication layer needs to be thinned to about 1.5 times the dead space (about 70 nm). However, thinning the multiplication layer to 70 nm increases the electric field in the multiplication layer, and the tunnel current increases sharply, resulting in increased noise.

[0121] On the other hand, in the i-type InAs / AlAs digital alloy structure multiplication layer 4a of the back-illuminated APD according to the second embodiment, as shown in the graph of FIG. 13, the reciprocal of the applied electric field is 1.47×10 -6 cm / V, the dead space length is approximately 85 nm, and therefore the ionization rate ratio k can be made close to zero even if the thickness of the multiplication layer is approximately 1.5 times the dead space (approximately 130 nm). Therefore, the effect of the tunnel current is small in the back-illuminated APD according to the second embodiment.

[0122] In addition, in the InAs / AlAs digital alloy structure multiplication layer, the dead space is highly dependent on the applied electric field. For example, when the reciprocal of the applied electric field is 1.27×10 -6 In the case of cm / V, the dead space length is about 50 nm, so the multiplication layer needs to be thinned to 75 nm, as shown in the graph in Figure 13. In other words, the thickness of the InAs / AlAs digital alloy structure multiplication layer can be made thicker than that of the InAlAs random alloy structure multiplication layer.

[0123] Fig. 15 is a diagram showing the layer thickness dependence of the ionization rate ratio and the tunnel current on the multiplication layer (experimental values ​​and literature values). The inventors fabricated APDs having an InAs / AlAs digital alloy structure multiplication layer and an InAlAs random alloy structure multiplication layer, respectively, measured the ionization rate ratio k, and further plotted the results in Fig. 15 together with the measurement results of Literature 1 and 2 described in Fig. 15. Literature 1 and 2 in Fig. 15 are as follows:

[0124] (1)Reference 1 Yuan Yuan,et al.,“Temperature dependence of the ionization coefficients of InAlAs and AlGaAs digital alloys”pp.794,Vol.6,No.8 / August 2018 / Photonics Research (2) Literature 2 Wenyang Wang,et al.,“Characteristics of thin InAlAs digital alloy avalanche photodiodes” pp.3841,Vol.46,No.16 / 15 August 2021 / Optics Letters

[0125] As shown in FIG. 15, in the InAlAs random alloy multiplication layer, the effect of reducing the ionization rate ratio k by the dead space cannot be realized unless the thickness of the multiplication layer is 80 nm or less. On the other hand, if the thickness of the multiplication layer is made thinner than 80 nm, the tunnel current increases rapidly and tunnel breakdown occurs. When the thickness of the multiplication layer is around 60 nm, the reduction of the ionization rate ratio k and the limitation of the tunnel current are barely compatible, but the margin of the layer thickness is only a few nm, making it extremely difficult to stably manufacture APDs. In addition, the ionization rate ratio k is large at 0.12. In other words, with the conventional InAlAs random alloy multiplication layer, it is difficult to apply the effect of reducing the ionization rate ratio k by making the layer thinner to APDs.

[0126] On the other hand, in the InAs / AlAs digital alloy structure multiplication layer of the present disclosure, as discovered by the inventors, the dead space is large, and therefore, as the multiplication layer is thinned, the ionization rate ratio k starts to decrease to 0.1 or less at a layer thickness of 170 nm, as shown in Fig. 15. Here, the ionization rate ratio k is determined from the measured value of the multiplication noise, and is the minimum value of the ionization rate ratio in the range of multiplication factors 1 to 10. For the same ionization rate ratio k, the thickness of the InAs / AlAs digital alloy structure multiplication layer is more than twice as large as that of the InAlAs random alloy structure multiplication layer.

[0127] As shown in FIG. 15, in an APD with a pn junction diameter of 20 μm, if the lower limit of the thickness of the multiplication layer for which the tunnel current is 1 μA is 40 nm, then the optimum thickness range for an InAs / AlAs digital alloy structure multiplication layer is from 40 nm to 170 nm, and the thickness within this range can be fabricated with sufficient reproducibility.

[0128] The thickness of the InAs / AlAs digital alloy multiplication layer, which can sufficiently reduce the ionization rate ratio k due to the dead space effect, is the reciprocal of the applied electric field of 1.47×10 -6 In the case of InAs / AlAs digital alloy structure multiplication layer, the thickness is approximately twice the length of the dead space, and considering that the length of the dead space is 85 nm as shown in FIG. 15, 170 nm, which is twice the length of the dead space, is a suitable upper limit for the thickness of the InAs / AlAs digital alloy structure multiplication layer.

[0129] In addition, in order to control the ionization rate ratio k to 0.05 or less in the InAs / AlAs digital alloy structure multiplication layer, the thickness of the multiplication layer is preferably 150 nm or less, as shown in Fig. 15. Furthermore, in order to achieve a tunnel current of 1 µA or less and an ionization rate ratio k of approximately zero, the optimum thickness of the multiplication layer is in the range of 60 nm to 130 nm. If a margin of 10 nm is set for the fabrication of the APD, the thickness of the multiplication layer is preferably set in the range of 70 nm to 120 nm.

[0130] Also, from FIG. 13, the length of the dead space is preferably 50 nm to 90 nm. The ratio of the length of the dead space to the thickness of the multiplication layer is preferably 29% or more, which is the minimum dead space length of 50 nm divided by the maximum multiplication layer thickness of 170 nm. As the ratio increases, the ionization rate ratio k becomes smaller, but it cannot exceed 100%. This is because multiplication does not occur when the ionization rate ratio k exceeds 100%. Therefore, in principle, the ratio of the length of the dead space to the thickness of the multiplication layer is preferably 29% or more and less than 100%. Furthermore, since the thickness of the multiplication layer in this prototype was 120 nm, the optimal range confirmed experimentally is 42% (= 50 nm / 120 nm) to 75% (= 90 nm / 120 nm).

[0131] The inventors have considered the reason why the ionization rate ratio k=0 can be achieved in the InAs / AlAs digital alloy structure multiplication layer of the present disclosure, whereas the ionization rate ratio k=0 could not be achieved in the conventional InAlAs random alloy structure multiplication layer.

[0132] If the electron dead space length is De and the hole dead space length is Dh, the conditions for achieving the ionization rate ratio k = 0 are expressed by the following formulas (8) and (9). Note that formula (8) represents the condition for the difference in the dead space lengths, and formula (9) represents the condition for the tunnel current. Dhe=Dh―De>0 (8) Dh>Tmin (9)

[0133] Here, Dhe is the difference between the dead space lengths of holes and electrons. Tmin is the minimum thickness of the multiplication layer at which the tunnel current becomes small enough that it does not affect noise, and the thicker the multiplication layer, the smaller the tunnel current becomes. As shown in the conceptual diagram of Figure 14C, when the thickness of the multiplication layer becomes equal to or smaller than the dead space length of holes, holes are no longer multiplied and the ionization rate ratio k = 0, so the condition for the difference in the dead space length is set as shown in the above formula (8).

[0134] 13 and 15, in the case of the InAlAs random alloy structure multiplication layer, the ionization rate ratio k starts to decrease when the multiplication layer is thinned, at values ​​De of about 40 nm and Dh of about 80 nm. Since the pn junction diameter is 20 μm and the tunnel current is set to 100 nA or less, the minimum layer thickness Tmin=90 nm, and therefore the InAlAs random alloy structure does not satisfy the tunnel current condition, and it is impossible to achieve the ionization rate ratio k=0.

[0135] On the other hand, in the case of an InAs / AlAs digital alloy structure multiplication layer, the ionization rate ratio k starts to decrease as the multiplication layer is thinned at values ​​De of about 80 nm and Dh of about 170 nm, and when the pn junction diameter is 20 μm and the tunnel current is 100 nA or less, the minimum layer thickness Tmin = 90 nm, so there exists a multiplication layer thickness that satisfies the condition of the ionization rate ratio k = 0. Note that the minimum layer thickness Tmin is the same for the InAs / AlAs digital alloy structure multiplication layer and the InAlAs random alloy structure multiplication layer because the band gaps of the two are the same.

[0136] Specifically, in the case of a random alloy structure, De is about 40 nm and Dh is about 80 nm, whereas in the case of a digital alloy structure, the inventors found that De is about 80 nm and Dh is about 170 nm.

[0137] In the InAs / AlAs digital alloy structure multiplication layer, the difference in lattice constant between the InAs (lattice constant = 0.606 nm) and AlAs (lattice constant = 0.566 nm) that make up the superlattice is very large at 6.55%, which means that the dopants in the electric field relaxation layer, that is, the impurities, may diffuse into the InAs / AlAs digital alloy structure multiplication layer during the fabrication process, causing disorder within the multiplication layer.

[0138] 16A to 16D are conceptual diagrams showing the ionization rate in the multiplication layer and the electric field relaxation layer, in which Fig. 16A shows the ionization rate in the case of the InAlAs random alloy structure multiplication layer, Fig. 16B shows the ionization rate in the case of the InAs / AlAs digital alloy structure multiplication layer, Fig. 16C shows the ionization rate in the case of the partially disordered InAs / AlAs digital alloy structure multiplication layer, and Fig. 16D shows the ionization rate in the case of a combination of a thick electric field relaxation layer and an InAs / AlAs digital alloy structure multiplication layer. Compared with the InAlAs random alloy structure multiplication layer shown in Fig. 16A, the dead space length of the InAs / AlAs digital alloy structure multiplication layer shown in Fig. 16B is long, but the dead space length of the partially disordered InAs / AlAs digital alloy structure multiplication layer due to dopant diffusion from the electric field relaxation layer is short as shown in Fig. 16C.

[0139] In order to avoid the influence of disorder in the InAs / AlAs digital alloy structure multiplication layer, the selection of the material and dopant of the electric field relaxation layer and the doping concentration are important. The impurity diffusion equation is expressed by the following equation (10). dN / dt=D(d 2 N / d 2 x)-F (10)

[0140] In formula (10), N is the impurity concentration, t is time, D is the diffusion constant, x is the position, and F is the external force acting on the diffusion. Examples of materials for the electric field buffer layer include InP, an InAlAs random alloy structure, and an InAs / AlAs digital alloy structure. Examples of p-type dopants for the electric field buffer layer include Be and Zn. Considering the p-type dopant, a combination of a Be-doped p-type InP electric field buffer layer and an InAs / AlAs digital alloy structure multiplication layer is preferable. This is because Be has a small diffusion constant D and also forms a potential barrier between the InAs / AlAs digital alloy structure multiplication layer. The potential barrier corresponds to F in formula (10).

[0141] In order to prevent the variation in the amount of electric field relaxation, that is, the product of the layer thickness and the carrier concentration, from increasing when the thickness of the electric field relaxation layer varies, the carrier concentration of the electric field relaxation layer is set to 2×10 18 cm -3 The following is preferable. When InAlAs is used as the material for the electric field relaxation layer, Zn doping is optimal, and the carrier concentration is 2×10 18 cm -3 The following is optimal. Note that 2×10 18 cm -3 When the impurity concentration is higher than 5×10, the inactive impurities increase and diffusion becomes more likely. 18 cm -3 The following is required:

[0142] The electric field relaxation amount ΔE is expressed by the following formula (11). ΔE=W q N / ε (11) In equation (11), W is the thickness of the electric field relaxation layer, q is the elementary charge, N is the carrier concentration of the electric field relaxation layer, and ε is the dielectric constant. If the electric field relaxation amount ΔE is constant, when the carrier concentration of the electric field relaxation layer is increased, the thickness of the electric field relaxation layer must be reduced in inverse proportion to the carrier concentration.

[0143] The carrier concentration N of the electric field relaxation layer is 5×10 18 cm -3 In order to prevent the dead space length from being shortened due to impurity diffusion into the multiplication layer, the carrier concentration of the field relaxation layer is set to 5×10 18 cm -3 The electric field relaxation layer must have a thickness of 10 nm or more.

[0144] On the other hand, as shown in Fig. 16D, when the electric field buffer layer becomes thicker than 1.5 times the dead space length of the electric field buffer layer, multiplication occurs in the electric field buffer layer. As shown in Fig. 13, in the random alloy structure, the dead space length is 45 nm or less, so the layer thickness of the electric field buffer layer made of the random alloy structure needs to be 70 nm or less. On the other hand, in the InAs / AlAs digital alloy structure, the dead space length is 85 nm or less, so the layer thickness of the digital alloy structure electric field buffer layer needs to be 130 nm or less.

[0145] The lengths of the dead spaces shown in FIGS. 16A to 16D have the following relationship: dead space (FIG. 16A)<dead space (FIG. 16D<dead space (FIG. 16C)<dead space (FIG. 16B).

[0146] <Effect of the digital alloy structure multiplication layer of the semiconductor photodiode (APD) according to the second embodiment> First, a first effect of the semiconductor light receiving element 110 according to the second embodiment will be quantitatively described below. The 3 dB bandwidth fc of a conventional APD is expressed by the following formula (12), where the bandwidth limitation due to the RC time constant is frc, the bandwidth limited by the carrier transit time is ftr, and the bandwidth limitation due to the multiplication time is fm. fc_APD=1 / ((1 / frc) 2 +(1 / ftr) 2 +(1 / fm) 2 ) 0.5 (12)

[0147] On the other hand, the 3 dB bandwidth fc of the APD having the InAs / AlAs digital alloy structure multiplication layer according to the first and second embodiments is limited only by the RC time constant and the carrier transit time according to equations (7) and (12) because the ionization rate ratio k is close to zero, and therefore can be expressed by the following equation (13). fc_APD=1 / ((1 / frc) 2 +(1 / ftr) 2 ) 0.5 (13) In equation (13), the transit time ftr of a carrier includes the transit time through the light absorption layer plus the transit time through the multiplication layer.

[0148] Since the RC time constant is inversely proportional to the sum of the thicknesses of the light absorption layer and the multiplication layer, while the transit time is directly proportional, equation (13) has a maximum value. In other words, the maximum bandwidth occurs when frc=ftr. By substituting frc=ftr, equation (13) can be expressed as the following equation (14). fc=ftr / √2 (14)

[0149] Moreover, the 3 dB bandwidth ftr determined by the running time is expressed by the following equation (15). ftr=3.5Vav / (2πWt) (15)

[0150] In equation (15), Vav is the average saturation transit velocity of electrons and holes, and Wt is the total thickness of the light absorption layer and the multiplication layer. For example, in the case of InGaAs, Vav is 5.35×10 6 In addition, if the thickness of the multiplication layer is 100 nm and the thickness of the light absorption layer is 400 nm, then Wt = 500 nm.

[0151] Vav=5.35×10 6 When cm / s and Wt=500 nm are substituted into formula (15), ftr=59.6 GHz is obtained. Furthermore, when the calculated ftr is substituted into formula (14), the 3 dB bandwidth of the APD having the InAs / AlAs digital alloy structure multiplication layer of the second embodiment is 42.2 GHz. Therefore, it is clear from the above consideration that the APD having the InAs / AlAs digital alloy structure multiplication layer according to the second embodiment can meet the bandwidth of 37.5 GHz required for a 50G-PON system. In the description of the device, system, etc. described later, the APD having the InAs / AlAs digital alloy structure multiplication layer according to the second embodiment of the present disclosure is called the DA-APD of the present disclosure.

[0152] <Advantages of the second embodiment> As described above, the semiconductor photodetector according to the second embodiment further includes a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and thus has the effect of providing a semiconductor photodetector that operates in a wider response band and has high receiving sensitivity.

[0153] Variation 1 of embodiment 2 <Features of the semiconductor photodetector (APD) according to the first modification of the second embodiment> 17 is a cross-sectional view showing an element structure of a back-illuminated APD which is an example of a semiconductor photodetector 120 according to Modification 1 of Embodiment 2. The semiconductor photodetector 120 according to Modification 1 of Embodiment 2 is structurally different from the semiconductor photodetector 110 according to Embodiment 2 in that the window layer of the semiconductor photodetector 110 according to Embodiment 2 is a p-type InP window layer 9, whereas the window layer of the semiconductor photodetector 110 according to Embodiment 2 is composed of two layers, that is, an i-type InP first window layer 9b and a p-type InAlAs second window layer 9c, from the i-type InAlAs surface protection layer 8 side.

[0154] In the configuration of the back-illuminated APD according to the first modification of the second embodiment, the semiconductor layers from the n-type InP conductive layer 2 to the i-type InAlAs surface protective layer 8 are the same as those in the back-illuminated APD according to the second embodiment, and therefore their description will be omitted.

[0155] In the back-illuminated APD according to the first modification of the second embodiment, an i-type InAlAs first window layer 9b having a thickness of 0.1 to 1 μm and an i-type InP first window layer 9b having a carrier concentration of 5×10 17 ~8×10 18 cm -3 and a p-type InAlAs second window layer 9c having a layer thickness of 0.1 to 2.0 μm and a carrier concentration of 5×10 17 ~8×10 18 cm -3 and a p-type InGaAs contact layer 10 having a ring shape that fits around the outer periphery of the light receiving region 60, which has a layer thickness of 0.05 to 0.5 μm and is approximately circular in top view.

[0156] As in the back-illuminated APD according to the second embodiment, the i-type InAlAs surface protection layer 8 may be an i-type InP layer, the first window layer may be an InAlAs layer, and the second window layer may be a p-type InP layer.

[0157] <Function of Semiconductor Photodetector (APD) According to Modification 1 of Second Embodiment> The back-illuminated APD according to the first modification of the second embodiment has the same actions and effects as the back-illuminated APD according to the second embodiment. As described above, the back-illuminated APD according to the first modification of the second embodiment has the i-type InP first window layer 9b, and therefore the thickness of the depletion layer below the ring-shaped p-type InGaAs contact layer 10 is thicker by the thickness of the i-type InP first window layer 9b. When the thickness of the i-type InP first window layer 9b is 0.3 μm, formula (4) becomes formula (16) below.

[0158] 13.5×8.85×10 -18 F / μm×(78.5μm 2 / 0.6μm +122.5μm 2 / (0.9μm+0.3μm))=28fF (16)

[0159] Since the pn junction capacitance Cpn of the back-illuminated APD according to the first embodiment calculated from equation (4) is reduced from 32 fF, which is the pn junction capacitance Cpn of the back-illuminated APD according to the first modification of the second embodiment calculated from equation (16), to 28 fF, which is the pn junction capacitance Cpn of the back-illuminated APD according to the first modification of the second embodiment, the RC time constant can be reduced in the back-illuminated APD according to the first modification of the second embodiment. On the other hand, since the thickness of the depletion layer in the light-receiving region 60 in the back-illuminated APD according to the first modification of the second embodiment does not change, the transit time of carriers does not increase. As a result, the response band of the entire APD is improved, that is, a wide response band is obtained.

[0160] <Effects of Modification 1 of Embodiment 2> As described above, in the semiconductor photodetector of the first modification of the second embodiment, the window layer is formed of two layers, that is, the i-type InP first window layer and the p-type InAlAs second window layer. This reduces the pn junction capacitance, thereby providing an advantageous effect of providing a semiconductor photodetector that operates in a wider response band and has high reliability.

[0161] Variation 2 of embodiment 2 <Features of Semiconductor Photodetector (APD) According to Modification 2 of Embodiment 2> 18 is a cross-sectional view showing an element structure of a back-illuminated APD which is an example of a semiconductor photodetector 130 according to Modification 2 of Embodiment 2. The semiconductor photodetector 130 according to Modification 2 of Embodiment 2 is structurally different from the semiconductor photodetector 110 according to Embodiment 2 in that, in the semiconductor photodetector 110 according to Embodiment 2, the upper surface of the i-type InAlAs surface protection layer 8 immediately below the p-type InP window layer 9 serves as the terrace surface 41 in the terrace portion 40, and this i-type InAlAs surface protection layer 8 relaxes the electric field applied to the side portion exposed to the mesa groove 35 of the i-type InAs / AlAs digital alloy structure multiplication layer 4a, whereas in the semiconductor photodetector 130 according to Modification 2 of Embodiment 2, the upper surface of the p-type InAlAs electric field relaxation layer 5 immediately below the i-type InGaAs light absorption layer 6 serves as the terrace surface 41a in the terrace portion 40a. That is, the outer periphery of the p-type InGaAs contact layer 10 having a ring shape when viewed from above is etched down to the p-type InAlAs electric field buffer layer 5 so that the terrace surface 41a is formed by the upper surface of the p-type InAlAs electric field buffer layer 5.

[0162] In the back-illuminated APD according to the second embodiment, the i-type InAlAs surface protective layer 8 formed between the i-type InAlGaAs graded layer 7 and the p-type InP window layer 9 functions as both a surface protective layer and a graded layer. On the other hand, in the back-illuminated APD according to the second modification of the second embodiment, the i-type InAlAs layer formed between the i-type InAlGaAs graded layer 7 and the p-type InP window layer 9 functions solely as the i-type InAlAs graded layer 8a.

[0163] The p-type InAlAs electric field buffer layer 5 may have either a random alloy structure or a digital alloy structure. The p-type electric field buffer layer may be made of a p-type InP layer. A graded layer made of an i-type InAlGaAs layer or an i-type InGaAsP layer may be provided between the p-type InAlAs electric field buffer layer 5 and the i-type InGaAs light absorption layer 6.

[0164] The terrace surface 41a in the terrace portion 40a may be formed not only by the upper surface of the p-type InAlAs electric field buffer layer 5, but also by an intermediate surface of the p-type InAlAs electric field buffer layer 5 or an intermediate surface of the i-type InAs / AlAs digital alloy structure multiplication layer 4a.

[0165] When a graded layer is provided between the p-type InAlAs electric field buffer layer 5 and the i-type InGaAs light absorption layer 6, the terrace surface 41a in the terrace portion 40a may be configured as an upper surface or an intermediate surface of the graded layer. Furthermore, even if the terrace surface 41a is configured as a surface of the i-type InGaAs light absorption layer 6 remaining on the p-type InAlAs electric field buffer layer 5 with a layer thickness of 100 nm or less, there is no problem because the electric field is buffered by the terrace portion 40a. That is, in the back-illuminated APD according to the second modification of the second embodiment, the terrace surface 41a may be the upper surface of the p-type InAlAs electric field buffer layer 5 or within a range of 100 nm in layer thickness in the vertical direction from the upper surface of the p-type InAlAs electric field buffer layer 5.

[0166] <Functions and Effects of Semiconductor Photodetector (APD) According to Modification 2 of Second Embodiment> In the back-illuminated APD according to the second embodiment, the i-type InGaAs light absorption layer 6 is present below the terrace surface 41 as shown in Fig. 12, but in the back-illuminated APD according to the second modification of the second embodiment, the i-type InGaAs light absorption layer 6 is not present below the terrace surface 41a as shown in Fig. 18. The i-type InGaAs light absorption layer 6, which has a small band gap, causes dark current, but in the back-illuminated APD according to the second modification of the second embodiment, the semiconductor layers other than the light-receiving region 60 and the p-type InGaAs contact layer 10 are removed by etching down to the top surface of the p-type InAlAs electric field relaxation layer 5. As a result, the area of ​​the i-type InGaAs light absorption layer 6 is reduced, which has the effect of reducing the dark current.

[0167] 12, in the back-illuminated APD according to the second embodiment, when incident light 90 is incident on the Fe-doped InP substrate 1 having a thickness of 100 μm or more, the light beam spreads as the light propagates through the Fe-doped InP substrate 1, and the light is also absorbed in the i-type InGaAs light absorption layer 6 outside the light-receiving region 60, generating electrons and holes. The electrons and holes generated in the terrace portion 40 and the like outside the light-receiving region 60 have a long distance to the p-type region, and therefore take a long time to travel, which may result in deterioration of the frequency response. Therefore, in the case of a back-illuminated APD, care must be taken to prevent the light beam from spreading and the optical axis of the light from shifting from the light-receiving region.

[0168] On the other hand, in the back-illuminated APD according to the second modification of the second embodiment, the i-type InGaAs light absorption layer 6 below the terrace portion 40a is removed in order to reduce light absorption in areas other than the light-receiving region 60, so that the incident light spreads in the direction of the terrace portion 40a and is not absorbed even if it is incident on the terrace portion 40a. In other words, even if the beam of the incident light 90 spreads inside the back-illuminated APD, the response band is not deteriorated.

[0169] By thermally diffusing the p-type impurity only into the light-receiving region 60, the p-type impurity diffusion region 20 is made deeper, while the p-type region below the ring-shaped p-type InGaAs contact layer 10 remains shallow. As a result, the electric field applied to the side portion of the i-type InGaAs light absorption layer 6 is reduced, and a highly reliable back-illuminated APD is obtained.

[0170] In addition, the side surface of the i-type InAs / AlAs digital alloy structure multiplication layer 4a on the side of the mesa groove 35, to which a high electric field is applied, is located further outward than the terrace portion 40a and is farther away from the p-type InP window layer 9. As a result, the electric field applied to the side surface of the i-type InAs / AlAs digital alloy structure multiplication layer 4a during APD operation is reduced, resulting in a highly reliable back-illuminated APD.

[0171] As the lower limit of the terrace width Lt, a terrace width Lt of 1 μm or more is preferable because it is easy to process the terrace portion 40a and the electric field applied to the side surface exposed to the mesa groove 35 is relaxed. On the other hand, if the terrace width Lt is too long, that is, if the area of ​​the terrace portion 40a is too wide, the area of ​​the i-type InAs / AlAs digital alloy structure multiplication layer 4a increases, which causes a problem of increasing the dark current. Therefore, the upper limit of the terrace width Lt is preferably 300 μm or less. Furthermore, considering that the element resistance increases as the distance between the light receiving region 60 and the n-type electrode 50 increases, the terrace width Lt is more preferably 50 μm or less. Therefore, it can be said that the terrace width Lt is preferably in the range of 1 μm to 50 μm.

[0172] When a SiN film or SiO2 film is formed on a semiconductor layer by chemical vapor deposition (CVD) using a source gas containing hydrogen, hydrogen is taken up into the semiconductor layer and combines with impurities (dopants) and vacancies. When the impurities combine with hydrogen, the impurities become inactivated and the carrier concentration decreases. This phenomenon is called hydrogen passivation. To efficiently induce the film formation reaction, heat, light, or plasma is used, and plasma enhanced chemical vapor deposition (PECVD) is commonly used. With plasma enhanced CVD, hydrogen passivation is particularly likely to occur due to the large reaction energy. If the upper surface or intermediate surface of the electric field relaxation layer made of a p-type InAlAs layer or a p-type InP layer is used as the terrace surface 41a, hydrogen passivation occurring during the deposition of the surface protective film 11 made of an insulating film by the plasma-excited CVD method reduces the activation rate of p-type impurities such as Zn and Be contained in the p-type electric field relaxation layer 5, and the carrier concentration due to the p-type impurities in the p-type electric field relaxation layer 5 located below the terrace portion 40a decreases. That is, a hydrogen passivation region 45 is formed inside the p-type electric field relaxation layer 5 located below the terrace portion 40a. As a result of the formation of the hydrogen passivation region 45, the electric field concentration in the multiplication layer located below the terrace portion 40a is relaxed, and edge breakdown, i.e., local multiplication in the side portion exposed to the mesa groove 35, does not occur, and low noise characteristics specific to the digital alloy structure multiplication layer are obtained.

[0173] <Effects of Modification 2 of Embodiment 2> As described above, according to the semiconductor photodetector of the second modification of the second embodiment, the upper surface of the p-type electric field relaxation layer is the terrace surface of the terrace portion, and therefore the electric field applied to the side portion of the i-type InGaAs light absorption layer is kept small, thereby achieving an effect of realizing a semiconductor photodetector having low dark current, low noise, and high reliability, and in which the response band does not deteriorate even if the incident light beam spreads inside the semiconductor photodetector.

[0174] Variation 3 of embodiment 2 <Features of Semiconductor Photodetector (APD) According to Modification 3 of Second Preferred Embodiment> 19 is a cross-sectional view showing an element structure of a back-illuminated APD which is an example of a semiconductor photodetector 140 according to the third modification of the second embodiment. The semiconductor photodetector 140 according to the third modification of the second embodiment is structurally different from the semiconductor photodetector 130 according to the second modification of the second embodiment in that the i-type InAlGaAs graded layer 7 and the i-type InGaAs light absorbing layer 6 below the p-type InP window layer 9 in the semiconductor photodetector 130 according to the second modification of the second embodiment are both i-type conductive, whereas the p-type InAlGaAs graded layer 7a and the upper part of the InGaAs light absorbing layer are p-type in the semiconductor photodetector 140 according to the third modification of the second embodiment. That is, the InGaAs light absorbing layer is composed of two layers, an i-type InGaAs first light absorbing layer 6a and a p-type InGaAs second light absorbing layer 6b, from the side in contact with the p-type InAlAs electric field relaxation layer 5.

[0175] The i-type InGaAs first light absorbing layer 6a is provided on its upper side with a carrier concentration of 5×10 17 ~8×10 18 cm -3 A p-type InGaAs second light absorption layer 6b having a thickness of 0.4 μm or less is formed, and a p-type InAlGaAs graded layer 7a having a thickness of 5 to 100 nm and a composition wavelength that becomes shorter in stages, and a p-type InAlAs graded layer 7b having a thickness of 10 to 200 nm are formed on the upper side of the p-type InGaAs second light absorption layer 6b. The p-type InP window layer 9 and the subsequent semiconductor layers above the p-type InAlAs graded layer 7b are the same as those in the semiconductor light receiving element 130 according to the second modification of the second embodiment.

[0176] Here, when the upper part of the light absorption layer is a p-type semiconductor layer, that is, when the p-type InGaAs second light absorption layer 6b is provided, holes tend to flow from the p-type InGaAs second light absorption layer 6b to the p-type InP window layer 9, so that the p-type InAlGaAs graded layer 7a and the p-type InAlAs graded layer 7b are not necessarily required.

[0177] <Functions and Effects of Semiconductor Photodetector (APD) According to Modification 3 of Second Embodiment> In the semiconductor light receiving element 140 according to the third modification of the second embodiment, the entire light absorption layer is p-type up to the p-type InGaAs second light absorption layer 6b located at the upper side, so that the diffusion time is further shortened. Therefore, it is possible to prevent an increase in dark current due to thermal diffusion of the p-type impurity contained in the p-type InAlAs electric field buffer layer 5, and a deterioration in multiplication noise due to disordering of the i-type InAs / AlAs digital alloy structure multiplication layer 4a caused by the thermal diffusion of the p-type impurity.

[0178] Variation 4 of embodiment 2 <Features of Semiconductor Photodetector (APD) According to Modification 4 of Second Preferred Embodiment> Fig. 20 is a cross-sectional view showing an element structure of a back-illuminated APD which is an example of a semiconductor photodetector 150 according to Modification 4 of Embodiment 2. The semiconductor photodetector 150 according to Modification 4 of Embodiment 2 is structurally different from the semiconductor photodetector 140 according to Modification 3 of Embodiment 2 shown in Fig. 19 in that, while the semiconductor photodetector 140 according to Modification 3 of Embodiment 2 has a p-type electric field buffer layer made of a p-type InAlAs layer and has a p-type impurity diffusion region 20, the semiconductor photodetector 150 according to Modification 4 of Embodiment 2 has a p-type InP layer and does not have a p-type impurity diffusion region.

[0179] When the electric field relaxation layer is made of a p-type InP layer, examples of p-type impurities to be doped in advance into the p-type InP layer include Zn, C, Be, and Mg. In the fourth modification of the second embodiment, as described above, no p-type impurity diffusion region is provided on the inner periphery side of the p-type InGaAs contact layer 10. Therefore, the boundary between the i-type region and the p-type region inside the InGaAs light absorption layer made up of two layers, the i-type InGaAs first light absorption layer 6a and the p-type InGaAs second light absorption layer 6b, i.e., the interface where the i-type InGaAs first light absorption layer 6a and the p-type InGaAs second light absorption layer 6b contact each other, is uniform in the horizontal direction, i.e., in the direction parallel to the surface of the Fe-doped InP substrate 1.

[0180] <Functions and Effects of Semiconductor Photodetector (APD) According to Modification 4 of Second Embodiment> When forming insulating films such as SiN and SiO2 films on a p-type InP layer, a phenomenon occurs in which hydrogen is taken into the semiconductor layer during processing such as plasma processing in an atmosphere containing hydrogen. When hydrogen is taken into the p-type semiconductor layer, the hydrogen inactivates the p-type impurities. This phenomenon is called hydrogen passivation.

[0181] The hydrogen passivation inactivates the p-type impurities contained in the p-type InP electric field buffer layer 5a, thereby reducing the carrier concentration of the p-type InP electric field buffer layer 5a. In the p-type InP electric field buffer layer 5a exposed on the outer periphery of the terrace portion 40, the carrier concentration is easily reduced by hydrogen passivation. That is, a hydrogen passivation region 45a is formed inside the p-type InP electric field buffer layer 5a located below the terrace portion 40a. Furthermore, a carrier concentration reduction region is formed inside the i-type InAs / AlAs digital alloy structure multiplication layer 4a located below the hydrogen passivation region 45a.

[0182] In the hydrogen passivation region 45a, which is a portion of the p-type InP electric field relaxation layer 5a where the carrier concentration is reduced, that is, in the region where the amount of electric field relaxation is reduced, multiplication is less likely to occur in the i-type InAs / AlAs digital alloy structure multiplication layer 4a in contact with the hydrogen passivation region 45a. Therefore, an effect is achieved in which edge breakdown is suppressed at the side portion of the i-type InAs / AlAs digital alloy structure multiplication layer 4a.

[0183] Hydrogen that is taken into the semiconductor layer due to hydrogen passivation generated by the formation of the insulating film is desorbed and reduced during high-temperature heat treatment processes after the formation of the insulating film. Actual measurements show that hydrogen is 2×10 17 ~1×10 18 cm -3 The carrier concentration of the p-type InP electric field relaxation layer 5a before hydrogen passivation occurs is 5×10 17 ~2×10 18 cm -3 Therefore, 2 × 10 17 ~1×10 18 cm-3 The introduction of hydrogen of this concentration into the p-type InP electric field buffer layer 5a reduces the carrier concentration of the p-type InP electric field buffer layer 5a by about half. Therefore, the formation of the hydrogen passivation region 45a can reduce the carrier concentration of the p-type InP electric field buffer layer 5a located below the terrace portion 40, which provides an advantage of enhancing the effect of suppressing edge breakdown.

[0184] Hydrogen is also incorporated into the semiconductor layer during epitaxial crystal growth. However, the hydrogen concentration in the semiconductor material lattice-matched to the InP substrate without hydrogen passivation is 5×10 16 cm -3 p-type InP electric field relaxation layer 5a is 5×10 17 ~2×10 18 cm -3 The carrier concentration of the p-type InP electric field relaxation layer 5a is 5×10 17 ~2×10 18 cm -3 It is believed that the effect of hydrogen passivation is realized if hydrogen is present in the p-type InP electric field buffer layer 5a at a concentration of the same order as that of the p-type InP electric field buffer layer 5a. Therefore, the hydrogen concentration taken into the p-type InP electric field buffer layer 5a exposed to the terrace portion 40, i.e., the hydrogen concentration in the hydrogen passivation region 45a, is 2×10 17 ~1×10 18 cm -3 A range of 100% is preferable.

[0185] Here, in the above-mentioned p-type InP electric field relaxation layer 5a, the carrier concentration due to p-type impurities is 5×10 17 ~2×10 18 cm -3 The optimum thickness of the electric field relaxation layer in this case will be explained. The electric field relaxation amount is expressed as elementary charge × carrier concentration × layer thickness of multiplication layer / (relative dielectric constant · dielectric constant of vacuum). In order to obtain the electric field relaxation amount of 700 kV / cm required for the electric field relaxation layer, if the relative dielectric constant of the electric field relaxation layer is 13, the carrier concentration due to the p-type impurity should be 5 × 10 17 cm -3In this case, the thickness of the electric field relaxation layer is 100 nm, and the carrier concentration is 2×10 18 cm -3 In this case, the thickness of the electric field buffer layer is 25 nm. Therefore, in the p-type InP electric field buffer layer 5a, the carrier concentration due to the p-type impurity is 5×10 17 ~2×10 18 cm -3 In the case where the thickness is within this range, the layer thickness is preferably within the range of 25 to 100 nm.

[0186] For example, in Patent Document 6, in order to reduce the amount of electric field relaxation on the outer periphery side of the electric field relaxation layer, the layer thickness of the electric field relaxation layer in the outer periphery is thinned by etching. On the other hand, in Modification 4 of the second embodiment, the amount of electric field relaxation in the terrace portion 40 can be reduced by the hydrogen passivation effect simply by forming the surface protection film 11 made of, for example, a SiN film on the terrace surface 41 of the terrace portion 40, and as a result, excess noise due to edge breakdown can be suppressed. As described above, in Modification 4 of the second embodiment, the manufacturing process of the structure for suppressing edge breakdown is simplified, and further, since etching of the electric field relaxation layer, which is poor in controllability, is not performed, the variation in element characteristics is also small. Also, in Modification 4 of the second embodiment, since the thermal diffusion of p-type impurities, which is a high-temperature heat treatment, is not performed, the digital alloy structure multiplication layer is not disordered, and therefore an APD with low noise characteristics can be easily realized.

[0187] In addition, in the second, third and fifth modifications (described later) of the second embodiment, the electric field buffer layer is formed of a p-type InP layer, and thus the same effect as in the fourth modification of the second embodiment can be obtained. As in the fourth modification of the second embodiment, the preferred ranges of the p-type impurity carrier concentration and layer thickness of the electric field buffer layer are a p-type impurity carrier concentration of 5×10 17 ~2×10 18 cm -3 and the layer thickness is within a range of 25 to 100 nm.

[0188] Modification 5 of the second embodiment <Features of Semiconductor Photodetector (APD) According to Modification 5 of Second Preferred Embodiment> 21 is a cross-sectional view showing the element structure of a back-illuminated APD which is an example of a semiconductor photodetector 160 according to Modification 5 of Embodiment 2. The semiconductor photodetector 160 according to Modification 5 of Embodiment 2 is characterized in that it has two terraces: a first terrace 42a having the p-type InAlAs electric field buffer layer 5 below the i-type InGaAs light absorption layer 6 as its outermost surface, and a second terrace 42b having the i-type InAlAs surface protective layer 8 below the p-type InP window layer 9 as its outermost surface.

[0189] The semiconductor light receiving element 160 according to the fifth modification of the second embodiment includes an Fe-doped InP substrate 1, a first mesa structure 30 having an n-type InP conductive layer 2, an n-type InAlAs conductive layer 3, an i-type InAs / AlAs digital alloy structure multiplication layer 4a, and a p-type InAlAs electric field relaxation layer 5, which are sequentially formed on the Fe-doped InP substrate 1, and an i-type InGaAs light absorption layer 6, a p-type InAlGaAs graded layer 7a, and , an i-type InAlAs surface protection layer 8, a first terrace portion 42a consisting of the outermost surface of the first mesa structure 30 exposed on the outer periphery of the second mesa structure 31, a third mesa structure 32 formed on the second mesa structure 31 and having a p-type InP window layer 9 having a band gap larger than that of the i-type InGaAs light absorption layer 6, and a second terrace portion 42b consisting of the outermost surface of the second mesa structure 31 exposed on the outer periphery of the third mesa structure 32.

[0190] As an example of a method for manufacturing the semiconductor light receiving element 160 according to the fifth modification of the second embodiment, there is a manufacturing method in which the p-type InP window layer 9 in the second embodiment is etched to form the second terrace portion 42b as shown in Fig. 5, and then the i-type InAlAs surface protective layer 8, the p-type InAlGaAs graded layer 7a, and the i-type InGaAs light absorption layer 6 are removed by etching to form the first terrace portion 42a as shown in Fig. 22. After the first terrace portion 42a is formed, a mesa groove 35 is formed whose etched surface reaches the n-type InP conductive layer 2, and the surface protective film 11, the n-type electrode 50, the p-type electrode 51, and the back surface antireflection film 16 are formed in the same manner as in the second embodiment.

[0191] The terrace width Lt suitable for both the first terrace portion 42a and the second terrace portion 42b is preferably 1 μm or more, which is easy to process and relaxes the electric field applied to the mesa groove 35. On the other hand, if the terrace width Lt is too wide, the areas of the i-type InGaAs light absorption layer 6 and the i-type InAs / AlAs digital alloy structure multiplication layer 4a increase, and the dark current increases. In consideration of the above, the total terrace width Lt of the first terrace portion 42a and the second terrace portion 42b is preferably 300 μm or less, and further, considering that the element resistance increases when the distance between the light receiving region 60 and the n-type electrode 50 increases, it is preferably 50 μm or less. From the above, it can be said that the terrace width Lt of both the first terrace portion 42a and the second terrace portion 42b is preferably within the range of 1 μm to 50 μm.

[0192] <Functions and Effects of Semiconductor Photodetector (APD) According to Modification 5 of Second Embodiment> When a large electric field is applied to the exposed side surfaces of the i-type InAs / AlAs digital alloy structure multiplication layer 4a, the p-type InAlAs electric field relaxation layer 5, and the i-type InGaAs light absorption layer 6, the dark current changes over time, causing a problem of loss of reliability. In the semiconductor light receiving element 160 according to the fifth modification of the second embodiment, the second terrace 42b is provided in addition to the first terrace 42a, so that the distance from the p-type InP window layer 9 to the exposed side surfaces of the i-type InGaAs light absorption layer 6 can be increased, and the electric field applied to the side surfaces of the i-type InGaAs light absorption layer 6 can be relaxed.

[0193] Furthermore, the first terrace 42a, like the second modification of the second embodiment, reduces electric field concentration on the side surface of the i-type InAs / AlAs digital alloy structure multiplication layer 4a, preventing edge breakdown, i.e., local multiplication on the side surface, thereby providing the effect of stably obtaining low noise that is characteristic of a digital alloy structure multiplication layer. As described above, by forming the first terrace 42a and the second terrace 42b, it is possible to provide a highly reliable APD in which the dark current and multiplication noise are stable over a long period of time.

[0194] Embodiment 3 <Features of the semiconductor photodetector (APD) according to the third embodiment> Fig. 23 is a cross-sectional view showing an element structure of a front-illuminated APD which is an example of a semiconductor light receiving element 170 according to embodiment 3. The difference from the semiconductor light receiving element 110 according to embodiment 2 shown in Fig. 12 is that the semiconductor light receiving element 110 according to embodiment 2 is a back-illuminated APD in which light is incident from the back side of a semiconductor substrate, whereas the semiconductor light receiving element 170 according to embodiment 3 is a front-illuminated APD in which light is incident from the front side of a semiconductor substrate.

[0195] The front-illuminated APD, which is an example of the semiconductor light-receiving element 170 according to the third embodiment, includes an n-type InP substrate 1a and a semiconductor layer having a carrier concentration of 5×10 17 ~8×10 18 cm -3 and an n-type InAlAs conductive layer 3 having a thickness of 0.1 to 1.0 μm, an i-type InAs / AlAs digital alloy structure multiplication layer 4a, and a carrier concentration of 1×10 16 ~5×10 18 cm -3 The semiconductor device includes a p-type InAlAs electric field relaxation layer 5 having a thickness of 10 to 100 nm, an i-type InGaAs light absorption layer 6 having a thickness of 0.1 to 2.0 μm, an i-type InAlGaAs graded layer 7 having a thickness of 5 to 100 nm in which the composition wavelength is gradually shortened, and an i-type InAlAs surface protection layer 8 having a thickness of 10 to 200 nm. The n-type InP substrate 1a is exposed on the outer periphery as a semiconductor layer. The first mesa structure 30 has a substantially circular surface as viewed from above. 17 ~8×10 18 cm -3 and a p-type InP window layer 9 having a layer thickness of 0.1 to 3.0 μm and a carrier concentration of 5×10 17 ~8×10 18 cm -3a p-type InGaAs contact layer 10 having a ring shape along the outer periphery of a light receiving region 60 having a layer thickness of 0.05 to 0.5 μm and a substantially circular shape in a top view, a second mesa structure 31 having a substantially circular surface in a top view, a p-type impurity diffusion region 20 provided in a part of the p-type InP window layer 9 and the i-type InGaAs light absorption layer 6 on the inner periphery side of the ring-shaped p-type InGaAs contact layer 10, a terrace portion 40 consisting of a first mesa structure 30 exposed on the outer periphery side of the second mesa structure 31 and having a terrace surface 41 having a width of 1.0 μm or more in the outer periphery direction, and a front-side antireflection coating 15 made of a SiN film formed on the inner periphery of the ring-shaped p-type InGaAs contact layer 10, i.e., on the surface of the p-type InP window layer 9 corresponding to the approximately circular light-receiving region 60; a mesa groove 35 reaching the n-type InP substrate 1a on the outer periphery of the first mesa structure 30; a light-shielding metal film 66 made of a metal film covering the terrace surfaces 41 of the terrace portion 40 and the side portions of the first mesa structure 30; a p-type electrode 51a provided on the front surface of the ring-shaped p-type InGaAs contact layer 10; and an n-type electrode 50a provided on the back surface of the n-type InP substrate 1a.

[0196] The light-shielding metal film 66 is made of the same material as the p-type electrode 51a, such as Ti / Au or Ti / Pt / Au, from the contact surface side. As described above, the p-type impurity diffusion region 20 is provided on the inner peripheral side of the ring-shaped p-type InGaAs contact layer 10 so as to reach the i-type InGaAs light absorption layer 6.

[0197] Here, i-type means undoped, or p-type or n-type with a carrier concentration of 5×10 17 cm -3 The case is as follows. Since the semiconductor light receiving element 110 according to the second embodiment uses an Fe-doped InP substrate 1, the n-type electrode 50 needs to be formed on the front side of the Fe-doped InP substrate 1. On the other hand, the semiconductor light receiving element 170 according to the third embodiment uses an n-type InP substrate 1a as shown in Fig. 23, so that the n-type electrode 50a can be formed on the back side of the n-type InP substrate 1a.

[0198] <Actions and Effects of Semiconductor Photodetector (APD) According to Third Embodiment> In the case of a back-illuminated APD, which is an example of the semiconductor photodetector 110 according to the second embodiment, when light is incident on the Fe-doped InP substrate 1 having a layer thickness of 100 μm or more, the light beam spreads and enters the i-type InGaAs light absorption layer 6 other than the light-receiving region 60, and the light is absorbed also in the region other than the light-receiving region 60, generating electrons and holes.

[0199] In areas other than the light-receiving region 60, such as the terrace portion 40 and the lower side of the p-type InGaAs contact layer 10, the depletion layer is thick, so the time it takes for generated carriers such as electrons and holes to travel is long. Therefore, in the case of a back-illuminated APD, it is necessary to prevent the light beam from spreading and the optical axis from shifting from the light-receiving region 60.

[0200] On the other hand, in the front-illuminated APD according to the third embodiment, the light-shielding metal film 66 is arranged in areas other than the light-receiving region 60, such as the terrace portion 40, so that even if the incident light is incident on the terrace portion 40, it is not absorbed by the i-type InGaAs light absorption layer 6. In addition, because the surface of the ring-shaped p-type InGaAs contact layer 10 is covered with the p-type electrode 51, light is not incident on the i-type InGaAs light absorption layer 6 located below the p-type InGaAs contact layer 10. As a result, even if the light beam spreads or the optical axis shifts inside the front-illuminated APD, carrier components with a slow response speed are not generated, and an effect is achieved in which a semiconductor photodetector (APD) with a wide response band is obtained.

[0201] Embodiment 4 24 is a configuration diagram showing an optical line terminal (OLT) 260 of a 50G-PON system according to the third embodiment. The optical line terminal 260 includes a forward error correction (FEC) 261, a driver amplifier 262, a light source 263, a wavelength division multiplexing (WDM) 264, a clock data recovery (CDR) 265 which is a clock and data recovery circuit, a limiting amplifier 266, a burst TIA 267, and a DA-APD 268 of the present disclosure.

[0202] It should be noted that the DA-APD of the present disclosure refers to the APD described in the above-mentioned second embodiment, modifications 1 to 5 of the second embodiment, and third embodiment, in which the multiplication layer has an InAs / AlAs digital alloy structure.

[0203] 25 is a configuration diagram showing an optical line terminal (ONU) of a 50G-PON system according to embodiment 4. The optical line terminal 270 includes a WDM 271, a light source 272, a driver amplifier 273, an FEC 274, a DA-APD 275 of the present disclosure, a TIA 276, a limiting amplifier 277, and a CDR 278.

[0204] 26 is a configuration diagram showing an optical line terminal (OLT) 250a of a 50G-PON system as a comparative example. The optical line terminal 250a as the comparative example includes a forward error correction (FEC) circuit FEC251, a driver amplifier 252, a light source 253, a wavelength division multiplexing (WDM) circuit WDM254, a digital signal processing circuit DSP255, an analog-to-digital converter (ADC) circuit ADC256, a burst TIA257, and a conventional APD258.

[0205] As shown in the optical line terminal 250a of the 50G-PON system in the comparative example shown in Fig. 26, the 50G-PON system in the comparative example requires digital bandwidth compensation, that is, the DSP 255. On the other hand, in the 50G-PON system using the DA-APD of the present disclosure, digital bandwidth compensation is not required. That is, as shown in the optical line terminal (ONU) of the 50G-PON system according to the fourth embodiment shown in Fig. 25, if the DA-APD of the present disclosure is used, a wide response band and high receiving sensitivity are possible, so that it is possible to simplify the DSP circuit, save power, and reduce the output power of the SOA.

[0206] To increase the number of branches in a PON system and eliminate the need for an SOA, it is necessary to improve the signal-to-noise ratio of the receiver and increase the receiving sensitivity. For example, if an optical demultiplexer is added to increase the number of branches from the current level, the amount of light will be halved, so the signal-to-noise ratio must be improved by at least 3 dB. The signal-to-noise ratio of a receiver using an APD is expressed by the following equation (17). SN ratio=Iph 2 M 2 / (2q(Iph+Id)M 2 ·F·B +4Kb T Ft B / Rt) (17)

[0207] In equation (17), Iph is the photocurrent of the APD, M is the gain, q is the unit charge, Id is the dark current to be multiplied, F is the excess noise factor of the APD, B is the bandwidth, Kb is the Boltzmann constant, T is the absolute temperature, Ft is the noise figure of the amplifier, and Rt is the input resistance. The term on the left of the denominator represents the shot noise of the APD, and the term on the right of the denominator represents the thermal noise of the amplifier.

[0208] To simplify equation (17), we assume that Id is sufficiently smaller than Iph, and that the APD shot noise term and the amplifier thermal noise term are equal when the gain is at the maximum SNR. If we then replace the amplifier thermal noise term with the APD shot noise term, the SNR can be expressed by the following equation (18). SN ratio=Iph / (4q F B) (18)

[0209] Moreover, the excess noise factor F is given by the following equation (19). F = M(1-(1-k)·((M-1) 2 / M 2 )) (19)

[0210] In the case of the conventional InAlAs random alloy multiplication layer, when the layer is thinned to the extent that the dead space effect appears (approximately 70 nm), the tunnel current increases and the noise worsens as described above. In order to minimize the tunnel current, it is necessary to reduce the pn junction diameter to several μm or less, but this makes the alignment precision when focusing the light on the APD strict. Although it is inferior to the noise of the digital alloy multiplication layer, it is possible to reduce the noise to a certain extent even with the random alloy multiplication layer by thinning the multiplication layer in this way, but since the pn junction has a small diameter, there are restrictions in terms of productivity, etc. For this reason, the ionization rate ratio k for the non-thinned InAlAs multiplication layer is set to 0.2 and the system is designed. When the ionization rate ratio k=0.2 and the multiplication factor is 12 times, the excess noise factor F=3.9.

[0211] On the other hand, in the 50G-PON system according to the fourth embodiment, an APD with an InAs / AlAs digital alloy structure as a multiplication layer, that is, the DA-APD of the present disclosure, is applied as a semiconductor light receiving element. In the case of the InAs / AlAs digital alloy structure multiplication layer of the present disclosure, the dead space effect works even with a layer thickness of 100 nm or more, so it can be applied to an APD. In this case, the ionization rate ratio k=0, and when the multiplication factor is 12 times, the excess noise factor F=1.9. Therefore, the excess noise is about half that of the conventional APD. As a result, the DA-APD of the present disclosure is applied, and the signal-to-noise ratio is improved by 3 dB.

[0212] Generally, in a 50G-PON system, inserting one stage of a 2-way demultiplexer to increase the number of branches increases the loss by 3 dB. Therefore, by applying the DA-APD disclosed herein as a semiconductor photodetector, it becomes possible to insert one more stage of demultiplexer into a 50G-PON system.

[0213] 27 is a diagram illustrating a configuration of an optical line terminal (OLT) of a 50G-PON system according to embodiment 4. The optical line terminal 260a of the 50G-PON system includes an FEC 261, a driver amplifier 262, a light source 263, a WDM 264, a DSP 265a, an ADC 266a, a burst TIA 267, and a DA-APD 268 of the present disclosure.

[0214] 28 is a diagram illustrating a configuration of an optical line terminal (ONU) of a 50G-PON system according to embodiment 4. The optical line terminal 260b of the 50G-PON system includes an FEC 261, a driver amplifier 262, a light source 263, a WDM 264, a DSP 265a, an ADC 266a, a TIA 267a, and a DA-APD 268 of the present disclosure.

[0215] The effect of the semiconductor light receiving element according to the present disclosure will be further explained. In the DA-APD of the present disclosure, the APD having an InAs / AlAs digital alloy structure multiplication layer controls the thickness of the multiplication layer within a preset range to set the ionization rate ratio k to zero, so that the multiplication time in formula (7) becomes almost zero. As a result, the response band of the APD does not deteriorate even if the multiplication factor is increased. In other words, in the DA-APD of the present disclosure, the response band is limited only by the RC time constant and the carrier travel time, as in the conventional PD. Therefore, it is possible to widen the response band required for the 50G-PON system, and reception is possible without digital band compensation by DSP.

[0216] In addition, when the ionization rate ratio k approaches zero, excess noise that deteriorates receiver sensitivity is suppressed, making it unnecessary to amplify the optical signal using an SOA. Furthermore, even in PON systems other than 50G-PON systems, it becomes possible to achieve more branching than before. As a result, PON systems can be made cheaper and more energy-efficient.

[0217] <Advantages of the Fourth Embodiment> As described above, according to the optical line terminal of embodiment 4, the DA-APD disclosed herein is used as the semiconductor photodetector, thereby achieving the effect of obtaining an optical line terminal that can increase the transmission distance of optical signals and reduce power consumption.

[0218] Embodiment 5. Fig. 29 is a diagram illustrating a configuration of a multi-level intensity modulation transmitting / receiving apparatus 300 according to embodiment 5. Fig. 30A and Fig. 30B are conceptual diagrams illustrating assumed received waveforms in the multi-level intensity modulation transmitting / receiving apparatus 300 according to embodiment 4.

[0219] The multilevel intensity modulation transmitting / receiving device 300 is a multilevel intensity modulation transmitting / receiving device using a PAM (Pulse Amplitude Modulation) method, which is a multilevel intensity modulation method. In the transmitting section, a digital signal generated in a DSP 301 is converted to an analog signal in a DAC 302a, amplified in a driver amplifier 303, and driven by a light source 304 consisting of a DFB laser or EML to emit an optical signal to an optical fiber cable 310.

[0220] Meanwhile, in the receiving section, the light passes through the optical fiber cable 310 and the optical system and enters the DA-APD 305, which is the semiconductor light receiving element of the present disclosure, where the optical signal is converted into a current and multiplied. The optical signal is then amplified in the Linear-TIA 306, converted into a digital signal in the ADC 302b, and signal processing is performed by the DSP 301.

[0221] <Functions and Effects of the Multilevel Intensity Modulation Transmitter / Receiver According to the Fifth Embodiment> In a PAM-based multilevel intensity modulation transmitting / receiving device 300, it is necessary to receive not only binary signals of 1 and 0 such as NRZ (None Return to Zero) and RZ (Return to Zero), but also, for example, four values ​​of different optical signal intensity in PAM4 (Pulse Amplitude Modulation-4). An assumed example of a PAM4 received waveform is shown in the conceptual diagram of FIG. 30A. An index called TDECQ (Transmitter Dispersion and Eye Closure Quaternary) is used to judge the quality of the received waveform in PAM4. TDECQ is calculated by the following equation (20). TDECQ(dB)=10·log(OMA / (6·Qt·R)) (20)

[0222] In equation (20), the optical modulation amplitude (OMA) is the total amplitude from level 0 to level 3, Qt is a value that depends on the SER (Symbol Error Rate) defined by the IEEE (Institute of Electrical and Electronics Engineers), and R is the additional noise value required to achieve the SER value. TDECQ (dB) is defined as, for example, 3 dB or less. To reduce TDECQ (dB), (1) The eye opening at each level must be uniform. (2) Low noise at each level is necessary.

[0223] In order to ensure uniform eye openings for each of the four levels of optical signal strength, the semiconductor photodetector must have excellent linearity. Here, a semiconductor photodetector has good linearity when the photocurrent Iph increases in proportion to the optical input power Pin. In other words, the linearity is good if Iph / Pin is constant even if the optical input power Pin changes.

[0224] In addition, PAM needs to receive signals with low to high intensity, so it needs to have a good dynamic range. In other words, if the amount of decrease in Iph / Pin is small even if the optical input power Pin increases, the dynamic range can be said to be good. As shown in the received waveform in the conceptual diagram of Fig. 30B for explanation, if the linearity and dynamic range deteriorate, the eye opening formed between level 2 and level 3 deteriorates.

[0225] In the case of PDs and APDs, the linearity deteriorates when the photocurrent increases with an increase in optical input, which causes an increase in the number of holes and electrons traveling in the multiplication layer and the light absorption layer, changing the electric field distribution in the multiplication layer and the light absorption layer. This phenomenon is called the space charge effect.

[0226] The inventors have studied a model of degradation of the linearity of an APD. Figures 31A and 31B are conceptual diagrams for explaining the operation of a PD when a high optical input is applied. As shown in Figure 31A, when the optical input increases and the photocurrent increases, a space charge effect acts as if a voltage drop occurs due to the series resistance and no voltage is applied to the pn junction. This voltage drop reduces the multiplication factor. This is because the generated electrons and holes affect the electric field distribution, as shown in Figure 31B. The series resistance Rli that degrades the linearity of an APD is expressed by the following equation (21). Rli = Rsc + Rd + Rlo (21)

[0227] In equation (21), Rsc is the resistance due to the space charge effect, Rd is the element resistance, and Rlo is the load resistance. Rd and the load resistance are usually several tens of Ω, but Rsc can be several hundreds of Ω or more.

[0228] The inventors have found that, when the time it takes for electrons and holes generated by light absorption to pass through the depletion layer is Td, Rsc can be expressed by the following formula (22). Rsc=W Td / (2εS) (22) In equation (22), W is the thickness of the depletion layer, ε is the dielectric constant, and S is the pn junction area. The resistance Rsc due to the space charge effect is proportional to the time it takes for electrons and holes to pass through the depletion layer, Td. Therefore, it is possible to reduce the resistance Rsc by increasing the speed at which electrons and holes travel and reducing Td.

[0229] In the DA-APD disclosed herein, the multiplication time is short, so the response band does not deteriorate even when used at a high multiplication factor. Therefore, even if the amount of light absorbed in the optical absorption layer is small, the receiver sensitivity can be increased by operating at a high multiplication factor, making it possible to thin the optical absorption layer, which in turn reduces the resistance Rsc. As a result, the eye opening becomes uniform, so that the TDECQ satisfies the specified value. Furthermore, it becomes possible to increase the transmission distance and reduce the driving current of the transmitting laser.

[0230] The case where the DA-APD of the present disclosure is used will be described below. First, the operation of the APD at high light input will be described. FIG. 32 is a conceptual diagram for explaining the operation of the APD at high light input. When a large number of electrons and holes are generated in the multiplication layer, the electric field in the multiplication layer of the APD changes, that is, the so-called space charge effect occurs. Due to the occurrence of this space charge effect, the multiplication factor of the APD decreases and the linearity deteriorates. As described above, since the deterioration of the linearity of the APD is caused by the series resistance Rsc, it is necessary to reduce the residence time Tdm of the electrons and holes in the depletion layer. In particular, when the multiplication factor increases, the residence time Tdm in the multiplication layer increases. Tdm is the same as the so-called multiplication time, and is expressed by the following formula (23). Residence time Tdm=multiplication time=2πNkMτav (23)

[0231] In equation (23), N is the Emmons coefficient (which depends gently on the ionization rate ratio k), M is the multiplication factor, and τav is the average time it takes for electrons and holes to travel through the multiplication layer. The one-way transit time for carriers to traverse the multiplication layer is excluded from the residence time Tdm. When the ionization rate ratio k=0.5 (InP), 0.2 (InAlAs), 0.1 (Si), and 0 to 0.001 (InAs / AlAs digital alloy structure), N is 0.55, 0.83, 1.1, and 2.0, respectively.

[0232] Figure 33 shows the residence time Tdm (estimated value) of electrons and holes for each material that composes the multiplication layer. In the InAs / AlAs digital alloy structure multiplication layer, the residence time Tdm in the multiplication layer is dramatically reduced. In other words, since electrons and holes are quickly discharged from the multiplication layer, the space charge effect in the multiplication layer is suppressed, and as a result, the linearity and dynamic range are improved in the InAs / AlAs digital alloy structure multiplication layer.

[0233] As a result, while the conventional APD had a non-uniform PAM4 eye opening as shown in the conceptual diagram of Fig. 30B, the DA-APD of the present disclosure has a uniform eye opening as shown in the conceptual diagram of Fig. 30A, making it possible for the TDECQ to satisfy the specified value. Therefore, when the DA-APD of the present disclosure is used, an APD can be used in a PAM transceiver as well, making it possible to increase the transmission distance of an optical signal and reduce the drive current of the transmitting laser.

[0234] <Advantages of the Fifth Embodiment> As described above, according to the multi-level intensity modulation transceiver of embodiment 5, the DA-APD disclosed herein is used as the semiconductor photodetector, thereby achieving the effect of obtaining a multi-level intensity modulation transceiver that can increase the transmission distance of an optical signal and reduce power consumption.

[0235] Embodiment 6 Fig. 34 is a schematic diagram showing the configuration of a radio on fiber system 400 (Radio on fiber: RoF) according to the sixth embodiment. Fig. 35 is a schematic diagram showing the configuration of a radio on fiber system 450, which is a comparative example. The radio on fiber system 400 includes a light source 401, a transmission line 402 such as an optical fiber cable, a DA-APD 403 of the present disclosure, and an antenna 404.

[0236] In a radio-on-fiber system 400 according to the sixth embodiment, an analog electrical amplitude signal is input to a light source 401 such as an LD and converted into an optical amplitude signal. The converted optical amplitude signal is transmitted through an optical fiber cable, i.e., a transmission line 402. The transmitted optical amplitude signal is multiplied and converted into an electrical amplitude signal using a DA-APD 403 of the present disclosure. The converted electrical amplitude signal is transmitted to an antenna 404 and radiated as a radio wave signal.

[0237] The radio-on-fiber system 400 according to the sixth embodiment can efficiently supply a signal to the antenna 404 that is located at a distance from the electric signal source. In addition, since no analog-to-digital or digital-to-analog conversion is performed during transmission, the system has a simple configuration and consumes little power.

[0238] <Functions and Effects of Radio on Fiber System According to Sixth Embodiment> In the comparative example radio-on-fiber system 450 shown in FIG. 35, if a signal is attenuated during transmission through the optical fiber cable, the signal cannot be amplified by the PD 406, and therefore a sufficient radio signal cannot be emitted from the antenna.

[0239] Furthermore, when a conventional APD is used, as shown in the conceptual diagrams of Figures 31A and 31B, an increase in the number of electrons and holes in the multiplication layer causes a change in the electric field distribution, resulting in saturation of the multiplication factor and making it impossible to ensure a dynamic range. This causes problems such as not only being unable to obtain a sufficient amplitude of the electrical signal, but also distorting the analog signal. As a result, it is difficult to apply a conventional APD to the radio-on-fiber system 450 of the comparative example.

[0240] On the other hand, in the DA-APD of the present disclosure used in the radio-on-fiber system 400 according to the sixth embodiment, the multiplication time is short, so that the response band does not deteriorate even when used at a high multiplication factor. Therefore, even if the amount of light absorbed in the optical absorption layer is small, the reception sensitivity can be increased by operating at a high multiplication factor, so that the optical absorption layer can be made thinner, and the resistance Rsc can be reduced by making the optical absorption layer thinner. As a result, a response with good linearity can be obtained over a wide dynamic range, and a large current amplitude can be obtained. In this way, the radio-on-fiber system 400 is configured using the DA-APD of the present disclosure, so that it is possible to output a strong radio wave signal with good linearity even if the optical transmission distance is long.

[0241] Furthermore, in the DA-APD403 of the present disclosure, as shown in FIG. 33, the residence time Tdm of electrons and holes in the multiplication layer is short, so that the change in the electric field distribution in the multiplication layer is suppressed. As a result, a response with excellent linearity can be obtained over a wide dynamic range. In other words, since the DA-APD403 of the present disclosure multiplies the signal, the original signal can be reproduced and a large current amplitude can be obtained.

[0242] The DA-APD 403 of the present disclosure can be used with a multiplication factor in the range of 1.2 to 10. However, since a larger multiplication factor causes signal distortion, it is preferable to use a multiplication factor in the range of 1.2 to 5. In addition, considering the loss of the optical fiber and the quantum efficiency of the APD, which is not 100% but about 80%, it is optimal to use a multiplication factor of 2 to 3 to compensate for such loss.

[0243] <Advantages of the Sixth Embodiment> As described above, according to the radio-on-fiber system of the sixth embodiment, the DA-APD of the present disclosure is used to configure the radio-on-fiber system, which has the effect of providing a radio-on-fiber system capable of outputting a strong radio signal even if the optical transmission distance is long.

[0244] Embodiment 7 36 is a schematic diagram illustrating a configuration of a digital coherent receiving device 500 according to the seventh embodiment. The digital coherent receiving device 500 according to the seventh embodiment is characterized in that it uses a DA-APD 505a according to the present disclosure.

[0245] In digital coherent communication, optical signals in which both phase and intensity are modulated are polarization-multiplexed and transmitted through optical fibers. In a digital coherent receiving device 500, an optical signal input from an optical fiber cable 501 is first polarization-separated by a polarization separator 502. After polarization separation, each polarized signal light is input to a 90-degree hybrid device 503a and a 90-degree hybrid device 503b, respectively. Meanwhile, a laser light locally emitted from a semiconductor laser 504 is separated into two signals with a phase shift of 90 degrees from each other.

[0246] The signal light and the laser light are multiplexed, and the signal light is further separated into orthogonal components (I, Q) and output. The four optical signals, i.e., four optical signals in total, each consisting of orthogonal I and Q components for each polarization, are respectively incident on four balanced detectors 505 arranged in 90-degree hybrid devices 503a, 503b, each consisting of two DA-APDs 505a of the present disclosure connected in series as a pair. The electrical signal output from the balanced detector 505 is input to the DSP 506. The digital coherent receiving device 500 according to the seventh embodiment has the above-mentioned configuration.

[0247] <Function of the digital coherent receiving device according to the seventh embodiment> FIG. 37A is a conceptual diagram for explaining a waveform expected in a digital coherent receiving device which is a comparative example, and FIG. 37B is a conceptual diagram for explaining a waveform expected in a digital coherent receiving device according to embodiment 7.

[0248] In the conventional balanced detector, a PD was used as a semiconductor light receiving element that receives signal light. On the other hand, when the DA-APD505a of the present disclosure is used, it is possible to multiply the signal, so that it is possible to suppress the local light to a small value. In addition, when the conventional APD is used, as shown in the conceptual diagram of FIG. 32, when the number of electrons and holes in the multiplication layer increases, the electric field distribution changes, so that the multiplication factor is saturated and the dynamic range cannot be secured. For this reason, not only is it not possible to obtain a sufficient amplitude of the electrical signal, but there is also a problem that the analog signal is distorted. As a result, as shown in the conceptual diagram of FIG. 37A, in the comparative example, the interval between the waveform A1 and the waveform B1 becomes narrow, and the intensity signal of the constellation waveform is distorted, so that it is difficult to apply the APD.

[0249] On the other hand, in the DA-APD of the present disclosure used in the digital coherent receiving device 500 according to the seventh embodiment, the multiplication time is short, so that the response band does not deteriorate even when used at a high multiplication factor. Therefore, even if the amount of light absorbed in the light absorbing layer is small, the reception sensitivity can be increased by operating at a high multiplication factor, so that it is possible to make the light absorbing layer thinner, and since the thinner light absorbing layer makes it less susceptible to the influence of the resistance Rsc due to the space charge effect, a constellation waveform with excellent linearity over a wide dynamic range can be obtained.

[0250] Furthermore, in the DA-APD 505a of the present disclosure, as shown in Fig. 33, the residence time Tdm of electrons and holes in the multiplication layer is short, so that changes in the electric field distribution in the multiplication layer are suppressed. As a result, as shown in the conceptual diagram of Fig. 37B, when the DA-APD 505a of the present disclosure is used, the interval between waveform A and waveform B becomes wider, and a constellation waveform with excellent linearity over a wide dynamic range is obtained. In other words, even if a signal is multiplied by the APD, the original signal can be reproduced, and a large current amplitude can be obtained.

[0251] The gain of the DA-APD 505a of the present disclosure can be within a range of 1.2 to 10. However, since a larger gain causes signal distortion, it is preferable to use the gain within a range of 1.2 to 5.

[0252] <Advantages of the Seventh Embodiment> As described above, according to the digital coherent receiving device of the seventh embodiment, the DA-APD of the present disclosure is applied as a semiconductor photodetector for receiving an optical signal, thereby making it possible to reduce the drive current of the local light (laser), that is, to reduce the power consumption of the digital coherent receiving device.

[0253] Embodiment 8 38 is a schematic diagram illustrating a configuration of a SPAD sensor system according to embodiment 8. A SPAD sensor system 600 includes an optoelectronic measurement circuit 601, a SPAD sensor 602 including a DA-APD according to the present disclosure, and a quenching circuit 603.

[0254] SPADs can be used not only to count the number of photons but also as highly sensitive light receiving elements. However, they require constant cycling from A: Quenching voltage, which will be described later, to B: Geiger mode voltage, which will be described later. The cycling period is on the order of nanoseconds to microseconds. If the cycling period between A: Quenching voltage and B: Geiger mode voltage can be shortened, it is possible to increase the response speed of the SPAD.

[0255] In other words, when the DA-APD of the present disclosure is used in a SPAD, switching between A: Quenching voltage and B: Geiger mode voltage with high response speed becomes possible, and the response band of the SPAD sensor 602 can be improved.

[0256] Furthermore, when the DA-APD 505a of the present disclosure is used in the SPAD sensor system 600, photons incident on the SPAD sensor system 600 are absorbed in the light absorption layer of the SPAD sensor 602 made of the DA-APD of the present disclosure, generating pairs of electrons and holes, and the electrons flow into the multiplication layer. An electric field about 10% higher than the avalanche breakdown electric field is applied to the multiplication layer.

[0257] This state is called the Geiger mode. In the Geiger mode, the electrons are 10 6 The electrons generated flow as a current and are passed through the photoelectron measurement circuit 601. If the current generated by one photon is known in advance, it is possible to count the number of photons incident on the SPAD sensor system 600.

[0258] FIG. 39A is a conceptual diagram showing the expected multiplication characteristics of a SAPD sensor system as a comparative example, and FIG. 39B is a conceptual diagram showing the expected multiplication characteristics of a SAPD sensor system according to the eighth embodiment. If an electric field equal to or greater than the avalanche breakdown electric field is continuously applied to the multiplication layer, an excess current will flow, so the voltage applied to the SPAD sensor 602 is quickly reduced after detecting a photon to weaken the electric field of the multiplication layer. This is called quenching. That is, as shown in the comparison of the multiplication characteristics of the SPAD sensor in the conceptual diagrams of FIG. 39A and FIG. 39B, the voltage is reduced from B: Geiger mode voltage to A: quenching voltage to stop the chain multiplication, and then the voltage is increased again from A: quenching voltage to B: Geiger mode voltage to make it possible to receive the incident photons with high sensitivity.

[0259] The quenching circuit 603 that controls the voltage can be a passive circuit or an active circuit. In a passive circuit, when a current flows due to a photon incident on the SPAD sensor 602, a voltage drop occurs in a resistor connected in series to the SPAD sensor 602, and the voltage applied to the SPAD sensor 602 decreases. In other words, the quenching circuit 603 operates to repeatedly apply to the SPAD sensor 602 a voltage equal to or greater than the breakdown voltage and a voltage less than the breakdown voltage.

[0260] <Actions and Effects of the SPAD Sensor System According to the Eighth Embodiment> The SPAD sensor system 600 according to the eighth embodiment can be used not only for counting the number of photons but also as a highly sensitive semiconductor light receiving element. However, it is necessary to constantly repeat the process from B: Geiger mode voltage to A: quenching voltage. The repetition period is on the order of nanoseconds to microseconds. If the difference between A: quenching voltage and B: Geiger mode voltage can be reduced, the repetition period can be shortened, and the response speed of the SPAD sensor system 600 can be increased.

[0261] In the passive quenching circuit 603, it is possible to reduce the resistance value connected in series to the SPAD sensor 602, thereby increasing the response speed of the SPAD sensor 602. In addition, in the active quenching circuit 603, the voltage amplitude is reduced, which allows for simplification of the drive circuit and power saving, and further allows for a wider response band.

[0262] In the DA-APD disclosed herein, the multiplication time is short, so the response band does not deteriorate even when used at a high multiplication factor. Therefore, even if the amount of light absorbed in the light absorption layer is small, the reception sensitivity can be increased by operating at a high multiplication factor, so it is possible to make the light absorption layer thinner. By making the light absorption layer thinner, the resistance Rsc can be reduced, and the breakdown voltage can also be reduced. When the DA-APD disclosed herein is used in a SPAD, the difference between the quenching voltage and the Geiger mode voltage, i.e., the applied voltage difference, can be reduced, so that the response band can be improved and the quenching circuit can be simplified and power saving can be achieved.

[0263] The effect of using the InAs / AlAs digital alloy structure of the present disclosure as a multiplication layer will be described below. In the InAs / AlAs digital alloy structure multiplication layer of the present disclosure, as shown in the conceptual diagrams of FIG. 14A and FIG. 14B, the dead space length is long, so multiplication does not occur at low electric fields. However, as the electric field is increased, the dead space length becomes shorter, so the multiplication factor increases rapidly and leads to breakdown. In an APD with an InAlAs random alloy structure multiplication layer and an APD with an InAs / AlAs digital alloy structure multiplication layer having a thick multiplication layer, if the voltage at which the dark current exceeds 10 μA is set as the breakdown voltage, the multiplication factor at 90% of the breakdown voltage exceeds 10 times. On the other hand, in the InAs / AlAs digital alloy structure multiplication layer of the present disclosure, the multiplication factor at a voltage at 90% of the breakdown voltage is 10 times or less.

[0264] The voltage required for breakdown depends on the device structure, such as the thickness of the light absorption layer and the carrier concentration of the electric field relaxation layer, so here we verify the effect using the quantifiable electric field of the multiplication layer. Note that above the reach-through voltage (up to 12 V), the voltage applied to the SPAD sensor 602 is proportional to the electric field of the multiplication layer.

[0265] 40 is a diagram showing the calculation of the difference between the quenching electric field and the Geiger mode electric field for each material constituting the multiplication layer. It can be seen that in the InAs / AlAs digital alloy structure multiplication layer of the present disclosure, the difference between the quenching electric field and the Geiger mode electric field of each multiplication layer is 170 kV / cm, which is peculiarly low. The electric field is 120 kV / cm lower than that of an InAs / AlAs digital alloy structure multiplication layer having a superlattice structure similar to the InAs / AlAs digital alloy structure multiplication layer of the present disclosure but a layer thickness of 200 nm or more that is not thinned.

[0266] <Advantages of the Eighth Embodiment> As described above, according to the SPAD sensor system of embodiment 8, the DA-APD of the present disclosure is used in the SPAD sensor, so that the difference between the quenching electric field and the Geiger mode electric field, i.e., the applied voltage difference, can be reduced, resulting in an effect of obtaining a SPAD sensor system that enables an improved response band, a simplified quenching circuit, and reduced power consumption.

[0267] Embodiment 9 Fig. 41 is a diagram illustrating a configuration of a LiDAR (Light Detection And Ranging) device according to embodiment 9. Fig. 42A is a conceptual diagram illustrating an expected received waveform at the APD of a LiDAR device that is a comparative example, and Fig. 42B is a conceptual diagram illustrating an expected received waveform at the APD of a LiDAR device 700 according to embodiment 9.

[0268] A LIDAR device 700 according to the ninth embodiment includes a light source 701, a DA-APD 702 of the present disclosure, a TIA 703, and a distance measurement circuit 704. The light source 701 emits pulsed light (hereinafter referred to as pulsed light) or frequency-modulated light.

[0269] In the LIDAR device 700 according to the ninth embodiment, the distance to the object 705 is calculated by measuring the time it takes for the pulsed light emitted from the light source to hit the object 705 and return to the semiconductor light receiving element. An LD or the like is used as the light source 701. To measure long distances, the amount of light from the LD needs to be increased, but an upper limit is set for the amount of light emitted from the LD for eye safety reasons. For this reason, it is necessary to increase the reception sensitivity of the semiconductor light receiving element. Therefore, in the LIDAR device 700 according to the ninth embodiment, the DA-APD 702 disclosed herein is used as the semiconductor light receiving element with a high multiplication factor.

[0270] The detected light pulse is multiplied by the DA-APD 702 of the present disclosure and converted into a current pulse. It is then amplified by the TIA 703 and input to the distance measurement circuit 704, and the time when the intensity of the pulse signal exceeds a preset discrimination line is determined as the arrival time, as shown in the conceptual diagrams of Figures 42A and 42B. The timing of the emission of the light pulse from the light source 701 is input as a signal to the distance measurement circuit 704, and the distance to the object 705 can be calculated by multiplying the time difference between the two by the speed of light and dividing the result by 2. A method is also used in which frequency-modulated light is emitted and the distance is calculated from the frequency difference between the emitted wave and the reflected wave.

[0271] <Functions and Effects of the LIDAR Device According to the Ninth Embodiment> Since the reflectance of the object 705 is not necessarily high and the reflection direction varies, it is necessary to detect weak light with an APD. In a conventional APD, as shown in the conceptual diagram of FIG. 42A, when the voltage is set to achieve high multiplication and the APD is operated, the multiplication time becomes long and the current pulse width output from the APD becomes wide. In addition, the tunnel current increases, making it difficult to distinguish the optical pulse. Even in a method of calculating the distance from the frequency difference between the emitted wave and the reflected wave, it becomes difficult to distinguish the frequency.

[0272] On the other hand, the DA-APD of the present disclosure used in the LIDAR device 700 according to the ninth embodiment can obtain high sensitivity even in cases where the light receiving sensitivity of a conventional APD is insufficient. As a result, not only can it measure the distance to a distant object 705, but it also reduces power consumption by reducing the optical output of the light source 701, and is safer for the eyes.

[0273] Furthermore, in the DA-APD505a of the present disclosure, even at a high multiplication factor of 20 or more, the tunnel current does not increase as described in the explanation of FIG. 15, so that it is easy to identify weak light. Also, as shown in FIG. 33, the residence time in the multiplication layer is short, so that a current pulse with a large peak intensity is obtained as shown in the conceptual diagram of FIG. 42B, and therefore the identification sensitivity is high. As a result, not only is it possible to measure the distance to a distant object, but the optical output of the light source can be reduced, so that power consumption is reduced, and further, safety to the eyes is improved.

[0274] <Effects of the 9th embodiment> As described above, according to the LIDAR device of embodiment 9, the reflected light from an object is received by the DA-APD of the present disclosure, which makes it possible to measure the distance to a distant object, reduces the power consumption of the light source, and provides a LIDAR device that is also safer for the eyes.

[0275] Although the present disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to application to a particular embodiment, but may be applied to the embodiments alone or in various combinations.

[0276] Therefore, countless modifications not illustrated are assumed within the scope of the technology of the present disclosure, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component and combining it with a component of another embodiment. [Explanation of symbols]

[0277] 1 Fe-doped InP substrate, 2 n-type InP conductive layer, 3 n-type InAlAs conductive layer, 4 i-type InAlAs multiplication layer, 4a i-type InAs / AlAs digital alloy structure multiplication layer, 5 p-type InAlAs electric field relaxation layer, 5a p-type InP electric field relaxation layer, 6 i-type InGaAs light absorption layer, 6a i-type InGaAs first light absorption layer, 6b p-type InGaAs second light absorption layer, 7 i-type InAlGaAs graded layer, 7a p-type InAlGaAs graded layer, 8 i-type InAlAs surface protection layer, 8a i-type InAlAs graded layer, 9 p-type InP window layer, 9a i-type InP window layer, 9b i-type InP first window layer, 9c p-type InAlAs second window layer, 10 p-type InGaAs contact layer, 10a i-type InGaAs contact layer, 11 surface protection film, 12 selective diffusion mask, 15 front-side anti-reflection film, 16 Backside anti-reflection film, 20, 20a p-type impurity diffusion region, 30 first mesa structure, 31 second mesa structure, 32 third mesa structure, 33 mesa structure, 35 mesa groove, 40, 40a terrace portion, 41, 41a terrace surface, 42a first terrace portion, 42b second terrace portion, 45, 45a hydrogen passivation region, 50, 50a n-type electrode, 51, 51a p-type electrode, 52 backside electrode, 60 light receiving region, 66 light shielding metal film, 100, 110, 120, 130, 140, 150, 160, 170, 200 semiconductor light receiving element, 250a, 260, 260a, 260b, 270 optical line termination device, 251, 261, 274 FEC, 252, 262, 273, 303 Driver amplifier, 253, 263, 272, 304, 401, 701 Light source, 254, 264, 271 WDM, 255, 265a, 301, 506 DSP, 256, 266a, 302b ADC, 258 APD, 257, 267 Burst TIA, 265, 278 CDR, 266, 277 Limiting amplifier, 267a, 276, 703 TIA, 268, 275, 305, 403, 505a, 702 DA-APD, 300 Multi-level intensity modulation transmitter / receiver, 302a DAC, 310, 501 Optical fiber cable, 306 Linear-TIA, 400, 450 Radio-on-fiber system, 402 Transmission line, 404 Antenna, 406 PD, 500 digital coherent receiving device, 501 optical fiber cable, 502 polarization separator, 503a, 503b90 degree hybrid device, 504, semiconductor laser, 505, balanced detector, 600, SPAD sensor system, 601, photoelectron measurement circuit, 602, SPAD sensor, 603, quenching circuit, 700, lidar device, 704, ranging circuit, 705, object

Claims

1. A substrate; a first mesa structure having at least an n-type semiconductor layer, a multiplication layer, a p-type electric field buffer layer, a light absorption layer, and an i-type semiconductor layer having a band gap larger than that of the light absorption layer, which are sequentially formed on the substrate; a second mesa structure formed on the first mesa structure, the second mesa structure including at least a window layer having a band gap larger than that of the light absorption layer and a ring-shaped p-type contact layer; a terrace portion formed on the outermost surface of the first mesa structure and exposed on the outer periphery side of the second mesa structure; a p-type region provided in a region extending from the window layer on the inner periphery of the ring-shaped p-type contact layer and the window layer side surface of the light absorption layer toward the substrate; A semiconductor light receiving element comprising:

2. 2. The semiconductor light-receiving element according to claim 1, wherein the window layer is made up of two layers, an i-type first window layer and a p-type second window layer, from the side in contact with the first mesa structure.

3. A substrate; a first mesa structure having at least an n-type semiconductor layer, a multiplication layer, and an electric field relaxation layer sequentially formed on the substrate; a second mesa structure formed on the first mesa structure, the second mesa structure including at least a light absorption layer, a window layer having a band gap larger than that of the light absorption layer, and a ring-shaped p-type contact layer; a terrace portion formed on the outermost surface of the first mesa structure and exposed on the outer periphery side of the second mesa structure; a p-type region provided in a region extending from the window layer on the inner periphery of the ring-shaped p-type contact layer and the window layer side surface of the light absorption layer toward the substrate; A semiconductor light receiving element comprising:

4. 4. The semiconductor light-receiving element according to claim 3, wherein the light-absorbing layer is made up of two layers, an i-type first light-absorbing layer and a p-type second light-absorbing layer, from the side in contact with the first mesa structure.

5. 5. The semiconductor light-receiving element according to claim 3, wherein the electric field relaxation layer is made of a p-type InAlAs layer.

6. 5. The semiconductor light-receiving element according to claim 3, wherein the electric field relaxation layer is made of a p-type InP layer.

7. A substrate; a first mesa structure having at least an n-type semiconductor layer, a multiplication layer, and a p-type field buffer layer sequentially formed on the substrate; a second mesa structure formed on the first mesa structure and having at least a light absorption layer and an i-type surface protection layer; a first terrace portion formed on the outermost surface of the first mesa structure exposed on the outer periphery side of the second mesa structure; a third mesa structure formed on the second mesa structure, the third mesa structure including at least a window layer having a band gap larger than that of the light absorption layer and a ring-shaped p-type contact layer; a second terrace portion formed on the outermost surface of the second mesa structure exposed on the outer periphery side of the third mesa structure; a p-type region provided on an inner periphery of the ring-shaped p-type contact layer in a portion from the window layer side surface of the light absorption layer toward the substrate; A semiconductor light receiving element comprising:

8. 8. The semiconductor light-receiving element according to claim 7, wherein the second mesa structure further comprises an i-type semiconductor layer on the light-absorbing layer, the i-type semiconductor layer having a band gap larger than that of the light-absorbing layer.

9. A semiconductor light-receiving element described in any one of claims 1, 3, 4, 7, and 8, characterized in that the thickness of the depletion layer inside the light absorption layer below the p-type region is smaller than the thickness of the depletion layer inside the light absorption layer below the ring-shaped p-type contact layer.

10. 10. The semiconductor light-receiving element according to claim 9, wherein the thickness of the p-type region inside the light absorption layer is 0.1 μm or more and 0.3 μm or less.

11. 10. The semiconductor light-receiving element according to claim 9, wherein the p-type impurity contained in the p-type region is any one of zinc, cadmium, magnesium, and beryllium.

12. 8. The semiconductor light-receiving element according to claim 1, wherein the window layer has a p-type conductivity.

13. 9. The semiconductor light-receiving element according to claim 1, wherein the multiplication layer has a digital alloy structure.

14. 14. The semiconductor light-receiving element according to claim 13, wherein the digital alloy structure is a structure in which InAs layers and AlAs layers are alternately stacked.

15. 5. The semiconductor light-receiving element according to claim 1, further comprising a surface protection film made of an insulating film that covers at least the side surfaces of the first mesa structure, the side surfaces of the second mesa structure, and the surfaces of the terrace portions.

16. 16. The semiconductor light-receiving element according to claim 15, further comprising a light-shielding metal film provided at least on the surface of the surface protection film covering the terrace portion and on the surface of the surface protection film covering the side portion of the first mesa structure.

17. 5. The semiconductor light-receiving element according to claim 1, wherein a hydrogen passivation region is formed inside the semiconductor layer in contact with the underside of the terrace portion.

18. The hydrogen concentration in the hydrogen passivation region is 2×10 17 cm -3 1x10 or more 18 cm -3 18. The semiconductor light-receiving element according to claim 17, wherein the range is as follows:

19. A semiconductor light-receiving element according to claim 1, wherein the p-type region is a p-type impurity diffusion region.

20. epitaxially growing, on a substrate, at least an n-type semiconductor layer, a multiplication layer, a p-type electric field buffer layer, a light absorbing layer, an i-type semiconductor layer having a band gap larger than that of the light absorbing layer, a window layer having a band gap larger than that of the light absorbing layer, and a p-type contact layer in that order; forming a selective diffusion mask made of an insulating film having a substantially circular opening on the surface of the p-type contact layer; forming a p-type impurity diffusion region whose bottom extends from the opening to at least the inside of the light absorbing layer; removing the selective diffusion mask; processing the p-type contact layer into a ring shape that follows the outer periphery of a light-receiving region; forming a second mesa structure by etching the outer periphery of the light receiving region until the i-type semiconductor layer is exposed at least on the surface; forming a first mesa structure by etching a portion other than a predetermined region from the outer periphery of the second mesa structure; A method for manufacturing a semiconductor light receiving element comprising:

21. 21. The method for manufacturing a semiconductor light-receiving element according to claim 20, wherein the p-type impurity diffusion region is formed by a vapor phase diffusion method or a solid phase diffusion method.

22. The semiconductor light-receiving element according to any one of claims 1 to 4, 7 and 8; an optical multiplexer / demultiplexer that inputs an optical signal to the semiconductor light-receiving element; an amplifier circuit that amplifies the electrical signal output from the semiconductor light-receiving element; a clock data recovery circuit connected to the amplifier circuit and recovering clock data from the amplified electrical signal; a forward error correction circuit connected to the clock data recovery circuit for correcting an error in the clock data; An optical line terminal comprising:

23. The semiconductor light-receiving element according to any one of claims 1 to 4, 7 and 8; an optical multiplexer / demultiplexer that inputs an optical signal to the semiconductor light-receiving element; an amplifier circuit that amplifies the electrical signal output from the semiconductor light-receiving element; an analog-to-digital conversion circuit connected to the amplifier circuit and converting the amplified electrical signal into a digital signal; a digital signal processing circuit connected to the analog-to-digital conversion circuit and processing the digital signal; a forward error correction circuit connected to the digital signal processing circuit for correcting errors in the digital signal; An optical line terminal comprising:

24. a semiconductor light-receiving element according to any one of claims 1 to 4, 7 and 8, which receives a multilevel intensity-modulated optical signal; an amplifier circuit that amplifies the electrical signal output from the semiconductor light-receiving element; an analog-to-digital conversion circuit connected to the amplifier circuit and converting the amplified electrical signal into a digital signal; a digital signal processing circuit connected to the analog-to-digital conversion circuit and processing the digital signal; A multilevel intensity modulation transmitting and receiving device comprising:

25. a light source that emits an analog modulated optical signal; a semiconductor light-receiving element according to any one of claims 1 to 4, 7 and 8, which receives the analog-modulated optical signal; a transmission path for transmitting the analog electrical signal output from the semiconductor light receiving element to an antenna; an antenna connected to the transmission line and configured to emit the analog electrical signal as a radio wave signal; A radio-on-fiber system comprising:

26. The semiconductor light-receiving element according to any one of claims 1 to 4, 7 and 8; a polarization separator that separates the polarizations of the intensity- and phase-modulated polarization multiplexed optical signal; a 90-degree hybrid that splits and combines the optical signals output from the polarization splitter; a digital signal processing circuit connected to the 90-degree hybrid device and processing a digital signal; A digital coherent receiving device comprising:

27. a SPAD sensor configured by the semiconductor light receiving element according to any one of claims 1 to 4, 7 and 8; a quenching circuit that repeatedly applies a voltage equal to or greater than a breakdown voltage and a voltage less than the breakdown voltage to the SPAD sensor; an optoelectronic measurement circuit that measures the electrical signal output from the SPAD sensor; A SPAD sensor system comprising:

28. a light source that emits pulsed or frequency-modulated light; a semiconductor light-receiving element according to any one of claims 1 to 4, 7 and 8, which receives light emitted from the light source and reflected by an object; an amplifier circuit that amplifies the electrical signal output from the semiconductor light-receiving element; a distance measuring circuit that calculates a distance based on the electrical signal amplified by the amplifier circuit; A lidar device comprising:

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