Power semiconductor device, power semiconductor device manufacturing method, power semiconductor module, and power conversion device

Abstract

The power semiconductor device (100, 100A, 100B) includes a support plate (10), a power semiconductor element (20), a first electrode (23), a second electrode (24), and a first bonding material (30). The support plate has a first surface (10a) and a second surface (10b) opposite the first surface. The power semiconductor element has a third surface (20a) and a fourth surface (20b) opposite the third surface. The first electrode and the second electrode are disposed on the third surface and the fourth surface, respectively. The power semiconductor element is disposed on the support plate such that the first electrode faces the second surface with the first bonding material interposed therebetween.

Description

[Technical Field]

[0001] The present disclosure relates to a power semiconductor device, a method for manufacturing a power semiconductor device, a power semiconductor module, and a power conversion device. [Background technology]

[0002] Japanese Patent Laid-Open No. 2007-19461 (Patent Document 1) and Japanese Patent Laid-Open No. 2013-12690 (Patent Document 2) describe methods for processing semiconductor wafers. In the methods for processing semiconductor wafers described in Patent Documents 1 and 2, the central portion of the semiconductor wafer in a plan view is ground from the back surface side, thereby thinning the semiconductor wafer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-19461 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-12690 Summary of the Invention [Problem to be solved by the invention]

[0004] When a semiconductor wafer is thinned, the thickness of the semiconductor element obtained from the semiconductor wafer is reduced, and the electrical resistance and thermal resistance are reduced. However, the thinning of the semiconductor element reduces its mechanical strength, which can cause cracks or chips in the semiconductor element during the mounting process.

[0005] The present disclosure has been made in view of the above-mentioned problems of the conventional techniques. More specifically, the present disclosure provides a semiconductor device that can suppress cracking and chipping of semiconductor elements. [Means for solving the problem]

[0006] The power semiconductor device of the present disclosure includes a support plate, a power semiconductor element, a first electrode, a second electrode, and a first bonding material. The support plate has a first surface and a second surface opposite the first surface. The power semiconductor element has a third surface and a fourth surface opposite the third surface. The first electrode and the second electrode are disposed on the third surface and the fourth surface, respectively. The power semiconductor element is disposed on the support plate such that the first electrode faces the second surface with the first bonding material interposed therebetween. [Effects of the Invention]

[0007] According to the semiconductor device of the present disclosure, cracking and chipping of the semiconductor element can be suppressed. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device 100. [Figure 2A] FIG. 1 is a cross-sectional view of a semiconductor device 100 according to a first modification. [Figure 2B] FIG. 10 is a cross-sectional view of a semiconductor device 100 according to a second modification. [Figure 3] FIG. 10 is a cross-sectional view of a semiconductor device 100 according to a third modification. [Figure 4] 1A to 1C are diagrams illustrating the manufacturing process of the semiconductor device 100. [Figure 5] FIG. 10 is a cross-sectional view illustrating a preparation step S1. [Figure 6] FIG. 10 is a cross-sectional view illustrating the element structure forming step S2. [Figure 7] FIG. 10 is a cross-sectional view illustrating a grinding step S3. [Figure 8] FIG. 10 is a cross-sectional view illustrating an electrode forming step S4. [Figure 9] FIG. 10 is a cross-sectional view illustrating a support base joining step S5. [Figure 10] FIG. 10 is a cross-sectional view illustrating a dicing step S6. [Figure 11] FIG. 2 is a cross-sectional view of the semiconductor device 100A. [Figure 12] FIG. 2 is a cross-sectional view of the semiconductor device 100B. [Figure 13]FIG. 2 is a cross-sectional view of a semiconductor module 200. [Figure 14] FIG. 10 is a cross-sectional view of a semiconductor module 200 according to a modified example. [Figure 15] 1 is a block diagram showing a configuration of a power conversion system to which a power conversion device 300 is applied. DETAILED DESCRIPTION OF THE INVENTION

[0009] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant description will not be repeated.

[0010] Embodiment 1 A power semiconductor device according to the first embodiment will be described. The power semiconductor device according to the first embodiment is designated as a semiconductor device 100.

[0011] (Configuration of semiconductor device 100) The configuration of the semiconductor device 100 will be described below.

[0012] 1 is a cross-sectional view of a semiconductor device 100. As shown in FIG.

[0013] The support plate 10 is a plate-shaped member. The support plate 10 has a first surface 10a and a second surface 10b. The second surface 10b is the surface opposite to the first surface 10a. The first surface 10a and the second surface 10b are end surfaces of the support plate 10 in the thickness direction.

[0014] Because heat and current pass through the support plate 10, the support plate 10 is preferably made of a material with high electrical and thermal conductivity. The material used for the support plate 10 is preferably selected so as to minimize the difference in linear expansion coefficient between the support plate 10 and the semiconductor element 20. The support plate 10 is made of, for example, aluminum (Al), an Al alloy, an Al-Si-C alloy, copper (Cu), a Cu alloy, molybdenum (Mo), or the like.

[0015] The semiconductor element 20 is a semiconductor element for power generation. Examples of the semiconductor element 20 include a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), and a Schottky barrier diode. However, the semiconductor element 20 is not limited to these, and the following description will be given using a MOSFET as an example of the semiconductor element 20.

[0016] The semiconductor element 20 has a third surface 20a and a fourth surface 20b. The fourth surface 20b is the surface opposite to the third surface 20a. The third surface 20a and the fourth surface 20b are end surfaces in the thickness direction of the semiconductor element 20. The semiconductor element 20 has a semiconductor substrate 21 and an insulating film 22. The back surface of the semiconductor substrate 21 forms the third surface 20a. The insulating film 22 is disposed on the front surface of the semiconductor substrate 21 and forms the fourth surface 20b.

[0017] The semiconductor substrate 21 is made of, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (Ga2O3). The insulating film 22 is made of, for example, silicon oxide (SiO2). Although not shown, the semiconductor substrate 21 has a drain region formed on the back surface, a source region formed on the front surface, a drift region formed on the drain region, and a body region formed between the drift region and the source region. The conductivity type of the drain region, drift region, and source region is, for example, n-type. The conductivity type of the body region is, for example, p-type. Although not shown, a gate insulating film is formed on the body region sandwiched between the source region and drift region, and a gate electrode is formed on the gate insulating film.

[0018] When the semiconductor substrate 21 is made of Ga2O3, the thickness of the semiconductor element 20 is, for example, 0.1 mm or less, 0.05 mm or less, or 0.02 mm or less. The thickness of the semiconductor element 20 may be equal to or less than the epitaxially grown film thickness. The epitaxially grown film thickness is a single crystal film grown on the underlying single crystal substrate in alignment with the crystal plane of the single crystal substrate. In other words, when the thickness of the semiconductor element 20 is equal to or less than the epitaxially grown film thickness, it means that the underlying single crystal substrate has been completely removed. The thickness of the semiconductor element 20 is the distance between the third surface 20a and the fourth surface 20b.

[0019] An electrode 23 is disposed on the third surface 20a. An electrode 24 and an electrode 25 are disposed on the fourth surface 20b. A main current flows through the electrodes 23 and 24, and the electrode 25 controls the main current. The electrodes 23 and 24 are electrically connected to the drain region and the source region, respectively. The electrode 25 is electrically connected to the gate electrode. In the example shown in FIG. 1, the electrode 25 is located near the edge, but the arrangement of the electrode 25 is not limited to this example. The shape of the electrode 25 is not particularly limited, and may be a rectangle, an ellipse (including a circle), a combination of an ellipse and a rectangle, etc. in a plan view. The size of the electrode 25 is also not particularly limited. Other terminals, such as auxiliary terminals such as a current sensing terminal and a temperature sensing terminal, may be disposed on the fourth surface 20b. Note that when the semiconductor element 20 is a diode, such auxiliary terminals are often not disposed.

[0020] These electrodes may be formed of Al, Al alloy, Cu, Cu alloy, or may have a two-layer structure of Al / Cu or a multilayer structure including gold (Au) and silver (Ag). These electrodes may also contain titanium (Ti) or the like as a diffusion prevention layer, may contain nickel (Ni) silicide as an underlayer to ensure ohmic contact with the semiconductor substrate 21, and may have a thin film of Au or the like formed on the surface to prevent oxidation and improve bonding. Furthermore, a Cu-based or Ni-based plating film may be formed on the surface of these electrodes.

[0021] The semiconductor element 20 is disposed on the support plate 10 such that the electrode 23 faces the second surface 10b via the bonding material 30. The electrode 23 is bonded to the second surface 10b by the bonding material 30. Because current and heat pass through the bonding material 30, the bonding material 30 is formed of, for example, a sintered body containing Cu or Ag particles. The bonding material 30 may be a Sn—Cu alloy or a Sn—Ag alloy, and the electrode 23 and the second surface 10b may be bonded by liquid phase diffusion bonding. In this case, the thickness of the bonding material 30 may be, for example, 0.02 mm or less. The bonding material 30 may be a solder alloy.

[0022] In a plan view, the distance between the edge of the active region of the semiconductor element 20 and the edge of the semiconductor element 20 is L s and the distance between the edge of the semiconductor element 20 and the edge of the support plate 10 is L c The distance between the second surface 10b and the fourth surface 20b is t c The thickness of the support plate 10 is t s Let's say. L s , L c、 t c and t s Between them, L c ≧(t c +t s )-L s It is preferable that the relationship (Equation 1) is satisfied. For example, L s is 0.3mm, t c is 0.06mm, t s If is 0.3 mm, L c It is sufficient that Ls is 0.06 mm or more. Although Ls may differ for each side defining the outer periphery of the semiconductor element 20 in plan view, it is preferable that formula 1 is satisfied for all sides.

[0023] <Modification 1 and Modification 2> 2A is a cross-sectional view of a semiconductor device 100 according to Modification 1. FIG. 2B is a cross-sectional view of a semiconductor device 100 according to Modification 2. As shown in FIGS. 2A and 2B, in the semiconductor device 100, in order to satisfy Formula 1, the support plate 10 may have a shape in which the cross section widens only at the end on the first surface 10a side, or may have a shape in which the cross section widens between the first surface 10a and the second surface 10b. Although not shown, the side surface of the support plate 10 may be curved in cross section.

[0024] <Variation 3> 3 is a cross-sectional view of a semiconductor device 100 according to Modification 3. As shown in FIG. 3, the support plate 10 may have a semiconductor layer 11, and metal films 12 and 13. The semiconductor layer 11 is made of, for example, Si or SiC. The metal films 12 and 13 are disposed on the back surface and front surface of the semiconductor layer 11, respectively. The metal films 12 and 13 are in ohmic contact with the semiconductor layer 11.

[0025] (Method of manufacturing the semiconductor device 100) A method for manufacturing the semiconductor device 100 will be described below.

[0026] Fig. 4 is a manufacturing process diagram of the semiconductor device 100. As shown in Fig. 4, the manufacturing method of the semiconductor device 100 includes a preparation step S1, an element structure formation step S2, a grinding step S3, an electrode formation step S4, a support base bonding step S5, and a dicing step S6.

[0027] FIG. 5 is a cross-sectional view illustrating the preparation step S1. As shown in FIG. 5, in the preparation step S1, a semiconductor wafer 40 is prepared. The semiconductor wafer 40 has a back surface 40a and a front surface 40b. The back surface 40a and the front surface 40b are end faces in the thickness direction of the semiconductor wafer 40. In a plan view, the semiconductor wafer 40 has an outer periphery 41 and a central portion 42. The central portion 42 is the portion where the device structure of the semiconductor element 20 is formed. In a plan view, the central portion 42 is located inside the outer periphery 41. The width of the outer periphery 41 is about several mm.

[0028] 6 is a cross-sectional view illustrating the element structure forming step S2. As shown in Fig. 6, in the element structure forming step S2, a source region, a drain region, a drift region, and a body region are formed in the central portion 42, and electrodes 24 and 25 are also formed. Although not shown, in the element structure forming step S2, a gate insulating film, a gate electrode, an insulating film 22, wiring, etc. are also formed.

[0029] FIG. 7 is a cross-sectional view illustrating the grinding step S3. As shown in FIG. 7, in the grinding step S3, grinding is performed on the back surface 40a located in the central portion 42. By polishing the central portion 42 while leaving the peripheral portion 41, the peripheral portion 41 forms a rib, thereby suppressing warpage of the semiconductor wafer 40. The grinding may include, for example, a first grinding (rough grinding) performed using first abrasive grains, a second grinding performed after the first grinding using second abrasive grains having a smaller diameter than the first abrasive grains, and polishing performed after the second grinding. Any two of the first grinding, second grinding, and polishing may be performed. Furthermore, polishing is preferably performed by a method with a low processing load, such as CMP (Chemical Mechanical Polishing). After the grinding step S3 and before the electrode formation step S4, cleaning may be performed.

[0030] FIG. 8 is a cross-sectional view illustrating the electrode forming step S4. As shown in FIG. 8, in the electrode forming step S4, an electrode 23 is formed on the back surface 40a. FIG. 9 is a cross-sectional view illustrating the support table joining step S5. As shown in FIG. 9, in the support table joining step S5, the support table 14 is joined to the electrode 23 with the bonding material 30. More specifically, first, the semiconductor wafer 40 is placed on the support table 14 so that the back surface 40a located in the central portion 42 faces the support table 14 with the bonding material 30 interposed therebetween.

[0031] Second, the semiconductor wafer 40 is heated while being pressed against the support table 14, thereby bonding the electrode 23 and the support table 14 with the bonding material 30. The bonding material 30 may be applied to the support table 14, to the electrode 23, or to both the support table 14 and the electrode 23. The pressure is preferably 10 MPa or less to prevent cracking of the semiconductor wafer 40. When the semiconductor wafer 40 is made of Ga2O3, low pressure or pressure due to its own weight alone may be used.

[0032] In the dicing step S6, the semiconductor wafer 40 and the support base 14 are cut to obtain a plurality of individual semiconductor devices 100. The cut support base 14 becomes the support plate 10. Dicing is performed, for example, with the surface 40b facing up. FIG. 10 is a cross-sectional view illustrating the dicing step S6. As shown in FIG. 10, when dicing is performed with the surface 40b facing up, the outer periphery 41 is cut off, for example, by laser irradiation. This prevents the semiconductor wafer 40 from being supported by the outer periphery 41, making it easier to apply dicing tape. Note that grinding the outer periphery 41 so that it is flush with the support base 14 can also prevent the semiconductor wafer 40 from being supported only by the outer periphery 41.

[0033] After this, the first dicing is performed. In the first dicing, only the portion (semiconductor wafer 40) above the support base 14 is cut. In the second dicing, the support base 14 is cut with a cutting width narrower than that of the first dicing. This results in a structure in which the edges of the support plate 10 extend beyond the edges of the semiconductor elements 20 as shown in FIG. 1. Note that by adjusting the depth of the first dicing, the structure of the support plate 10 as shown in FIG. 2A or 2B can be obtained. Note that dicing may be performed with the back surface 40a facing up.

[0034] (Effects of the semiconductor device 100) The effects of the semiconductor device 100 will be described below.

[0035] The semiconductor element 20 is thinned by grinding or the like during the wafer process to reduce electrical resistance and thermal resistance. As a result, cracks and chips may occur in the semiconductor element 20 during the mounting process. In particular, when Ga2O3 is used for the semiconductor substrate 21 used in the semiconductor element 20, Ga2O3 has a wider band gap than SiC and is a promising material that can also reduce costs, but because it has low thermal conductivity, it is highly necessary to process it thin, and because it is easily cleaved, the problem of cracks and chips when processed thin is easily apparent.

[0036] In this regard, in the semiconductor device 100, the semiconductor element 20 is supported by the support plate 10. Therefore, according to the semiconductor device 100, even if the semiconductor element 20 is processed to be thin or the semiconductor substrate 21 is formed of a brittle material, cracks or chips are suppressed from occurring in the semiconductor element 20 during the mounting process.

[0037] Heat generated in the semiconductor element 20 is transferred from the second surface 10b to the first surface 10a while spreading at an angle of approximately 45°. At this time, if the relationship of Equation 1 is satisfied, the heat spread is not impeded. If the bonding material 30 is formed of a sintered body containing metal particles and has a thickness of 0.02 mm or less, the thermal resistance of the bonding material 30 can be particularly reduced. If the support plate 10 has a semiconductor layer 11, the difference in linear expansion coefficient between the support plate 10 and the semiconductor element 20 becomes smaller, and therefore the thermal stress caused by the difference in linear expansion coefficient is reduced.

[0038] Embodiment 2 A power semiconductor device according to embodiment 2 will be described. The power semiconductor device according to embodiment 2 is referred to as semiconductor device 100A. Here, differences from semiconductor device 100 will be mainly described, and overlapping descriptions will not be repeated.

[0039] FIG. 11 is a cross-sectional view of the semiconductor device 100A. As shown in FIG. 11, in the semiconductor device 100A, a metal film 26 is disposed on the electrodes 24 and 25. The metal film 26 is formed of, for example, Cu, Ni, or the like. The thickness of the metal film 26 is preferably 0.005 mm or more, and more preferably 0.01 mm or more. The metal film 26 is formed, for example, in the element structure formation step S2. However, the metal film 26 may also be formed after the dicing step S6.

[0040] When semiconductor substrate 21 is made of a material with low thermal conductivity, such as Ga2O3, transient heat does not easily escape from directly below electrode 24, which is the main heat source. In semiconductor device 100A, metal film 26 is disposed near this main heat source, which allows transient heat to escape more easily and improves short-circuit resistance.

[0041] Embodiment 3 A power semiconductor device according to embodiment 3 will be described. The power semiconductor device according to embodiment 3 is referred to as semiconductor device 100B. Here, differences from semiconductor device 100 will be mainly described, and overlapping descriptions will not be repeated.

[0042] 12 is a cross-sectional view of the semiconductor device 100B. As shown in FIG. 12, in the semiconductor device 100B, a metal block 28 is disposed on an electrode 24 with a bonding material 27 interposed therebetween. The bonding material 27 is formed of a material exhibiting good electrical and thermal conductivity. The bonding material 27 is, for example, a sintered body containing Ag or Cu particles. The metal block 28 is formed of, for example, Al, an Al alloy, Cu, a Cu alloy, or the like.

[0043] The method for supplying the bonding material 27 is not particularly limited, and the bonding material 27 may be applied to the electrode 24 or may be supplied as a sheet onto the electrode 24. When the semiconductor substrate 21 is made of Ga2O3, the bonding of the metal block 28 to the electrode 24 is preferably performed by applying a low pressure or pressure due to its own weight alone.

[0044] When semiconductor substrate 21 is made of a material with low thermal conductivity, such as Ga2O3, transient heat does not easily escape from directly below electrode 24, which is the main heat source. In semiconductor device 100B, metal block 28 is disposed near this main heat source, which allows transient heat to escape more easily and improves short-circuit resistance.

[0045] Embodiment 4 A description will be given of a power semiconductor module according to embodiment 4. The power semiconductor module according to embodiment 4 is referred to as a semiconductor module 200.

[0046] Fig. 13 is a cross-sectional view of a semiconductor module 200. As shown in Fig. 13, the semiconductor module 200 includes a semiconductor device 100A, a substrate 50, wiring members 61, 62, 63, and 64, a base plate 71, and an exterior case 72. In the example shown in Fig. 13, the semiconductor device 100A is used as the semiconductor device, but the semiconductor device 100 or the semiconductor device 100B may be used instead of the semiconductor device 100A.

[0047] The substrate 50 includes an insulating layer 51 and metal layers 52, 53, and 54. The insulating layer 51 is made of a ceramic such as silicon nitride (SiN), aluminum nitride (AlN), or aluminum oxide (Al2O3). The metal layer 52 is disposed on the back surface of the insulating layer 51, and the metal layers 53 and 54 are disposed on the front surface of the insulating layer 51. The metal layers 53 and 54 may or may not form a circuit pattern. However, the metal layers 53 and 54 must be electrically insulated from each other. Furthermore, the metal layer 54 only needs to be insulated from other electrical circuits and does not necessarily need to be on the same substrate 50. For example, in the case of a transfer mold module, the wiring member 63 may be directly connected to a lead frame, or the wiring member 63 itself may be the lead frame.

[0048] The thickness of the metal layer 52 is equal to the thickness of the metal layer 53 and the thickness of the metal layer 54. When the metal layer 53 and the metal layer 54 form a circuit pattern, the thickness of the metal layer 52 may be different from the thickness of the metal layer 53 and the thickness of the metal layer 54 in order to balance the volume of the metal layer 52 and the volume of the metal layer 53 and the metal layer 54. Note that, since no current flows through the metal layer 52, a layer made of a material that has high thermal conductivity but not high electrical conductivity, such as graphite, may be used instead of the metal layer 52. A heat spreader and an insulating sheet may be used instead of the substrate 50.

[0049] The semiconductor device 100A is disposed on the substrate 50 such that the support plate 10 faces the metal layer 53 with the bonding material 60 interposed therebetween. The wiring member 61 is disposed on the metal layer 53 with the bonding material 60 interposed therebetween. The wiring member 62 is disposed on the electrode 24 with the bonding material 60 interposed therebetween. One end of the wiring member 63 is bonded to the electrode 25 (metal film 26), and the other end of the wiring member 63 is bonded to the metal layer 54. The wiring member 64 is disposed on the metal layer 54 with the bonding material 60 interposed therebetween. As a result, the wiring members 61, 62, and 64 are electrically connected to the semiconductor device 100 and function as external terminals of the semiconductor module 200. The wiring members 61, 62, and 64 are, for example, bent plate-like members. The wiring member 63 is, for example, a wire made of Al or Cu. The bonding material 60 is, for example, a sintered body containing Ag or Cu particles. The wiring members 61, 62, 64 and the support plate 10 may be liquid phase diffusion bonded to the metal layer (metal layer 53, metal layer 54) on the insulating layer 51 using a Sn-Cu based alloy or a Sn-Ag based alloy as the bonding material 60.

[0050] The substrate 50 is disposed on the base plate 71 such that the metal layer 52 faces the base plate 71 with the bonding material 70 interposed therebetween. A cooler may be used instead of the base plate 71. The base plate 71 and the substrate 50 may be integrated together. In this case, the bonding material 70 is not necessary. In this case, the integrated structure may have fins. The bonding material 70 may be, for example, a solder alloy, but is not particularly limited to such a material. The outer case 72 is disposed on the outer peripheral edge of the base plate 71. The space defined by the outer case 72 and the base plate 71 is filled with a sealing material 73. The sealing material 73 may be, for example, epoxy or silicone gel. The sealing material 73 seals the semiconductor device 100A, the substrate 50, the wiring member 61, the wiring member 62, the wiring member 63, and the wiring member 64. However, the ends of the wiring members 61, 62, and 64 protrude from the sealing material 73. When the sealing material 73 is formed by transfer molding or the like, the exterior case 72 does not need to be provided.

[0051] FIG. 14 is a cross-sectional view of a semiconductor module 200 according to a modified example. As shown in FIG. 14, wiring members 65, 66, and 67 may be used instead of wiring members 61 and 62. Substrate 50 may further include a metal layer 55 disposed on the surface of insulating layer 51. Wiring member 65 is disposed on metal layer 55 with bonding material 60 interposed therebetween. One end of wiring member 66 is disposed on metal layer 55 with bonding material 60 interposed therebetween, and the other end of wiring member 66 is disposed on electrode 24 (metal film 26) with bonding material 60 interposed therebetween. Wiring member 67 is disposed on metal layer 53 with bonding material 60 interposed therebetween. As a result, wiring members 65 and 67 are electrically connected to semiconductor device 100A and function as external terminals of semiconductor module 200.

[0052] Embodiment 5 A power conversion device according to the fifth embodiment will be described. The power conversion device according to the fifth embodiment is designated as power conversion device 300.

[0053] In the fifth embodiment, the semiconductor devices according to the first to fourth embodiments are applied to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, the fifth embodiment will be described with reference to a case where the present disclosure is applied to a three-phase inverter.

[0054] (Configuration of power conversion device 300) The configuration of the power conversion device 300 will be described below.

[0055] 15 is a block diagram showing the configuration of a power conversion system to which the power conversion device 300 is applied. The power conversion system shown in FIG.

[0056] The power supply 410 is a DC power supply that supplies DC power to the power conversion device 300. The power supply 410 can be configured from various sources. For example, the power supply 410 can be configured from a DC system, a solar cell, or a storage battery. The power supply 410 may be configured from a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 410 may be configured from a DC / DC converter that converts DC power output from a DC system into predetermined power.

[0057] The load 420 is a three-phase motor driven by AC power supplied from the power conversion device 300. The load 420 is not limited to a specific application. The load 420 is a motor mounted on various electrical devices. The load 420 is used as a motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0058] The power conversion device 300 is a three-phase inverter connected between a power source 410 and a load 420. The power conversion device 300 converts DC power supplied from the power source 410 into AC power and supplies the AC power to the load 420. As shown in Fig. 15 , the power conversion device 300 has a main conversion circuit 301 that converts DC power into AC power and outputs it, and a control circuit 303 that outputs a control signal 304 to the main conversion circuit 301 to control the main conversion circuit 301.

[0059] (Detailed configuration of power conversion device 300) The configuration of the power conversion device 300 will be described in detail below.

[0060] Although not shown, the main conversion circuit 301 includes a switching element and a free wheel diode. The main conversion circuit 301 converts DC power supplied from the power source 410 into AC power by switching the switching element, and supplies the AC power to the load 420.

[0061] There are various specific circuit configurations for the main conversion circuit 301, but the main conversion circuit 301 according to embodiment 5 is a two-level three-phase full-bridge circuit, and is composed of six switching elements and six freewheeling diodes connected in anti-parallel to each switching element.

[0062] At least one of the switching element and each freewheel diode of the main conversion circuit 301 is a switching element or a freewheel diode included in a semiconductor device 302 corresponding to any one of the semiconductor devices according to the first to fourth embodiments.

[0063] The six switching elements are connected in series in pairs to form upper and lower arms. Each upper and lower arm constitutes one phase (U phase, V phase, W phase) of the half-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 301, are connected to a load 420. Note that a freewheeling diode is not essential for transistors with a body diode, such as MOS transistors, or transistors with a built-in diode and freewheeling diode function, such as RC-IGBTs. The switching elements themselves may be composed of multiple transistors.

[0064] The main conversion circuit 301 has a drive circuit (not shown) that drives each switching element. This drive circuit may be built into the semiconductor device 302, or may be configured separately from the semiconductor device 302. This drive circuit generates drive signals that drive the switching elements of the main conversion circuit 301, and supplies them to the control electrodes of the switching elements of the main conversion circuit 301.

[0065] More specifically, this drive circuit outputs to the control electrode of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off in accordance with control signal 304 from control circuit 303. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element. When maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0066] The control circuit 303 controls the switching elements of the main conversion circuit 301 so that the desired power is supplied to the load 420. More specifically, it calculates the time (on time) that each switching element of the main conversion circuit 301 should be in the on state based on the power to be supplied to the load 420. For example, the main conversion circuit 301 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 303 outputs a control command (control signal 304) to the drive circuit of the main conversion circuit 301 so that on signals and off signals are output to the switching elements that should be in the on state and the switching elements that should be in the off state at each point in time, respectively. The drive circuit of the main conversion circuit 301 outputs on or off signals as drive signals to the control electrodes of each switching element in accordance with the control signal 304.

[0067] (Effects of the power conversion device 300) According to the power conversion device 300, the semiconductor device according to any one of the first to fourth embodiments is applied as the semiconductor device 302 constituting the main conversion circuit 301, and therefore the semiconductor device 302 and the control circuit 303 can be easily connected.

[0068] In the fifth embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used. In addition, when power is supplied to a single-phase load, the present disclosure may also be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the present disclosure can also be applied to a DC / DC converter or an AC / DC converter.

[0069] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of this application is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0070] 10 Support plate, 10a First surface, 10b Second surface, 11 Semiconductor layer, 12, 13 Metal film, 14 Support base, 20 Semiconductor element, 20a Third surface, 20b Fourth surface, 21 Semiconductor substrate, 22 Insulating film, 23, 24, 25 Electrode, 26 Metal film, 27 Bonding material, 28 Metal block, 30 Bonding material, 40 Semiconductor wafer, 40a Back surface, 40b Front surface, 41 Outer periphery, 42 Center portion, 50 Substrate, 51 Insulating layer, 52, 53, 54, 55 Metal layer, 60 Bonding material, 61, 62, 63, 64, 65, 66, 67 Wiring member, 70 Bonding material, 71 Base plate, 72 Outer case, 73 Sealing material, 100, 100A, 100B Semiconductor device, 200 Semiconductor module, 300 Power conversion device, 301 Main conversion circuit, 302 Semiconductor device, 303 Control circuit, 304 Control signal, 410 Power supply, 420 Load, S1 Preparation process, S2 Element structure formation process, S3 Grinding process, S4 Electrode formation process, S5 Support base joining process, S6 Dicing process.

Claims

1. A power semiconductor device, A support plate; a power semiconductor element; a first electrode and a second electrode; a first bonding material; the support plate has a first surface and a second surface opposite to the first surface, the support plate is electrically conductive; the thickness of the support plate is greater than the thickness of the power semiconductor element; the power semiconductor element has a third surface and a fourth surface opposite to the third surface, the first electrode and the second electrode are disposed on the third surface and the fourth surface, respectively; The power semiconductor element is disposed on the support plate such that the first electrode faces the second surface with the first bonding material interposed therebetween.

2. 2. The power semiconductor device according to claim 1, wherein said power semiconductor element has a semiconductor substrate made of gallium oxide.

3. 2. The power semiconductor device according to claim 1, wherein said power semiconductor element has a thickness of 0.1 mm or less.

4. The distance between the edge of the active region of the power semiconductor element and the edge of the power semiconductor element in a plan view is L ｓ and the distance between the end of the power semiconductor element and the end of the support plate in a plan view is L ｃ and the distance between the second surface and the fourth surface is t ｃ and the thickness of the support plate is t ｓ Then, L ｃ ≧(t ｃ +t ｓ )-L ｓ 2. The power semiconductor device according to claim 1, wherein the following relationship is satisfied:

5. The power semiconductor device according to claim 1 , wherein the first bonding material is a sintered body of metal particles.

6. The power semiconductor device according to claim 1 , wherein the first bonding material has a thickness of 0.02 mm or less.

7. 2. The power semiconductor device according to claim 1, wherein said support plate is made of Cu, a Cu alloy, Al, an Al alloy, or an Al-Si-C alloy.

8. 2. The power semiconductor device according to claim 1, wherein the support plate has a semiconductor layer and a first metal film disposed on at least one of the first surface and the second surface and in ohmic contact with the semiconductor layer.

9. a second metal film disposed on the second electrode; the thickness of the second metal film is 0.005 mm or more; 2. The power semiconductor device according to claim 1, wherein said second metal film is made of Cu, a Cu alloy, Ni, or a Ni alloy.

10. A metal block and Further comprising a second bonding material, 2. The power semiconductor device according to claim 1, wherein the metal block is disposed on the second electrode with the second bonding material interposed therebetween.

11. 11. A method for manufacturing the power semiconductor device according to claim 1, further comprising the steps of: providing a semiconductor wafer having a front surface and a back surface; the semiconductor wafer has an outer periphery located on the outer periphery of the semiconductor wafer in a plan view, and a central portion located inside the outer periphery in a plan view, forming the power semiconductor element and the second electrode in the central portion; grinding the back surface located in the central portion; forming the first electrode on the back surface; a step of placing the semiconductor wafer so that the first electrode and the support stand face each other with the first bonding material interposed therebetween, and bonding the first electrode and the support stand with the first bonding material; and dicing the semiconductor wafer and the support base.

12. 12. The method for manufacturing a power semiconductor device according to claim 11, wherein the step of grinding the back surface includes at least two of a step of grinding the back surface with first abrasive grains, a step of grinding the back surface with second abrasive grains having a diameter smaller than that of the first abrasive grains, and a step of polishing the back surface.

13. The method for manufacturing a power semiconductor device according to claim 11 , wherein the step of dicing the semiconductor wafer and the support base is performed in a plurality of steps.

14. A power semiconductor module comprising the power semiconductor device according to claim 1 .

15. a main conversion circuit including the power semiconductor device according to any one of claims 1 to 10, which converts input power and outputs the converted power; a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit.

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