Semiconductor device and power conversion device

Abstract

This semiconductor device includes a MOSFET and comprises: a gallium oxide layer of a first conductivity type; a first gallium oxide region containing acceptor-type impurities selectively provided in an upper-layer portion of the gallium oxide layer; a second gallium oxide region of the first conductivity type selectively provided in an upper-layer portion of the first gallium oxide region; an oxide semiconductor layer of a second conductivity type, said oxide semiconductor layer being formed from an oxide semiconductor material different from gallium oxide and being formed in a trench running into the gallium oxide layer from the surface of the gallium oxide layer; and a main electrode provided so as to be in contact with the second gallium oxide region and the oxide semiconductor layer.

Description

Semiconductor device and power conversion device

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device made of gallium oxide.

[0002] Gallium oxide (Ga ２ O ３ ) has a band gap exceeding that of silicon carbide (SiC) and gallium nitride (GaN), making it an advantageous material for increasing the breakdown voltage and decreasing the resistance of power devices, and is expected to be a promising material for next-generation power devices.

[0003] As an example of a semiconductor device using a gallium oxide-based semiconductor, Patent Document 1 discloses a field effect transistor in which a silicon layer in which a channel region is formed is joined to a gallium oxide layer, and a p-type oxide semiconductor such as NiO is embedded in a trench reaching the gallium oxide layer to form a p-type semiconductor portion.

[0004] JP 2023-68447 A

[0005] In a heterojunction structure of a silicon layer and a gallium oxide layer as in Patent Document 1, resistance due to the heterojunction occurs at the heterojunction interface. This resistance is due to band gap mismatch (band offset), etc. Patent Document 1 does not mention that such resistance due to the heterojunction can cause problems in the operation of a metal-oxide-semiconductor field-effect transistor (MOSFET), and the engineers of the present disclosure have gained knowledge of this problem through their own research. Furthermore, in Patent Document 1, the channel region is formed of silicon, so the breakdown voltage of the semiconductor device is limited by the physical properties of silicon.

[0006] The present disclosure has been made to solve the above problems, and has an object to provide a MOS field effect transistor having a higher breakdown voltage.

[0007] The semiconductor device according to the present disclosure is a semiconductor device having a MOSFET, comprising: a gallium oxide layer of a first conductivity type; a first gallium oxide region containing acceptor-type impurities selectively provided in an upper layer portion of the gallium oxide layer; a second gallium oxide region of the first conductivity type selectively provided in an upper layer portion of the first gallium oxide region; an oxide semiconductor layer of a second conductivity type made of an oxide semiconductor material different from gallium oxide and formed in a trench provided from the surface of the gallium oxide layer to within the gallium oxide layer; and a main electrode provided so as to be in contact with the second gallium oxide region and the oxide semiconductor layer.

[0008] According to the semiconductor device according to the present disclosure, a semiconductor device having no heterojunction therein, no resistance component due to the heterojunction, low on-resistance, and high breakdown voltage can be obtained.

[0009] Fig. 10 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. Fig. 11 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. Fig. 12 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment. Fig. 13 is a cross-sectional view showing the structure of a semiconductor device according to a fourth embodiment. Fig. 14 is a cross-sectional view showing the structure of a semiconductor device according to a modification of the fourth embodiment. Fig. 15 is a cross-sectional view showing the structure of a semiconductor device according to a fifth embodiment. Fig. 16 is a cross-sectional view showing the structure of a semiconductor device according to a modification of the fifth embodiment. Fig. 17 is a block diagram showing the configuration of a power conversion system according to a sixth embodiment.

[0010] Hereinafter, embodiments of the technology according to the present disclosure will be described with reference to the drawings. The present technology is not limited to the embodiments shown here, and can be modified as appropriate without departing from the spirit of the technology. In addition, in the drawings shown below, the scale of each component or each component may differ from the actual scale in order to facilitate understanding, and the same applies between the drawings.

[0011] In addition, in the following description, terms such as "upper" and "lower" that indicate specific positions and directions may be used, but these terms are used for convenience to make it easier to understand the contents of the embodiments, and do not relate to the directions in which they are actually implemented.

[0012] First Preferred Embodiment FIG. 1 is a diagram showing the configuration of a semiconductor device 100 according to a first preferred embodiment, and is a cross-sectional view showing the structure of a unit cell constituting the semiconductor device. A plurality of unit cells shown in FIG. 1 are arranged in an active area of ​​the semiconductor device 100. In this preferred embodiment, a semiconductor device using gallium oxide (Ga ２ O ３ ), especially β-type gallium oxide (β-Ga ２ O ３ ) is used as a material for a vertical MOSFET.

[0013] The semiconductor device 100 according to the first embodiment is a β-Ga ２ O ３ The gallium oxide semiconductor layer 20 is formed using a gallium oxide semiconductor layer 20 comprising a gallium oxide substrate 4 (first gallium oxide layer), a drift layer 3 (gallium oxide layer) provided on the gallium oxide substrate 4, a well region 2 (first gallium oxide region) selectively provided in an upper portion of the drift layer 3, and a source region 1 (second gallium oxide region) selectively provided in an upper portion of the well region 2. The upper surface of the gallium oxide semiconductor layer 20 (the upper surface of the drift layer 3) in FIG. 1 is defined as a "first main surface," and the lower surface of the gallium oxide semiconductor layer 20 (the lower surface of the gallium oxide substrate 4) is defined as a "second main surface."

[0014] The gallium oxide substrate 4 is an n-type β-Ga substrate having a (001) plane as its main surface. ２ O ３ The thickness can be determined depending on the withstand voltage level of the semiconductor device 100, and can be, for example, about 1 μm to 700 μm. Here, the gallium oxide substrate 4 may be a semiconductor substrate made of gallium oxide, or a layer made of gallium oxide epitaxially grown on a semiconductor substrate made of a material other than gallium oxide may be used. Furthermore, the crystal plane of the gallium oxide substrate 4 is not limited to the (001) plane, and other plane orientations may be used.

[0015] The gallium oxide substrate 4 contains at least one of n-type dopants, silicon, chlorine, tin, and germanium, at a concentration of 1×10 １８ cm －３ ~5 x 10２１ cm －３ It is added at a moderate concentration.

[0016] The drift layer 3 is made of n-type β-Ga ２ O ３ The thickness can be determined depending on the breakdown voltage level of the semiconductor device 100, and can be, for example, about 5 μm to 100 μm.

[0017] The drift layer 3 is formed by, for example, a halide vapor phase epitaxy (HVPE) method or a metal organic chemical vapor deposition (MOCVD) method, and contains at least one of silicon, chlorine, tin, and germanium, which are n-type dopants, at a concentration of 1×10 １４ cm －３ ~1 x 10 １７ cm －３ It is added at a moderate concentration.

[0018] The well region 2 is formed by ion implantation or thermal diffusion so as to have a depth of 500 nm to 3 μm, and an acceptor-type impurity that forms an acceptor level is implanted at a concentration of 1×10 １５ cm －３ ~1 x 10 ２１ cm －３ The doping concentration is about 1000 . Candidates for acceptor-type impurities include, for example, nitrogen, magnesium, zinc, and phosphorus. When ion implantation is used, the ion implantation can be performed at a temperature higher or lower than room temperature.

[0019] The source region 1 is formed by ion implantation or thermal diffusion so as to have a depth of, for example, 10 nm to 1 μm, and at least one of n-type dopants, silicon, chlorine, tin, and germanium, is doped in an amount of 1×10 １８ cm －３ ~1 x 10 ２１ cm －３ It is added at a moderate concentration.

[0020] A p-type semiconductor layer 10 (oxide semiconductor layer) is provided from the first main surface of the gallium oxide semiconductor layer 20 to the inside of the drift layer 3 so as to sandwich the unit cell, and the side surface of the p-type semiconductor layer 10, in other words, the side surface of the trench, is in contact with the side surface of the source region 1. The p-type semiconductor layer 10 is, for example, a β-Ga ２O ３ Although a semiconductor layer different from the above can be used, a p-type β-Ga containing p-type impurities ２ O ３ can also be used.

[0021] The p-type semiconductor layer 10 contains a p-type impurity of 1×10 １５ cm －３ ~1 x 10 ２１ cm －３ Candidates for p-type impurities include, for example, nitrogen, magnesium, zinc, and phosphorus.

[0022] The p-type semiconductor layer 10 has a thickness equal to or greater than the depth of the well region 2, and is set to, for example, 500 nm to 9 μm. The p-type semiconductor layer 10 is formed by removing the drift layer 3 from the first main surface to a desired depth using etching such as dry etching to form a trench, and then filling the trench with a material such as NiO or Cu by chemical vapor deposition (CVD) or sputtering. ２ O, Ir ２ O ３ The p-type semiconductor layer 10 can be obtained by filling the trench with an oxide semiconductor such as gallium oxide semiconductor layer 20. Here, the p-type semiconductor layer 10 may be formed not only within the trench but also in a portion exceeding the gallium oxide semiconductor layer 20, i.e., extending up to the upper part of the trench. Alternatively, the p-type semiconductor layer 10 may be formed only in a portion not exceeding the gallium oxide semiconductor layer 20, i.e., only in a portion lower than the upper end of the trench. Note that the oxide semiconductor is not limited to the above, and may be (IrGa) ２ O ３ It can also contain Ga, as in NiO and Cu. ２ It may also be a mixed crystal containing O or the like.

[0023] Between the upper surfaces of the adjacent well regions 2, a gate insulating film 5 is formed from above the edge of one source region 1 to above the edge of the other source region 1, and a gate electrode 6 is formed on the gate insulating film 5. The gate electrode 6 is preferably formed of a metal material, n-type polysilicon, or p-type polysilicon, and in particular, a high-concentration p-type (p ＋It is more preferable that the polysilicon layer is made of polysilicon (type 1). The polysilicon layer can be formed by CVD or sputtering. It can also be made of a laminated film of polysilicon and metal.

[0024] The gate insulating film 5 is made of SiO ２ , SiN, HfO ２ , Al ２ O ３ , La ２ O ３ , Y ２ O ３ , ZrO ２ Films such as these can be formed using a CVD method, an atomic layer deposition (ALD) method, a pulsed laser deposition (PLD) method, or an electron beam (EB) evaporation method.

[0025] On the first main surface of the gallium oxide semiconductor layer 20, an interlayer insulating film 7 is formed so as to cover the gate electrode 6 and the outside thereof. A source electrode 8 (main electrode) is formed on the interlayer insulating film 7. The gate electrode 6 and the source electrode 8 are electrically isolated by the interlayer insulating film 7. The interlayer insulating film 7 is made of SiO ２ Although a film or a SiN film can be used, SiO ２ The dielectric constant of the film is 3.9, which is ２ O ３ Therefore, the interlayer insulating film 7 in contact with the gallium oxide semiconductor layer 20 is made of SiO ２ If the interlayer insulating film 7 is made of a gallium oxide semiconductor layer 20, an electric field nearly three times that of the gallium oxide semiconductor layer 20 will be applied to the interlayer insulating film 7. Therefore, from the viewpoint of breakdown resistance, the relative dielectric constant of the interlayer insulating film 7 is set to be equal to that of a silicon oxide film (SiO ２ ) is preferable. However, generally, the relative dielectric constant and the band gap are inversely proportional to each other, and the higher the relative dielectric constant of a material, the smaller the band gap. Therefore, if the interlayer insulating film 7 is made of a material with a high relative dielectric constant, it is difficult to ensure a sufficient band offset with respect to the gallium oxide semiconductor layer 20. Therefore, the interlayer insulating film 7 is preferably made of a material with a dielectric constant of SiO ２ The lower layer is a high-k film with a higher band gap than the lower layer, and the SiO ２A two-layer structure can be used in which a high-k film is placed on the upper layer. This allows for both high breakdown voltage and low leakage current. ２ , HfO ２ , Al ２ O ３ , BaTiO ３ , MgF ２ The high-k film can be formed by CVD or sputtering.

[0026] A contact hole CH is formed in the interlayer insulating film 7, reaching the gallium oxide semiconductor layer 20, and the source electrode 8 is electrically connected to the source region 1 of the gallium oxide semiconductor layer 20 and the p-type semiconductor layer 10 through the contact hole CH.

[0027] A drain electrode 9 is formed on the second main surface of the gallium oxide semiconductor layer 20. The drain electrode 9 is electrically connected to the gallium oxide substrate 4.

[0028] The source electrode 8 and the drain electrode 9 are formed by depositing a metal film using a CVD method or a sputtering method and patterning the metal film by selective wet etching using a photolithography technique. A Ti / Al laminated structure is suitable as the material for the source electrode 8 and the drain electrode 9, and the film thickness is, for example, 20 nm for Ti and 3 μm for Al.

[0029] The semiconductor device 100 according to the first embodiment described above has a channel region 11 and a drift layer 3 made of β-Ga ２ O ３ Since the semiconductor device is formed of the above, it does not have a heterojunction, and the resistance component caused by the heterojunction is eliminated, resulting in a semiconductor device with low on-resistance and high breakdown voltage.

[0030] Furthermore, by disposing the p-type semiconductor layer 10 near the well region 2, a depletion layer extends from the p-type semiconductor layer 10 to below the well region 2, including a region under the gate electrode called a JFET region, thereby achieving a high breakdown voltage. Note that the source region 1, the well region 2, and the drift layer 3 are made of a material mainly containing gallium oxide, but have a band gap that is equal to or close to the band gap of the material of the adjacent p-type semiconductor layer 10, and is significantly different from the band gap of silicon. Therefore, compared to a case in which the source region, the well region, and the drift layer in a MOSFET are made of silicon, the present disclosure can contribute to mitigating the effect of band mismatch at the interfaces between the source region 1, the well region 2, and the drift layer 3 and the p-type semiconductor layer 10, while mitigating the electric field in or near the well region 2 itself.

[0031] Furthermore, since the source electrode 8 is in direct contact with the p-type semiconductor layer 10, there is no intervening layer and no voltage drop occurs, so the potential of the source electrode 8 and the potential of the p-type semiconductor layer 10 tend to be the same, which has the effect of stabilizing the potential of the p-type semiconductor layer 10.

[0032] Furthermore, since the side surfaces of the source region 1 contact the side surfaces of the p-type semiconductor layer 10 and the source electrode 8 contacts the source region 1 over a wide area, current easily flows from the source electrode 8 to the source region 1, which has the effect of stabilizing the operation of the MOSFET.

[0033] Furthermore, by forming the p-type semiconductor layer 10 deeper than the well region 2, an electrolysis relaxation effect can be obtained within the semiconductor device, particularly near the bottom of the well region 2. That is, by forming the p-type semiconductor layer 10 0.2 μm or more deeper than the well region 2, an electrolysis relaxation effect can be obtained, and at 0.5 μm or more, an even greater electrolysis relaxation effect can be obtained, and at 1 μm or more, an even greater electrolysis relaxation effect can be obtained.

[0034] Furthermore, the donor concentration of the JFET region sandwiched between the well regions 2 can be made higher than that of the drift layer 3. In this case, it is possible to prevent a depletion layer from extending from the well region 2 to the JFET region and causing narrowing of the current path, and the drift layer 3 can be made highly concentrated and serve as a low-resistance layer.

[0035] 2 is a diagram showing the configuration of a semiconductor device 200 according to a second embodiment, and is a cross-sectional view showing the structure of a unit cell constituting the semiconductor device. In FIG. 2, the same components as those in the semiconductor device 100 described with reference to FIG. 1 are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0036] In the semiconductor device 200 according to the second embodiment, the drift layer 3 is composed of an upper drift layer 32 in contact with part of the side surface of the p-type semiconductor layer 10, and a lower drift layer 31 that is closer to the gallium oxide substrate 4 than the upper drift layer 32. The lower drift layer 31 is provided to a thickness that allows it to contact the bottom surface of the p-type semiconductor layer 10 from above the gallium oxide substrate 4, and the concentration of the n-type dopant in the upper drift layer 32 is set to be higher than that of the lower drift layer 31. The upper drift layer 32 is provided in a JFET region sandwiched between well regions 2.

[0037] The higher the concentration of the n-type dopant in the upper drift layer 32, the higher the conductivity in the current path, and the greater the effect of reducing the resistance of the MOSFET. For example, when the concentration of the n-type dopant in the lower drift layer 31 is 1×10 １４ cm －３ ~1 x 10 １７ cm －３ In this case, making the resistance of the MOSFET lower by 1.2 times or more that of the lower drift layer 31 is effective, making the resistance lower by 1.5 times or more is even greater, and making the resistance lower by 2 times or more is even greater.

[0038] Furthermore, the pn junction between the p-type semiconductor layer 10 and the upper drift layer 32 can be called a super junction (SJ), which reduces the resistance of the upper drift layer 32 and suppresses the depletion layer extending from the well region 2, thereby preventing the current path from being narrowed.

[0039] The semiconductor device 200 of the second embodiment described above has the same effects as the semiconductor device 100 of the first embodiment, and by having the upper drift layer 32, the resistance of the MOSFET can be further reduced.

[0040] 3 is a diagram showing the configuration of a semiconductor device 300 according to a third embodiment, and is a cross-sectional view showing the structure of a unit cell constituting the semiconductor device. In FIG. 3, the same components as those in the semiconductor device 100 described with reference to FIG. 1 are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0041] In the semiconductor device 300 according to the third embodiment, the side surface of the source region 1 does not contact the side surface of the p-type semiconductor layer 10, i.e., the side surface of the trench. Instead, the well region 2 is formed between the side surface of the source region 1 and the side surface of the p-type semiconductor layer 10. Therefore, the source electrode 8 contacts all of the source region 1, the well region 2, and the p-type semiconductor layer 10. Since the source electrode 8 is in direct contact with the well region 2, it is unlikely to contain a resistance component such as a band offset. This makes it easier for the potentials of the source electrode 8 and the well region 2 to be the same, stabilizing the potential of the well region 2 and resulting in a low-resistance, high-voltage MOSFET with stable switching operation. Even if the source electrode 8 does not contact the well region 2 in the cross section shown in FIGS. 1 and 2 , it may contact the well region 2 in another cross section, for example, in a region other than the active region. It may also contact the well region 2 in a cross section where the source region 1 is thinned out. The above-described effects can be achieved in these cases as well.

[0042] According to the semiconductor device 300 of the third embodiment described above, it is possible to obtain a low-resistance, high-voltage MOSFET that has the same effects as the semiconductor device 100 of the first embodiment, and also has a stable potential in the well region 2 and stable operation during switching of the MOSFET.

[0043] 4 is a diagram showing the configuration of a semiconductor device 400 according to a fourth embodiment, and is a cross-sectional view showing the structure of a unit cell that constitutes the semiconductor device. In FIG. 4, the same components as those in the semiconductor device 300 described with reference to FIG. 3 are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0044] In the semiconductor device 400 according to the fourth embodiment, a p-type semiconductor layer 10A is provided from the first main surface of the gallium oxide semiconductor layer 20 to the inside of the drift layer 3 so as to sandwich the unit cell, and the side surface of the p-type semiconductor layer 10A, in other words, the side surface of the trench, is not in contact with the side surface of the source region 1. The p-type semiconductor layer 10A is made of β-Ga as in the p-type semiconductor layer 10. ２ O ３ Although a semiconductor layer different from the above can be used, a p-type β-Ga containing p-type impurities ２ O ３ can also be used.

[0045] The p-type semiconductor layer 10A has a thickness thinner than the depth of the well region 2, and when the depth of the well region 2 is 500 nm to 9 μm, the p-type semiconductor layer 10A can be made shallower by, for example, 0.05 μm or more, 0.1 μm or more, or 0.2 μm or more.

[0046] The thickness of the p-type semiconductor layer 10A can be reduced depending on the concentration of the p-type impurity added. If the concentration of the p-type impurity is increased, the depletion layer will be more likely to extend toward the drift layer 3 below the well region 2, while the depletion layer will be prevented from extending into the p-type semiconductor layer 10A, thereby suppressing dielectric breakdown.

[0047] The p-type semiconductor layer 10A is formed by removing the drift layer 3 from the first main surface to a corresponding depth by etching such as dry etching to form a trench, and then filling the trench with a material such as NiO or Cu by CVD or sputtering. ２ O, Ir ２ O ３ This can be obtained by forming an oxide semiconductor such as a p-type semiconductor layer 10A and filling it in. Therefore, by thinning the p-type semiconductor layer 10A, the process of forming a trench by etching and the process of filling the trench with an oxide semiconductor can be simplified, and the manufacturing process of the semiconductor device 400 can be simplified.

[0048] If the p-type semiconductor layer 10A is made shallower than the depth of the well region 2, for example, by 0.05 μm or more, the effect of simplifying the manufacturing process is obtained, if it is made shallower by 0.1 μm or more, the effect of simplifying the manufacturing process is even greater, and if it is made shallower by 0.2 μm or more, the effect of simplifying the manufacturing process is even greater.

[0049] According to the semiconductor device 400 of the fourth embodiment described above, it is possible to obtain a low-resistance, high-voltage MOSFET with a simplified manufacturing process while achieving the same effects as the semiconductor device 100 of the first embodiment.

[0050] 5 is a diagram showing the configuration of a semiconductor device 400A according to a modification of the fourth embodiment, and is a cross-sectional view showing the structure of a unit cell constituting the semiconductor device. In Fig. 5, the same components as those in the semiconductor device 400 described using Fig. 4 are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0051] In the semiconductor device 400A, the side of the source region 1 is in contact with the side of the p-type semiconductor layer 10, in other words, the side of the trench, and the source electrode 8 is in contact with the source region 1 over a wide area, so that current easily flows from the source electrode 8 to the source region 1, which has the effect of stabilizing the operation of the MOSFET.

[0052] 6 is a diagram showing the configuration of a semiconductor device 500 according to a fifth embodiment, and is a cross-sectional view showing the structure of a unit cell that constitutes the semiconductor device. In FIG. 5, the same components as those in the semiconductor device 300 described with reference to FIG. 3 are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0053] In the semiconductor device 500 according to the fifth embodiment, p-type semiconductor layers 10B are provided above the outermost surface of the drift layer 3 on the first main surface of the gallium oxide semiconductor layer 20 so as to sandwich the unit cell. The p-type semiconductor layer 10B may be provided on the drift layer 3, or may be provided on the source region 1 or the well region 2. The p-type semiconductor layer 10B is made of β-Ga as in the p-type semiconductor layer 10. ２ O ３ Although a semiconductor layer different from the above can be used, a p-type β-Ga containing p-type impurities ２O ３ can also be used.

[0054] The p-type semiconductor layer 10B has a thickness that is approximately equal to or less than the depth of the well region 2, and when the depth of the well region 2 is 500 nm to 9 μm, the p-type semiconductor layer 10B can be made thinner by, for example, 0.05 μm or more, 0.1 μm or more, or 0.2 μm or more.

[0055] The thickness of p-type semiconductor layer 10B can be made thinner depending on the concentration of the p-type impurity added, and while increasing the concentration of the p-type impurity makes it easier for the depletion layer to extend toward drift layer 3 below well region 2, it also prevents the depletion layer from extending into p-type semiconductor layer 10B, making it possible to prevent dielectric breakdown even when the p-type semiconductor layer is made thinner. Note that p-type semiconductor layer 10 may be made thicker if the impurity concentration is kept low.

[0056] The p-type semiconductor layer 10B is formed by depositing NiO, Cu, etc., using a mask by, for example, CVD or sputtering. ２ O, Ir ２ O ３ This can be obtained by selectively forming an oxide semiconductor such as the gallium oxide semiconductor layer 20 using a mask. Therefore, etching for providing a trench in the gallium oxide semiconductor layer 20 is not required, and the manufacturing process of the semiconductor device 500 can be simplified.

[0057] Furthermore, if the p-type semiconductor layer 10B is made thinner than the depth of the well region 2 by, for example, 0.05 μm or more, the effect of shortening the time required to form the oxide semiconductor is added, and the effect of simplifying the manufacturing process is enhanced, if it is made shallower by 0.1 μm or more, the effect of simplifying the manufacturing process is further enhanced, and if it is made shallower by 0.2 μm or more, the effect of simplifying the manufacturing process is even enhanced. In these cases, by adjusting the thickness and p-type impurity concentration of the p-type semiconductor layer 10B, it is possible to achieve both an improvement in the breakdown voltage of the semiconductor device and an improvement in productivity.

[0058] According to the semiconductor device 500 of the fifth embodiment described above, it is possible to obtain a low-resistance, high-voltage MOSFET with a simplified manufacturing process while achieving the same effects as the semiconductor device 100 of the first embodiment.

[0059] 7 is a diagram showing the configuration of a semiconductor device 500A according to a modification of the fifth embodiment, and is a cross-sectional view showing the structure of a unit cell constituting the semiconductor device. In Fig. 7, the same components as those in the semiconductor device 500 described using Fig. 6 are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0060] In the semiconductor device 500A, the side of the source region 1 is in contact with the drift layer 3, and the source electrode 8 is in contact with the source region 1 over a wide area, so that current easily flows from the source electrode 8 to the source region 1, which has the effect of stabilizing the operation of the MOSFET.

[0061] It is understood that the above description is illustrative in all aspects, and that countless modified examples not illustrated can be envisioned. For example, while a planar-gate MOSFET has been shown in this disclosure, the MOSFET may be a trench-gate MOSFET in which a gate insulating film and a gate electrode are formed in a trench that penetrates the well region 2 and reaches the drift layer 3. In this case, a p-type semiconductor layer 10 is provided so as to contact the side of the well region 2 opposite the trench gate, and the thickness of the p-type semiconductor layer 10 can be equal to or greater than the depth of the well region 2. Furthermore, the p-type semiconductor layer 10 can also be formed above the semiconductor layer 20, as shown in FIG. 6 or FIG. 7 .

[0062] It should be noted that the embodiments can be freely combined, and the embodiments can be modified or omitted as appropriate.

[0063] Sixth Embodiment In this embodiment, the semiconductor device according to any one of the above-described first to fifth embodiments is applied to a power conversion device. Although application of the semiconductor device according to any one of the first to fifth embodiments is not limited to a specific power conversion device, the sixth embodiment will be described below as a case where the semiconductor device according to any one of the first to fifth embodiments is applied to a three-phase inverter.

[0064] FIG. 8 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0065] The power conversion system shown in Fig. 8 is composed of a power supply 1000, a power conversion device 2000, and a load 3000. The power supply 1000 is a DC power supply and supplies DC power to the power conversion device 2000. The power supply 1000 can be composed of various components, such as a DC system, a solar cell, or a storage battery, or it can be composed of a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 1000 can also be composed of a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0066] The power conversion device 2000 is a three-phase inverter connected between the power supply 1000 and the load 3000, and converts DC power supplied from the power supply 1000 into AC power and supplies the AC power to the load 3000. As shown in Fig. 8 , the power conversion device 2000 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals that drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs control signals to the drive circuit 202.

[0067] The load 3000 is a three-phase electric motor driven by AC power supplied from the power conversion device 2000. The load 3000 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0068] The power conversion device 2000 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheel diodes (not shown). The switching elements convert DC power supplied from the power supply 1000 into AC power, which is supplied to the load 3000. The main conversion circuit 201 can have a variety of specific circuit configurations. The main conversion circuit 201 according to this embodiment is a two-level, three-phase full-bridge circuit, which can be configured with six switching elements and six freewheel diodes connected in anti-parallel to each switching element. At least one of the switching elements and freewheel diodes of the main conversion circuit 201 is configured with a semiconductor device according to any one of the first to fifth embodiments. Two of the six switching elements are connected in series to form upper and lower arms, which form each phase (U phase, V phase, and W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 3000.

[0069] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit 202 outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0070] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 3000. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 3000. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 203 then outputs a control command (control signal) to the drive circuit 202 so that an on signal is output to the switching element that should be in the on state at each time point, and an off signal is output to the switching element that should be in the off state at each time point. In accordance with this control signal, the drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0071] In the power conversion device of this embodiment, a semiconductor device according to any one of embodiments 1 to 5 is applied as the switching element of the main conversion circuit 201, so that a power conversion device using a semiconductor device with low on-resistance and high withstand voltage is obtained.

[0072] In the present embodiment, an example has been described in which the semiconductor device according to any one of the first to fifth embodiments is applied to a two-level three-phase inverter, but the application of the semiconductor device according to any one of the first to fifth embodiments is not limited to this, and the semiconductor device can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used, and when power is supplied to a single-phase load, the semiconductor device according to any one of the first to fifth embodiments may be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the semiconductor device according to any one of the first to fifth embodiments can also be applied to a DC / DC converter or an AC / DC converter.

[0073] Furthermore, a power conversion device to which the semiconductor device according to any one of the first to fifth embodiments is applied is not limited to cases in which the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0074] 1 source region, 2 well region, 3 drift layer, 4 gallium oxide substrate, 5 gate insulating film, 6 gate electrode, 7 interlayer insulating film, 8 source electrode, 9 drain electrode, 10, 10A, 10B p-type semiconductor layer, 31 lower drift layer, 32 upper drift layer, 1000 power supply, 2000 power conversion device, 201 main conversion circuit, 202 drive circuit, 203 control circuit, 3000 load.

Claims

1. A semiconductor device comprising a MOSFET, A first-type conductive gallium oxide layer, A first gallium oxide region containing acceptor-type impurities selectively provided in the upper part of the gallium oxide layer, A second gallium oxide region of a first conductivity type is selectively provided in the upper layer of the first gallium oxide region, A second conductivity type oxide semiconductor layer is formed in a trench provided from the surface to the interior of the gallium oxide layer, and is composed of an oxide semiconductor material different from gallium oxide. A semiconductor device comprising: a second gallium oxide region and a main electrode provided in contact with the oxide semiconductor layer.

2. The aforementioned oxide semiconductor layer is The semiconductor device according to claim 1, having a thickness greater than or equal to the depth of the first gallium oxide region.

3. The aforementioned oxide semiconductor layer is The semiconductor device according to claim 1, having a thickness that does not exceed the depth of the first gallium oxide region.

4. The second gallium oxide region is, A semiconductor device according to any one of claims 1 to 3, which is in contact with the side surface of the trench.

5. The second gallium oxide region is, A semiconductor device according to any one of claims 1 to 3, wherein it does not come into contact with the side surface of the trench.

6. The main electrode is, A semiconductor device according to any one of claims 1 to 3, which is in contact with the first gallium oxide region.

7. A semiconductor device comprising a MOSFET, A first-type conductive gallium oxide layer, A first gallium oxide region containing acceptor-type impurities selectively provided in the upper part of the gallium oxide layer, A second gallium oxide region of a first conductivity type is selectively provided in the upper layer of the first gallium oxide region, A second conductivity type oxide semiconductor layer is provided on the gallium oxide layer, and the oxide semiconductor layer is composed of an oxide semiconductor material different from gallium oxide. A semiconductor device comprising: a second gallium oxide region and a main electrode provided in contact with the oxide semiconductor layer.

8. The second gallium oxide region is, The semiconductor device according to claim 7, provided so as not to exceed the first gallium oxide region in a plan view.

9. The second gallium oxide region is, The semiconductor device according to claim 7, wherein the side surface is provided in contact with the gallium oxide layer.

10. The first gallium oxide layer of a first conductivity type is provided beneath the gallium oxide layer, The gallium oxide layer is The lower layer in contact with the first gallium oxide layer, A semiconductor device according to claim 1 or claim 7, comprising an upper layer provided on the lower layer and having a higher concentration of first conductivity type impurities than the lower layer.

11. The semiconductor device according to claim 10, wherein the upper layer is provided in a JFET region sandwiched between two opposing first gallium oxide regions.

12. A semiconductor device according to claim 1 or claim 7, comprising a main conversion circuit that converts and outputs input power, A drive circuit that outputs a drive signal to the semiconductor device to drive the semiconductor device, A power conversion device comprising a control circuit that outputs a control signal to the drive circuit for controlling the drive circuit.