Semiconductor Device

Abstract

A first base plate (1) and a second base plate (2) are bonded together with a conductive bonding material (3). The second base plate (2) has a lower thermal conductivity than the first base plate (1). A semiconductor chip (4) is provided on the first base plate (1). An electronic component (5) is provided on the second base plate (2). An outer frame (9) is provided on the first base plate (1) and the second base plate (2) and surrounds the semiconductor chip (4) and the electronic component (5). A cap (12) is bonded onto the outer frame (9) and hermetically seals the semiconductor chip (4) and the electronic component (5).

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] In a semiconductor device in which a semiconductor chip and electronic components are mounted on a base plate, heat is transferred from the semiconductor chip, which is the heat source, to the electronic components via the base plate. For this reason, when a semiconductor chip that generates a large amount of heat is used, electronic components with a low rated temperature cannot be used. In response to this, it has been proposed to suppress heat transfer by separating the base plate between the chip and the electronic components (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2002 / 017400 Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor device in which a semiconductor chip and electronic components are hermetically sealed within a package, there has been a problem that the airtightness is lost when the base plate is separated.

[0005] The present disclosure has been made to solve the above-mentioned problems, and has an object to obtain a semiconductor device that can ensure airtightness while suppressing heat transfer from a semiconductor chip to an electronic component. [Means for solving the problem]

[0006] A semiconductor device according to the present disclosure includes a first base plate, a second base plate bonded to the first base plate with a conductive bonding material and having a lower thermal conductivity than the first base plate, a semiconductor chip provided on the first base plate, electronic components provided on the second base plate, an outer frame provided on the first base plate and the second base plate and surrounding the semiconductor chip and the electronic components, and a cap bonded on the outer frame and hermetically sealing the semiconductor chip and the electronic components. The joint surface between the first base plate and the second base plate is inclined. It is characterized by: Effect of the Invention

[0007] In the present disclosure, the second base plate on which the electronic components are mounted has a lower thermal conductivity than the first base plate on which the semiconductor chip is mounted. This makes it possible to suppress heat transfer from the semiconductor chip to the electronic components. In addition, since the first base plate and the second base plate are bonded with a bonding material, the inside of the package can be hermetically sealed. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. [Diagram 2] 3 is a diagram showing the upper surfaces of first and second base plates according to the first embodiment. FIG. [Diagram 3] FIG. 11 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 4] FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Diagram 5] 13 is a diagram showing the upper surfaces of the first and second base plates according to the third embodiment. FIG. [Figure 6] 6 is a cross-sectional view taken along the line AA' in FIG. 5. [Figure 7] FIG. 6 is a cross-sectional view taken along the line BB′ in FIG. 5. [Figure 8] FIG. 11 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. [Figure 9] 13 is a diagram showing the upper surfaces of the first and second base plates according to the fourth embodiment. FIG. [Figure 10]FIG. 11 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. [Figure 11] 13 is a diagram showing the upper surface of a first base plate according to embodiment 5. FIG. [Figure 12] FIG. 13 is a cross-sectional view showing a semiconductor device according to a sixth embodiment. [Figure 13] 13 is a diagram showing the upper surface of a first base plate according to embodiment 6. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] A semiconductor device according to an embodiment will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

[0010] First embodiment FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. FIG. 2 is a diagram showing the top surfaces of a first and second base plate according to the first embodiment. A first base plate 1 and a second base plate 2 are joined by a conductive joining material 3. The joining material 3 is Ag brazing material, AuSn solder, or the like. The first base plate 1 is made of, for example, a Cu-Mo alloy. The second base plate 2 is made of an Fe-Ni-Co alloy. The second base plate 2 has a lower thermal conductivity than the first base plate 1. A cheaper material can be selected for the second base plate 2 with low heat dissipation than for the first base plate 1 with high heat dissipation, thereby reducing costs.

[0011] A semiconductor chip 4 is provided on a first base plate 1. An electronic component 5 is provided on a second base plate 2. A bottom electrode 4a of the semiconductor chip 4 is electrically connected to the first base plate 1 via a bonding material 6. A bottom electrode 5a of the electronic component 5 is electrically connected to the second base plate 2 via a bonding material 7. Since the first base plate 1 and the second base plate 2 are electrically connected via the bonding material 3, the bottom electrode 4a of the semiconductor chip 4 and the bottom electrode 5a of the electronic component 5 can be connected to a common ground potential.

[0012] The upper electrode 4b of the semiconductor chip 4 and the upper electrode 5b of the electronic component 5 are electrically connected by a wire 8. The semiconductor chip 4 is, for example, a high-frequency amplifier of a monolithic microwave integrated circuit (MMIC). The electronic component 5 is, for example, a capacitor shunt-connected to the input side of the semiconductor chip 4.

[0013] An outer frame 9 is provided on the first base plate 1 and the second base plate 2, and surrounds the semiconductor chip 4 and the electronic component 5. The outer frame 9 has a three-layer structure of ceramics 9a to 9c and a seal ring 9d. The upper surface of the upper ceramic 9c is metallized and is bonded to the lower surface of the seal ring 9d with a bonding material 10. The lower surface of the middle ceramic 9b is metallized and is bonded to the outer periphery of the upper surface of the first base plate 1 and the second base plate 2 with a bonding material 11. A cap 12 is bonded to the upper surface of the seal ring 9d with a bonding material 13, and the semiconductor chip 4 and the electronic component 5 in the package are hermetically sealed. The space between the first base plate 1 and the second base plate 2 is completely filled with the bonding material 3, and the spaces between the middle ceramic 9b and the first base plate 1 and the second base plate 2 are also completely filled with the bonding material 11, and are airtight.

[0014] The same material may be used for the bonding materials 3, 6, 7, 10, 11, and 13. However, while brazing filler metal can be used to bond metal and ceramic, solder cannot be used as is. Therefore, when solder is used as the bonding materials 10 and 11, it is necessary to metallize the top surface of the upper ceramic 9c and the bottom surface of the middle ceramic 9b in advance.

[0015] As described above, in this embodiment, the second base plate 2 on which the electronic components 5 are mounted has a lower thermal conductivity than the first base plate 1 on which the semiconductor chip 4 is mounted. This makes it possible to suppress heat transfer from the semiconductor chip 4 to the electronic components 5 while dissipating heat from the semiconductor chip 4. As a result, even if a semiconductor chip 4 that generates a large amount of heat is used, it is possible to use electronic components 5 with a low rated temperature. In addition, since the first base plate 1 and the second base plate 2 are bonded with the bonding material 3, the inside of the package can be hermetically sealed. This makes it possible to prevent deterioration of the semiconductor chip 4 due to moisture or gas outside the package.

[0016] Ceramic capacitors used in high frequency devices mainly use high dielectric constant barium titanate-based materials. This material has temperature characteristics, and the capacitance change is large in the high temperature range, so the rated temperature is low. Therefore, this embodiment is particularly effective when the electronic component 5 is a ceramic capacitor that uses high dielectric constant barium titanate-based material.

[0017] The band gap of GaN is 3.4 eV, which is larger than the band gap of GaAs, which is 1.424 eV. When the band gap of a semiconductor material is high, the dielectric breakdown voltage is high and it is possible to operate at a high voltage. Since GaN devices generate more heat than GaAs devices, this embodiment is particularly effective when the semiconductor chip 4 is a GaN device.

[0018] Embodiment 2 3 is a cross-sectional view showing a semiconductor device according to the second embodiment. The bonding surfaces of the first base plate 1 and the second base plate 2 are inclined. Therefore, when the first base plate 1 and the second base plate 2 are put into a high-temperature furnace for bonding, the first base plate 1 and the second base plate 2 are held in contact with each other by friction. Therefore, it is sufficient to place the first base plate 1 and the second base plate 2 on a flat jig, and there is no need to use a jig that forcibly brings the two into contact with each other.

[0019] The downward spread of heat from the semiconductor chip 4 follows the 45 degree rule. For this reason, it is desirable that the bonding surface of the first base plate 1 is inclined at 45 degrees with respect to the bottom surface of the first base plate 1. This ensures that heat dissipation from the semiconductor chip 4 is not impeded. The other configurations and effects are the same as those of the first embodiment.

[0020] Third embodiment FIG. 4 is a cross-sectional view showing a semiconductor device according to the third embodiment. FIG. 5 is a view showing the upper surfaces of the first and second base plates according to the third embodiment. FIG. 6 is a cross-sectional view taken along the line AA' in FIG. 5. FIG. 7 is a cross-sectional view taken along the line BB' in FIG. 5. The lower region of the bonding surface of the first base plate 1 and the lower region of the bonding surface of the second base plate 2 are bonded by the bonding material 3. An alumina coat 14 is applied to the upper region of the bonding surface of the second base plate 2. The alumina coat 14 has poor wettability with the bonding material 3 compared to the material of the second base plate 2. The alumina coat 14 may be applied to the upper region of the bonding surface of the first base plate 1. That is, the upper region of the bonding surface of the first base plate 1 or the second base plate 2 is treated to prevent the bonding material 3 from spreading. Therefore, the bonding material 3 does not spread between the upper region of the bonding surface of the first base plate 1 and the upper region of the bonding surface of the second base plate 2, and an air layer 15 exists. This air layer 15 can further suppress the heat transfer from the semiconductor chip 4 to the electronic component 5. As a result, it can further suppress the temperature rise of the electronic component 5. The other configurations and effects are the same as those of the first embodiment.

[0021] Fourth embodiment FIG. 8 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. FIG. 9 is a diagram showing the upper surfaces of the first and second base plates according to the fourth embodiment. The second base plate 2 is disposed on the first base plate 1 and has an opening 2a. The semiconductor chip 4 is provided on the first base plate 1 in the opening 2a of the second base plate 2 without going through the second base plate 2. Even with this configuration, it is possible to suppress heat transfer from the semiconductor chip 4 to the electronic component, and to hermetically seal the inside of the package. The other configurations and effects are the same as those of the first embodiment.

[0022] Fifth embodiment FIG. 10 is a cross-sectional view showing a semiconductor device according to the fifth embodiment. FIG. 11 is a view showing the upper surface of the first base plate according to the fifth embodiment. An alumina coat 14 is applied to the upper surface of the first base plate 1 below the electronic component 5. The alumina coat 14 has poor wettability with the bonding material 3 compared to the material of the first base plate 1. That is, below the electronic component 5, a treatment is applied to the upper surface of the first base plate 1 to prevent the bonding material 3 from spreading. Therefore, below the electronic component 5, the bonding material 3 does not spread, and an air layer 15 exists between the first base plate 1 and the second base plate 2. This air layer 15 can further suppress the heat transfer from the semiconductor chip 4 to the electronic component 5. As a result, the temperature rise of the electronic component 5 can be further suppressed. The other configurations and effects are the same as those of the fourth embodiment.

[0023] Sixth embodiment FIG. 12 is a cross-sectional view showing a semiconductor device according to the sixth embodiment. FIG. 13 is a view showing the top surface of a first base plate according to the sixth embodiment. In the fifth embodiment, the second base plate 2 is not bonded to the first base plate 1 between the air layer 15 and the semiconductor chip 4, and has a floating cantilever structure. In contrast, in the present embodiment, the first base plate 1 and the second base plate 2 are bonded by a bonding material 3 in a region surrounding the entire periphery of the air layer 15. By supporting the entire periphery of the air layer 15, the second base plate 2 is less likely to break than the cantilever structure of the fifth embodiment. Other configurations and effects are the same as those of the fifth embodiment. [Explanation of symbols]

[0024] 1 first base plate, 2 second base plate, 2a opening, 3 bonding material, 4 semiconductor chip, 4a, 5a lower electrode, 4b, 5b upper electrode, 5 electronic component, 8 wire, 9 outer frame, 12 cap, 14 alumina coating (treatment to prevent spreading of bonding material), 15 air layer

Claims

1. The first base plate and A second base plate is bonded to the first base plate by a conductive bonding material and has a lower thermal conductivity than the first base plate, A semiconductor chip provided on the first base plate, An electronic component provided on the second base plate, An outer frame provided on the first base plate and the second base plate, surrounding the semiconductor chip and the electronic component, The system comprises a cap bonded to the outer frame and hermetically sealing the semiconductor chip and the electronic component, A semiconductor device characterized in that the joining surfaces of the first base plate and the second base plate are inclined.

2. The semiconductor device according to claim 1, characterized in that the bonding surface is inclined at 45 degrees with respect to the bottom surface of the first base plate.

3. A first base plate and A second base plate is bonded to the first base plate by a conductive bonding material and has a lower thermal conductivity than the first base plate, A semiconductor chip provided on the first base plate, An electronic component provided on the second base plate, An outer frame provided on the first base plate and the second base plate, surrounding the semiconductor chip and the electronic component, The system comprises a cap bonded to the outer frame and hermetically sealing the semiconductor chip and the electronic component, The lower region of the joint surface of the first base plate and the lower region of the joint surface of the second base plate are joined by the joining material. The upper region of the joint surface of the first base plate or the second base plate is treated to prevent the bonding material from spreading. A semiconductor device characterized in that an air layer exists between the upper region of the bonding surface of the first base plate and the upper region of the bonding surface of the second base plate.

4. A first base plate and A second base plate is bonded to the first base plate by a conductive bonding material and has a lower thermal conductivity than the first base plate, A semiconductor chip provided on the first base plate, An electronic component provided on the second base plate, An outer frame provided on the first base plate and the second base plate, surrounding the semiconductor chip and the electronic component, The system comprises a cap bonded to the outer frame and hermetically sealing the semiconductor chip and the electronic component, The second base plate is placed on the first base plate and has an opening, The semiconductor chip is provided on the first base plate at the opening, A semiconductor device characterized in that, below the electronic component, the upper surface of the first base plate is treated to prevent the bonding material from wetting and spreading, and an air layer exists between the first base plate and the second base plate.

5. The semiconductor device according to claim 4, characterized in that the first base plate and the second base plate are joined by the joining material in the region surrounding the air layer.

6. The first base plate and the second base plate are electrically connected via the bonding material. The lower electrode of the semiconductor chip is electrically connected to the first base plate. The lower electrode of the electronic component is electrically connected to the second base plate. The semiconductor device according to any one of claims 1 to 5, characterized in that the upper electrode of the semiconductor chip and the upper electrode of the electronic component are electrically connected by a wire.

7. The semiconductor chip is a high-frequency amplifier, The semiconductor device according to claim 6, characterized in that the aforementioned electronic component is a capacitor.

8. The semiconductor device according to claim 7, characterized in that the aforementioned electronic component is a ceramic capacitor using a high dielectric constant barium titanate-based material.

9. The semiconductor device according to claim 7 or 8, characterized in that the semiconductor chip is a GaN device.

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