Semiconductor device and method for manufacturing semiconductor device

Abstract

The purpose of the present invention is to provide a technology capable of enhancing the embedding property of a conductive member in a recess of an interlayer insulating film. This semiconductor device comprises: a semiconductor layer; a gate electrode provided in a gate trench provided to the semiconductor layer with a gate insulating film therebetween, and provided with a recess in the center of the upper part; and an interlayer insulating film provided in a gate trench on the upper part of the gate electrode, and provided with a recess in the center of the upper part. The interlayer insulating film defines the recess of the interlayer insulating film, and has two or more upper surfaces inclined to each other.

Description

Semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In recent years, a semiconductor device has been proposed in which a gate electrode is provided in a gate trench via a gate insulating film, and an interlayer insulating film is provided entirely within the gate trench on the gate electrode (see, for example, Patent Document 1). Note that a conductive member such as a source electrode is provided on the interlayer insulating film.

[0003] Japanese Patent Application Laid-Open No. 2023-5683

[0004] However, in a structure in which a recess having a steep step is provided on the upper surface of an interlayer insulating film, when a conductive member such as a source electrode is formed in the recess, the conductive member that is deposited on the sidewall of the recess may connect to each other so as to surround a cavity. If the cavity is closed before the conductive member is deposited in the deep part of the recess, a cavity is formed inside the recess, which causes a problem of poor embedding of the conductive member in the recess.

[0005] The present disclosure has been made in view of the above-mentioned problems, and aims to provide a technique that can improve the embedding of a conductive member in a recess in an interlayer insulating film.

[0006] The semiconductor device according to the present disclosure comprises a semiconductor layer, a gate electrode provided in a gate trench provided in the semiconductor layer via a gate insulating film, the gate electrode having a recess in the center of its upper portion, and an interlayer insulating film provided in the gate trench above the upper portion of the gate electrode, the interlayer insulating film having two or more upper surfaces that are inclined relative to each other and define the recess in the interlayer insulating film.

[0007] According to the present disclosure, the interlayer insulating film has two or more upper surfaces that define a recess in the interlayer insulating film and are inclined relative to each other, and this configuration can improve the embedding of the conductive member in the recess in the interlayer insulating film.

[0008] The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0009] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment; 2 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment; 3 is a cross-sectional view showing a manufacturing method of a semiconductor device according to a first embodiment; 4 is a cross-sectional view showing a configuration of a semiconductor device according to a first modification; 5 is a cross-sectional view showing a configuration of a semiconductor device according to a second modification; 6 is a cross-sectional view showing a configuration of a semiconductor device according to a third modification; 7 is a cross-sectional view showing a configuration of a semiconductor device according to a fifth modification; 8 is a cross-sectional view showing a configuration of a semiconductor device according to a sixth modification; 9 is a cross-sectional view showing a configuration of a semiconductor device according to a seventh modification; 10 is a cross-sectional view showing a configuration of a semiconductor device according to a eighth modification;

[0010] Hereinafter, embodiments will be described with reference to the accompanying drawings. Features described in each of the following embodiments are merely examples, and not all features are necessarily required. Furthermore, in the following description, similar components in multiple embodiments are denoted by the same or similar reference numerals, and different components will be mainly described. Furthermore, in the following description, specific positions and directions such as "top," "bottom," "left," "right," "front," or "back" do not necessarily correspond to the positions and directions in actual implementation. Furthermore, a certain portion having a higher concentration than another portion may mean, for example, that the average concentration of the certain portion is higher than the average concentration of the other portion. Conversely, a certain portion having a lower concentration than another portion may mean, for example, that the average concentration of the certain portion is lower than the average concentration of the other portion. Furthermore, although the following description will be given assuming that the first conductivity type is n-type and the second conductivity type is p-type, the first conductivity type may also be p-type and the second conductivity type may also be n-type.

[0011] 1 and 2 are cross-sectional views showing the configuration of a semiconductor device according to a first preferred embodiment of the present invention. Note that the cross-sectional views in Fig. 1 and Fig. 2 are taken at different positions in the extension direction of a gate trench 7, which will be described later.

[0012] Hereinafter, the semiconductor device according to the first embodiment will be described as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited to this. The semiconductor device according to the first embodiment may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or an RC-IGBT (Reverse Conducting-IGBT), which is a semiconductor switching element including a diode.

[0013] The semiconductor device of FIG. 1 includes a semiconductor layer 1 , a gate insulating film 2 , a gate electrode 3 , an interlayer insulating film 4 , and a source electrode 6 .

[0014] The semiconductor layer 1 is made of, for example, silicon (Si) or a wide bandgap semiconductor, and includes at least one of a normal semiconductor wafer and an epitaxially grown layer. In this specification, for example, "at least one of A, B, C, ..., and Z" means any one of all combinations of one or more types selected from the group A, B, C, ..., and Z.

[0015] Wide band gap semiconductors include, for example, silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga ２ O ３ ), diamond, etc. When the semiconductor layer 1 is made of a wide band gap semiconductor, the semiconductor element can operate stably under high temperatures and high voltages, and can achieve high switching speeds.

[0016] The semiconductor layer 1 in FIG. 1 includes a drift region 1a, a low resistance region 1b, a well region (also called a base region) 1c, a source region 1d, a contact region 1e, and an electric field relaxation region 1f.

[0017] The drift region 1a is －The low resistance region 1b is an n-type region and is provided above the drift region 1a. The low resistance region 1b is a part of the drift region 1a. The well region 1c is a p-type region and is provided on the low resistance region 1b. The source region 1d is an n-type region. ＋ This is a mold region and is provided on the well region 1c.

[0018] The contact region 1e is p ＋ 1 and 2, depending on the position in the extension direction of the gate trench 7, the contact region 1e may or may not be provided.

[0019] The semiconductor layer 1 is provided with gate trenches 7 that extend from the top surface of the source region 1 d through the well region 1 c. In plan view, the gate trenches 7 may or may not have a stripe shape. The electric field relaxation region 1 f is a p-type region and is provided on the bottom surface of the gate trench 7.

[0020] The configuration of the semiconductor layer 1 is not limited to that shown in Fig. 1. For example, the configuration shown in Fig. 1 may include a p-type impurity region (not shown) that is provided along the gate trench 7 and connects the well region 1c and the electric field relaxation region 1f. Also, for example, the well region 1c and the source region 1d may not be provided in some areas.

[0021] The gate insulating film 2 is provided in the gate trench 7, and the gate electrode 3 is provided in the gate trench 7 via the gate insulating film 2. A recess 3a is provided in the center of the upper portion of the gate electrode 3.

[0022] The interlayer insulating film 4 is provided in the gate trench 7 above the gate electrode 3. In the first embodiment, the entire interlayer insulating film 4 is provided in the gate trench 7, and the upper end of the interlayer insulating film 4 is located lower than the upper end of the semiconductor layer 1 (i.e., the upper end of the source region 1d).

[0023] A recess 5 is provided in the center of the upper part of the interlayer insulating film 4. The interlayer insulating film 4 also includes a first interlayer insulating film 4a and a second interlayer insulating film 4b provided in the center of the upper part of the first interlayer insulating film 4a. The first interlayer insulating film 4a has a first upper surface 5a.

[0024] The second interlayer insulating film 4b has a second top surface 5b that is inclined with respect to the first top surface 5a and whose orientation is discontinuous with that of the first top surface 5a. That is, the first top surface 5a and the second top surface 5b are inclined with respect to each other, so that the angle formed between the second top surface 5b and a plane extending from the first top surface 5a is greater than 0 degrees and smaller than 90 degrees. In the first embodiment, the first top surface 5a is inclined with respect to the in-plane direction of the semiconductor layer 1 (corresponding to the left-right direction in FIGS. 1 and 2 ), and the second top surface 5b is parallel or approximately parallel to the in-plane direction.

[0025] The first upper surface 5a and the second upper surface 5b, which are inclined to each other, define a recess 5 in the upper part of the interlayer insulating film 4. It is preferable that there is no step between the first upper surface 5a and the second upper surface 5b.

[0026] The source electrode 6 is provided on the interlayer insulating film 4 and is electrically connected to the source region 1d and the contact region 1e. A drain electrode (not shown) is provided below the semiconductor layer 1. When a voltage equal to or greater than the threshold voltage is applied to the gate electrode 3, a channel is formed in the well region 1c on the gate electrode 3 side, and a current flows between the source electrode 6 and the drain electrode via the channel.

[0027] 3 and 4 are cross-sectional views showing a method for manufacturing a semiconductor device according to the first preferred embodiment, and correspond to FIG. － A well region 1c and a source region 1d are formed by ion-implanting, for example, p-type impurities and n-type impurities into an upper portion of a semiconductor substrate 21. Note that a region of the semiconductor substrate 21 where the ion-implanted regions such as the well region 1c are not formed becomes the drift region 1a.

[0028] Next, a patterned mask 22 is formed on the source region 1d, and the semiconductor substrate 21 exposed from the mask 22 is etched to form the gate trench 7. After the gate trench 7 is formed, the mask 22 is removed.

[0029] Then, for example, p-type impurities and n-type impurities are ion-implanted into the upper part of the semiconductor substrate 21 to form a low-resistance region 1b and an electric field relaxation region 1f, and if necessary, a p-type impurity region that connects the well region 1c and the electric field relaxation region 1f is formed.

[0030] Thereafter, a gate insulating film 2 is formed in the gate trench 7 by, for example, thermal oxidation or CVD (Chemical Vapor Deposition). Then, as shown in Fig. 4, a polysilicon film 23 is formed on the semiconductor substrate 21 and in the gate trench 7, and the polysilicon film 23 is etched to form a gate electrode 3. The upper portion of the gate electrode 3 is located between the lower end and the upper end of the source region 1d.

[0031] Next, a first interlayer insulating film 4a is formed on the gate insulating film 2 and the gate electrode 3, and a second interlayer insulating film 4b is formed on the first interlayer insulating film 4a. The first interlayer insulating film 4a and the second interlayer insulating film 4b are then etched to form a first upper surface 5a and a second upper surface 5b that define the recess 5. In this first embodiment, the etching rates of the first interlayer insulating film 4a and the second interlayer insulating film 4b are different, resulting in discontinuity between the orientations of the first upper surface 5a and the second upper surface 5b. The first interlayer insulating film 4a is made of, for example, tetraethoxysilane (TEOS), and the second interlayer insulating film 4b is made of, for example, borophosphosilicate glass (BPSG). Subsequently, a source electrode 6, a drain electrode, and the like are formed, completing the semiconductor device.

[0032] Summary of First Embodiment If the recess 5 has a steep step, that is, the aspect ratio of the recess 5 is equal to or greater than a certain level, and a conductive member to be the source electrode 6 is formed in the recess 5, the conductive member deposited on the sidewall of the recess 5 may connect to each other so as to surround a cavity. If the cavity is closed before the conductive member is deposited in the deep portion of the recess 5, a cavity is formed inside the recess 5, which causes a problem of poor embedding of the conductive member in the recess 5.

[0033] In contrast, in the semiconductor device according to the first embodiment, the interlayer insulating film 4 provided in the gate trench 7 has two upper surfaces that are inclined toward each other and define the recess 5 in the interlayer insulating film 4. With this configuration, the cross-sectional shape of the recess 5 in the interlayer insulating film 4 becomes smooth, and it is possible to prevent the cavity from being closed before the conductive material is deposited in the deep portion of the recess 5. Therefore, it is possible to prevent the cavity from being formed inside the recess 5, and it is possible to improve the embedding property of the conductive material in the recess 5.

[0034] In addition, this is expected to reduce the electrical resistance of the source electrode 6, improve the uniformity of the barrier metal provided between the source electrode 6 and the interlayer insulating film 4, and improve the connection strength of the wire or lead wire connected to the source electrode 6.

[0035] In the first embodiment, the interlayer insulating film 4 includes the first interlayer insulating film 4a and the second interlayer insulating film 4b, which have different etching rates. With this configuration, the first upper surface 5a and the second upper surface 5b can be easily formed.

[0036] <Modification 1> In the first embodiment, the interlayer insulating film 4 is two films (first interlayer insulating film 4 a and second interlayer insulating film 4 b), but this is not limited to this. For example, as shown in Fig. 5, the interlayer insulating film 4 may be a single film formed by patterning so as to have two upper surfaces that define the recess 5 of the interlayer insulating film 4 and are inclined relative to each other.

[0037] In the above description, the interlayer insulating film 4 defines the recess 5 and has two upper surfaces that are inclined to each other, but the number of such upper surfaces may be more than two. The more the number of upper surfaces that are inclined to each other increases, the smoother the cross-sectional shape of the recess 5 in the interlayer insulating film 4 becomes, and the more easily the conductive material can be embedded in the recess 5.

[0038] 6 , in the first embodiment, an inclined surface 1h may be provided between the upper surface 1g of the semiconductor layer 1 and the side surface 7a of the gate trench 7. With this configuration, the cross-sectional shape of the recess formed by combining the inclined surface 1h and the recess 5 of the interlayer insulating film 4 becomes smooth.

[0039] Therefore, the combined recess can also achieve the same effect as that achieved with the recess 5. That is, the embedding property of the source electrode 6 in the combined recess can be improved, and as a result, a reduction in the electrical resistance of the source electrode 6, an improvement in the uniformity of the barrier metal, and an improvement in the connection strength of the wire or lead wire can be expected.

[0040] <Modification 3> In the first embodiment, the first upper surface 5a is inclined with respect to the in-plane direction of the semiconductor layer 1, and the second upper surface 5b is parallel or substantially parallel to the in-plane direction. However, this is not limited to this. Depending on the etching rates of the first interlayer insulating film 4a and the second interlayer insulating film 4b, the second upper surface 5b may be inclined with respect to the in-plane direction of the semiconductor layer 1, and the first upper surface 5a may be parallel or substantially parallel to the in-plane direction, as shown in FIG. 7 . Even in this case, the interlayer insulating film 4 provided in the gate trench 7 has two upper surfaces that define the recess 5 of the interlayer insulating film 4 and are inclined with respect to each other, thereby improving the embedding property of the conductive material in the recess 5.

[0041] <Modification 4> Fig. 8 is a plan view showing the configuration of a semiconductor device according to Modification 4, Fig. 9 is a cross-sectional view taken along line A-A in Fig. 8, and Fig. 10 is a cross-sectional view taken along line B-B in Fig. 8. For convenience, in Fig. 9 and subsequent figures, some of the components described up to this point are omitted or simplified.

[0042] As shown in FIGS. 9 and 10 , a mesa portion 9, which is an upper portion of the semiconductor layer 1, is adjacent to a termination region 8 of the semiconductor layer 1. The termination region 8 is a region surrounding an active region in which a semiconductor cell functioning as a MOSFET is provided, and a breakdown voltage structure such as a guard ring (not shown) is provided in the termination region 8. The mesa portion 9 in FIG. 10 is a portion between the gate trench 7 and a trench 10 provided in the termination region 8. It is preferable that the depth of the gate trench 7 and the depth of the trench 10 are the same or substantially the same. With this configuration, the depth of the depletion layer in the drift region 1a can be made uniform, thereby suppressing a decrease in the breakdown voltage of the semiconductor device due to electric field concentration around the periphery of the active region.

[0043] The semiconductor device according to the fourth modification includes, in addition to the components described in the first embodiment, an insulating film 11 and a coated insulating film 13 shown in Figures 9 and 10, and a conductive portion 12 shown in Figure 10. For example, the insulating film 11, the conductive portion 12, and the coated insulating film 13 are formed in parallel with the gate insulating film 2, the gate electrode 3, and the interlayer insulating film 4. The partial electrode 3b shown in Figures 9 and 10 is a part of the gate electrode 3. Note that the partial electrode 3b does not necessarily have to be provided in the cross section of Figure 10.

[0044] The gate pad 31 in Fig. 8 is electrically connected to the partial electrode 3b via a contact hole (not shown) in the covering insulating film 13 in Fig. 9 and Fig. 10. The source pad 32 in Fig. 8 is electrically connected to the source electrode 6 in Fig. 1. The insulating film 11 in Fig. 9 and Fig. 10 is provided on the upper surface 9a of the mesa portion 9, on the side surface 9b of the mesa portion 9 on the termination region 8 side, and on the bottom surface of the trench 10.

[0045] The partial electrode 3b in Fig. 9 is provided on the mesa portion 9 of the semiconductor layer 1 via an insulating film 11. In the example of Fig. 9, the partial electrode 3b is provided on the top surface 9a, the side surface 9b, and the bottom surface of the trench 10 via the insulating film 11. The conductive portion 12 in Fig. 10 is provided on the side surface 9b and the bottom surface of the trench 10 via the insulating film 11.

[0046] The insulating cover film 13 is provided on the insulating film 11, the conductive portion 12, and the partial electrode 3b. As shown in Fig. 10, the insulating cover film 13 covers the corner 9c between the upper surface 9a and the side surface 9b of the mesa portion 9. With this configuration, the insulating cover film 13 can suppress dielectric breakdown at the corner 9c.

[0047] 11 is a cross-sectional view showing the configuration of a semiconductor device according to Modification 5, and corresponds to Fig. 10 of Modification 4. In Modification 5, gate trench 7 includes a first gate trench 7b closest to termination region 8 of semiconductor layer 1, and a second gate trench 7c separate from first gate trench 7b. Second gate trench 7c is provided in a region separated from termination region 8 by, for example, several μm to several tens of μm.

[0048] The upper end of the interlayer insulating film 4 provided in the second gate trench 7 c is lower than the upper end of the interlayer insulating film 4 provided in the first gate trench 7 b. With this configuration, the thickness of the source electrode 6 above the second gate trench 7 c can be increased, and therefore, a reduction in the electrical resistance of the source electrode 6 can be expected.

[0049] 12 is a cross-sectional view showing the configuration of a semiconductor device according to Modification 6, and corresponds to Fig. 10 of Modification 4. In Modification 6, in the configuration of Modification 4, end face 13a of coated insulating film 13 is provided on mesa portion 9 and is inclined toward termination region 8 with respect to the upward direction of semiconductor layer 1. With this configuration, the cross-sectional shape of the recess formed by combining end face 13a and recess 5 of interlayer insulating film 4 becomes smooth.

[0050] Therefore, the combined recess can also achieve the same effect as that achieved with the recess 5. That is, the embedding property of the source electrode 6 in the combined recess can be improved, and as a result, a reduction in the electrical resistance of the source electrode 6, an improvement in the uniformity of the barrier metal, and an improvement in the connection strength of the wire or lead wire can be expected.

[0051] 13 is a cross-sectional view showing the configuration of a semiconductor device according to Modification 7, and corresponds to FIG. 1 of Embodiment 1. In Modification 7, the thickness of the upper part of gate insulating film 2 is greater than the thickness of the remaining part of gate insulating film 2. With this configuration, the breakdown voltage capability of the upper part of gate insulating film 2 can be increased.

[0052] <Modification 8> Fig. 14 is a plan view showing the configuration of a semiconductor device according to Modification 8, Fig. 15 is a cross-sectional view taken along line CC in Fig. 14, and Fig. 16 is a cross-sectional view taken along line E-E in Fig. 14. Note that the configuration described so far (such as the configuration in Fig. 1) is applied to the cross-sectional configuration taken along line D-D in Fig. 14.

[0053] In the eighth modification, as shown in FIG. 15, a portion of the gate electrode 3 (i.e., the portion marked with line C-C in FIG. 14) is provided on the mesa portion 9 of the semiconductor layer 1 via a gate insulating film 2, which is an insulating film. Also, as shown in FIGS. 15 and 16, a coated insulating film 14 is provided on the gate insulating film 2. Between the cross-sectional configuration taken along line C-C in FIG. 14 (the configuration of FIG. 15) and the cross-sectional configuration taken along line D-D in FIG. 14 (e.g., the configuration of FIG. 1), the coated insulating film 14 covers the upper surface of the mesa portion 9 of the active region via the gate insulating film 2, as shown in FIG. 16. The coated insulating film 14 may be the same as the coated insulating film 13 described in the fourth modification. This configuration allows one portion of the gate pad 31 to be provided between source pads 32 as shown in FIG. 14, or three portions of the gate pad 31 to be provided between source pads 32 as shown in FIG. 17, thereby increasing the design flexibility of the semiconductor device.

[0054] In this disclosure, 'a' and 'an' mean one or more. Therefore, 'a', 'an', 'one or more', and 'at least one' can be used interchangeably.

[0055] It is possible to freely combine the various modified examples, and to modify or omit the various modified examples as appropriate.

[0056] The above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned.

[0057] 1 semiconductor layer, 1a drift region, 1c well region, 1d source region, 1g upper surface, 1h inclined surface, 2 gate insulating film, 3 gate electrode, 3a recess, 3b partial electrode, 4 interlayer insulating film, 4a first interlayer insulating film, 4b second interlayer insulating film, 5 recess, 5a first upper surface, 5b second upper surface, 7 gate trench, 7a side surface, 7b first gate trench, 7c second gate trench, 8 termination region, 9 mesa portion, 9a upper surface, 9b side surface, 9c corner portion, 11 insulating film, 13, 14 covering insulating film, 13a end surface.

Claims

1. A semiconductor device comprising: a semiconductor layer; a gate electrode provided in a gate trench provided in the semiconductor layer with a gate insulating film interposed therebetween, the gate electrode having a recess in the center of its upper portion; and an interlayer insulating film provided in the gate trench above the gate electrode, the interlayer insulating film having two or more upper surfaces that are inclined relative to each other and that define the recess in the interlayer insulating film.

2. A semiconductor device according to claim 1, wherein the two or more upper surfaces include a first upper surface and a second upper surface, and the interlayer insulating film includes a first interlayer insulating film having the first upper surface, and a second interlayer insulating film provided on at least a portion of the upper part of the first interlayer insulating film and having the second upper surface.

3. A semiconductor device according to claim 1 or 2, wherein an inclined surface is provided between the upper surface of the semiconductor layer and the side surface of the gate trench.

4. A semiconductor device according to claim 2, wherein the first upper surface is inclined with respect to an in-plane direction of the semiconductor layer.

5. A semiconductor device according to claim 2, wherein the second upper surface is inclined with respect to an in-plane direction of the semiconductor layer.

6. A semiconductor device according to any one of claims 1 to 5, further comprising a covering insulating film that covers at least the corner between the top surface of the mesa portion, which is the upper part of the semiconductor layer, and the side surface of the mesa portion on the termination region side.

7. A semiconductor device according to any one of claims 1 to 5, wherein the gate trenches include a first gate trench closest to the termination region of the semiconductor layer and a second gate trench separate from the first gate trench, and the upper end of the interlayer insulating film provided in the second gate trench is lower than the upper end of the interlayer insulating film provided in the first gate trench.

8. A semiconductor device according to claim 6, wherein an end face of the insulating coating film is provided on the mesa portion and is inclined upward toward the termination region.

9. A semiconductor device according to any one of claims 1 to 8, wherein the thickness of the upper portion of the gate insulating film is greater than the thickness of the portion of the gate insulating film other than the upper portion.

10. A semiconductor device according to any one of claims 1 to 5, wherein a portion of the gate electrode is provided on a mesa portion, which is an upper portion of the semiconductor layer, via an insulating film.

11. A semiconductor device according to any one of claims 1 to 10, wherein the semiconductor layer includes a drift region of a first conductivity type, a well region of a second conductivity type provided on the drift region, and a source region of the first conductivity type provided on the well region, and the gate trench penetrates the well region from an upper surface of the source region.

12. A semiconductor device according to any one of claims 1 to 11, wherein the upper end of the interlayer insulating film is located lower than the upper end of the semiconductor layer.

13. A method for manufacturing a semiconductor device, comprising: forming a gate electrode having a recess in its upper center through a gate insulating film in a gate trench provided in a semiconductor layer; forming an interlayer insulating film having a recess in its upper center in the gate trench above the gate electrode; and forming the interlayer insulating film having two or more upper surfaces that are inclined relative to each other and that define the recess in the interlayer insulating film.

14. A method for manufacturing a semiconductor device according to claim 13, wherein the two or more upper surfaces include a first upper surface and a second upper surface, and the interlayer insulating film includes: a first interlayer insulating film having the first upper surface; and a second interlayer insulating film having an etching rate different from that of the first interlayer insulating film, provided on at least a portion of the upper part of the first interlayer insulating film, and having the second upper surface.