Semiconductor device, inverter device, and method for manufacturing semiconductor device
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Filing Date
- 2024-04-26
- Publication Date
- 2025-10-30
AI Technical Summary
Existing semiconductor devices face challenges in reducing inductance, which affects high-speed switching performance due to the presence of components like the block electrode plate and bonding material between the element lower and top electrode plates, leading to increased inductance and reliability issues from moisture penetration.
The semiconductor device design includes an insulating substrate with exposed input terminals, where the P terminal is exposed from the top surface and the N terminal from the side surface of the package, allowing for a reduced distance between the bus bar and the input terminal, thereby minimizing inductance and ensuring insulation.
This configuration effectively reduces inductance, enhances reliability by preventing moisture penetration, and maintains uniform electromagnetic induction, enabling high-speed switching with improved semiconductor performance.
Abstract
Description
Semiconductor device, inverter device, and method of manufacturing the semiconductor device
[0001] The present disclosure relates to semiconductor devices.
[0002] Patent Document 1 discloses a semiconductor device having a structure in which a semiconductor element is mounted on a lower electrode plate. In this semiconductor device, a block electrode plate is bonded to the top surface of the semiconductor element, the top surface of the block electrode plate is exposed from the top surface of the package and bonded to the top electrode plate, and a part of the lower electrode plate is exposed from the side surface of the package as a bus bar.
[0003] International Publication No. 2011 / 092859
[0004] Inductance is an important electrical performance factor for semiconductor devices. The smaller the inductance, the more the switching loss is suppressed, and the semiconductor device can handle high-speed switching. The majority of the inductance of a semiconductor device is determined by the wiring between the capacitor. In order to reduce inductance, it is very effective to bring the round-trip current paths between the capacitor and the device closer together.
[0005] In other words, in order to reduce inductance in the semiconductor device of Patent Document 1, it is very effective to place the bus bar of the element lower electrode plate and the top electrode plate close to each other. However, between the element lower electrode plate and the top electrode plate, the semiconductor element, the block electrode plate, and the bonding material for bonding them are sandwiched. Furthermore, if the thickness of the block electrode plate and the bonding material is reduced, it becomes difficult to form a loop in the aluminum wire commonly used as control wiring, and in some cases the aluminum wire is exposed on the top surface of the package. In addition, moisture penetrates through the interface between the block electrode plate and the molding resin, reducing the reliability of the semiconductor element. Therefore, in the semiconductor device of Patent Document 1, it is difficult to reduce inductance by narrowing the gap between the element lower electrode plate and the top electrode plate.
[0006] The present disclosure has been made to solve the above problems, and aims to reduce the inductance of a semiconductor device.
[0007] The semiconductor device of the present disclosure includes an insulating substrate, a first circuit pattern provided on an upper surface of the insulating substrate, a first input terminal, a semiconductor element mounted on the first circuit pattern, a second input terminal bonded to the upper surface of the semiconductor element, and a package made of molded resin that encapsulates the insulating substrate, the first circuit pattern, and the semiconductor element. The first input terminal has a first end bonded to the first circuit pattern and a second end opposite the first end bonded to the semiconductor element that are exposed from the upper surface of the package. The second input terminal has a second end opposite the first end bonded to the semiconductor element that are exposed from a side surface of the package.
[0008] In the semiconductor device of the present disclosure, since there are no components other than the mold resin, such as a semiconductor element, between the second input terminal and the top surface of the package, when a bus bar is connected to the second end of the first input terminal, the distance between the bus bar and the second input terminal can be narrowed, thereby reducing inductance. Objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.
[0009] 1 is a plan view of a semiconductor device. 2 is a cross-sectional view of a semiconductor device. 3 is a plan view of an inverter device. 4 is a cross-sectional view of an inverter device. 5 is a circuit diagram of an inverter device. 6 is a cross-sectional view showing a manufacturing process of an inverter device. 7 is a cross-sectional view showing a manufacturing process of an inverter device. 8 is a cross-sectional view showing a manufacturing process of an inverter device. 9 is a cross-sectional view showing a manufacturing process of an inverter device. 10 is a cross-sectional view showing a manufacturing process of an inverter device. 11 is a cross-sectional view showing a manufacturing process of an inverter device. 12 is a cross-sectional view showing a manufacturing process of an inverter device. 13 is a cross-sectional view showing a manufacturing process of an inverter device. 14 is a plan view of an inverter device in which two semiconductor devices are connected in parallel for each of the U, V, and W phases.
[0010] <A. First Embodiment> <A-1. Configuration> Fig. 1 is a plan view of a semiconductor device 101 according to a first embodiment. Fig. 2 is a cross-sectional view of the semiconductor device 101.
[0011] The semiconductor device 101 includes an insulating substrate 1, first circuit patterns 2a and 2b formed on the upper surface of the insulating substrate 1, and a second circuit pattern 2c formed on the lower surface of the insulating substrate 1. A semiconductor element 4a is mounted on the first circuit pattern 2a with a bonding material 3a such as solder or silver. A semiconductor element 4b is mounted on the first circuit pattern 2b with a bonding material 3b such as solder or silver.
[0012] The first circuit pattern 2b is joined to a block-shaped P terminal 11 by a joining material 10 such as solder or silver. The P terminal 11 is also referred to as a first input terminal. In other words, the P terminal 11, which is the first input terminal, has a first end joined to the first circuit pattern 2b and a second end opposite the first end. With this configuration, when the P terminal 11 is laser-welded to a P bus bar 18 (described later), damage to the molded resin 12 due to the heat of the laser is avoided because there is no molded resin 12 below the P terminal 11.
[0013] A main circuit region such as an emitter on the top surface of the semiconductor element 4a is connected to the N terminal 6 by a bonding material 5a such as solder. The N terminal 6 is also referred to as a second input terminal. In other words, the N terminal 6, which is the second input terminal, has a first end bonded to the semiconductor element 4a and a second end opposite the first end.
[0014] Similarly, the main circuit area, such as the emitter on the top surface of semiconductor element 4b, is connected to AC terminal 7 by solder or other bonding material 5b. The signal areas on the top surfaces of semiconductor elements 4a and 4b are connected to signal terminal 9 by aluminum wire 8.
[0015] The insulating substrate 1, first circuit patterns 2a and 2b, second circuit pattern 2c, semiconductor elements 4a and 4b, N terminal 6, AC terminal 7, and signal terminal 9 are sealed with molded resin 12. That is, molded resin 12 constitutes a package that seals these components. However, a second end of N terminal 6 opposite to a first end bonded to semiconductor element 4a is exposed and extends from side surface 13 of the package. One end of AC terminal 7 is exposed and extends from side surface 14 opposite to side surface 13 of the package. Furthermore, signal terminal 9 is exposed and extends from side surfaces 13 and 14 of the package. Furthermore, a second end of P terminal 11 opposite to a first end bonded to first circuit pattern 2b is exposed and protrudes slightly from top surface 15 of the package.
[0016] Fig. 3 is a plan view of inverter device 201 according to embodiment 1. Fig. 4 is a cross-sectional view of inverter device 201.
[0017] The inverter device 201 includes at least one semiconductor device 101 and a capacitor 26. Normally, a number of inverter devices 201 equal to a natural number multiple of three are arranged to form the area enclosed by the dashed line in the circuit diagram of Fig. 5, but for simplicity, Figs. 3 and 4 show the inverter device 201 as including one semiconductor device 101.
[0018] The semiconductor device 101 is mounted on a cooler 17 via a bonding material 16 such as heat dissipation grease or solder.
[0019] Capacitor 26 includes a P electrode 20 and an N electrode 22. P electrode 20 and P terminal 11 are connected by P bus bar 18, which is a first bus bar. P bus bar 18 and P terminal 11 are connected by welding at connection portion 19. P bus bar 18 and P electrode 20 are connected by welding at connection portion 21. N terminal 6 and N electrode 22 are connected by welding at connection portion 23.
[0020] P bus bar 18 is disposed directly above N terminal 6 inside the package. Furthermore, insulating papers 24, 25 are inserted between P electrode 20 and P bus bar 18 and N electrode 22 and N terminal 6 to ensure insulation. Insulating paper 25 also extends over the package. That is, insulating papers 24, 25 are provided between the P bus bar and N terminal 6 and N electrode 22 at positions on the package and in positions that do not overlap with the package in a plan view.
[0021] The signal terminal 9 is bent upward and connected to a control board (control circuit) not shown.
[0022] 3 and 4 show a state in which the N-electrode 22 and the N-terminal 6 are directly welded. However, depending on the arrangement of the capacitor 26 and the semiconductor device 101, an N-bus bar, which is a second bus bar, may be interposed between the N-electrode 22 and the N-terminal 6. That is, the N-electrode 22 and the N-bus bar may be welded, and the N-bus bar may be welded to the N-terminal 6. In this case, the N-bus bar is placed as close as possible to the P-bus bar 18. Furthermore, insulating paper is inserted between the N-bus bar and the P-bus bar 18 to ensure insulation between them.
[0023] 5 is a circuit diagram of an inverter device 201. This inverter device 201 includes three semiconductor devices 101 that form U, V, and W poles. The AC terminal 7 of the semiconductor device 101 serves as one of the U, V, and W poles and is connected to the motor 34. A capacitor 26 and a battery 36 are connected in parallel between the P terminal 11 and the N terminal 6 of the semiconductor device 101. A signal terminal 9 of the semiconductor device 101 is connected to a control circuit 33.
[0024] Although the above description has been given of a configuration in which the P terminal 11 is exposed from the top surface 15 of the package and the N terminal 6 is exposed from the side surface 13 of the package, the P terminal 11 and the N terminal 6 may be reversed. In other words, the configuration may be such that the P terminal 11 is exposed from the side surface 13 of the package and the N terminal 6 is exposed from the top surface 15 of the package.
[0025] 6 to 13 are cross-sectional views showing the manufacturing process of the inverter device 201. The manufacturing process of the inverter device 201 will be described below with reference to FIGS.
[0026] First, the die bonding process shown in FIG. 6 is performed. In the die bonding process, a bonding material 3a is applied to the first circuit pattern 2a of the insulating substrate 1, and a semiconductor element 4a is mounted on the bonding material 3a. A bonding material 3b is applied to the first circuit pattern 2b, and a semiconductor element 4b is mounted on the bonding material 3b. A bonding material 10 is applied to the first circuit pattern 2b, and a P terminal 11 is mounted on the bonding material 10. Next, the bonding materials 3a, 3b, and 10 are melted by reflow or the like to bond the semiconductor element 4a to the first circuit pattern 2a, and the semiconductor element 4b and the P terminal 11 to the first circuit pattern 2b. Here, the bonding materials 3a, 3b, and 10 are described as solder, but the bonding materials 3a, 3b, and 10 may also be Ag or Cu. In this case, the semiconductor elements 4a and 4b and the P terminal 11 are bonded by sintering.
[0027] Next, the lead bonding process shown in FIG. 7 is performed. In the lead bonding process, bonding materials 5a and 5b are mounted on the surface bonding portions of the semiconductor elements 4a and 4b, respectively, and a lead frame is mounted on top of them. The bonding materials 5a and 5b are then melted by reflow or the like to bond the lead frame to the semiconductor elements 4a and 4b. At this point, the lead frame is an integrated unit connected to the frame. In the lead processing process described below, the lead frame is separated from the frame to become independent N terminals 6, AC terminals 7, and signal terminals 9. However, for simplicity of explanation, FIG. 7 shows the N terminals 6, AC terminals 7, and signal terminals 9 separated from the frame.
[0028] Next, the wire bonding process is performed as shown in Fig. 8. In the wire bonding process, the wire pads of the semiconductor elements 4a and 4b are connected to the signal terminals 9 by ultrasonic bonding with aluminum wires 8 having a diameter of about 100 µm to 400 µm.
[0029] Next, the molding process shown in FIG. 9 is performed. The semiconductor device 101, which has undergone the wire bonding process, is placed in the lower mold of the mold together with a resin tablet, which will be the material for the mold resin 12. Next, the upper mold is closed, and the resin tablet is gelled as the mold resin 12 at a high temperature of approximately 180°C. Pressure is applied and the resin is poured into the cavity (cavity) within the mold through the runner and gate. The gelled mold resin 12 hardens again at high temperature and is molded into the shape of the cavity, i.e., the package. The package is then removed from the mold. Note that in this process, the second end of the P terminal 11 does not contact the upper mold of the mold, so pressure is not applied to the insulating substrate 1 through the P terminal 11, preventing cracking of the insulating substrate 1. The mold resin 12 is also formed to cover the second end of the P terminal 11. In other words, the P terminal 11 is not exposed from the package.
[0030] Next, the P terminal exposing step shown in FIG. 10 is performed. Specifically, the molded resin 12 on and around the upper surface of the P terminal 11 is removed by blasting, liquid honing, laser, or the like, thereby exposing the upper surface of the P terminal 11 from the upper surface 15 of the package. While the molded resin 12 can be removed by cutting, this is not preferable because stress or vibration to the P terminal 11 during cutting may affect the bond between the P terminal 11 and the first circuit pattern 2b and the adhesion between the P terminal 11 and the molded resin 12. As described above, removing the molded resin 12 on and around the upper surface of the P terminal 11 by blasting, liquid honing, laser, or the like can prevent the occurrence of gaps between the first input terminal and the molded resin 12 or cracks in the insulating substrate 1.
[0031] Next, the lead frame is cut into a desired shape and bent, thereby separating the N terminal 6, the AC terminal 7, and the signal terminal 9. In this way, the semiconductor device 101 is completed.
[0032] 11 , the semiconductor device 101 is mounted on the cooler 17 via a bonding material 16 such as solder or thermal grease. When solder is used as the bonding material 16, a difference in melting point must be provided between the solder (bonding material 16) and the solder inside the package (bonding materials 3a, 3b, 5a, 5b, 10) so that the solder does not melt when heated to melt the solder. When thermal grease is used as the bonding material, a separate means is required to press and fix the semiconductor device 101 against the cooler 17.
[0033] 12, the N-electrode 22 of the capacitor 26 is placed on the N-terminal 6 of the semiconductor device 101, and they are joined by laser welding or the like at the connection portion 23. Insulating paper 25 is also placed between the N-electrode 22 and the P-electrode 20.
[0034] 13 , insulating paper 24 is placed on N electrode 22, extending from insulating paper 25 onto the package, and P bus bar 18 is placed on top of that. P bus bar 18 is then connected to P electrode 20 at connection portion 21 and to P terminal 11 at connection portion 19 by laser welding or the like. Note that protrusions or grooves for positioning insulating paper 24 or P bus bar 18 may be provided on top surface 15 of the package.
[0035] Furthermore, the AC terminals 7 of the semiconductor device 101 are joined by laser welding or the like to AC bus bars that output to a motor or the like (not shown), thus completing the inverter device 201. In three-phase AC, the AC terminals 7 serve as U, V, and W poles.
[0036] The semiconductor device in Patent Document 1 has a structure in which cooling tubes are pressed against the top and bottom of the semiconductor element to cool it from both sides. Therefore, the block electrode plate exposed on the top surface of the package had to be directly bonded to the semiconductor element. Therefore, the block electrode plate was coated with polyamide resin or the like before transfer molding to improve adhesion to the molding resin.
[0037] <A-3. Effects> Inductance is an important electrical performance factor for semiconductor devices. The smaller the inductance, the more the switching loss is suppressed, and the semiconductor device can handle high-speed switching. The majority of the inductance of a semiconductor device is determined by the wiring between the device and the capacitor. In order to reduce inductance, it is very effective to bring the round-trip current paths between the device and the capacitor closer together.
[0038] That is, in order to reduce the inductance of the semiconductor device of Patent Document 1, it is very effective to bring the bus bar of the element lower electrode plate and the upper electrode plate closer together. However, the semiconductor element, the block electrode plate, and the bonding material for bonding them are sandwiched between the element lower electrode plate and the upper electrode plate. The most effective way to narrow the gap between the element lower electrode plate and the upper electrode plate is to make the block electrode plate thinner. However, if the block electrode plate is made thinner, even if the block electrode plate is coated with a polyamide resin, moisture from the outside can easily penetrate through the interface between the block electrode plate and the molding resin, thereby reducing the reliability of the semiconductor device.
[0039] Furthermore, if the top surface of the package is ground to expose the block electrode plate after transfer molding, the stress caused by the machining process is likely to damage the adhesion between the block electrode plate and the molding resin or the joint between the block electrode plate and the semiconductor element. This concern becomes more pronounced as the block electrode plate becomes thinner. Therefore, it is difficult to reduce inductance using the structure described in Patent Document 1.
[0040] In contrast, a semiconductor device 101 according to this embodiment includes an insulating substrate 1, first circuit patterns 2a and 2b provided on the upper surface of the insulating substrate 1, a P terminal 11 serving as a first input terminal, semiconductor elements 4a and 4b mounted on the first circuit patterns 2a and 2b, an N terminal 6 serving as a second input terminal bonded to the upper surface of the semiconductor element 4a, and a package made of molded resin 12 that seals the insulating substrate 1, the first circuit patterns 2a and 2b, and the semiconductor elements 4a and 4b. A second end of the P terminal 11 opposite to a first end bonded to the first circuit pattern 2b is exposed from an upper surface 15 of the package, and a second end of the N terminal 6 opposite to a first end bonded to the semiconductor element 4a is exposed from a side surface 13 of the package. With the above configuration, the semiconductor device 101 can reduce inductance by narrowing the wiring spacing between the N terminal 6 and a P bus bar 18, which is a round-trip path for current. Since the P bus bar 18 is joined to the upper surface of the P terminal 11, the distance between the P bus bar 18 and the N terminal 6 can be narrowed by bringing the height of the P terminal 11 closer to the height of the upper surface of the N terminal 6.
[0041] Furthermore, since the P terminal 11 exposed on the top surface 15 of the package is not directly bonded to the semiconductor element 4b, even if peeling occurs between the P terminal 11 and the molded resin 12, the path for moisture penetration is long, and a decrease in reliability is suppressed.
[0042] Furthermore, when removing the molding resin 12 covering the top surface of the P terminal 11, a laser or a blast is used to prevent stress from being applied due to machining.
[0043] The smaller the gap between the P bus bar 18 and the N terminal 6, the more effective it is in reducing inductance, but at the same time, insulation between them is also necessary. If the molded resin 12 on the N terminal 6 is too thin, it will be difficult for the molded resin 12 to wrap around the N terminal 6 during transfer molding, resulting in holes and cracks, making it difficult to ensure insulation. Therefore, the thickness of the molded resin 12 on the N terminal 6 is preferably between 0.5 mm and 1.0 mm. However, even if holes or cracks occur in the molded resin 12 on the N terminal 6, these can be easily visually confirmed from the surface, preventing poor insulation.
[0044] FIG. 14 is a plan view of an inverter device 201 in which two semiconductor devices 101 are arranged and wired in parallel for each of the U, V, and W poles. Some semiconductor devices with conventional structures reduce cost by configuring the signal terminals, N terminals, P terminals, and AC terminals all on a single lead frame. In this case, the P and N terminals are exposed side-by-side from the side of the resin package. Assume that two such semiconductor devices are arranged and wired in parallel for each of the U, V, and W poles, as in FIG. 13 . For two semiconductor devices that switch simultaneously, the N and P terminals of the first semiconductor device are represented as N1 and P1, and the N and P terminals of the second semiconductor device are represented as N2 and P2. The input terminals connected to the capacitors are arranged in the following order: N1, P1, N2, P2. As a result, P1, sandwiched between N1 and N2, and N2, sandwiched between P1 and P2, have smaller inductance than the N1 and P2 terminals at both ends due to electromagnetic induction, which may result in switching timing errors.
[0045] However, in the semiconductor device 101 of this embodiment, the N terminal 6 is exposed from the side surface 13 of the package and the P terminal 11 is exposed from the top surface 15 of the package, so even if two semiconductor devices 101 that switch simultaneously are placed side by side, P1 and P2, and N1 and N2 will have equal electromagnetic induction. In other words, the mutual inductance is uniform, so that imbalance in the switching speed of each semiconductor element 4 a, 4 b is suppressed.
[0046] The semiconductor elements 4a and 4b may be made of SiC. The technique of the present disclosure that makes the mutual inductance uniform is particularly effective for semiconductor elements made of SiC that are used for high-speed switching.
[0047] Furthermore, in order to pass a large current, P terminal 11 and N terminal 6 require a certain degree of cross-sectional area. Therefore, if P terminal 11 and N terminal 6 were exposed side by side on the side surface of the package, the width of the package would increase. However, in semiconductor device 101 of this embodiment, of P terminal 11 and N terminal 6, only N terminal 6 is exposed on the side surface of the package, so the package can be made smaller.
[0048] The above-described embodiment can be modified or omitted as appropriate. The above description is an example in every respect. It is understood that countless variations not illustrated can be envisioned.
[0049] 1 Insulating substrate, 2a, 2b First circuit pattern, 2c Second circuit pattern, 3a, 3b, 5a, 5b, 10, 16 Bonding material, 4a, 4b Semiconductor element, 6 N terminal, 7 AC terminal, 8 Aluminum wire, 9 Signal terminal, 11 P terminal, 12 Molded resin, 13, 14 Side of package, 15 Top surface of package, 17 Cooler, 18 P bus bar, 19, 21, 23 Connection portion, 20 P electrode, 22 N electrode, 24, 25 Insulating paper, 26 Capacitor, 33 Control circuit, 34 Motor, 36 Battery, 101 Semiconductor device, 201 Inverter device.
Claims
1. A semiconductor device comprising: an insulating substrate; a first circuit pattern provided on an upper surface of the insulating substrate; a first input terminal; a semiconductor element mounted on the first circuit pattern; a second input terminal bonded to an upper surface of the semiconductor element; and a package made of molded resin that encapsulates the insulating substrate, the first circuit pattern, and the semiconductor element, wherein a second end of the first input terminal opposite to a first end bonded to the first circuit pattern is exposed from the upper surface of the package, and a second end of the second input terminal opposite to a first end bonded to the semiconductor element is exposed from a side surface of the package.
2. The semiconductor device according to claim 1, wherein the first input terminal is block-shaped and is directly mounted on the first circuit pattern.
3. The semiconductor device according to claim 1, wherein the second end of the first input terminal protrudes from the top surface of the package.
4. An inverter device comprising: at least one semiconductor device according to claim 1; a capacitor; a first bus bar connecting said capacitor to said first input terminal; and a second bus bar connecting said capacitor to said second input terminal, wherein said first bus bar is disposed directly above said second input terminal on said package.
5. The inverter device according to claim 4, further comprising insulating paper provided between the first bus bar and the second bus bar on the package and at a position not overlapping with the package in a plan view.
6. The inverter device according to claim 4, wherein the at least one semiconductor device is a plurality of semiconductor devices arranged in parallel.
7. The inverter device according to claim 4, wherein the semiconductor element is made of SiC.
8. A method for manufacturing a semiconductor device, comprising: mounting a semiconductor element on a first circuit pattern provided on the upper surface of an insulating substrate; bonding a first input terminal to the first circuit pattern; bonding a second input terminal to the upper surface of the semiconductor element; molding a package consisting of a molded resin that encapsulates the insulating substrate, the first circuit pattern, the semiconductor element, the first input terminal, and the second input terminal; exposing a second end of the first input terminal opposite to a first end bonded to the upper surface of the semiconductor element from the upper surface of the package; and exposing a second end of the second input terminal opposite to the first end bonded to the upper surface of the semiconductor element from a side surface of the package.
9. The method for manufacturing a semiconductor device according to claim 8, wherein the package is molded to cover the second end of the first input terminal by molding in such a way that the second end of the first input terminal does not come into contact with a mold, and then the molding resin covering the second end of the first input terminal is removed to expose the second end of the first input terminal from the top surface of the package.