Semiconductor device manufacturing method and wiring board

Abstract

An example of a method for manufacturing a semiconductor device using a bridge die is disclosed. Copper posts 22 are provided on a carrier substrate 20, and a semiconductor die 40 serving as a bridge die is attached between the copper posts 22. The semiconductor die 40 is attached by a resin layer 43 that covers the terminal electrodes 42 so that the terminal electrodes 42 face the carrier substrate 20 (face down). The resin layer 43 is hardened to form an encapsulant layer 23. A wiring layer 24 is formed on one side of the encapsulant layer 23, and the carrier substrate 20 is separated to form a wiring layer 28 on the other side. The active dies 50 and 55 are attached to this interposer P to obtain a semiconductor device 1. According to this manufacturing method, the bridge die is attached face down, so that reliable attachment can be achieved. The expensive active die is attached last, so that manufacturing costs can be reduced. For the resin layer 43, NCF or DAF is preferably used.

Description

[Technical field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a wiring board. [Background technology]

[0002] In recent years, with the rapid advancement of electronic devices such as AI / HPC, the size and density of semiconductor packages have increased dramatically. The package structure is not limited to surface mounting with high density, but the package structure and mounting process are becoming more complex and diverse, such as inorganic (silicon) or organic interposer (Bridge die / RDL) technology, 2.xD mounting using it, and 3D mounting (HBM / Chiplet) technology using TSV. For example, Resonac Inc., with its main base of operations at the Packaging Solutions Center, is developing next-generation semiconductor packaging process technology from the customer's (semiconductor manufacturer's) perspective, combining mounting processes and materials.

[0003] As a technique in the field of semiconductor packages, Patent Document 1 discloses a method for manufacturing a semiconductor device in which a semiconductor die is mounted face-up on a carrier and sealed, a wiring layer is formed on the sealing layer, and another semiconductor die is mounted on the wiring layer. Patent Document 2 discloses another method for manufacturing a semiconductor device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2021 / 0098421 [Patent Document 2] US Patent Application Publication No. 2022 / 0093526 Summary of the Invention [Problem to be solved by the invention]

[0005] In the manufacturing method of a semiconductor device described in Patent Document 1, a conceivable way to mount a semiconductor die on a support is to use a collet to suck up the terminal electrode side of the semiconductor die, lift it up, and then mount the semiconductor die face-up on the support. In this case, the outer periphery of the semiconductor die is sucked up by the collet so as to avoid the internal region where the terminal electrodes are provided. However, if mounting is performed in such a sucked state, the mounting of the semiconductor die may not be reliable.

[0006] An object of the present disclosure is to provide a method for manufacturing a semiconductor device that can reliably attach a semiconductor member (semiconductor die). [Means for solving the problem]

[0007] [1] The present disclosure relates to a method for manufacturing a semiconductor device, comprising the steps of: providing a conductive columnar member having a first end and an opposite second end on a first support, the first end being located on the first support side; attaching a semiconductor member including a semiconductor substrate having a first surface and an opposite second surface, a terminal electrode provided on the first surface side of the semiconductor substrate, and a resin layer provided on the first surface side so as to cover the terminal electrode, to the first support so that the first surface faces the support; forming a first sealing material layer on the first support to seal the columnar member and the semiconductor member; forming a first wiring layer on the first sealing material layer, the first wiring layer being electrically connected to at least the columnar member; separating the first support from the first sealing material layer; grinding at least the resin layer so as to expose the tip of the terminal electrode; and forming a second wiring layer on the first sealing material layer, the second wiring layer being electrically connected to at least one of the terminal electrode and the columnar member, on the first sealing material layer where the terminal electrode is exposed.

[0008] In this method for manufacturing a semiconductor device, the semiconductor member is attached to the first support so that the first surface on which the terminal electrodes are provided faces the support. In other words, the semiconductor member is attached face down. Therefore, when the semiconductor member is sucked with a collet or the like for bonding, it is not necessary to suck the terminal electrode side, and the semiconductor member can be attached reliably. When picking up the semiconductor member before bonding, the terminal electrode side may be sucked with a collet once (and then the semiconductor member is turned over for bonding), but in this case, since the terminal electrodes are covered with a resin layer, it is not necessary to suck the outer periphery with a collet, and the semiconductor member can be picked up reliably.

[0009] In addition, in this method for manufacturing a semiconductor device, the semiconductor chip connected to the semiconductor member can be attached at the end of the process (for example, after the first wiring layer and the second wiring layer are formed), so if a defect occurs during the process, the semiconductor chip, which is an expensive active die, can be prevented from being attached. This reduces the overall manufacturing cost.

[0010] [2] The method for producing a semiconductor device according to [1] above preferably further comprises a step of curing the resin layer containing the curable resin composition after attaching the semiconductor member to the first support and before forming the first encapsulant layer. In this case, it is possible to prevent the semiconductor member from being misaligned when forming (encapsulating) the first encapsulant layer.

[0011] [3] In the method for manufacturing a semiconductor device according to the above [1] or [2], the resin layer formed when the semiconductor member is attached to the first support may be a semi-cured or uncured curable resin composition. In this case, the semiconductor member can be reliably attached to the first support at a predetermined position.

[0012] [4] In any one of the methods for manufacturing a semiconductor device according to the above [1] to [3], the resin layer preferably has a visible light transmittance of 30% or more. In this case, the positions of the terminal electrodes of the semiconductor member can be confirmed before attachment, and the semiconductor member can be attached to a predetermined position on the first support with high accuracy.

[0013] [5] In any one of the above methods for manufacturing a semiconductor device [1] to [4], in the step of attaching the semiconductor member, it is preferable to determine the positions of the terminal electrodes through the resin layer, and attach the semiconductor member to a predetermined position on the first support based on the result of the determination. In this case, the positions of the terminal electrodes of the semiconductor member can be directly or indirectly confirmed, and the semiconductor member can be attached to the predetermined position on the first support with high accuracy.

[0014] [6] In any one of the methods for manufacturing a semiconductor device according to the above [1] to [5], the resin layer may contain an inorganic filler. In this case, the hardness (elastic modulus, etc.) of the resin layer can be improved, and bending or cracking of the semiconductor member can be suppressed. Furthermore, the inclusion of an inorganic filler can suppress warping of the semiconductor member including the resin layer.

[0015] [7] In the method for producing a semiconductor device according to [6] above, the content of the inorganic filler may be 30 mass% or more based on the total amount of solids contained in the resin layer. In this case, warping of the semiconductor member can be more reliably suppressed.

[0016] [8] In the manufacturing method of a semiconductor device according to [6] or [7] above, the inorganic filler may have an average particle size of 20 μm or less. In this case, even if the terminal electrodes and their pitch of the semiconductor member are fine, the resin and filler can be inserted (filled) between the terminal electrodes, and the terminal electrodes can be reliably covered with the resin layer. In addition, the cured resin layer can be prevented from warping.

[0017] [9] In any one of the methods for manufacturing a semiconductor device according to [1] to [8] above, the elastic modulus of the resin layer at room temperature when cured may be 10 MPa or more. In this case, bending and cracking of the semiconductor member can be further suppressed. Furthermore, when the cured resin layer is polished to expose the head of the terminal electrode, the polishing operation can be easily performed. The elastic modulus here means Young's modulus. Room temperature means 25°C. The cured resin layer may not be completely cured, and may be hard enough to be polished in the polishing operation.

[0018]

[10] In any one of the methods for manufacturing a semiconductor device according to the above [1] to [9], the resin layer may be formed by laminating a non-conductive adhesive film (NCF) or a die attach film (DAF). In this case, it is preferable that the resin layer is formed by laminating an NCF.

[0019]

[11] In any one of the above methods for manufacturing a semiconductor device [1] to

[10] , the thickness of the resin layer may be between 100% and 150% of the height of the terminal electrodes. In this case, the thickness of the resin layer and the height of the terminal electrodes are approximately equal, so that the semiconductor member can be lifted and attached more reliably.

[0020]

[12] In any of the above methods for manufacturing a semiconductor device [1] to

[11] , the resin layer may be formed by laminating a resin film, and the thickness of the resin film before lamination may be between 75% and 150% of the height of the terminal electrodes. In this case, when the resin film is laminated, the thickness of the resin layer and the height of the terminal electrodes become approximately equal, so that the semiconductor member can be lifted and attached more reliably.

[0021]

[13] The method for manufacturing a semiconductor device according to any one of [1] to

[12] above may further include a step of grinding the first sealing material layer after forming the first sealing material layer and before forming the first wiring layer so as to expose the second end of the columnar member. In this case, the first wiring layer connected to the columnar member can be formed more reliably.

[0022]

[14] Any of the above methods for manufacturing a semiconductor device [1] to

[13] may further include a step of providing a second support on the first wiring layer after forming the first wiring layer, and may separate the first support from the first encapsulant layer after providing the second support. In this case, various manufacturing steps can be performed in a state in which the first encapsulant layer is supported by any of the supports, so that a semiconductor device using a thin first encapsulant layer can be manufactured. Furthermore, even if the first encapsulant layer is thin, warping or cracking can be prevented.

[0023]

[15] The method for manufacturing a semiconductor device according to

[14] above may further include a step of providing connection bumps on the surface of the first wiring layer opposite to the first encapsulant layer, and the step of providing the connection bumps may be performed before providing the second support on the first wiring layer or after separating the second support from the first wiring layer. When the connection bumps are formed before providing the second support on the first wiring layer, an active die such as a logic die can be attached in the last step, so that it is not necessary to attach an expensive active die when the wiring board is defective, and the manufacturing cost can be reduced. In addition, when the connection bumps are formed after separating the second support from the first wiring layer, many steps can be performed on the wiring board without the connection bumps, so that various steps such as forming the second wiring layer can be easily performed, and the manufacturing efficiency can be improved.

[0024]

[16] In any one of the methods for manufacturing a semiconductor device according to the above [1] to

[15] , the semiconductor member may have a fine wiring layer between the first surface of the semiconductor substrate and the terminal electrode. In this case, the fine circuit in the semiconductor substrate and the terminal electrode can be reliably connected to each other.

[0025]

[17] In any one of the above methods for manufacturing a semiconductor device [1] to

[16] , the semiconductor member may have an internal electrode extending in a thickness direction of the semiconductor substrate, a first end of the internal electrode may be connected to the second wiring layer via a terminal electrode, and a second end of the internal electrode may be connected to the first wiring layer. In this case, a through electrode such as a TSV (Through Silicon Via) can be provided in the semiconductor substrate, improving the degree of freedom in wiring design. In addition, miniaturization of wiring can be promoted.

[0026]

[18] It is preferable that the method for manufacturing a semiconductor device according to any one of the above [1] to

[17] further comprises the step of attaching at least one semiconductor chip to the surface of the second wiring layer opposite to the first sealing material layer.

[0027]

[19] In the method for manufacturing a semiconductor device according to

[18] above, in the step of attaching the semiconductor chips, it is preferable to attach a first semiconductor chip and a second semiconductor chip as at least one semiconductor chip to the second wiring layer, and it is preferable that the first semiconductor chip and the second semiconductor chip are electrically connected by a semiconductor member. In this case, the semiconductor member can be used as a so-called bridge die.

[0028]

[20] The method for manufacturing a semiconductor device according to

[18] or

[19] above may further include a step of forming a second encapsulant layer for encapsulating at least one semiconductor chip. In this case, the semiconductor chip is reliably protected by the encapsulant layer.

[0029]

[21] In any one of the above methods for manufacturing a semiconductor device [1] to

[20] , at least one of the first connection portion between the columnar member and the first wiring layer and the second connection portion between the columnar member and the second wiring layer is preferably connected without solder. In this case, it is not necessary to consider the diffusion of solder, and therefore the design of the semiconductor device can be simplified accordingly.

[0030]

[22] In any one of the above methods for manufacturing a semiconductor device [1] to

[21] , the columnar member may be provided in a substrate having a first surface and a second surface on the opposite side. In the step of providing the columnar member, a connection member including the columnar member, the substrate, another terminal electrode provided on the first surface side of the substrate, and another resin layer provided on the first surface side of the substrate so as to cover the other terminal electrode may be attached to the first support with the first surface facing the support, thereby providing the columnar member on the first support. In this case, the step of providing the columnar member can be simplified. Also, the attachment of the semiconductor member and the connection member can be performed in parallel, thereby improving manufacturing efficiency.

[0031]

[23] In the method for manufacturing a semiconductor device according to

[22] above, in the step of forming the first encapsulating layer, the connecting member may be encapsulated together with the semiconductor member, in the step of grinding, the resin layer and the other resin layer may be ground so that the other terminal electrode is exposed together with the terminal electrode, and in the step of forming the second wiring layer, the second wiring layer may be formed so that the second wiring layer is electrically connected to each of the terminal electrode and the other terminal electrode. In this case, even when the connecting member is used, the semiconductor device can be manufactured in the same way as when the columnar member is directly formed.

[0032]

[24] The method for manufacturing a semiconductor device according to

[22] or

[23] above may further include a step of grinding a part of the semiconductor substrate and a part of the substrate together with the first encapsulant layer so as to expose the second ends of the columnar members, after forming the first encapsulant layer and before forming the first wiring layer. In this case, even when the connecting member is used, the semiconductor device can be manufactured in the same manner as when the columnar members are directly formed.

[0033]

[25] In another aspect, the present disclosure relates to a wiring board used in manufacturing a semiconductor device. The wiring board includes a semiconductor member, a conductive columnar member having a first end and a second end opposite to the semiconductor member and disposed adjacent to the semiconductor member, a first encapsulant layer for encapsulating the semiconductor member and the columnar member, a first wiring layer disposed on the first encapsulant layer and electrically connected to at least the columnar member, and a second wiring layer disposed on the surface of the first encapsulant layer opposite to the first wiring layer and electrically connected to at least one of the terminal electrode and the columnar member. The semiconductor member of the wiring board includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a terminal electrode disposed on the first surface side of the semiconductor substrate, and a resin layer disposed on the first surface side so as to expose the tip of the terminal electrode and cover the other part of the terminal electrode. Such a wiring board can be used as an interposer for mounting a semiconductor chip to manufacture a semiconductor device.

[0034]

[26] In yet another aspect, the present disclosure relates to a method for manufacturing a semiconductor device. The method includes the steps of providing the wiring board of

[25] and mounting a first semiconductor chip and a second semiconductor chip on a second wiring layer of the wiring board. In the mounting step, the first semiconductor chip is electrically connected to the second semiconductor chip by a semiconductor member. In this case, a semiconductor device in which the semiconductor member functions as a bridge die can be easily manufactured.

[0035]

[27] In the method for manufacturing a semiconductor device according to

[26] above, the first semiconductor chip may include a logic chip, and the second semiconductor chip may include a memory chip. In this case, the logic chip can be easily connected to the memory chip via a bridge die. Effect of the Invention

[0036] According to the present disclosure, it is possible to provide a method for manufacturing a semiconductor device that allows for reliable attachment of a semiconductor member. [Brief description of the drawings]

[0037] [Figure 1]FIG. 1 is a cross-sectional view showing an example of a cross-sectional configuration of a semiconductor device according to a first embodiment. [Diagram 2] 2(a) to 2(d) are cross-sectional views illustrating a method for manufacturing the semiconductor device shown in FIG. [Diagram 3] 3(a) and 3(b) are enlarged cross-sectional views showing the semiconductor member to be attached in FIG. 2(c). [Figure 4] 4(a) to 4(d) are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 1, illustrating steps carried out after the step shown in FIG. 2(d). [Diagram 5] 5(a) to 5(c) are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 1, illustrating a step performed after the step shown in FIG. 4(d). [Figure 6] 6(a) to 6(c) are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 1, illustrating steps carried out after the step shown in FIG. 5(c). [Figure 7] FIG. 7 is a cross-sectional view showing an example of a cross-sectional configuration of the semiconductor device according to the second embodiment. [Figure 8] 8(a) to 8(d) are cross-sectional views illustrating a method for manufacturing the semiconductor device shown in FIG. [Figure 9] 9(a) to 9(c) are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 7, illustrating steps carried out after the step shown in FIG. 8(d). [Figure 10] 10(a) to 10(c) are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 7, illustrating steps carried out after the step shown in FIG. 9(c). [Figure 11] 11(a) to 11(c) are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 7, illustrating steps carried out after the step shown in FIG. 10(c). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same or corresponding parts are given the same reference numerals, and duplicated descriptions will be omitted. Furthermore, unless otherwise specified, the positional relationships such as up, down, left, and right are based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios of the drawings are not limited to the illustrated ratios.

[0039] In this specification, the term "layer" includes a structure having a shape formed on the entire surface as well as a structure having a shape formed on a part of the surface when observed in a plan view. In this specification, the term "process" includes not only an independent process, but also a process that cannot be clearly distinguished from other processes, as long as the intended effect of the process is achieved. In this specification, "(meth)acrylic" means acrylic or its corresponding methacrylic. In addition, when a plurality of substances corresponding to each component are present in the composition, the content of each component in the composition means the total amount of the plurality of substances present in the composition, unless otherwise specified.

[0040] In this specification, a numerical range indicated using "~" indicates a range including the numerical values ​​before and after "~" as the minimum and maximum values, respectively. In a numerical range described in stages in this specification, the upper limit or lower limit of a numerical range of a certain stage may be replaced with the upper limit or lower limit of a numerical range of another stage. In a numerical range described in this specification, the upper limit or lower limit of the numerical range may be replaced with a value shown in an example.

[0041] [First embodiment] FIG. 1 is a diagram showing an example of a semiconductor device manufactured by the manufacturing method according to the first embodiment. As shown in FIG. 1, the semiconductor device 1 includes semiconductor dies 2 and 3, semiconductor dies 4 and 5, wiring layers 6 and 7, encapsulant layers 8 and 9, connection electrodes 10, connection bumps 11, and underfills 12 and 13. Such a semiconductor device 1 is mounted on a substrate M. The substrate M is, for example, a motherboard. A structure S in which the semiconductor device 1 is further mounted on the substrate M may also be referred to as a semiconductor device. In the semiconductor device 1, a wiring layer 6, an encapsulant layer 8 that encapsulates the semiconductor dies 4 and 5 and the connection electrodes 10, a wiring layer 7 electrically connected to the semiconductor dies 4 and 5 and the connection electrodes 10, and an encapsulant layer 9 that encapsulates the semiconductor dies 2 and 3 are sequentially stacked on the substrate M.

[0042] The semiconductor dies 2 and 3 (first semiconductor chip, second semiconductor chip) may be, for example, semiconductor chips such as an LSI chip (logic chip), a CMOS sensor, or a memory chip, and may be so-called active dies. Each of the semiconductor dies 2 and 3 has terminal electrodes 2a and 3a and fine wiring layers 2b and 3b provided on the terminal electrodes 2a and 3a side. In the semiconductor device 1, the semiconductor dies 2 and 3 are mounted so that the terminal electrodes 2a and 3a face the semiconductor dies 4 and 5 and the wiring layer 7. An underfill material is introduced into the connection area of ​​the terminal electrodes 2a and 3a and hardens to form an underfill 13. In addition, the semiconductor dies 2 and 3 are sealed by a sealing material constituting the sealing material layer 9, and each surface is exposed to the outside.

[0043] The semiconductor dies 4 and 5 (semiconductor members) may be, for example, a bridge die or a silicon capacitor, and may be so-called passive dies. The semiconductor dies 4 and 5 may be active dies. The semiconductor dies 4 and 5 are very thin semiconductor dies, and may have a thickness of, for example, 100 μm or less, and may have a thickness of 50 μm or less. Each of the semiconductor dies 4 and 5 has a terminal electrode 4a, 5a and a fine wiring layer 4b, 5b provided on the terminal electrode 4a, 5a side. The terminal electrodes 4a, 5a of the semiconductor dies 4 and 5 and their pitch are also becoming smaller, and the diameter of each of the terminal electrodes 4a and 5a is, for example, 10 μm to 50 μm, and the height of each of the terminal electrodes 4a and 5a is, for example, 20 μm to 50 μm. The terminal pitch (separation distance) between the terminal electrodes 4a and the terminal pitch (separation distance) between the terminal electrodes 5a is, for example, 5 μm to 20 μm. However, the size and pitch of the terminal electrodes 4a and 5a are not limited to those described above.

[0044] In the semiconductor device 1, the semiconductor dies 4 and 5 are disposed so that the terminal electrodes 4a and 5a face the semiconductor dies 2 and 3. As an example, the semiconductor die 4 is a bridge die, and connects the semiconductor die 2 and the semiconductor die 3 to each other via the wiring portion 7a of the wiring layer 7 (second wiring layer). The semiconductor die 5 is connected to the semiconductor die 3 via the wiring portion 7a of the wiring layer 7, and is not connected to the semiconductor die 2. When the semiconductor dies 4 and 5 further have through electrodes 4c and 5c, the semiconductor dies 4 and 5 may connect the semiconductor dies 2 and 3 to the wiring portion 6a of the wiring layer 6 (first wiring layer) via the through electrodes 4c and 5c.

[0045] The wiring layers 6 and 7 are rewiring layers and have wiring portions 6a and 7a and insulating portions 6b and 7b covering the wiring portions 6a and 7a, respectively. The wiring layers 6 and 7 may have the same wiring pitch and wiring width, but it is preferable that the wiring pitch and wiring width of the wiring layer 7 are narrower than the wiring pitch and wiring width of the wiring layer 6. The wiring portion 6a of the wiring layer 6 is connected to a connection bump 11. The connection bump 11 is, for example, a solder bump. An underfill material is introduced into the connection region of the connection bump 11 and hardens to form an underfill 12.

[0046] The encapsulant layers 8 and 9 are layers that encapsulate the semiconductor dies with an encapsulant, and are encapsulated with an encapsulant containing, for example, epoxy resin, etc. The encapsulant layer 8 encapsulates the semiconductor dies 4 and 5. The encapsulant layer 9 encapsulates the semiconductor dies 2 and 3.

[0047] The connection electrodes 10 are conductive columnar members that connect the wiring layers 6, 7 (wiring portions 6a, 7a) and are so-called posts or pillars. The connection electrodes 10 are made of, for example, copper. The connection electrodes 10 are provided adjacent to the semiconductor dies 4, 5. The height of the connection electrodes 10 is approximately the same as the thickness of the semiconductor dies 4, 5. The diameter of the connection electrodes 10 is, for example, 10 μm to 50 μm. The connection electrodes 10 are encapsulated together with the semiconductor dies 4, 5 by an encapsulant and are located in the encapsulant layers 8, 9. The semiconductor dies 4, 5 are disposed between the connection electrodes 10.

[0048] In the semiconductor device 1, the semiconductor dies 4 and 5 are provided in the encapsulant layer 8 in a face-up state. The semiconductor dies 4 and 5 are provided with a resin layer (see resin layers 33 and 43 in FIG. 3) formed to cover the terminal electrodes 4a and 5a. The tips of the terminal electrodes 4a and 5a are exposed to the outside of the resin layer and connected to the wiring portion 7a, while the other parts of the terminal electrodes 4a and 5a are covered by the resin layer. Although the details will be described later, such a resin layer is made of a resin film containing a thermosetting adhesive such as a non-conductive film (NCF) or a die attach film (DAF), or a liquid thermosetting adhesive, and is a cured resin layer obtained by curing any of the adhesive layers. That is, the material constituting the resin layer is in a semi-cured (B stage) state and then in a fully cured (C stage) state by a subsequent curing process. The curing method may be either heat or light. However, the resin layer of the semiconductor dies 4 and 5 may be in a cured state that has not yet reached a fully cured state, as long as it does not interfere with the semiconductor device 1. The curable resin composition constituting the resin layers of the semiconductor dies 4 and 5 includes a thermosetting resin. The curable resin composition may further include a curing agent, a curing accelerator, and an inorganic filler.

[0049] Next, an example of a method for manufacturing the semiconductor device 1 will be described with reference to Fig. 2 to Fig. 6. Fig. 2 and Fig. 4 to Fig. 6 are cross-sectional views sequentially illustrating the method for manufacturing the above-mentioned semiconductor device 1. Fig. 3 is an enlarged cross-sectional view of a semiconductor member.

[0050] In this method for manufacturing a semiconductor device, first, a temporary fixing layer 21 is formed on a carrier substrate 20 (first support), as shown in (a) of Fig. 2. The carrier substrate 20 is, for example, a glass substrate. The temporary fixing layer 21 is, for example, a curable adhesive layer, and is configured to be peeled off together with the carrier substrate 20 by light, heat, or the like in a process described later.

[0051] Subsequently, as shown in FIG. 2B, a plurality of posts 22 are formed on the temporary fixing layer 21. Each post 22 is a conductive columnar member, and is made of, for example, copper. Each post 22 has a first end 22a and a second end 22b on the opposite side, and is formed so that the first end 22a of each post 22 is located on the carrier substrate 20 side. The post 22 corresponds to the connection electrode 10 shown in FIG. 1. Since the semiconductor dies 30 and 40 are placed on the carrier substrate 20 (temporary fixing layer 21) in a process to be described later, the post 22 is not placed in that region. Such a post 22 can be manufactured by, for example, a semi-additive method. The height of the post 22 may be, for example, 50 μm to 200 μm, or 75 μm to 180 μm. The diameter of the post 22 may be, for example, 10 μm to 50 μm.

[0052] Next, as shown in (a) and (b) of FIG. 3, semiconductor dies 30 and 40 (semiconductor members) are prepared. As shown in (a) of FIG. 3, the semiconductor die 30 has a semiconductor substrate 31, a plurality of terminal electrodes 32, a resin layer 33, a fine wiring layer 34, and an internal electrode 35. The semiconductor die 30 corresponds to the semiconductor die 5 shown in FIG. 1. The semiconductor substrate 31 is made of, for example, silicon or the like, and has a first surface 31a and a second surface 31b on the opposite side. The plurality of terminal electrodes 32 are provided on the first surface 31a side of the semiconductor substrate 31. The plurality of terminal electrodes 32 are, for example, copper pillars provided on the first surface 31a side of the semiconductor substrate 31, and are connected to wiring (not shown) in the semiconductor substrate 31. The diameter of each terminal electrode 32 is, for example, 10 μm to 50 μm, the terminal pitch (spaced distance) between the terminal electrodes 32 is, for example, 5 μm to 20 μm, and the height of the terminal electrodes 32 is, for example, 20 μm to 50 μm, however, the sizes of the terminal electrodes 32 are not limited to these.

[0053] The resin layer 33 is a resin member formed of a thermosetting adhesive (curable resin composition) provided on the first surface 31a side so as to cover the multiple terminal electrodes 32. The resin layer 33 may be formed so as to cover the entire first surface 31a of the semiconductor substrate 31, or may be formed so that the tips of the terminal electrodes 32 are exposed from the surface of the resin layer 33. The semiconductor die 30 is attached (attached) onto the temporary fixing layer 21 of the carrier substrate 20 by the resin layer 33. The resin layer 33 can be formed by attaching (attaching) a resin film containing a resin composition such as a non-conductive adhesive film (NCF) or a die attach film (DAF). The resin film before being attached may be between 75% and 150% or between 100% and 120% of the height of the multiple terminal electrodes 32, and is preferably a film having a thickness similar to the height of the terminal electrodes 32. The resin layer 33 is a semi-cured or uncured curable resin composition when the semiconductor die 30 is attached to the carrier substrate 20. Such a resin layer 33 may have a transmittance of 30% or more for visible light, preferably a transmittance of 50% or more for visible light, and more preferably a transmittance of 80% or more for visible light. In this case, when attaching the semiconductor die 30 to the carrier substrate 20 in a process described later, the positions of the multiple terminal electrodes 32 can be determined through the resin layer 33, and the semiconductor die 30 can be attached to a predetermined position on the carrier substrate 20 with high accuracy based on the result of the determination. The resin layer 33 may be a liquid adhesive containing a thermosetting adhesive (curable resin composition) similar to the resin film, which is applied to the first surface 31a of the semiconductor substrate 31.

[0054] The thickness of the resin layer 33 may be, for example, 50 μm or less, 20 μm or less, 10 μm or less, 9 μm or less, 8 μm or less, or 7 μm or less, or 1 μm or more, 2 μm or more, 3 μm or more, 4 μm or more, 5 μm or more, or 10 μm or more. The thickness of the resin layer 33 may be between 100% and 150% of the height of the multiple terminal electrodes 32, or may be between 100% and 120%, and is preferably the same thickness as the height of the terminal electrodes 32. Note that the thickness of the resin layer 33 here means the thickness in an uncured or semi-cured state, and the height of the multiple terminal electrodes 32 means the average height of the multiple terminal electrodes 32.

[0055] The fine wiring layer 34 is a wiring layer located between the semiconductor substrate 31 and the resin layer 33. The fine wiring layer 34 has a wiring portion 34a and an insulating portion 34b that covers the wiring portion 34a. The wiring portion 34a electrically connects the wiring or internal electrode 35 in the semiconductor substrate 31 to the terminal electrode 32. The semiconductor die 30 does not necessarily have to have the fine wiring layer 34.

[0056] The internal electrode 35 is an electrode that connects the wiring layers provided on both sides of the semiconductor die 30, and is formed to extend in the thickness direction of the semiconductor substrate 31. The internal electrode 35 corresponds to the through electrode 4c shown in FIG. 1. The internal electrode 35 has a first end 35a and a second end 35b on the opposite side. The first end 35a is connected to the corresponding terminal electrode 32 via the fine wiring layer 34. On the other hand, the second end 35b of the internal electrode 35 is not exposed to the outside at the stage where the semiconductor die 30 is attached to the carrier substrate 20 (stage (c) of FIG. 2), and is located within the semiconductor substrate 31. By grinding the second surface 31b of the semiconductor substrate 31 in a process described later (stage (a) of FIG. 4), the second end 35b of the internal electrode 35 is exposed to the outside, and the internal electrode 35 functions as a through electrode. The semiconductor die 30 does not need to have the internal electrode 35 that serves as a through electrode.

[0057] The semiconductor die 40 has a similar configuration to the semiconductor die 30, and includes a semiconductor substrate 41, a plurality of terminal electrodes 42, a resin layer 43, a fine wiring layer 44, and an internal electrode 45, as shown in FIG. 3B. The semiconductor die 40 corresponds to the semiconductor die 4 shown in FIG. 1. The semiconductor substrate 41 is made of, for example, silicon, and has a first surface 41a and a second surface 41b on the opposite side. The plurality of terminal electrodes 42 are provided on the first surface 41a side of the semiconductor substrate 41. The plurality of terminal electrodes 42 are connected to wiring (not shown) in the semiconductor substrate 41. The size, height, etc. of the terminal electrodes 42 are similar to those of the terminal electrodes 32. The resin layer 43 is an adhesive member provided on the first surface 41a side so as to cover the plurality of terminal electrodes 42. The semiconductor die 40 is attached (attached) to the temporary fixing layer 21 of the carrier substrate 20 by the resin layer 43. The resin layer 43 can be formed by laminating (attaching) a resin film containing a resin composition such as NCF or DAF. The resin film before lamination may be between 75% to 150% or between 100% to 120% of the height of the terminal electrodes 42, and is preferably a film having a thickness similar to the height of the terminal electrodes 42. The resin layer 43 is a semi-cured or uncured curable resin composition when the semiconductor die 40 is attached to the carrier substrate 20. The resin composition constituting the resin layer 43 can be the same as that of the resin layer 33.

[0058] The fine wiring layer 44 is a wiring layer located between the semiconductor substrate 41 and the resin layer 43. The fine wiring layer 44 has a wiring portion 44a and an insulating portion 44b covering the wiring portion 44a. The wiring portion 44a electrically connects the wiring or the internal electrode 45 in the semiconductor substrate 41 to the terminal electrode 42. The internal electrode 45 is an electrode that connects the wiring layers provided on both sides of the semiconductor die 40, and has a first end 45a and a second end 45b on the opposite side. The first end 45a is connected to the corresponding terminal electrode 42 via the fine wiring layer 44. The second end 45b is not exposed to the outside at the stage when the semiconductor die 40 is attached to the carrier substrate 20. By grinding the second surface 41b of the semiconductor substrate 41, the second end 45b of the internal electrode 45 is exposed to the outside, and the internal electrode 45 functions as a through electrode. The semiconductor die 40 does not need to have the fine wiring layer 44 and the internal electrode 45.

[0059] Each of the semiconductor dies 30, 40 described above can be fabricated by dividing a wafer or panel-shaped semiconductor substrate including a large number of semiconductor dies 30, 40 having the layer structure described above.

[0060] Here, an example of the adhesive constituting the resin layers 33, 43 will be described. As such an adhesive, an adhesive containing (a) an epoxy resin, (b) a curing agent, (c) a polymer component having a weight average molecular weight of 10,000 or more, (d) an inorganic filler having an average particle size of 100 nm or less, and (e) a glycidyl-based silane coupling agent can be used. In this adhesive, the content of the inorganic filler (d) may be 20 to 40 mass %. Note that the adhesive constituting the resin layers 33, 43 is not limited to the adhesive described below.

[0061] Examples of the epoxy resin of component (a) include epoxy resins having two or more epoxy groups in the molecule, and bisphenol A type epoxy resins, bisphenol F type epoxy resins, naphthalene type epoxy resins, phenol novolac type epoxy resins, cresol novolac type epoxy resins, phenol aralkyl type epoxy resins, biphenyl type epoxy resins, triphenylmethane type epoxy resins, dicyclopentadiene type epoxy resins, various polyfunctional epoxy resins, etc. can be used. The component (a) can be used alone or in combination of two or more. The content of component (a) is, for example, 10 to 50 mass% based on the total amount of the thermosetting adhesive.

[0062] Examples of the hardener of component (b) include phenolic resin-based hardeners, acid anhydride-based hardeners, amine-based hardeners, imidazole-based hardeners, and phosphine-based hardeners. When component (b) contains a phenolic hydroxyl group, acid anhydrides, amines, or imidazoles, it is likely to exhibit flux activity that suppresses the formation of an oxide film at the connection, and connection reliability and insulation reliability can be easily improved. Each hardener will be described below.

[0063] (i) Phenolic resin hardener Examples of the phenolic resin-based curing agent include curing agents having two or more phenolic hydroxyl groups in the molecule, and can be phenol novolac, cresol novolac, phenol aralkyl resin, cresol naphthol formaldehyde polycondensate, triphenylmethane type polyfunctional phenol, various polyfunctional phenol resins, etc. The phenolic resin-based curing agent can be used alone or in combination of two or more kinds.

[0064] The equivalent ratio (phenolic hydroxyl group / epoxy group, molar ratio) of the phenolic resin-based curing agent to the above component (a) is preferably 0.3 to 1.5, more preferably 0.4 to 1.0, and even more preferably 0.5 to 1.0, from the viewpoint of excellent curability, adhesion, and storage stability. When the equivalent ratio is 0.3 or more, the curability and adhesion tend to be improved, and when it is 1.5 or less, there is no excess of unreacted phenolic hydroxyl group remaining, the water absorption rate is kept low, and insulation reliability tends to be further improved.

[0065] (ii) Acid anhydride curing agent Examples of the acid anhydride curing agent include methylcyclohexanetetracarboxylic dianhydride, trimellitic anhydride, pyromellitic anhydride, benzophenonetetracarboxylic dianhydride, and ethylene glycol bisanhydrotrimellitate. The acid anhydride curing agent may be used alone or in combination of two or more.

[0066] The equivalent ratio (anhydride group / epoxy group, molar ratio) of the acid anhydride curing agent to the component (a) is preferably 0.3 to 1.5, more preferably 0.4 to 1.0, and even more preferably 0.5 to 1.0, from the viewpoint of excellent curability, adhesion, and storage stability. When the equivalent ratio is 0.3 or more, the curability and adhesion tend to be improved, and when it is 1.5 or less, there is no excess of unreacted acid anhydride remaining, the water absorption rate is kept low, and insulation reliability tends to be further improved.

[0067] (iii) Amine-based hardener As the amine-based curing agent, for example, dicyandiamide can be used.

[0068] The equivalent ratio (amine / epoxy group, molar ratio) of the amine-based curing agent to the component (a) is preferably 0.3 to 1.5, more preferably 0.4 to 1.0, and even more preferably 0.5 to 1.0, from the viewpoint of excellent curability, adhesion, and storage stability. When the equivalent ratio is 0.3 or more, the curability and adhesion tend to be improved, and when it is 1.5 or less, there is no excess of unreacted amine remaining, and insulation reliability tends to be further improved.

[0069] (iv) Imidazole-based curing agents Examples of the imidazole-based curing agent include 2-phenylimidazole, 2-phenyl-4-methylimidazole, 1-benzyl-2-methylimidazole, 1-benzyl-2-phenylimidazole, 1-cyanoethyl-2-undecylimidazole, 1-cyano-2-phenylimidazole, 1-cyanoethyl-2-undecylimidazole trimellitate, 1-cyanoethyl-2-phenylimidazolium trimellitate, 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine, 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine, and 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine. -[2'-undecylimidazolyl-(1')]-ethyl-s-triazine, 2,4-diamino-6-[2'-ethyl-4'-methylimidazolyl-(1')]-ethyl-s-triazine, 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine isocyanuric acid adduct, 2-phenylimidazole isocyanuric acid adduct, 2-phenyl-4,5-dihydroxymethylimidazole, 2-phenyl-4-methyl-5-hydroxymethylimidazole, and adducts of epoxy resins and imidazoles. Among these, from the viewpoint of further excellent curing properties, storage stability, and connection reliability, 1-cyanoethyl-2-undecylimidazole, 1-cyano-2-phenylimidazole, 1-cyanoethyl-2-undecylimidazole trimellitate, 1-cyanoethyl-2-phenylimidazolium trimellitate, 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine, 2,4-diamino-6-[2'-ethyl-4'-methylimidazolyl-(1')]-ethyl-s-triazine, 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine isocyanuric acid adduct, 2-phenylimidazole isocyanuric acid adduct, 2-phenyl-4,5-dihydroxymethylimidazole, and 2-phenyl-4-methyl-5-hydroxymethylimidazole are preferred. The imidazole-based curing agent can be used alone or in combination of two or more kinds. These may also be microencapsulated to form latent curing agents.

[0070] The content of the imidazole-based curing agent is preferably 0.1 to 20 parts by mass, and more preferably 0.1 to 10 parts by mass, relative to 100 parts by mass of component (a). When the content of the imidazole-based curing agent is 0.1 part by mass or more, the curability tends to be improved, and when it is 20 parts by mass or less, the adhesive composition does not cure before a metal bond is formed, and connection defects tend not to occur.

[0071] (v) Phosphine-based curing agents Examples of phosphine-based curing agents include triphenylphosphine, tetraphenylphosphonium tetraphenylborate, tetraphenylphosphonium tetra(4-methylphenyl)borate, and tetraphenylphosphonium(4-fluorophenyl)borate.

[0072] The content of the phosphine-based curing agent is preferably 0.1 to 10 parts by mass, and more preferably 0.1 to 5 parts by mass, relative to 100 parts by mass of component (a). When the content of the phosphine-based curing agent is 0.1 part by mass or more, the curability tends to be improved, and when it is 10 parts by mass or less, the adhesive for semiconductors does not cure before a metal bond is formed, and connection defects tend not to occur.

[0073] The phenolic resin-based curing agent, the acid anhydride-based curing agent, and the amine-based curing agent may each be used alone or in combination of two or more. The imidazole-based curing agent and the phosphine-based curing agent may each be used alone, or may be used together with the phenolic resin-based curing agent, the acid anhydride-based curing agent, or the amine-based curing agent.

[0074] As the (b) component, from the viewpoint of excellent curing properties, it is preferable to use a combination of phenol and imidazole, a combination of acid anhydride and imidazole, a combination of amine and imidazole, or imidazole alone. Since productivity improves when connecting in a short time, it is more preferable to use imidazole alone, which has excellent fast curing properties. In this case, since volatile components such as low molecular weight components can be suppressed by curing in a short time, the occurrence of voids can also be easily suppressed.

[0075] Examples of the (c) polymer component having a weight average molecular weight of 10,000 or more (excluding compounds corresponding to the (a) component) include phenoxy resin, polyimide resin, polyamide resin, polycarbodiimide resin, cyanate ester resin, (meth)acrylic resin, polyester resin, polyethylene resin, polyethersulfone resin, polyetherimide resin, polyvinyl acetal resin, urethane resin, acrylic rubber, etc., among which, from the viewpoint of excellent heat resistance and film formability, phenoxy resin, polyimide resin, (meth)acrylic resin, acrylic rubber, cyanate ester resin, polycarbodiimide resin, etc. are preferred, and phenoxy resin, polyimide resin, (meth)acrylic resin, and acrylic rubber are more preferred. The (c) component can be used alone or as a mixture or copolymer of two or more kinds.

[0076] The mass ratio of component (c) to component (a) is not particularly limited, but in order to maintain the film shape, the content of component (a) is preferably 0.01 to 5 parts by mass, more preferably 0.05 to 4 parts by mass, and even more preferably 0.1 to 3 parts by mass per part by mass of component (c). If the content is 0.01 part by mass or more, the curability and adhesive strength tend to be improved, and if the content is 5 parts by mass or less, the film-forming property and membrane-forming property tend to be improved.

[0077] The weight average molecular weight of the (c) component is 10,000 or more in terms of polystyrene, but in order to show good film formability by itself, it is preferably 30,000 or more, more preferably 40,000 or more, and even more preferably 50,000 or more. When the weight average molecular weight is 10,000 or more, the film formability tends to be improved. In this specification, the weight average molecular weight means the weight average molecular weight measured in terms of polystyrene using high performance liquid chromatography (Shimadzu Corporation C-R4A).

[0078] The (d) component is not particularly limited as long as it is an inorganic filler with an average particle size of 100 nm or less, and examples thereof include insulating inorganic fillers. Examples of insulating inorganic fillers include glass, silica, alumina, titanium oxide, carbon black, mica, boron nitride, and the like, and among these, silica, alumina, titanium oxide, boron nitride, and the like are preferred, and silica, alumina, and boron nitride are more preferred. The insulating inorganic filler may be whiskers, and examples of the whiskers include aluminum borate, aluminum titanate, zinc oxide, calcium silicate, magnesium sulfate, boron nitride, and the like. The insulating inorganic filler may be used alone or in combination of two or more types. The shape, particle size, and content of the (d) component are not particularly limited. The (d) component may be used alone or in combination of two or more types.

[0079] From the viewpoint of improving visibility, the average particle size of component (d) is 100 nm or less. From the viewpoint of improving visibility, the average particle size of component (d) is preferably 60 nm or less. From the viewpoint of improving adhesive strength, component (d) is preferably an inorganic filler having an average particle size of 60 nm or less that has been surface-treated with (meth)acrylic silane.

[0080] The content of component (d) is 20 to 40 mass% based on the total amount of the adhesive. When the content of component (d) is 20 mass% or more, adhesive strength is high and reflow resistance tends to be improved. When the content of component (d) is 40 mass% or less, thickening can be prevented and connection reliability can be improved.

[0081] There are no particular limitations on the component (e) so long as it is a glycidyl-based silane coupling agent. If it is a glycidyl-based silane coupling agent, it acts with the epoxy resin to improve adhesive strength. The content of the component (e) is preferably 1 to 5 parts by mass, more preferably 1.5 to 4% by mass, relative to 100 parts by mass of the component (d). When the content is 1 part by mass or more, adhesive strength tends to improve, and when it is 5 parts by mass or less, defects such as the generation of voids can be prevented.

[0082] The adhesive according to the present embodiment may further contain additives such as a fluxing agent, a resin filler, an antioxidant, a silane coupling agent (excluding compounds corresponding to component (e)), a titanium coupling agent, a leveling agent, etc. These additives may be used alone or in combination of two or more. The content of these additives may be appropriately adjusted so that the effect of each additive is exerted.

[0083] As another type of adhesive constituting the resin layers 33, 43, an adhesive containing a high molecular weight resin component and a thermosetting component may be used. The high molecular weight resin component may contain at least one resin selected from the group consisting of acrylic rubber, polyimide, and phenoxy resin. The high molecular weight resin component may have a reactive group such as an epoxy group. The weight average molecular weight of the high molecular weight resin component (standard polystyrene equivalent value according to the GPC method) may be 100,000 to 3,000,000. The content of the high molecular weight resin component may be 30 to 80 parts by mass with respect to 10 parts by mass of the total mass of the resin layer 33.

[0084] The thermosetting component contained in this other type of adhesive is a compound having a reactive group that forms a crosslinked structure by self-polymerization and / or reaction with a curing agent. The thermosetting component may include at least one selected from the group consisting of epoxy resin, bismaleimide resin, triazine resin, and phenol resin. The content of the thermosetting component may be 1 to 30 parts by mass with respect to 100 parts by mass of the resin layer 33. This other type of adhesive may include other components as necessary. Examples of the other components include a curing agent that reacts with the thermosetting component, a curing accelerator that promotes the reaction between the thermosetting component and the curing agent, a coupling agent (e.g., a silane coupling agent), and an inorganic filler (e.g., silica).

[0085] A specific example of the inorganic filler contained in this other type of adhesive is glass, as described above. The average particle size of the inorganic filler may be, for example, 20 μm or less, or 10 μm or less, and the maximum particle size of the inorganic filler may be, for example, 30 μm or less. It is preferable that the average particle size of the inorganic filler is 5 μm or less, and the maximum particle size of the inorganic filler is 20 μm or less. By having the average particle size of 10 μm or less and the maximum particle size of 30 μm or less, it is possible to fill the gaps between the terminals when forming the resin layer on the terminal surface, and to suppress warping after the resin layer is cured. There is no particular limit to the lower limit of the average particle size and the lower limit of the maximum particle size of the inorganic filler, but both may be 0.001 μm or more.

[0086] The average particle size and maximum particle size of the inorganic filler can be measured, for example, by using a scanning electron microscope (SEM) to measure the particle size of about 20 inorganic fillers. The measurement method using SEM can be, for example, by preparing a sample by heat-curing (preferably at 150 to 180°C for 1 to 10 hours) a resin composition containing the inorganic filler, cutting the center of the sample, and observing the cross section with SEM. In this case, it is preferable that the probability of the presence of fillers with a particle size of 3 μm or less in the cross section is 80% or more of the total fillers.

[0087] The content of the inorganic filler may be 10% by mass to 95% by mass based on the total amount of solids contained in the adhesive before curing. The content of the inorganic filler contained in the adhesive is preferably 20% by mass or more, more preferably 30% by mass or more, particularly preferably 40% by mass or more, and preferably 40% by mass to 95% by mass based on the total amount of solids contained in the adhesive (resin layers 33, 43) before curing. The elastic modulus (Young's modulus, after curing) of such a resin layer 33 may be, for example, 10 MPa or more, or 1.0 GPa or more at room temperature (25° C.). The linear expansion coefficient of the resin layer 33 at a temperature equal to or lower than the glass transition temperature may be, for example, 10 ppm / K to 200 ppm / K.

[0088] Returning to FIG. 2, the description will be continued. Next, when the preparation of the semiconductor dies 30, 40 is completed, as shown in FIG. 2(c), the semiconductor dies 30, 40 are attached to the carrier substrate 20 so that the lower surfaces on which the terminal electrodes 32, 42 (see FIG. 3(a) and (b)) are provided face the carrier substrate 20. At this time, the entire upper surfaces (second surfaces 31b, 41b) of the semiconductor dies 30, 40 are vacuum-adsorbed by a collet to perform bonding. The collet is made of an elastic material such as rubber. The semiconductor dies 30, 40 are moved to a predetermined position on the carrier substrate 20 by the vacuum-adsorbed collet, and are attached to the predetermined position of the carrier substrate 20 by the resin layers 33, 43. During this attachment, the terminal electrodes 32, 42 of the semiconductor dies 30, 40 are covered by the resin layers 33, 43, so that the terminal electrodes 32, 42 are protected. This results in the state shown in FIG. 2(c). In this step, the semiconductor dies 30, 40 are arranged face-down with the terminal electrodes 32, 42 facing downward.

[0089] When attaching the semiconductor die 30, 40, the positions of the terminal electrodes 32, 42 in the planar direction may be determined through the resin layers 33, 43 of the semiconductor die 30, 40, and the semiconductor die 30, 40 may be attached to a predetermined position on the carrier substrate 20 based on the result of the determination. When the resin layers 33, 43 have a transmittance equal to or higher than a predetermined value (for example, when the transmittance for visible light is 30% or more), such position determination before attachment can be performed, and the positional relationship between the terminal electrodes 32, 42 and the posts 22 can be made highly accurate. When the carrier substrate 20 is a transparent member such as a glass substrate, the positions of the posts 22 and the terminal electrodes 32, 42 can be determined from below the carrier substrate 20. The positions of the terminal electrodes 32, 42 may be directly determined through the resin layers 33, 43, or the positions of the terminal electrodes 32, 42 may be indirectly determined by determining the positions of positioning markings provided on the surfaces on the first surfaces 31a, 41a sides through the resin layers 33, 43. The positions of the terminal electrodes 32, 42 may be determined by other methods, and are not particularly limited.

[0090] Next, after the attachment of the semiconductor dies 30, 40 is completed, the resin layers 33, 43 containing the curable resin composition are cured before the semiconductor dies 30, 40 are encapsulated. The resin layers 33, 43 are cured using either heat or light, or both. This fixes the semiconductor dies 30, 40 to the carrier substrate 20. Note that the fixation here is sufficient as long as the semiconductor dies 30, 40 are fixed to a degree that does not cause positional deviation during encapsulation, which will be described later.

[0091] Next, as shown in FIG. 2(d), an encapsulant layer 23 (first encapsulant layer) that encapsulates the posts 22 and the semiconductor dies 30, 40 with an encapsulant is formed on the carrier substrate 20. The encapsulant layer 23 is formed containing a thermosetting resin such as an epoxy resin, and is cured by heat or the like after the encapsulation. The resin layers 33, 43 of the semiconductor dies 30, 40 may be further cured by this thermal curing. The encapsulant constituting the encapsulant layer 23 is composed of a thermosetting resin composition, and contains, for example, an epoxy resin and a curing agent. The encapsulant constituting the encapsulant layer 23 may further contain an inorganic filler, for example, a silica filler. The average particle diameter of the inorganic filler contained in the encapsulant may be, for example, 50 μm or less, 25 μm or less, 10 μm or less, or 0.01 μm or less. The encapsulant constituting the encapsulant layer 23 preferably contains an inorganic filler with a large particle size in order to suppress warping during or after the manufacture of the semiconductor device 1, and preferably contains an inorganic filler with an average particle size larger than the average particle size of the inorganic filler contained in the resin layers 33, 43 of the semiconductor dies 30, 40.

[0092] Subsequently, when the encapsulant layer 23 is formed, the encapsulant layer is ground by CMP or the like to thin the encapsulant layer 23a after grinding as shown in FIG. 4(a). The elastic modulus (Young's modulus) of the encapsulant layer 23, 23a may be, for example, 3.0 GPa or more. The linear expansion coefficient of the encapsulant layer 23, 23a may be 5 ppm / K to 150 ppm / K, and the difference between the linear expansion coefficient of the encapsulant layer 23a and the linear expansion coefficient of the resin layer 33, 43 is 100 ppm / K or less. This grinding results in the semiconductor dies 30a, 40a in which the second ends 35b, 45b, which are the tips of the internal electrodes 35, 45, are exposed outside the encapsulant layer 23a. This grinding also exposes the second ends 22b of the multiple posts 22 outside the encapsulant layer 23a. The second ends 22b of the multiple posts 22 may be slightly ground.

[0093] Subsequently, when the encapsulant layer 23a is formed, as shown in FIG. 4B, a wiring layer 24 (first wiring layer) is formed on the encapsulant layer 23a. The wiring layer 24 may be, for example, a redistribution layer (RDL). The wiring layer 24 is provided with a wiring portion 24a and an insulating portion 24b covering the wiring portion 24a. The wiring portion 24a connects an external device to the semiconductor dies 50, 55 described later, and is connected, for example, to the second end 22b of each post 22 and the second end 35b, 45b of the internal electrodes 35, 45 of the semiconductor dies 30a, 40a. The wiring portion 24a may be configured to include, for example, a copper pillar. A known method can be used as a method for manufacturing the wiring layer 24 including the wiring portion 24a. In this manufacturing method, since the positioning of the post 22 and the semiconductor dies 30, 40 is performed with high precision as described above, the wiring portion 24a can be formed using mask exposure. In this case, the manufacturing efficiency of the wiring layer 24 can be significantly improved. Furthermore, a terminal on the opposite side (upper side in the figure) of the wiring portion 24a may be formed with a connection bump 25. The connection bump 25 may be, for example, a solder bump.

[0094] Subsequently, after the wiring layer 24 is formed, a carrier substrate 26 (second support) is provided on the wiring layer 24, as shown in (c) of FIG. 4. This results in a state in which a structure including the sealing material layer 23a, the wiring layer 24, etc. is sandwiched between the carrier substrate 20 and the carrier substrate 26. When providing the carrier substrate 26, a temporary fixing layer 27 may be provided on the wiring layer 24 side. The temporary fixing layer 27 may be the same as the temporary fixing layer 21. When the connection bumps 25 are formed, the temporary fixing layer 27 preferably has a thickness that protects the connection bumps 25.

[0095] Next, after the carrier substrate 26 is provided, the carrier substrate 20 is separated from the sealing material layer 23a as shown in (d) of Fig. 4. In this separation, the temporary fixing layer 21 is irradiated with laser light or heated to reduce the adhesiveness of the temporary fixing layer 21, and the carrier substrate 20 is peeled off and separated from the sealing material layer 23a.

[0096] Next, when the carrier substrate 20 is separated, the encapsulant layer 23a is ground by CMP or the like, and is further thinned to a ground encapsulant layer 23b as shown in FIG. 5(a). In this grinding, the terminal electrodes 32, 42 provided in the resin layers 33, 43 of the semiconductor dies 30b, 40b are ground until they are exposed to the outside. The ground resin layers 33, 43 may have a thickness of 20 μm or more. When the encapsulant layer 23a including the resin layers 33, 43 is ground, the tips of the terminal electrodes 32, 42 and the tips of the posts 22 may also be ground in the same manner. Such grinding may be performed by grinding with a grinder or the like, or may be an etching process. It is preferable to perform a cleaning process after grinding.

[0097] Next, when the grinding of the encapsulant layer is completed and the terminal electrodes 32, 42 are exposed to the outside, as shown in FIG. 5B, a wiring layer 28 (second wiring layer) electrically connected to the terminal electrodes 32, 42 and the posts 22 is formed on the encapsulant layer 23b from which the resin layers 33, 43 have been ground. The wiring layer 28 may be, for example, a redistribution layer (RDL). The wiring layer 28 is provided with a wiring portion 28a and an insulating portion 28b covering the wiring portion 28a. The wiring portion 28a connects the posts 22 and the semiconductor dies 30b, 40b to the semiconductor dies 50, 55 described later, and is connected, for example, to the first end 22a of each post 22 and the terminal electrodes 32, 42 and the first ends 35a, 45a of the internal electrodes 35, 45 of the semiconductor dies 30b, 40b. The wiring portion 28a may be configured to include, for example, a copper pillar. The method of manufacturing the wiring layer 28 including the wiring portion 28a can be a known method, as in the case of the wiring layer 24. In this manufacturing method, since the positioning of the post 22 and the terminal electrodes 32, 42 of the semiconductor dies 30b, 40b is performed with high precision as described above, the wiring layer 28 can be formed using mask exposure. In this case, the manufacturing efficiency of the wiring layer 28 can be significantly improved. It is preferable that the wiring pitch and wiring width of the wiring portion 28a are finer than the wiring pitch and wiring width of the wiring portion 24a. This allows the semiconductor dies 50, 55 with fine structures to be connected. In this manner, the interposer P (wiring board) is manufactured. Note that the connection points (first connection points) between the post 22 and the wiring layer 24 and the connection points (second connection points) between the post 22, the terminal electrodes 32, 42 and the wiring layer 28 are connected without soldering.

[0098] Subsequently, when the wiring layer 28 is formed, as shown in FIG. 5(c), the semiconductor dies 50, 55 (first semiconductor chip, second semiconductor chip) are attached to the surface 28c (the lower surface in the figure) of the wiring layer 28 opposite to the sealing material layer 23b. At this time, the terminal electrodes of the semiconductor dies 50, 55 are connected to the tips of the wiring parts 28a of the wiring layer 28. This connection may be made via solder. The semiconductor dies 50, 55 are, for example, semiconductor chips such as an LSI chip (logic chip), a CMOS sensor, a memory chip, or the like, and may be so-called active dies. The semiconductor dies 50, 55 correspond to the semiconductor dies 3, 2 shown in FIG. 1. Here, it is sufficient that one or more semiconductor chips are attached, but it is preferable to attach two or more semiconductor chips. In this process, the semiconductor die 50 and the semiconductor die 55 are electrically connected to each other by the built-in semiconductor die 40b. The built-in semiconductor die 30b is connected to the semiconductor die 50. Each post 22 is similarly connected to semiconductor dies 50 and 55 via wiring layer 28 .

[0099] 6A, the semiconductor dies 50 and 55 are encapsulated on the wiring layer 28 with an encapsulant to form an encapsulant layer 29 (second encapsulant layer) on the wiring layer 28. The encapsulant layer 29, like the encapsulant layer 23, is configured to include a thermosetting resin such as an epoxy resin, and is cured after encapsulation.

[0100] Subsequently, the semiconductor dies 50 and 55 are encapsulated with an encapsulant to form the encapsulant layer 29, which may then be ground until the surfaces 50a and 55a of the semiconductor dies 50 and 55 are exposed from the surface of the encapsulant layer, as shown in Fig. 6(b), thereby thinning the encapsulant layer 29 to the encapsulant layer 29a shown in Fig. 6(b).

[0101] Subsequently, after grinding to the sealing material layer 29a, as shown in Fig. 6(c), the temporary fixing layer 27 is irradiated with laser light or heated to reduce the adhesiveness of the temporary fixing layer 27, and the carrier substrate 26 is peeled off and separated from the wiring layer 24. As a result, the connection bumps 25 are exposed to the outside. In the above description, an example is shown in which the connection bumps 25 are produced by the process shown in Fig. 4(b), but the present invention is not limited to this, and the connection bumps 25 may be provided on the wiring layer 24 after the temporary fixing layer 27 is separated.

[0102] In this manner, the semiconductor device 1 shown in Fig. 6(c) and Fig. 1 is manufactured. Such a semiconductor device 1 is mounted on a substrate M. At this time, an underfill material is applied between the semiconductor device 1 and the substrate M. Thereafter, the underfill material is cured by thermal curing or the like to manufacture the semiconductor device (structure S) shown in Fig. 1.

[0103] As described above, in the manufacturing method of the semiconductor device according to the first embodiment, the semiconductor dies 30, 40 are attached to the carrier substrate 20 so that the first surfaces 31a, 41a on which the terminal electrodes 32, 42 are provided face the carrier substrate 20. That is, the semiconductor dies 30, 40 are attached face down. Therefore, when the semiconductor dies 30, 40 are bonded by sucking them with a collet or the like, it is not necessary to suck the terminal electrode side, and the semiconductor dies 30, 40 can be attached reliably. When picking up the semiconductor dies 30, 40 before bonding, the terminal electrodes 32, 42 side may be sucked with a collet once (and then the die is turned over and bonded), but in this case, since the terminal electrodes 32, 42 are covered with the resin layers 33, 43, it is not necessary to suck the outer periphery with a collet, and the semiconductor dies 30, 40 can be picked up reliably.

[0104] In addition, in this method for manufacturing a semiconductor device, the semiconductor dies 50 and 55 connected to the semiconductor dies 30 and 40 can be attached at the end of the process (for example, after the wiring layers 24 and 28 are formed), so if a defect occurs during the process, the semiconductor dies 50 and 55, which are expensive active dies, can be left unattached. This reduces the overall manufacturing cost.

[0105] [Second embodiment] Next, a semiconductor device according to a second embodiment and a method for manufacturing the same will be described with reference to Figures 7 to 11. Descriptions of points that overlap with the semiconductor device according to the first embodiment and the method for manufacturing the same will be omitted.

[0106] Fig. 7 is a diagram showing an example of a semiconductor device manufactured by the manufacturing method according to the second embodiment. As shown in Fig. 7, the semiconductor device 1A includes semiconductor dies 2 and 3, semiconductor dies 4 and 5, wiring layers 6 and 7, encapsulant layers 8 and 9, connection bumps 11, and underfills 12 and 13. The semiconductor device 1 is mounted on a substrate M. This semiconductor device 1A differs from the semiconductor device 1 according to the first embodiment in that a connection member 60 including a plurality of connection electrodes 10 is further provided.

[0107] The connection member 60 includes a plurality of connection electrodes 10, a substrate 61 in which the connection electrodes 10 are provided, a terminal electrode 62 (another terminal electrode) provided on a first surface side (upper side in the figure) of the substrate 61, and a resin layer 63 (another resin layer) provided on the first surface side (upper side in the figure) of the substrate 61 so as to cover the terminal electrode 62. The connection member 60 may further include a fine wiring layer 64.

[0108] The substrate 61 is made of silicon or the like, similar to the semiconductor substrates of the semiconductor dies 4 and 5. The substrate 61 may be made of other materials (e.g., resin or the like). The connection electrodes 10 are through electrodes that penetrate such a substrate 61, and their functions are similar to those of the first embodiment. In the semiconductor device 1A according to the second embodiment, the connection member 60 has a configuration similar to that of the semiconductor dies 4 and 5, and may have a fine wiring layer 64 between the resin layer 63 and the connection electrodes 10.

[0109] Next, an example of a method for manufacturing the semiconductor device 1A will be described with reference to Figures 8 to 11. Figures 8 to 11 are cross-sectional views sequentially showing a method for manufacturing the semiconductor device 1A described above.

[0110] In this method for manufacturing a semiconductor device, as shown in FIG. 8(a), a temporary fixing layer 21 is formed on a carrier substrate 20 (first support).

[0111] Next, as shown in FIG. 8(b), a connection member 60 is prepared in which a plurality of posts 22 are provided inside a substrate 61. The connection member 60 includes a substrate 61 having a plurality of posts 22, a first surface 61a and a second surface 61b opposite thereto, a terminal electrode 62 provided on the first surface 61a side of the substrate 61, and a resin layer 63 provided on the first surface 61a side of the substrate 61 so as to cover the terminal electrode 62. In the connection member 60, the first end 22a of the post 22 is connected to the terminal electrode 62, while the second end 22b of the post 22 is located inside the substrate 61. The connection member 60 may further include a fine wiring layer 64 between the substrate 61 and the resin layer 63. The fine wiring layer 64 connects the post 22 and the terminal electrode 62. The resin layer 63 may be made of the same material as the resin layers 33 and 43 of the semiconductor dies 30 and 40. The fine wiring layer 64 has a configuration corresponding to the fine wiring layers 34 and 44.

[0112] Next, when the preparation of the connection member 60 is completed, the connection member 60 is attached to the carrier substrate 20 so that the lower surface on which the terminal electrodes 62 are provided faces the carrier substrate 20. At this time, the entire upper surface (second surface 61b) of the connection member 60 is vacuum-adsorbed and bonded by a collet. The connection member 60 is moved to a predetermined position on the carrier substrate 20 by the vacuum-adsorbed collet, and is attached to the predetermined position of the carrier substrate 20 by a resin layer 63. During attachment, the terminal electrodes 62 of the connection member 60 are covered by the resin layer 63, so that the terminal electrodes 62 are protected. In addition, the semiconductor dies 30 and 40 are attached to the carrier substrate 20 at the same time as the installation of the connection member 60, or before or after the installation of the connection member 60. The method of attaching the semiconductor dies 30 and 40 is the same as that of the first embodiment. As a result, the state shown in FIG. 8(b) is obtained. In this process, the connection member 60 and the semiconductor dies 30 and 40 are arranged in a face-down state in which the terminal electrodes face downward.

[0113] Next, after the attachment of the semiconductor dies 30, 40 and the connecting member 60 is completed, the resin layers 33, 43, 63 containing the curable resin composition are cured before sealing the semiconductor dies 30, 40 and the connecting member 60. The resin layers 33, 43, 63 are cured using either heat or light or both. As a result, the semiconductor dies 30, 40 and the connecting member 60 are fixed to the carrier substrate 20.

[0114] 8(c), an encapsulant layer 23 is formed on the carrier substrate 20 to encapsulate the connection member 60 including the plurality of posts 22 and the semiconductor dies 30 and 40 with an encapsulant. After encapsulation, the encapsulant layer 23 is cured by heat or the like. The resin layers 33, 43, and 63 may be further cured by this thermal curing.

[0115] Next, after the encapsulant layer 23 is formed, the encapsulant layer is ground by CMP or the like to thin it into a ground encapsulant layer 23a as shown in FIG. 8(d). This grinding process results in the semiconductor dies 30a, 40a in which the second ends 35b, 45b, which are the tips of the internal electrodes 35, 45, are exposed outside the encapsulant layer 23a. This grinding process also exposes the second ends 22b of the posts 22 outside the encapsulant layer 23a.

[0116] Subsequently, after the encapsulant layer 23a is formed, the wiring layer 24 is formed on the encapsulant layer 23a as shown in (a) of Fig. 9. The wiring portion 24a of the wiring layer 24 connects an external device to the semiconductor dies 50, 51, and is connected, for example, to the second end 22b of each post 22 and the second end 35b, 45b, which is the tip of the internal electrode 35, 45 of the semiconductor dies 30a, 40a (see also (d) of Fig. 8). In addition, a connection bump 25 may be formed on the terminal on the opposite side (upper side in (a) of Fig. 9) of the wiring portion 24a.

[0117] Subsequently, after the wiring layer 24 is formed, as shown in (b) of Fig. 9, a carrier substrate 26 is provided on the wiring layer 24. When providing the carrier substrate 26, a temporary fixing layer 27 may be provided on the wiring layer 24 side. Thereafter, as shown in (c) of Fig. 9, the carrier substrate 20 is separated from the sealing material layer 23a.

[0118] Next, when the carrier substrate 20 is separated, the encapsulant layer 23a is ground by CMP or the like, and is further thinned to a ground encapsulant layer 23b as shown in FIG. 10(a). In this grinding, the terminal electrodes 32, 42 provided in the resin layers 33, 43 of the semiconductor dies 30, 40 are ground until they are exposed to the outside. In addition, the terminal electrodes 62 provided in the resin layer 63 of the connection member 60a are ground until they are exposed to the outside. The ground resin layers 33, 43, 63 may have a thickness of 20 μm or more. When the encapsulant layer 23a is ground, the tips of the terminal electrodes 32, 42 and the tips of the posts 22 may also be ground in the same manner.

[0119] 10(b), the wiring layer 28 electrically connected to the terminal electrodes 32, 42, 62 is formed on the sealing material layer 23b from which the resin layers 33, 43, 63 have been ground. The wiring portion 28a of the wiring layer 28 connects the posts 22 and the semiconductor dies 30, 40 to the semiconductor dies 50, 55, and is connected, for example, to the first ends 22a of the posts 22 and the terminal electrodes 32, 42 and the first ends 35a, 45a of the internal electrodes 35, 45 of the semiconductor dies 30, 40.

[0120] Subsequently, after the wiring layer 28 is formed, the semiconductor dies 50 and 55 are attached to a surface 28c (the bottom surface in the figure) of the wiring layer 28 opposite to the encapsulant layer 23b, as shown in Fig. 10(c). In this process, the semiconductor die 50 and the semiconductor die 55 are electrically connected to each other by the built-in semiconductor die 40b. The built-in semiconductor die 30b is connected to the semiconductor die 50. Each post 22 is similarly connected to the semiconductor dies 50 and 55 via the wiring layer 28.

[0121] Next, after the semiconductor dies 50 and 55 are mounted, the semiconductor dies 50 and 55 are encapsulated on the wiring layer 28 with an encapsulant to form an encapsulant layer 29 on the wiring layer 28, as shown in FIG. 11(a). The encapsulant layer 29 is cured after encapsulation. Then, as shown in FIG. 11(b), grinding may be performed until the surfaces of the semiconductor dies 50 and 55 are exposed from the surface of the encapsulant layer. As a result, the encapsulant layer 29 is thinned to an encapsulant layer 29a shown in FIG. 11(b).

[0122] Next, when the sealing material layer 29a is ground, as shown in FIG. 11(c), the temporary fixing layer 27 is irradiated with laser light or heated to reduce the adhesiveness of the temporary fixing layer 27, and the carrier substrate 26 is peeled off and separated from the wiring layer 24. This exposes the connection bumps 25 to the outside. In this manner, the semiconductor device 1A shown in FIG. 11(c) and FIG. 7 is manufactured. Such a semiconductor device 1A is mounted on a substrate M. At this time, an underfill material is applied between the semiconductor device 1 and the substrate M. Thereafter, the underfill material is cured by thermal curing or the like to manufacture the semiconductor device shown in FIG. 7.

[0123] As described above, in the method for manufacturing a semiconductor device according to the second embodiment, similarly to the first embodiment, the semiconductor dies 30, 40 are attached to the carrier substrate 20 such that the first surfaces 31a, 41a on which the terminal electrodes 32, 42 are provided face toward the carrier substrate 20. That is, the semiconductor dies 30, 40 are attached face down. This allows the attachment of the semiconductor dies 30, 40 to be performed reliably. Also, in this method, the connection member 60 is attached to the carrier substrate 20 such that the first surface 61a on which the terminal electrodes 62 are provided faces toward the carrier substrate 20. That is, the connection member 60 is attached face down. This allows the attachment of the connection member 60 to be performed reliably.

[0124] In addition, in this semiconductor device manufacturing method, similarly to the first embodiment, the semiconductor dies 50 and 55 connected to the semiconductor dies 30 and 40 can be attached at the end of the process, so that if a defect occurs during the process, the semiconductor dies 50 and 55, which are expensive active dies, can be left unattached, thereby reducing the overall manufacturing cost.

[0125] Furthermore, in this method of manufacturing a semiconductor device, instead of forming the posts 22 individually on the carrier substrate 20, a connection member 60 including a plurality of posts 22 is formed in advance, and the posts 22 are provided by attaching the connection member 60 to the carrier substrate 20. This simplifies the formation of the posts 22. Furthermore, by forming the connection member 60 to have the same configuration and material as the semiconductor dies 30, 40 (excluding the circuits in the semiconductor dies), the process of picking up and attaching the semiconductor dies 30, 40 and the connection member 60 can be simplified, and manufacturing efficiency can be significantly improved.

[0126] Although the embodiments of the present disclosure have been described above, the present invention is not limited to the above-described embodiments, and appropriate modifications may be made without departing from the spirit of the present disclosure. [Explanation of symbols]

[0127] 1, 1A... semiconductor device, 2, 3, 50, 55... semiconductor die (first semiconductor chip, second semiconductor chip), 4, 5, 30, 40... semiconductor die (semiconductor member), 4a, 5a, 32, 42... terminal electrode, 6, 24... wiring layer (first wiring layer), 7, 28... wiring layer (second wiring layer), 8, 23, 23a, 23b... encapsulant layer (first encapsulant layer), 9, 29, 29a... encapsulant layer (second encapsulant layer), 10... connection electrode, 11... connection bump, 20... carrier substrate (first support), 22... post, 22a... first end, 22b... second end, 23, 23a, 23b... encapsulant layer (first encapsulant layer), 24... wiring layer (first wiring layer), 25...connection bump, 26...carrier substrate (second support), 28...wiring layer (second wiring layer), 29, 29a...encapsulant layer (second encapsulant layer), 30, 30a, 30b, 40, 40a, 40b...semiconductor die (semiconductor member), 31, 41...semiconductor substrate, 31a, 41a...first surface, 31b, 41b...second surface, 32, 42...terminal electrode, 33, 43...resin layer, 34, 44...fine wiring layer, 35, 45...internal electrode, 35a, 45a...first end, 35b, 45b...second end, 50, 55...semiconductor die (semiconductor chip), 60, 60a...connection member, 61...substrate, 62...terminal electrode, 63...resin layer, 64...fine wiring layer.

Claims

1. providing a conductive columnar member on a first support, the columnar member having a first end and a second end opposite the first end, the first end being located on the first support side; A step of attaching a semiconductor member including a semiconductor substrate having a first surface and a second surface on the opposite side, a terminal electrode provided on the first surface side of the semiconductor substrate, and a resin layer provided on the first surface side so as to cover the terminal electrode, to the first support such that the first surface faces the first support; A step of curing the resin layer containing a curable resin composition after attaching the semiconductor member to the first support and before sealing the columnar member and the semiconductor member; forming a first encapsulant layer on the first support to encapsulate the columnar member and the semiconductor member; forming a first wiring layer on the first sealing material layer, the first wiring layer being electrically connected to at least the columnar member; separating the first support from the first encapsulant layer; grinding at least the resin layer so as to expose a tip of the terminal electrode; forming a second wiring layer electrically connected to at least one of the terminal electrodes and the columnar member on the first sealing material layer where the terminal electrodes are exposed; A manufacturing method of a semiconductor device comprising:

2. The resin layer when the semiconductor member is attached to the first support is a semi-cured or uncured curable resin composition. The method for manufacturing a semiconductor device according to claim 1 .

3. The resin layer has a transmittance of 30% or more for visible light. The method for manufacturing a semiconductor device according to claim 1 or 2.

4. In the step of attaching the semiconductor member, a position of the terminal electrode is determined through the resin layer, and the semiconductor member is attached to a predetermined position of the first support based on a result of the determination. The method for manufacturing a semiconductor device according to claim 1 or 2.

5. The resin layer contains an inorganic filler. The method for manufacturing a semiconductor device according to claim 1 or 2.

6. The content of the inorganic filler is 30 mass% or more based on the total amount of solids contained in the resin layer. The method for manufacturing a semiconductor device according to claim 5 .

7. The average particle size of the inorganic filler is 20 μm or less. The method for manufacturing a semiconductor device according to claim 5 .

8. The elastic modulus of the resin layer when cured is 10 MPa or more at 25 ° C. The method for manufacturing a semiconductor device according to claim 1 or 2.

9. The resin layer is formed by laminating a non-conductive adhesive film (NCF) or a die attach film (DAF). The method for manufacturing a semiconductor device according to claim 1 or 2.

10. The thickness of the resin layer is between 100% and 150% of the height of the terminal electrode. The method for manufacturing a semiconductor device according to claim 1 or 2.

11. The resin layer is formed by laminating a resin film, The thickness of the resin film before bonding is between 75% and 150% of the height of the terminal electrode. The method for manufacturing a semiconductor device according to claim 1 or 2.

12. the step of grinding the first sealing material layer after forming the first sealing material layer and before forming the first wiring layer so that the second ends of the columnar members are exposed; The method for manufacturing a semiconductor device according to claim 1 or 2.

13. The method further includes providing a second support on the first wiring layer after forming the first wiring layer, separating the first support from the first encapsulant layer after providing the second support; The method for manufacturing a semiconductor device according to claim 1 or 2.

14. providing a connection bump on a surface of the first wiring layer opposite to the first sealing material layer; The step of providing the connection bumps is performed before providing the second support on the first wiring layer or after separating the second support from the first wiring layer. The method for manufacturing a semiconductor device according to claim 13.

15. The semiconductor member has a fine wiring layer between the first surface of the semiconductor substrate and the terminal electrode. The method for manufacturing a semiconductor device according to claim 1 or 2.

16. The semiconductor member has an internal electrode extending in a thickness direction of the semiconductor substrate, a first end of the internal electrode is connected to the second wiring layer via the terminal electrode; A second end of the internal electrode is connected to the first wiring layer. The method for manufacturing a semiconductor device according to claim 1 or 2.

17. The method further includes a step of attaching at least one semiconductor chip to a surface of the second wiring layer opposite to the first sealing material layer. The method for manufacturing a semiconductor device according to claim 1 or 2.

18. In the step of attaching the semiconductor chip, a first semiconductor chip and a second semiconductor chip are attached to the second wiring layer as the at least one semiconductor chip; The first semiconductor chip and the second semiconductor chip are electrically connected by the semiconductor member. The method for manufacturing a semiconductor device according to claim 17.

19. The method for manufacturing a semiconductor device according to claim 17, further comprising the step of forming a second encapsulant layer encapsulating the at least one semiconductor chip.

20. At least one of a first connection portion between the columnar member and the first wiring layer and a second connection portion between the columnar member and the second wiring layer is connected without soldering. The method for manufacturing a semiconductor device according to claim 1 or 2.

21. The columnar member is disposed in a substrate having a first surface and an opposite second surface; In the step of providing the columnar member, a connection member including the columnar member, the substrate, another terminal electrode provided on the first surface side of the substrate, and another resin layer provided on the first surface side of the substrate so as to cover the other terminal electrode is attached to the first support such that the first surface faces the first support, thereby providing the columnar member on the first support. The method for manufacturing a semiconductor device according to claim 1 or 2.

22. In the step of forming the first sealing material layer, the connection member is sealed together with the semiconductor member, In the grinding step, the resin layer and the another resin layer are ground so that the another terminal electrode is exposed together with the terminal electrode, In the step of forming the second wiring layer, the second wiring layer is formed so as to be electrically connected to the terminal electrode and the another terminal electrode. The method for manufacturing a semiconductor device according to claim 21 .

23. the step of grinding a part of the semiconductor substrate and a part of the substrate together with the first sealing material layer so as to expose the second ends of the columnar members after forming the first sealing material layer and before forming the first wiring layer; The method for manufacturing a semiconductor device according to claim 21 .