Semiconductor device

Abstract

According to the present invention, a main semiconductor element (20) and a circuit unit such as a temperature sensing unit (10), for protecting and controlling the main semiconductor element (20), are provided on the same semiconductor substrate (101) having a wide bandgap semiconductor as a material. The temperature sensing unit (10) is a horizontal SBD comprising: an n--type anode region (3) and a n+-type cathode contact region (4) selectively provided between the front surface of the semiconductor substrate (101) and a p-type well region (2); an anode electrode (5) in Schottky contact with the n--type anode region (3); and a cathode electrode (6) in ohmic contact with the n+-type cathode contact region (4). The temperature sensing unit (10) is surrounded by the p-type well region (2) and is electrically separated from the main semiconductor element (20) or another circuit unit. Accordingly, an inexpensive semiconductor device having a plurality of semiconductor elements on the same semiconductor substrate can be provided.

Description

Semiconductor Devices

[0001] This disclosure relates to semiconductor devices.

[0002] Patent Document 1 listed below describes a technology in which a pn junction diode formed by a pn junction between a p-type anode region and an n-type cathode region formed by ion implantation in the surface region of the same silicon carbide (SiC) substrate as the main semiconductor element is used as a temperature sensor. Patent Document 2 listed below describes a technology in which the temperature sensor has an npn junction formed by a diffusion region inside a silicon carbide semiconductor layer and a temperature sense current-carrying layer formed by a p-type silicon carbide semiconductor layer on the npn junction, and the temperature sense current-carrying layer reduces self-heating in the temperature sensor to maintain temperature detection accuracy.

[0003] JP 2017-79324 A JP 2020-98836 A

[0004] However, in the above-mentioned Patent Document 1, it is necessary to widen the gap between the temperature sensing unit and the main semiconductor element so that the temperature sensing unit is not affected by the body diode operation of the main semiconductor element, which increases the size of the semiconductor device and increases costs.In the above-mentioned Patent Document 2, the structure of the temperature sensor unit is complex, which increases the number of manufacturing processes and increases costs.

[0005] An object of this disclosure is to provide an inexpensive semiconductor device having a plurality of semiconductor elements on the same semiconductor substrate.

[0006] A semiconductor device according to one aspect of the present disclosure is a semiconductor device including two or more semiconductor elements inside a semiconductor substrate made of a wide bandgap semiconductor having a bandgap wider than that of silicon, and is as follows: A drift region is provided inside the semiconductor substrate; A well region is provided between a first main surface of the semiconductor substrate and the drift region, the well region forming a pn junction with the drift region; A lateral Schottky barrier diode is provided as the semiconductor element; The Schottky barrier diode is surrounded by the well region; The Schottky barrier diode has an anode region of the same conductivity type as the drift region, selectively provided between the first main surface and the well region, and an anode electrode in Schottky contact with the anode region at the first main surface.

[0007] The semiconductor device according to the present disclosure has the effect of providing an inexpensive semiconductor device having a plurality of semiconductor elements on the same semiconductor substrate.

[0008] FIG. 1 is a cross-sectional view showing the structure of a temperature sensing unit of a semiconductor device according to a first embodiment. FIG. 2 is a plan view showing an example layout of the semiconductor device according to the first embodiment as viewed from the front surface side of the semiconductor substrate. FIG. 3 is a cross-sectional view showing an example cross-sectional structure along the cutting line B1-B2-B3 of FIG. 2. FIG. 4 is a circuit diagram showing an equivalent circuit of FIG. 3. FIG. 5 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. FIG. 6 is a circuit diagram showing the equivalent circuit of FIG. 5. FIG. 7 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment. FIG. 8 is a circuit diagram showing the equivalent circuit of FIG. 7. FIG. 9 is a cross-sectional view showing the structure of a semiconductor device according to a fourth embodiment. FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a fifth embodiment. FIG. 11 is a cross-sectional view showing the structure of a semiconductor device according to a sixth embodiment. FIG. 12 is a cross-sectional view showing the structure of a semiconductor device of a reference example.

[0009] <Summary of Embodiments of the Present Disclosure> (1) A semiconductor device according to one aspect of the present disclosure is a semiconductor device including two or more semiconductor elements inside a semiconductor substrate made of a wide bandgap semiconductor having a bandgap wider than that of silicon, as follows: A drift region is provided inside the semiconductor substrate. A well region that forms a pn junction with the drift region is provided between a first main surface of the semiconductor substrate and the drift region. A lateral Schottky barrier diode is provided as the semiconductor element. The Schottky barrier diode is surrounded by the well region. The Schottky barrier diode has an anode region of the same conductivity type as the drift region, selectively provided between the first main surface and the well region, and an anode electrode that makes Schottky contact with the anode region at the first main surface.

[0010] According to the above disclosure, it is possible to form a Schottky barrier diode by utilizing the manufacturing process for fabricating a main semiconductor element on a semiconductor substrate. Therefore, when forming a main semiconductor element and a Schottky barrier diode, which serves as, for example, a temperature sensing portion for detecting the temperature of the main semiconductor element, on the same semiconductor substrate, the manufacturing process can be simplified and costs can be reduced.

[0011] (2) Furthermore, in the semiconductor device according to the present disclosure, in the above-described (1), when the carrier concentration of the drift region is N1, the thickness of the portion of the drift region facing the Schottky barrier diode in the depth direction is t1, the carrier concentration of the well region is N2, and the thickness of the portion of the well region facing the Schottky barrier diode in the depth direction is t2, N2×t2>N1×t1 may be satisfied.

[0012] According to the above disclosure, malfunction of the Schottky barrier diode can be suppressed.

[0013] (3) In the semiconductor device according to the present disclosure, in the above-mentioned (1) or (2), the entire periphery of the outer periphery of the anode electrode may be connected to the well region.

[0014] According to the above disclosure, the characteristics based on the Schottky barrier can be stabilized over the entire area within the plane of the anode electrode.

[0015] (4) In addition, in the semiconductor device according to this disclosure, in any one of (1) to (3) above, the well region may have a two-layer structure including a first well region surrounding the Schottky barrier diode and a second well region surrounding the first well region via the drift region.

[0016] According to the above disclosure, malfunction of the Schottky barrier diode can be further suppressed.

[0017] (5) Furthermore, the semiconductor device according to this disclosure, in any one of (1) to (4) above, may include a plurality of Schottky barrier diodes of the same structure that are arranged adjacent to each other in a direction parallel to the first main surface and connected in series.

[0018] According to the above disclosure, the voltage drop across the Schottky barrier diode can be doubled by the number of Schottky barrier diodes connected in series.

[0019] (6) Furthermore, in any one of (1) to (4) above, the semiconductor device according to this disclosure may include two Schottky barrier diodes of the same structure that are arranged adjacent to each other in a direction parallel to the first main surface and connected in anti-parallel.

[0020] According to the above disclosure, for example, a Schottky barrier diode having a function such as overvoltage protection, which is connected in anti-parallel to a Schottky barrier diode that serves as a temperature sensing section for detecting the temperature of a main semiconductor element, can be provided with the same structure as the temperature sensing section, thereby simplifying the manufacturing process and reducing costs.

[0021] (7) Furthermore, the semiconductor device according to this disclosure may be any one of the above-described (1) to (6), further comprising a surface electrode provided on the second main surface of the semiconductor substrate, and a recombination center may be introduced into at least a portion of the well region on the second main surface side that faces the Schottky barrier diode in the depth direction.

[0022] According to the above disclosure, the operation of the parasitic bipolar transistor can be suppressed, and therefore the malfunction of the Schottky barrier diode can be further suppressed.

[0023] (8) In the semiconductor device according to the present disclosure, in the above-mentioned (7), the recombination center may be a crystal defect caused by protons or helium.

[0024] According to the above disclosure, recombination centers can be easily introduced at predetermined locations.

[0025] (9) In addition, in the semiconductor device according to this disclosure, in any one of the above-mentioned (1) to (8), the material of the anode electrode may be titanium, nickel, molybdenum, aluminum, tungsten, or tantalum, or a silicide of any of these metals.

[0026] According to the above disclosure, the forward voltage of the Schottky barrier diode can be adjusted appropriately.

[0027] (10) In addition, in the semiconductor device according to any one of (1) to (9) above, the carrier concentration of the well region is 1.0×10 17 / cm 3 Above 3.0 x 10 20 / cm 3 It may be the following:

[0028] According to the above disclosure, the well region can be formed by utilizing the manufacturing process for fabricating the main semiconductor element on the semiconductor substrate.

[0029] (11) In addition, in the semiconductor device according to any one of (1) to (10) above, the Schottky barrier diode includes: a cathode contact region selectively provided between the first main surface and the well region, the cathode contact region having the same conductivity type as the anode region and a higher impurity concentration than the anode region; and a cathode electrode in ohmic contact with the cathode contact region on the first main surface. The carrier concentration of the cathode contact region is 1.0×10 18 / cm 3 Above 3.0 x 10 20 / cm 3 It may be the following:

[0030] According to the above disclosure, the cathode contact region can be formed using the manufacturing process for fabricating the main semiconductor element on the semiconductor substrate.

[0031] (12) In addition, in the semiconductor device according to any one of (1) to (11) above, the wide band gap semiconductor may be silicon carbide.

[0032] Furthermore, the forward voltage of the Schottky barrier diode can be adjusted to be approximately the same as the forward voltage of a pn junction diode formed from a silicon layer. In this case, for example, when configuring a temperature sensor using a Schottky barrier diode instead of a pn junction diode, existing measuring equipment and techniques for silicon can be used without changing the specifications.

[0033] <Findings underlying the present disclosure> First, the structure of a semiconductor device of a reference example will be described. FIG. 12 is a cross-sectional view showing the structure of a semiconductor device of a reference example. The semiconductor device 200 of the reference example shown in FIG. 12 includes a semiconductor substrate 201 made of silicon carbide (SiC), a main semiconductor element (not shown), and a temperature sensor 210 for detecting the temperature of the main semiconductor element. The semiconductor substrate 201 is a SiC substrate in which a SiC layer 203 of a predetermined conductivity type is epitaxially grown on the front surface of a starting substrate 202 of a predetermined conductivity type made of SiC. The main surface of the semiconductor substrate 201 facing the SiC layer 203 is the front surface, and the main surface facing the starting substrate 202 (the back surface of the starting substrate 202) is the back surface.

[0034] When the main semiconductor element is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor having an insulated gate made of a three-layer structure of metal-oxide film-semiconductor), a starting substrate 202 (n + -sub) is n + The SiC layer 203 is an n-type drain region. - The temperature sensing section 210 is formed of a silicon (Si) layer 205 deposited on the front surface of the semiconductor substrate 201 via an insulating layer 204.

[0035] A p-type anode region 211 and an n-type cathode region 212 (shown as p-type Si and n-type Si, respectively, in FIG. 12 ) are selectively formed within the Si layer 205 by ion implantation or the like. The p-type anode region 211 and the n-type cathode region 212 are adjacent to each other in a direction parallel to the front surface of the semiconductor substrate 201. A lateral p-n junction diode formed by the p-n junction between the p-type anode region 211 and the n-type cathode region 212 is used as the temperature sensor 210. An anode electrode 213 and a cathode electrode 214 are in ohmic contact with the p-type anode region 211 and the n-type cathode region 212, respectively.

[0036] In the semiconductor device 200 of the reference example described above, the temperature sensing unit 210 is formed using a material different from the main material of the main semiconductor element (SiC, i.e., the semiconductor substrate 201). This means that the temperature sensing unit 210 is formed in a separate process from the process of forming the main semiconductor element, which increases the number of manufacturing processes and increases costs. Therefore, the problem to be solved in this embodiment is to provide an inexpensive semiconductor device that uses the same semiconductor material as the main semiconductor element (i.e., the semiconductor substrate itself), simplifies the manufacturing process, and preferably enables miniaturization, and includes multiple semiconductor elements on the same semiconductor substrate.

[0037] Preferred embodiments of the semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0038] (Details of First Embodiment) A semiconductor device according to a first embodiment that solves the above-mentioned problems will be described below. FIG. 1 is a cross-sectional view showing the structure of a temperature sensing unit of a semiconductor device according to the first embodiment. A semiconductor device 100 according to the first embodiment shown in FIG. 1 includes a main semiconductor element (not shown) and a temperature sensing unit 10 for detecting the temperature of the main semiconductor element, on a semiconductor substrate (semiconductor chip) 101 whose semiconductor material is a semiconductor having a wider band gap than silicon (Si) (hereinafter referred to as wide band gap semiconductor). Here, an example will be described in which silicon carbide (SiC) is used as the wide band gap semiconductor material.

[0039] The semiconductor substrate 101 is a SiC substrate in which a SiC layer 103 of a predetermined conductivity type is epitaxially grown on the front surface of a starting substrate 102 of a predetermined conductivity type made of SiC. The semiconductor substrate 101 has a first main surface on the SiC layer 103 side as the front surface, and a second main surface (the back surface of the starting substrate 102) on the starting substrate 102 side as the back surface. When the main semiconductor element is, for example, a vertical MOSFET, the starting substrate 102 is an n-type + type drain region 11, + On the front surface of the starting substrate 102 of the mold - n-type drift region 1 - A SiC layer 103 is epitaxially grown on the back surface of the semiconductor substrate 101. The surface electrode on the back surface of the semiconductor substrate 101 is the drain electrode 23.

[0040] The temperature sensing section 10 is a lateral Schottky barrier diode (SBD) formed by, for example, ion implantation in the surface region of the front surface of the semiconductor substrate 101. The temperature sensing section 10 is formed using the same semiconductor material as the main semiconductor element and other circuit parts (i.e., the semiconductor substrate 101 itself, in this case, SiC). The temperature sensing section 10 and other elements (the main semiconductor element and other circuit parts) formed in the semiconductor substrate 101 are connected to the p-type well region 2 and the n-type well region 3. - The semiconductor layer is electrically isolated from the semiconductor drift region 1 by a pn junction (pn junction isolation).

[0041] Specifically, the p-type well region 2 is formed on the front surface of the semiconductor substrate 101 and on the n-type well region 2. - The p-type well region 2 is selectively provided between the n-type drift region 1 and the p-type well region 2. The p-type well region 2 is a diffusion region selectively formed by ion implantation inside the SiC layer 103. The p-type well region 2 may have a multi-layer structure in which a plurality of p-type regions with different impurity concentrations are adjacent to each other in the depth direction (the direction perpendicular to the front surface of the semiconductor substrate 101). - The drift region 1 is, in plan view (as viewed from the front surface side of the semiconductor substrate 101: not shown), a temperature sensing unit 10 ( - anode region 3 and n + The cathode contact region 4) is concentrically surrounded by the cathode contact region 4).

[0042] The SiC layer 103 includes an insulated gate structure (not shown) of the main semiconductor element, a p-type well region 2, and an n-type well region 3 (described later). + The portion excluding the cathode contact region 4 is n - n type drift region 1. - The n-type drift region 1 surrounds the p-type well region 2 and reaches the front surface of the semiconductor substrate 101. - The n-type drift region 1 surrounds the temperature sensing section 10 via the p-type well region 2. The p-type well region 2 is fixed to the same potential as the anode electrode 5 at a portion not shown. -The pn junction with the drift region 1 is reverse biased, so that the temperature sensing section 10 is electrically isolated from other elements formed in the semiconductor substrate 101 .

[0043] Between the front surface of the semiconductor substrate 101 and the p-type well region 2, a n-type semiconductor layer constituting the temperature sensing section 10 is provided. - anode region 3 and n + The n-type cathode contact regions 4 are selectively provided. - anode region 3 and n + The n-type cathode contact region 4 is adjacent to each other in a direction parallel to the front surface of the semiconductor substrate 101. - The n-type anode region 3 is formed by forming a SiC layer 103 (n-type anode layer 3) between the front surface of the semiconductor substrate 101 and the p-type well region 2 without ion implantation. - The type drift region 1) is selectively left as it is. + The cathode contact region 4 is a diffusion region selectively formed inside the SiC layer 103 by ion implantation.

[0044] n - The side surface of the anode region 3 and the n + The side surface of the cathode contact region 4 is - anode region 3 and n + The entire surface except for the junction surface with the n-type cathode contact region 4 is surrounded by the p-type well region 2. - anode region 3 and n + type cathode contact region 4 and n - The p-type well region 2 extends between the n-type drift region 1 and the n-type well region 2 up to the front surface of the semiconductor substrate 101. - anode region 3 and n - The width w1 of the portion between the p-type well region 2 and the temperature sensing portion 10 is equal to or greater than the thickness t2 of the portion facing the temperature sensing portion 10 in the depth direction of the p-type well region 2 .

[0045] The n-type well region 2 in the direction parallel to the front surface of the semiconductor substrate 101 + type cathode contact region 4 and n -The width w2 of the portion between the p-type well region 2 and the temperature sensing unit 10 is equal to or greater than the thickness t2 of the portion of the p-type well region 2 facing the temperature sensing unit 10 in the depth direction. - anode region 3 and n - The width w1 of the portion between the p-type well region 2 and the n-type drift region 1 in the direction parallel to the front surface of the semiconductor substrate 101 is + type cathode contact region 4 and n - The width w2 of the portion between the mold drift region 1 and the mold drift region 2 may be approximately the same.

[0046] Therefore, the p-type well region 2 is formed on the lower surface (the surface on the starting substrate 102 side) of the temperature sensing section 10, - The side surface of the anode region 3 and the n + The temperature sensing section 10 is surrounded under the same conditions from at least three directions of the side surface of the p-type cathode contact region 4. The carrier concentration (concentration of activated p-type impurities) N2 of the p-type well region 2, the thickness t2 of the portion of the p-type well region 2 facing the temperature sensing section 10 in the depth direction, and the n - N1, the carrier concentration (concentration of activated n-type impurities) in the n-type drift region 1; - The thickness t1 of the portion of the mold drift region 1 facing the temperature sensing unit 10 in the depth direction satisfies the following formula (1).

[0047] N2×t2>N1×t1 (1)

[0048] That is, the charge amount (=N2×t2) in the portion of the p-type well region 2 facing the temperature sensing unit 10 in the depth direction is expressed as n - The charge amount (=N1×t1) in the portion of the p-type drift region 1 facing the temperature sensing unit 10 in the depth direction is set to be larger than the charge amount (=N1×t1) in the portion of the p-type well region 2 facing the temperature sensing unit 10 in the depth direction. - When the pn junction with the type drift region 1 is reverse biased, a depletion layer spreads from the pn junction, electrically isolating the temperature sensing unit 10 from other elements formed in the semiconductor substrate 101, allowing the temperature sensing unit 10 to operate individually.

[0049] Furthermore, by satisfying the above formula (1), the p-type well region 2 and the n - When the pn junction with the type drift region 1 is reverse biased, n - Even if the portion of the n-type drift region 1 between the starting substrate 102 and the p-type well region 2 is completely depleted, the depletion layer - It is possible to prevent the n-type anode region 3 from being reached (punched through). - By completely depleting the portion of the p-type drift region 1 between the starting substrate 102 and the p-type well region 2, when a surge voltage is applied to the drain electrode 23, it is possible to suppress the flow of electronic current from the drain electrode 23 toward the front surface of the semiconductor substrate 101 into the temperature sensing unit 10.

[0050] In addition, the wider the widths w1 and w2 of the p-type well region 2, the closer the distance between the temperature sensing portion 10 and the n-type well region 2 in the direction parallel to the front surface of the semiconductor substrate 101. - The impurity concentration in the portion between the p-type well region 2 and the n-type drift region 1 can be reduced. By appropriately setting the widths w1 and w2 of the p-type well region 2 and forming the p-type well region 2 by utilizing, as much as possible, the formation processes for each portion of other elements formed in the semiconductor substrate 101, the manufacturing process for the semiconductor device 100 according to the first embodiment can be simplified. When the p-type well region 2 has a multilayer structure in which the impurity concentration varies in the depth direction, it is preferable to make the impurity concentration on the lower surface side of the p-type well region 2 relatively high.

[0051] For example, n - Type drift region 1 (n - The carrier concentration of the anode region 3 is 1.0×10 15 / cm 3 Above 5.0 x 10 16 / cm 3 It is about 3.0 × 10 or less, preferably 15 / cm 3 Above 2.0 x 10 16 / cm 3 The carrier concentration of the p-type well region 2 is preferably about 1.0×10 17 / cm 3 Above 3.0 x 10 20 / cm 3It is about the same as below. + The carrier concentration of the cathode contact region 4 is 1.0×10 18 / cm 3 Above 3.0 x 10 20 / cm 3 It is about the same as below. - An n-type CSL 18 (see FIG. 3 ), which will be described later, may be provided between the n-type drift region 1 and the p-type well region 2 .

[0052] The anode electrode 5 is formed on the front surface of the semiconductor substrate 101. - The anode electrode 5 is in Schottky contact with the n-type anode region 3. The anode electrode 5 is formed of a common metal that forms a Schottky contact with an n-type semiconductor, such as titanium (Ti), nickel (Ni), molybdenum (Mo), aluminum (Al), tungsten (W), or tantalum (Ta), or is formed of a compound (i.e., silicide) of any of these metals with Si. - The temperature characteristic of the forward voltage (voltage drop) of the lateral SBD utilizing the rectification of the Schottky contact formed at the junction with the anode region 3 is utilized as the temperature sensing section 10 .

[0053] The forward voltage of the SBD formed using the semiconductor substrate 101 itself as the material can be adjusted to be approximately the same as the forward voltage of the pn junction diode (temperature sensor 210: see FIG. 12 ) formed in the Si layer 205 on the semiconductor substrate 201, as in the reference example. Therefore, the temperature sensor 10 of the first embodiment can be applied in place of the temperature sensor 210 of the reference example without changing the specifications, allowing existing measurement equipment and measurement techniques to be reused. By appropriately selecting the metal material of the anode electrode 5, the forward voltage of the temperature sensor 10 can be appropriately adjusted. The metal material of the anode electrode 5 is chemically stabilized by being silicided.

[0054] Furthermore, by using an SBD formed using the semiconductor substrate 101 itself as the temperature sensor 10, the forward voltage of the temperature sensor 10 can be lowered compared to a parasitic pn junction diode (body diode) formed inside the semiconductor substrate 101. For example, when SiC is used as the material, the forward voltage of the SBD is approximately 0.5 V to 0.6 V, while the forward voltage of the body diode is approximately 2.2 V to 2.5 V, so the SBD conducts faster than the body diode. Because the temperature characteristics of the forward voltage of the SBD can be obtained individually before being affected by the body diode, the temperature measurement accuracy of the temperature sensor 10 is improved.

[0055] In addition, if a pn junction diode with the p-type well region 2 as a p-type anode region is used as the temperature sensor 10, the body diode operation of the main semiconductor element will cause the p-type well region 2 and the n - If the pn junction with the n-type drift region 1 acts as a body diode, the temperature sensor 10 will malfunction. For this reason, it is necessary to widen the gap between the p-type well region 2 and the main semiconductor element, which increases the size of the semiconductor device 100. On the other hand, in the first embodiment, the temperature sensor 10 is an SBD, and the pn junction with the n-type drift region 1 acts as a body diode. - Since there is no influence of the body diode due to the pn junction with the type drift region 1, the semiconductor device 100 can be made smaller.

[0056] The cathode electrode 6 is formed on the front surface of the semiconductor substrate 101. + The cathode electrode 6 is in ohmic contact with the n-type cathode contact region 4. The cathode electrode 6 can be formed using a common metal material that forms ohmic contact with the semiconductor substrate. When the main semiconductor element is, for example, a MOSFET, the anode electrode 5 can be formed simultaneously with the barrier metal of the main semiconductor element, and the cathode electrode 6 and the n-type cathode contact region 4 are in ohmic contact with the n-type cathode contact region 4. + The cathode contact region 4 is connected to the source electrode of the main semiconductor element and the n-type cathode contact region 4. + The anode electrode 5 and the cathode electrode 6 may also function as electrode pads (anode pad 7 and cathode pad 8: see FIG. 3).

[0057] An application example of the temperature sensing unit 10 described above will be described with reference to FIGS. 2 to 4. FIG. 2 is a plan view showing an example layout of a semiconductor device according to the first embodiment, as viewed from the front surface side of the semiconductor substrate. FIG. 2 shows an example layout of the entire semiconductor substrate 101 of FIG. 1, as viewed from the front surface side. FIG. 3 is a cross-sectional view showing an example cross-sectional structure taken along the cutting line B1-B2-B3 in FIG. 2. FIG. 4 is a circuit diagram showing an equivalent circuit of FIG. 3. Here, a MOSFET 20, which is a main semiconductor element, a temperature sensing unit 10, and other circuit units, such as an overvoltage protection unit 30, a current sensing unit 40, and an arithmetic circuit unit (not shown), are formed on the semiconductor substrate 101 shown in FIG. 1.

[0058] 2 , the semiconductor device 100 according to the first embodiment includes a main semiconductor element 20 and one or more circuit units for protecting and controlling the main semiconductor element 20 in an active region 111 of the same semiconductor substrate 101. The active region 111 has, for example, a substantially rectangular planar shape and is provided approximately in the center (chip center) of the semiconductor substrate 101. In an effective region (hereinafter referred to as the main effective region) 111a of the active region 111, a plurality of unit cells (functional units of the element) of the main semiconductor element 20, which are connected in parallel and have the same structure, are arranged. The main semiconductor element 20 is a vertical MOSFET that performs the main operation of the semiconductor device 100.

[0059] The main effective region 111a is a region through which the main current of the main semiconductor element 20 flows when the semiconductor device 100 is turned on. The main effective region 111a has, for example, a substantially rectangular planar shape and occupies most of the surface area of ​​the active region 111. A circuit unit for protecting and controlling the main semiconductor element 20 is arranged in a main ineffective region 111b of the active region 111 excluding the main effective region 111a. The main ineffective region 111b is a region in which unit cells of the main semiconductor element 20 are not arranged. The main ineffective region 111b has, for example, a substantially rectangular planar shape and is arranged between the main effective region 111a and the edge termination region 112.

[0060] The edge termination region 112 is a region between the active region 111 and the edge (chip edge) of the semiconductor substrate 101, and is adjacent to and surrounds the active region 111. The edge termination region 112 has the function of alleviating the electric field on the front surface side of the semiconductor substrate 101 to maintain a breakdown voltage. A typical breakdown voltage structure (not shown), such as a field limiting ring (FLR), a junction termination extension (JTE) structure, or a guard ring, is disposed in the edge termination region 112. The breakdown voltage is the limit voltage at which a semiconductor device does not malfunction or break down.

[0061] The source pad (electrode pad) 21 of the main semiconductor element 20 is disposed on the front surface of the semiconductor substrate 101 in the main effective region 111a. The main semiconductor element 20 has a higher current capacity than other circuit sections. Therefore, the source pad 21 of the main semiconductor element 20 has substantially the same planar shape as the main effective region 111a and covers substantially the entire surface of the main effective region 111a. Two source pads 21 having a substantially rectangular planar shape may be disposed so as to cover substantially the entire surface of the main effective region 111a. In this case, the portion 111c between the adjacent source pads 21 can be used as, for example, a main invalid region, in which a gate runner or the like can be disposed.

[0062] In addition to the temperature sensing unit 10 described above, for example, an overvoltage protection unit 30, a current sensing unit 40, an arithmetic circuit unit (not shown), etc. may be arranged as circuit units for protecting and controlling the main semiconductor element 20. The gate pad 22 of the main semiconductor element 20, the electrode pads (anode pad 7, cathode pad 8) of the temperature sensing unit 10, the electrode pads (anode pad 31, cathode pad 32) of the overvoltage protection unit 30, the electrode pads (hereinafter referred to as OC pads) 41 of the current sensing unit 40, and the electrode pads (not shown) of the arithmetic circuit unit are arranged on the front surface of the semiconductor substrate 101 in the main ineffective region 111b, away from the other electrode pads.

[0063] The anode pad 7 and cathode pad 8 of the temperature sensing unit 10 may be arranged adjacent to each other. The electrode pads other than the source pad 21 have, for example, a substantially rectangular planar shape and have the surface area necessary for bonding predetermined metal wiring (not shown), such as a terminal pin or wire. FIG. 1 shows a case where the electrode pads other than the source pad 21 are arranged in a row along the inner periphery of the edge termination region 112. FIG. 2 illustrates the source pad 21, gate pad 22, anode pad 7, cathode pad 8, anode pad 31, cathode pad 32, and OC pad 41 as rectangles labeled S, G, A, K, A, K, and OC, respectively.

[0064] The temperature sensing unit 10 has a function of detecting the temperature of the main semiconductor element 20 (semiconductor substrate 101) by utilizing the temperature characteristics of the forward voltage of the SBD. The overvoltage protection unit 30 is a diode that protects the main semiconductor element 20 from overvoltage (OV) such as a surge. The overvoltage protection unit 30 is preferably an SBD having the same structure as the temperature sensing unit 10 (see, for example, Figures 7 and 8 described below). The current sensing unit 40 is connected in parallel to the main semiconductor element 20, operates under the same conditions as the main semiconductor element 20, and has a function of detecting overcurrent (OC) flowing through the main semiconductor element 20.

[0065] The current sense unit 40 is a vertical MOSFET including a smaller number of unit cells having the same configuration as the main semiconductor element 20 than the number of unit cells of the main semiconductor element 20. The unit cells of the current sense unit 40 are arranged adjacent to each other in an area of ​​the semiconductor substrate 101 covered by OC pads 41, and are connected in parallel to each other by the OC pads 41. The arithmetic circuit unit has a function of controlling the temperature sense unit 10, the overvoltage protection unit 30, and the current sense unit 40. The arithmetic circuit unit has a function of controlling the main semiconductor element 20 based on output signals from the current sense unit 40, the temperature sense unit 10, and the overvoltage protection unit 30.

[0066] The arithmetic circuit unit is composed of multiple semiconductor elements, such as CMOS (Complementary MOS) circuits. When diodes other than the temperature sensing unit 10 and the overvoltage protection unit 30 are provided, the other diodes may also be SBDs having the same configuration as the temperature sensing unit 10. A p-type well region 2 for pn junction isolation may extend from the temperature sensing unit 10 side directly below the gate pad 22, directly below the electrode pads of the overvoltage protection unit 30 and other diodes, in the region covered by the OC pad 41 where unit cells of the current sensing unit 40 are not arranged, and directly below the electrode pads of the arithmetic circuit unit.

[0067] The cross-sectional structures of the main semiconductor element 20 and the temperature sensing unit 10 in Fig. 2 will be described with reference to Fig. 3. The main semiconductor element 20 is a vertical MOSFET having a trench gate structure on the front surface (first main surface on the SiC layer 103 side) of the semiconductor substrate 101 in the main effective region 111a. As described above, the semiconductor substrate 101 is made of SiC. + On the front surface of the starting substrate 102 of the mold - The starting substrate 102 is formed by epitaxially growing the n-type SiC layers 103a to 103c in this order. + This is the type drain region 11. The SiC layers 103a to 103c are the SiC layer 103 in FIG.

[0068] The trench gate structure includes a p-type base region 12, an n + type source region 13, p ++ The p-type base region 12, the n-type contact region (not shown), the trench 14, the gate insulating film 15, and the gate electrode 16. + type source region 13 and p ++ The p-type contact region 111a is a diffusion region formed by ion implantation inside the SiC layer 103c. The p-type base region 12 is connected to the front surface of the semiconductor substrate 101 in the main effective region 111a and the n-type base region 12b. - The n-type drift region 1 is provided between the n-type drift region 1 and the n-type drift region 2. + type source region 13 and p ++ The p-type contact regions are selectively provided between the front surface of the semiconductor substrate 101 and the p-type base region 12 .

[0069] n + type source region 13 and p ++ The contact regions are, for example, arranged alternately and repeatedly adjacent to each other in the longitudinal direction of the trenches 14 between the adjacent trenches 14. + type source region 13 and p ++ The n-type contact region is in contact with the source electrode 19 on the front surface of the semiconductor substrate 101. + The source region 13 faces the gate electrode 16 on the sidewall of the trench 14 via the gate insulating film 15. ++ The p-type contact region may not be provided. ++ Instead of the p-type contact region, the p-type base region 12 contacts the source electrode 19 on the front surface of the semiconductor substrate 101 .

[0070] The trench 14 is formed in a depth direction from the front surface of the semiconductor substrate 101. + The source region 13 and the base region 12 are terminated inside a CSL 18 (described later), or the source region 13 is terminated inside a CSL 18 (described later). + The trenches 14 extend linearly in a plan view (as viewed from the front surface side of the semiconductor substrate 101), and a plurality of trenches 14 are arranged adjacent to each other in a stripe pattern. The gate electrodes 16 are provided inside the trenches 14 via gate insulating films 15. An n-type insulating film 16 is provided between the trenches 14 and the outer periphery of the main effective region 111a. + The source region 13 may not be provided.

[0071] p-type base region 12 and n - Between the trench 14 and the drift region 1, the n + On the side of the p-type drain region 11 + A mold region 17 and a CSL 18 are selectively provided. + The p-type base region 17 and the CSL 18 are diffusion regions formed by ion implantation inside the SiC layers 103a and 103b. + type source region 13, p ++ type contact region, p +The portion excluding the p-type region 17 and CSL 18, the p-type well region 2 for pn junction isolation in the main invalid region 111b, and the voltage-resistant structure in the edge termination region 112 is n-type. - This is the type drift region 1.

[0072] n - The drift region 1 extends from the active region 111 to the edge of the chip and is exposed on the front surface of the semiconductor substrate 101 in the main ineffective region 111b and the edge termination region 112. + The p-type region 17 is disposed apart from the p-type base region 12 and faces the bottom surface of the trench 14 in the depth direction. + The type region 17 is fixed to the potential of the source electrode 19 at a portion not shown, and is depleted when the main semiconductor element 20 is turned off (or further depletes the CSL 18), thereby having the function of mitigating the electric field applied to the bottom surface of the trench 14. + The mold region 17 may surround the bottom surface of the trench 14 or may be spaced apart from the bottom surface of the trench 14 .

[0073] The CSL 18 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. - The impurity concentration is higher than that of the n-type drift region 1. + The CSL 18 is an n-type region having a lower impurity concentration than the source region 13. + Between the mold regions 17, p + The CSL 18 is provided in contact with the mold region 17. + The surface on the n-type source region 13 side is in contact with the p-type base region 12, and the bottom surface (n + the surface on the side of the n-type drain region 11 - The CSL 18 is in contact with the p-type base region 12 and the p-type drift region 1. + Between the mold region 17 and the trench 14 .

[0074] CSL18 is p + n than the mold region 17 + The p-type drain region 11 is +The CSL 18 may surround the p-type well region 2 for pn junction isolation directly below the temperature sensing section 10 and the n-type well region 17. - Between the n-type drift region 1 and the p-type well region 2, - The CSL 18 may be omitted. In this case, the n - The p-type drift regions 1 are adjacent to each other. + The p-type base region 12 is connected to the p-type region 17. + Between the mold region 17 and the trench 14 .

[0075] The diffusion region inside the SiC layer 103 may be formed by ion implantation while depositing (epitaxially growing) the SiC layers 103a to 103c. That is, after depositing the SiC layer 103a on the starting substrate 102, p + The p-type base region 12 and the n-type base layer 17 are selectively formed in the SiC layer 103a. After depositing the SiC layer 103b on the SiC layer 103a, the remaining portion of the CSL 18 is formed so as to penetrate the SiC layer 103b in the depth direction. After depositing the SiC layer 103c on the SiC layer 103b, the p-type base region 12 and the n-type base layer 17 are formed in the SiC layer 103c. + type source region 13 and p ++ Mold contact regions are selectively formed respectively.

[0076] The interlayer insulating film 9 is provided on substantially the entire front surface of the semiconductor substrate 101, and covers the gate electrode 16. The gate electrode 16 is electrically connected to a gate pad 22 (see FIG. 2) via a gate runner (not shown). Contact holes 9c and 9d are provided in the main effective region 111a, penetrating the interlayer insulating film 9 in the depth direction. The contact holes 9c and 9d have n + type source region 13 and p ++ When the main semiconductor element 20 is turned off, the n-type contact region is exposed. - A contact (electrical contact portion) is formed to extract minority carriers in the type drift region 1 to the source electrode 19 .

[0077] The source electrode 19 is in ohmic contact with the front surface of the semiconductor substrate 101 through the contact holes 9c and 9d. + type source region 13 and p ++ The source electrode 19 is, for example, a nickel silicide (NixSiy, where x and y are positive numbers) film. The source pad 21 is provided on the interlayer insulating film 9 and the source electrode 19 so as to fill the contact holes 9c and 9d. The source pad 21 is electrically connected to the p-type base region 12 and the n-type contact region 13 via the source electrode 19. + type source region 13 and p ++ The metal layer is electrically connected to the mold contact region.

[0078] The source pad 21 is, for example, an aluminum (Al) film or an Al alloy film. A barrier metal (not shown) may be provided between the source pad 21 and the interlayer insulating film 9 and the source electrode 19. The barrier metal has the function of preventing mutual reaction between regions facing each other across the barrier metal. The barrier metal may be a titanium nitride (TiN) film, a titanium (Ti) film, or the like. The drain electrode 23 is in ohmic contact with the entire back surface (the second main surface on the starting substrate 102 side) of the semiconductor substrate 101, and is n + The drain electrode 23 is electrically connected to the drain region 11. The drain electrode 23 also serves as a drain pad.

[0079] The temperature sensor 10 is a horizontal SBD formed on the surface area of ​​the front surface of the semiconductor substrate 101 in the main ineffective area 111b. - type anode region 3, n + The temperature sensing section 10 includes a p-type well region 2 and an n-type cathode contact region 4, an anode electrode 5, and a cathode electrode 6. - The p-type well region 2 is electrically isolated from the main semiconductor element 20 and other circuit parts by a pn junction with the main ineffective region 111b. - The p-type base region 12 and the p-type drift region 1 of the main semiconductor element 20 are provided between the p-type base region 12 and the p-type drift region 1 of the main semiconductor element 20. + It is connected to the mold area 17 .

[0080] The p-type well region 2 is + p + The p-type region 2a, the p-type region 2b, and the p-type region 2c are adjacent to each other in this order. + The p-type region 2a, the p-type region 2b, and the p-type region 2c are diffusion regions formed by ion implantation inside the SiC layers 103a to 103c. + The mold region 2 a is, for example, a p-type region of the main semiconductor element 20 + The p-type regions 2b and 2c are formed simultaneously with the p-type region 17. The p-type regions 2b and 2c are, for example, extensions of the p-type base region 12 of the main semiconductor element 20. + The p-type region 17 was formed at the same time. + A mold area may be disposed.

[0081] The p-type well region 2 is provided directly below the anode pad 7 and the cathode pad 8, and faces the entire surface of the anode pad 7 and the entire surface of the cathode pad 8 in the depth direction. The p-type well region 2 is electrically connected to the source electrode 19 via, for example, a contact hole 9d. + Type region 2a) and n - CSL 18 of main semiconductor element 20 may extend between p-type well region 2 and temperature sensing unit 10. In this case, thickness t2 and carrier concentration N2 of the portion of p-type well region 2 facing temperature sensing unit 10 in the depth direction are set so as to satisfy the condition obtained by multiplying the charge amount of CSL 18 by the right side of equation (1) above.

[0082] That is, the charge amount (=N2×t2) in the portion of the p-type well region 2 facing the temperature sensing unit 10 in the depth direction is - The charge amount (=n - Carrier concentration of the drift region 1 × n - The carrier concentration of the CSL 18 may be, for example, 1.0×10 17 / cm 3Above 1.0 x 10 18 / cm 3 It is about the following.

[0083] n - anode region 3 and n + The n-type cathode contact region 4 is selectively provided between the front surface of the semiconductor substrate 101 and the p-type well region 2 (p-type region 2c). - anode region 3 and n + The n-type cathode contact region 4 of the main semiconductor element 20 + The distance d1 to the p-type source region 13 is the n-type well region 2 in the direction parallel to the front surface of the semiconductor substrate 101. - Similarly to the widths w1 and w2 (see FIG. 1) of the portions adjacent to the p-type drift region 1, the thickness of the portion facing the temperature sensing section 10 in the depth direction of the p-type well region 2 should be equal to or greater than the thickness t2.

[0084] n - As described above, the n-type anode region 3 is formed by forming a SiC layer 103 (n-type layer 104) on the front surface of the semiconductor substrate 101 and the p-type well region 2 (p-type region 2c). - The type drift region 1) is selectively left as it is. - The mold anode region 3 is provided directly below the anode pad 7 (anode electrode 5) and faces the entire surface of the anode pad 7 in the depth direction. - The anode region 3 has a substantially rectangular planar shape that is larger than the anode pad 7, for example. - The die anode region 3 is exposed to a contact hole 9a that penetrates the interlayer insulating film 9 in the depth direction in the main ineffective region 111b.

[0085] n + The cathode contact region 4 is a diffusion region formed by ion implantation inside the SiC layer 103c, and is, for example, + It is formed at the same time as the n-type source region 13. + The cathode contact region 4 is provided directly below the cathode pad 8 and faces the entire surface of the cathode pad 8 in the depth direction. +The cathode contact region 4 has a substantially rectangular planar shape that is larger than the planar dimensions of the cathode pad 8, for example. + The cathode contact region 4 is exposed to a contact hole 9b that penetrates the interlayer insulating film 9 in the depth direction in the main ineffective region 111b.

[0086] The anode electrode 5 is n-type in the contact hole 9a. - The anode electrode 5 is in Schottky contact with the n-type anode region 3. The anode electrode 5 also serves as, for example, the anode pad 7. The anode electrode 5 is electrically connected to the source pad 21 of the main semiconductor element 20. The anode electrode 5 may be formed, for example, simultaneously with the barrier metal (not shown) of the main semiconductor element 20. The anode electrode 5 has an n-type anode region 3a and a n-type anode region 3b. The anode electrode 5 also serves as, for example, the anode pad 7. The anode electrode 5 is electrically connected to the source pad 21 of the main semiconductor element 20. The anode electrode 5 may be formed, for example, simultaneously with the barrier metal of the main semiconductor element 20. - The semiconductor device may have a multi-layer structure in which the anode pad 7 is in Schottky contact with the anode region 3 and is formed simultaneously with the source pad 21 of the main semiconductor element 20 .

[0087] The cathode electrode 6 is in ohmic contact with the front surface of the semiconductor substrate 101 through the contact hole 9a. + The cathode electrode 6 is electrically connected to the n-type cathode contact region 4. The cathode electrode 6 is formed, for example, at the same time as the source electrode 19 of the main semiconductor element 20. The cathode pad 8 is provided on the cathode electrode 6 so as to fill the contact hole 9b. The cathode pad 8 is electrically connected to the n-type cathode contact region 4 via the cathode electrode 6. + The cathode pad 8 is electrically connected to the cathode contact region 4. The cathode pad 8 is formed, for example, at the same time as the source pad 21 of the main semiconductor element 20.

[0088] The source pad 21, drain pad (drain electrode 23), and gate pad 22 of the main semiconductor element 20 are electrically connected to the source terminal S, drain terminal D, and gate terminal G of the arithmetic circuit unit, respectively. The anode pad 7 of the temperature sensing unit 10 is electrically connected to the source terminal S and anode terminal A of the arithmetic circuit unit. The cathode pad 8 of the temperature sensing unit 10 is electrically connected to the cathode terminal K of the arithmetic circuit unit.

[0089] The operation of the semiconductor device 100 according to the first embodiment will be described. A positive voltage is applied to the drain electrode 23 with respect to the source electrode 19 (source pad 21) of the main semiconductor element 20 (drain-source forward bias). + The p-type region 17 and the p-type base region 12, the CSL 18 and the n - The pn junction between the main semiconductor element 20 and the semiconductor drift region 1 is reverse biased. In this state, if the voltage applied to the gate electrode 16 of the main semiconductor element 20 is less than the gate threshold voltage, the main semiconductor element 20 remains in the off state. A voltage is applied to the current sensing unit 40 under the same conditions as the main semiconductor element 20, and the current sensing unit 40 remains in the off state.

[0090] On the other hand, when a voltage equal to or greater than the gate threshold voltage is applied to the source electrode 19 of the main semiconductor element 20 with the drain-source being forward biased, a channel (n-type inversion layer) is formed in the portion along the trench 14 of the p-type base region 12 of the main semiconductor element 20. As a result, the n-type inversion layer of the main semiconductor element 20 + The n-type drain region 11 passes through the channel + A current Ids flows toward the type source region 13, turning on the main semiconductor element 20. When the main semiconductor element 20 is turned on, a voltage is applied to the current sensing unit 40 under the same conditions as the main semiconductor element 20, turning on the current sensing unit 40.

[0091] When a sense current (current Ids flowing through the channel of the current sense unit 40) flows in the current sense unit 40, the n + A voltage drop occurs in a resistor (not shown) connected between the type source region and the ground point. Since the sense current of the current sense unit 40 increases in accordance with the magnitude of the current flowing through the main semiconductor element 20, the voltage drop in the resistor connected to the current sense unit 40 also increases. Therefore, by monitoring the magnitude of the voltage drop in the resistor connected to the current sense unit 40, it is possible to detect an overcurrent in the main semiconductor element 20.

[0092] During operation of the semiconductor device 100 (while the drain-source of the main semiconductor element 20 is forward biased), the temperature sensing unit 10 always receives n - anode region 3 and n + A forward current If continues to flow through the cathode contact region 4 toward the cathode electrode 6. In addition, during operation of the main semiconductor element 20, for example, an arithmetic circuit unit continues to monitor the forward voltage Vf (voltage drop in the temperature sensing unit 10) that occurs between the anode pad 7 and the cathode pad 8 of the temperature sensing unit 10 at room temperature (for example, about 25° C.).

[0093] The curve (forward voltage characteristics) showing the relationship between the forward current If and the forward voltage Vf of the temperature sensing unit 10 depends on temperature, with the forward voltage Vf decreasing as the temperature increases. By previously acquiring the temperature characteristics of the forward voltage Vf of the temperature sensing unit 10, the temperature of the main semiconductor element 20 (semiconductor substrate 101) can be acquired. When the arithmetic circuit unit detects a decrease in the forward voltage Vf of the temperature sensing unit 10, it determines that a high-temperature portion has occurred in the main semiconductor element 20, and the arithmetic circuit unit stops the supply of gate voltage to the main semiconductor element 20, thereby stopping the operation of the main semiconductor element 20.

[0094] The overvoltage protection unit 30 is connected in anti-parallel to the temperature sensing unit 10, for example (see FIG. 8 described later). The arithmetic circuit unit continuously monitors the forward voltage Vf (voltage drop in the overvoltage protection unit 30) occurring between the anode pad 31 and cathode pad 32 of the overvoltage protection unit 30. When the arithmetic circuit unit detects that the forward voltage Vf of the overvoltage protection unit 30 is an overvoltage that exceeds the withstand voltage of the semiconductor device 100, the arithmetic circuit unit stops the supply of gate voltage to the main semiconductor element 20, thereby stopping the operation of the main semiconductor element 20. This makes it possible to avoid damage to the main semiconductor element 20 due to the application of high voltages such as static electricity.

[0095] As described above, according to the first embodiment, the SBD formed using the semiconductor substrate itself as a material serves as the temperature sensor. The temperature sensor is surrounded by a p-type well region and has a n-type well region. -The temperature sensor and the p-type well region for p-n junction isolation are isolated from the main semiconductor element formed on the semiconductor substrate by a p-n junction with the p-type drift region. The temperature sensor and the p-type well region for p-n junction isolation can be formed using the manufacturing process for the main semiconductor element. This simplifies the manufacturing process and reduces costs.

[0096] In addition, by using the SBD formed using the semiconductor substrate itself as the temperature sensor, the temperature sensor can be - Therefore, the body diode action of the main semiconductor element does not affect the p-type well region and n-type drift region. - Even if the body diode formed by the pn junction with the p-type drift region operates, the temperature sensor section will not malfunction. The distance between the p-type well region and the main semiconductor element can be narrowed, which allows for the miniaturization of the semiconductor device.

[0097] Furthermore, according to the first embodiment, by using an SBD formed using the semiconductor substrate itself as the temperature sensor, the forward voltage of the temperature sensor can be made lower than that of a parasitic pn junction diode (body diode) formed inside the semiconductor substrate, and the temperature sensor becomes conductive earlier than the body diode. This makes it possible to individually obtain the temperature characteristics of the forward voltage of the temperature sensor before it is affected by the body diode, thereby improving the accuracy of temperature measurement by the temperature sensor 10.

[0098] (Details of Second Embodiment) A semiconductor device according to a second embodiment that solves the above-mentioned problems will be described below. Fig. 5 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment. Fig. 6 is a circuit diagram showing the equivalent circuit of Fig. 5. A semiconductor device 120 according to the second embodiment differs from the semiconductor device 100 according to the first embodiment (see Fig. 3) in that the semiconductor device 120 includes a plurality of (here, two) temperature sensing units 10 of the same structure that are arranged adjacent to each other in a row in a direction parallel to the front surface of the semiconductor substrate 101 and connected in series.

[0099] In the second embodiment, the p-type well region 2 collectively surrounds all the temperature sensing units 10 connected in series. - type anode region 3, n + The semiconductor substrate 101 includes a cathode contact region 4, an anode electrode 5, and a cathode electrode 6. Between the front surface of the semiconductor substrate 101 and the p-type well region 2, n electrodes are provided, the number of which is equal to the number of temperature sensing units 10 connected in series. - anode region 3 and n + The cathode contact regions 4 are alternately and repeatedly provided adjacent to each other in a direction parallel to the front surface of the semiconductor substrate 101 .

[0100] n of each temperature sensing unit 10 - Anode electrodes 5 are provided on the respective anode regions 3 via contact holes 9a. + A cathode electrode 6 is provided on each of the cathode contact regions 4 via a contact hole 9b. The anode electrode 5 of the temperature sensing unit 10 on the most upstream (front stage) side also serves as an anode pad 7. The anode pad 7 is electrically connected to the source terminal S and anode terminal A of the arithmetic circuit unit, as in the first embodiment.

[0101] The anode electrodes 5 of the temperature sensing sections 10 other than the most upstream temperature sensing section 10 extend over the interlayer insulating film 9 and are embedded in contact holes 9b exposing the cathode electrodes 6 of the temperature sensing sections 10 in the preceding stage, and are connected to the cathode electrodes 6. A cathode pad 8 is provided on the cathode electrode 6 of the most downstream (rear stage) temperature sensing section 10 so as to embed the contact holes 9b. The cathode pad 8 is electrically connected to the cathode terminal K of the arithmetic circuit section, as in the first embodiment.

[0102] As described above, according to the second embodiment, the voltage drop (forward voltage Vf) in the temperature sensing unit can be doubled by the number of temperature sensing units connected in series, and the same effect as that of the first embodiment can be obtained.

[0103] (Details of Third Embodiment) A semiconductor device according to a third embodiment that solves the above-mentioned problems will be described below. Fig. 7 is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment. Fig. 8 is a circuit diagram showing an equivalent circuit of Fig. 7. A semiconductor device 130 according to the third embodiment is the same as the semiconductor device 100 according to the first embodiment (see Fig. 2), except that it includes a temperature sensing unit 10 and an overvoltage protection unit 30 that have the same structure and are arranged adjacent to each other in a direction parallel to the front surface of the semiconductor substrate 101 and connected in anti-parallel.

[0104] In the third embodiment, the p-type well region 2 collectively surrounds the temperature sensor 10 and the overvoltage protection unit 30, which are connected in antiparallel. - type anode region 33, n + The cathode contact region 34, the anode electrode 35, and the cathode electrode 36 are provided. - type anode region 33, n + The cathode contact region 34, the anode electrode 35, and the cathode electrode 36 are the n-type electrodes of the temperature sensing section 10, respectively. - type anode region 3, n + The cathode contact region 4, the anode electrode 5 and the cathode electrode 6 have the same configuration.

[0105] n - The n-type anode region 33 + The n-type cathode contact region 4 - The anode region 3 is adjacent to the opposite side. + The cathode contact region 34 is an n-type - The n-type anode region 33 + The n-type cathode contact region 4 is adjacent to the n-type cathode contact region 4 on the opposite side. - type anode region 3, n + type cathode contact region 4, n - anode region 33 and n + The cathode contact regions 34 are adjacent to each other in this order in a line in a direction parallel to the front surface of the semiconductor substrate 101 .

[0106] In the main invalid area 111b, contact holes 9e and 9f penetrating the interlayer insulating film 9 in the depth direction are - anode region 33 and n + The n-type cathode contact region 34 is exposed. The anode electrode 35 is - The anode electrode 35 is in Schottky contact with the n-type anode region 33. The anode electrode 35 also serves as the anode pad 31. The cathode electrode 36 is in ohmic contact with the front surface of the semiconductor substrate 101 through the contact hole 9f. + The cathode contact region 34 is electrically connected to the cathode contact region 34 .

[0107] The cathode pad 32 is provided on the cathode electrode 36 so as to fill the contact hole 9f, and is connected to the n-type + The anode electrode 31 is electrically connected to the cathode contact region 34. The anode electrode 35, the cathode electrode 36, and the cathode pad 32 are formed simultaneously with the anode electrode 5, the cathode electrode 6, and the cathode pad 8, respectively. The anode pad 31 is electrically connected to the cathode terminal K of the arithmetic circuit section. The cathode pad 32 is electrically connected to the source terminal S and the anode terminal A of the arithmetic circuit section.

[0108] The second embodiment (see FIGS. 5 and 6) may be applied to the semiconductor device 130 according to the third embodiment, and a plurality of temperature sensing units 10 connected in series may be provided.

[0109] As described above, according to the third embodiment, the structure of the temperature sensing section in the first embodiment can be applied to the overvoltage protection section.

[0110] (Details of the Fourth Embodiment) A semiconductor device according to the fourth embodiment that solves the above-mentioned problems will be described below. FIG. 9 is a cross-sectional view showing the structure of the semiconductor device according to the fourth embodiment. A semiconductor device 140 according to the fourth embodiment differs from the semiconductor device 100 according to the first embodiment (see FIG. 3) in that the lower part (n + The point is that crystal defects 141 that become recombination centers (parts marked with an x) are introduced in the region (part on the side of the silicon-doped silicon-doped drain region 11).

[0111] In the fourth embodiment, at least the temperature sensing unit 10 (n - anode region 3 and n + Crystal defects 141 are introduced into the lower part of the p-type well region 2 directly below the p-type cathode contact region 4. The crystal defects 141 are formed by, for example, protons (H + The crystal defects 141 are introduced by ion implantation of helium (He) or by irradiation of oxygen. The crystal defects 141 act as recombination centers that promote the recombination of carriers near the bottom surface of the p-type well region, and have the function of suppressing the operation of a parasitic npn bipolar transistor.

[0112] Specifically, when the main semiconductor element 20 is in operation, the pn junction between the p-type well region 2 and the CSL 18 is reverse biased, and a positive voltage is applied to the drain electrode 23 of the main semiconductor element 20 relative to the cathode electrode 6 of the temperature sensing unit 10. The potential difference between the drain electrode 23 and the cathode electrode 6 increases, causing electrons to flow into the p-type well region 2, and this electron current acts as a base current to operate the parasitic npn bipolar transistor, causing a collector current Ic to flow from the drain electrode 23 toward the cathode electrode 6, which could cause the temperature sensing unit 10 to malfunction.

[0113] This parasitic npn bipolar transistor is + The p-type cathode contact region 4 serves as an emitter, the p-type well region 2 serves as a base, and the n + type drain region 11 and n - The p-type drift region 1 is the collector, and the forward current If of the temperature sensing unit 10 is the emitter current. Electrons flowing into the p-type well region 2 pass through the p-type well region 2 and the CSL 18 (or the n-type well region 2 if the CSL 18 is not present). - The current diffuses toward the pn junction with the n-type drift region 1) and flows into the drain electrode 23, thereby forming the collector current Ic of the parasitic npn bipolar transistor.

[0114] By introducing crystal defects 141, which serve as recombination centers, into the lower part of the p-type well region 2, carriers recombine and disappear in the lower part of the p-type well region 2. This makes it difficult for electrons to flow from the p-type well region 2 to the drain electrode 23, thereby reducing the amount of collector current Ic of the parasitic npn bipolar transistor. This makes it difficult for the collector current Ic of the parasitic npn bipolar transistor to flow into the p-type well region 2, thereby suppressing malfunction of the temperature sensing unit 10.

[0115] Crystal defects 141 that serve as recombination centers may be introduced below the p-type well region 2 in the semiconductor devices 120 and 130 according to the second and third embodiments (see FIGS. 5 to 8).

[0116] As described above, according to the fourth embodiment, it is possible to obtain the same effects as those of the first to third embodiments. Furthermore, according to the fourth embodiment, it is possible to suppress malfunction of the temperature sensing unit.

[0117] (Details of Fifth Embodiment) A semiconductor device according to a fifth embodiment that solves the above-mentioned problems will be described below. Fig. 10 is a cross-sectional view showing the structure of the semiconductor device according to the fifth embodiment. A semiconductor device 150 according to the fifth embodiment differs from the semiconductor device 100 according to the first embodiment (see Fig. 1) in that the entire outer periphery of the anode electrode 51 of the temperature sensing unit 50 is connected to the p-type well regions 2 and 52.

[0118] In the fifth embodiment, the temperature sensing unit 50 has n - type anode region 3, n + The n-type cathode contact region 4, the anode electrode 51, and the cathode electrode 6 are included. - type anode region 3, n + The configurations of the cathode contact region 4 and the cathode electrode 6 are the same as those of the temperature sensing section 10 of the first embodiment. The configuration of the anode electrode 51, other than the planar dimensions, is the same as that of the anode electrode 5 of the temperature sensing section 10 of the first embodiment.

[0119] The anode electrode 51 is - The anode region 3 has a substantially rectangular planar shape larger than the planar dimensions of the anode region 3, and has an n- The anode electrode 51 faces the entire surface of the p-type anode region 3. Three sides of the periphery of the anode electrode 51 are adjacent to the p-type well region 2 in the depth direction, and the remaining side of the periphery is adjacent to the p-type well region 52 in the depth direction. As a result, the entire periphery of the anode electrode 51 is connected to the p-type well regions 2 and 52.

[0120] The p-type well region 52 is provided in the surface region of the front surface of the semiconductor substrate 101, and - anode region 3 and n + The p-type well region 52 covers the upper end of the junction surface with the n-type cathode contact region 4 (the end on the front surface side of the semiconductor substrate 101). - anode region 3 and n + The electrode extends linearly in a direction parallel to the front surface of the semiconductor substrate 101 along the upper end of the junction surface with the p-type cathode contact region 4 and contacts the p-type well region 2 .

[0121] n - The n-type anode region 3 is surrounded by p-type well regions 2 and 52 in the surface region of the front surface of the semiconductor substrate 101. - However, by connecting the entire outer periphery of the anode electrode 51 to the p-type well regions 2 and 52, the characteristics based on the Schottky barrier can be stabilized over the entire area within the surface of the anode electrode 51.

[0122] The anode electrode 5 of the temperature sensing unit 10 in the semiconductor devices 120, 130, and 140 (see FIGS. 5 to 9) according to the second to fourth embodiments may be replaced with the anode electrode 51 and p-type well region 52 of the fifth embodiment. The anode electrode 35 of the overvoltage protection unit 30 in the semiconductor device 130 (see FIGS. 7 and 8) according to the third embodiment may be replaced with the anode electrode 51 and p-type well region 52 of the fifth embodiment.

[0123] As described above, according to the fifth embodiment, it is possible to obtain the same effects as those of the first embodiment. - The characteristics based on the Schottky barrier with the anode region can be stabilized over the entire area within the plane of the anode electrode.

[0124] (Details of Sixth Embodiment) A semiconductor device according to a sixth embodiment that solves the above-mentioned problems will be described below. Fig. 11 is a cross-sectional view showing the structure of the semiconductor device according to the sixth embodiment. A semiconductor device 160 according to the sixth embodiment differs from the semiconductor device 100 according to the first embodiment (see Fig. 1) in that the temperature sensing unit 60 is electrically isolated (pn junction isolated) from other elements (main semiconductor element and other circuit units) formed in the semiconductor substrate 101 by a two-layer structure of p-type well regions (first and second well regions) 2, 62.

[0125] In the sixth embodiment, the temperature sensing unit 60 has n - type anode region 3, n + The cathode contact region 4, the anode electrode 5, and the cathode electrode 6 are provided. - Similar to the first embodiment, a p-type well region 2 for pn junction isolation is provided between the n-type drift region 1 and the p-type well region 2. + A p-type well region 62 for pn junction isolation is provided between the source and drain regions 11 and at a distance from these regions.

[0126] Between the p-type well region 2 and the p-type well region 62, and between the p-type well region 62 and the n + Between the n-type drain region 11 - The p-type drift region 1 is the n-type well region 62. - The p-type well region 62 surrounds the p-type well region 2 via the anode drift region 1. The p-type well region 62 is fixed to the same potential as the anode electrode 5 at a portion not shown. The p-type well region 62 has the function of stabilizing the potential of the p-type well region 2.

[0127] During the switching operation of the main semiconductor element, a displacement current can be passed through the p-type well region 62, and it is possible to prevent the displacement current from flowing through the p-type well region 2. This makes it possible to prevent the potential of the p-type well region 2 from fluctuating during the switching operation of the main semiconductor element, thereby stabilizing the potential of the p-type well region 2.

[0128] n -In order to prevent the type drift region 1 from being completely depleted in the portion 61 between the p-type well regions 2 and 62, the carrier concentration of the p-type well region 62 is set to be high, or - The thickness t21 of the portion 61 between the p-type well regions 2 and 62 of the drift region 1 and the n-type well region 62 in the depth direction are - Type drift region 1 and n - For example, the p-type well region 62 may be formed as a p-type well for alleviating the electric field at the bottom of the trench 14 of the main semiconductor element. + It may be formed simultaneously with the mold region 17 (see FIG. 3).

[0129] The n-type well regions 2 and 62 in the direction parallel to the front surface of the semiconductor substrate 101 - anode region 3 and n - By widening the widths w1 and w11 of the portions between the p-type well regions 2 and 62 and the n-type drift region 1, the carrier concentration of the portions can be reduced. - anode region 3 and n - The portion between the first and second drift regions 1 may be formed simultaneously with, for example, the p-type base region 12 of the main semiconductor element.

[0130] The n-type well regions 2 and 62 in the direction parallel to the front surface of the semiconductor substrate 101 + type cathode contact region 4 and n - By widening the widths w2 and w12 of the portions between the p-type well regions 2 and 62 and the n-type drift region 1, the carrier concentration of the portions can be reduced. + type cathode contact region 4 and n - The portion between the first and second drift regions 1 may be formed simultaneously with, for example, the p-type base region 12 of the main semiconductor element.

[0131] The p-type well region 62 electrically separates the area surrounded by the p-type well region 62 from the area outside the p-type well region 62. -Instead of the p-type anode region 3, a p-type anode region is formed inside the SiC layer 103 by ion implantation, and the p-type anode region and the n-type anode region are + The temperature sensing section 60 may be a lateral pn junction diode (not shown) formed by a pn junction with the cathode contact region 4 .

[0132] The temperature sensing unit 10 and n in the semiconductor devices 120, 130, and 140 according to the second to fourth embodiments (see FIGS. 5 to 9) + A p-type well region 62 for pn junction isolation may be disposed between the n-type drain region 11 and the overvoltage protection unit 30 in the semiconductor device 130 according to the third embodiment (see FIGS. 7 and 8). + A p-type well region 62 for pn junction isolation may be disposed between the source and drain regions 11 .

[0133] As described above, according to the sixth embodiment, it is possible to obtain the same effects as those of the first embodiment. Furthermore, by forming a two-layer structure including the temperature sensing unit, other elements formed on the semiconductor substrate, and the p-type well region for pn junction isolation, it is possible to further suppress malfunction of the temperature sensing unit.

[0134] The present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the present disclosure. For example, a semiconductor device may be fabricated using a semiconductor substrate made of a wide bandgap semiconductor other than SiC (e.g., gallium nitride (GaN)).

[0135] As described above, the semiconductor device according to the present disclosure is useful as a power semiconductor device used in power conversion devices and power supply devices for various industrial machines and the like.

[0136] 1n - n-type drift regions 2, 52, 62 p-type well regions 2a to 2c p-type regions 3, 33 - Anode region 4, 34 n +1. Type cathode contact region 5, 35, 51, 213 Anode electrode 6, 36, 214 Cathode electrode 7, 31 Anode pad 8, 32 Cathode pad 9 Interlayer insulating film 9a to 9f Contact hole 10, 50, 60, 210 Temperature sensing section 11 n + p-type drain region 12 p-type base region 13 n + Type source region 14 Trench 15 Gate insulating film 16 Gate electrode 17 p + Mold region 18 CSL 19 Source electrode 20 Main semiconductor element 21 Source pad 22 Gate pad 23 Drain electrode 30 Overvoltage protection unit 40 Current sense unit 41 OC pad 61 n - 1. Portion of type drift region between p-type well regions 100, 120, 130, 140, 150, 160, 200 Semiconductor device 101, 201 Semiconductor substrate 102, 202 Starting substrate 103, 103a to 103c, 203 SiC layer 111 Active region 111a Main effective region 111b Main ineffective region 111c Portion between source pads 112 Edge termination region 141 Crystal defects 204 Insulating layer 205 Si layer 206 Surface electrode 211 P-type anode region 212 N-type cathode region A Anode terminal D Drain terminal G Gate terminal K Cathode terminal S Source terminal

Claims

1. A semiconductor device having two or more semiconductor elements inside a semiconductor substrate made of a wide bandgap semiconductor having a bandgap wider than that of silicon, comprising: a drift region provided inside the semiconductor substrate; a well region provided between a first main surface of the semiconductor substrate and the drift region, forming a pn junction with the drift region; and a lateral Schottky barrier diode provided as the semiconductor element and surrounded by the well region, wherein the Schottky barrier diode has: an anode region of the same conductivity type as the drift region, selectively provided between the first main surface and the well region; and an anode electrode making Schottky contact with the anode region at the first main surface.

2. The semiconductor device according to claim 1, characterized in that the following relationship is satisfied: N2×t2>N1×t1, where N1 is the carrier concentration of the drift region, t1 is the thickness of the portion of the drift region facing the Schottky barrier diode in the depth direction, N2 is the carrier concentration of the well region, and t2 is the thickness of the portion of the well region facing the Schottky barrier diode in the depth direction.

3. The semiconductor device according to claim 1, wherein the entire periphery of the outer periphery of said anode electrode is connected to said well region.

4. The semiconductor device according to claim 1, wherein the well region has a two-layer structure consisting of a first well region surrounding the Schottky barrier diode and a second well region surrounding the first well region via the drift region.

5. The semiconductor device according to claim 1, further comprising a plurality of Schottky barrier diodes of the same structure that are arranged adjacent to each other in a direction parallel to the first main surface and connected in series.

6. The semiconductor device according to claim 1, further comprising two Schottky barrier diodes of the same structure arranged adjacent to each other in a direction parallel to the first main surface and connected in anti-parallel.

7. The semiconductor device according to claim 1, further comprising a surface electrode provided on the second main surface of the semiconductor substrate, wherein a recombination center is introduced into at least a portion of the well region on the second main surface side that faces the Schottky barrier diode in the depth direction.

8. The semiconductor device according to claim 7, wherein the recombination centers are crystal defects caused by protons or helium.

9. The semiconductor device according to claim 1, wherein the material of the anode electrode is titanium, nickel, molybdenum, aluminum, tungsten, or tantalum, or a silicide of any of these metals.

10. The carrier concentration of the well region is 1.0×10 17 / cm 3 Above 3.0 x 10 20 / cm 3 2. The semiconductor device according to claim 1, wherein:

11. The Schottky barrier diode comprises: a cathode contact region selectively provided between the first main surface and the well region, the cathode contact region having the same conductivity type as the anode region and a higher impurity concentration than the anode region; and a cathode electrode in ohmic contact with the cathode contact region on the first main surface, wherein the carrier concentration of the cathode contact region is 1.0×10 18 / cm 3 Above 3.0 x 10 20 / cm 3 2. The semiconductor device according to claim 1, wherein:

12. The semiconductor device according to claim 1, wherein said wide band gap semiconductor is silicon carbide.