High-frequency amplifier

Abstract

A high-frequency amplifier (1) is provided with: an input matching circuit (1a); an output matching circuit (1b); FET cells (1c-1 to 1c-4) which are connected to the input matching circuit (1a) and to the output matching circuit (1b), and which are arranged side by side at the boundary between the input side and the output side; and a metal wall (1e) which has a ground potential and is provided between the input matching circuit (1a) and the output matching circuit (1b).

Description

High-frequency amplifier

[0001] The present disclosure relates to high frequency amplifiers.

[0002] In recent years, a technology has been proposed in which a tile-type module, which is a package of high-frequency components including a high-frequency amplifier configured with an MMIC (Monolithic Microwave Integrated Circuit) (hereinafter referred to as an MMIC high-frequency amplifier), is flip-chip mounted. For example, Non-Patent Document 1 describes a high-frequency module with a flip-chip structure. The flip-chip structure is expected to enable high-density integration and also to solve the problem of heat dissipation.

[0003] M. Kimura et al. , “An X-band High Power Tile-Type GaN TR Module for Low-Profile AESA”, 2021 IEEE MTT-S International Microwave Symposium (IMS), Atlanta, GA, USA, 2021, pp. 835-838.

[0004] When an MMIC high-frequency amplifier has a flip-chip structure as described in Non-Patent Document 1, the solid conductors at ground potential provided on the top and bottom of the chip reduce the isolation between the input matching circuit and the output matching circuit, which causes mutual interference and degrades the characteristics.

[0005] The present disclosure is intended to solve the above-mentioned problems, and has an object to provide a high-frequency amplifier that can suppress deterioration of characteristics due to mutual interference between an input matching circuit and an output matching circuit.

[0006] The high-frequency amplifier according to the present disclosure is a high-frequency amplifier configured with an MMIC having solid conductors of ground potential formed on the top and bottom thereof, and includes an input matching circuit, an output matching circuit, a plurality of transistor cells connected to the input matching circuit and the output matching circuit, respectively, and a conductor wall of ground potential provided between the input matching circuit and the output matching circuit.

[0007] According to the high-frequency amplifier of the present disclosure, by providing a conductor wall at ground potential between the input matching circuit and the output matching circuit, it is possible to suppress deterioration of characteristics due to mutual interference between the input matching circuit and the output matching circuit.

[0008] 7 is a top view showing an overview of a configuration example of the high-frequency amplifier according to the first embodiment. FIG. 8 is a top view showing the configuration of an FET cell according to the first embodiment. FIG. 9 is a sectional arrow showing a cross section of the FET cell according to the first embodiment taken along line CC of FIG. 2. FIG. 10 is a graph showing loss calculation results for a transmission line of a high-frequency signal provided in the high-frequency amplifier according to the first embodiment. FIG. 11 is a sectional arrow showing a cross section of a strip line according to the first embodiment taken along line A-A of FIG. 1. FIG. 12 is a sectional arrow showing a cross section of a coplanar line according to the first embodiment taken along line B-B of FIG. 1. FIG. 8 is a top view showing the configuration of an FET cell provided in a first modified example of the high-frequency amplifier according to the first embodiment. FIG. 9 is a sectional arrow showing a cross section of the FET cell of the first modified example taken along line D-D of FIG. 7. FIG. 9 is a top view showing the configuration of an FET cell provided in a second modified example of the high-frequency amplifier according to the first embodiment. FIG. 9 is a sectional arrow showing a cross section of the FET cell of the second modified example taken along line E-E of FIG. FIG. 11 is a top view showing the configuration of an FET cell provided in a third modified example of the high-frequency amplifier according to the first embodiment. FIG. 12 is a top view showing the configuration of an FET cell provided in a fourth modified example of the high-frequency amplifier according to the first embodiment. 12. FIG. 13 is a cross-sectional arrow diagram showing a cross section of an FET cell of Modification 4 taken along line F-F in FIG. 12. FIG. 14 is a top view showing an overview of a configuration example of an input matching circuit provided in a high-frequency amplifier according to a second embodiment. FIG. 15 is a cross-sectional arrow diagram showing a cross section of a matching circuit of Modification 1 of the second embodiment taken along line G-G in FIG. 14. FIG. 16 is a cross-sectional arrow diagram showing a cross section of a matching circuit of Modification 2 of the second embodiment taken along line G-G in FIG. 15. FIG. 17 is a cross-sectional arrow diagram showing a cross section of a matching circuit of Modification 3 of the second embodiment taken along line G-G in FIG.

[0009] First Embodiment. Fig. 1 is a top view showing an outline of a configuration example of a high-frequency amplifier 1 according to a first embodiment. In Fig. 1, the high-frequency amplifier 1 is configured as an MMIC having a flip-chip structure. Although not shown in Fig. 1 for simplicity of explanation, solid conductors at ground potential are formed above and below the high-frequency amplifier 1. As shown in Fig. 1, the high-frequency amplifier 1 is configured to include an input matching circuit 1a, an output matching circuit 1b, FET cells 1c-1 to 1c-4, electrodes 1d-1 to 1d-3, and a metal wall 1e.

[0010] The input matching circuit 1a is a circuit that transmits an input signal from a signal source to the high-frequency amplifier 1 with high efficiency and supplies it to the FET cells 1c-1 to 1c-4. For example, the input matching circuit 1a matches the output impedance of the signal source with the input impedance of the FET cells 1c-1 to 1c-4, thereby enabling maximum power transmission. The output matching circuit 1b is a circuit that efficiently transmits signals from the FET cells 1c-1 to 1c-4 and supplies them to an external load. For example, the output impedance of the FET cells 1c-1 to 1c-4 is matched with the input impedance of the load, thereby enabling maximum power transmission.

[0011] The FET cells 1c-1, 1c-2, 1c-3, and 1c-4 are transistor cells configured with field effect transistors (FETs). In each FET cell, the gate electrode is connected to a transmission line that constitutes the input matching circuit 1a, the source electrode is grounded, and the drain electrode is connected to a transmission line that constitutes the output matching circuit 1b. In the FET cell, the current in the channel is controlled by the voltage applied to the gate electrode. Note that, although FET cells are used as the transistor cells, transistor cells other than FETs can also be used.

[0012] Electrode 1d-1 is a ground potential electrode provided adjacent to FET cell 1c-1 located at one end of FET cells 1c-1, 1c-2, 1c-3, and 1c-4 arranged side by side between input matching circuit 1a and output matching circuit 1b. Electrode 1d-2 is a ground potential electrode provided adjacent to FET cell 1c-4 located at the other end of FET cells 1c-1, 1c-2, 1c-3, and 1c-4 arranged side by side between input matching circuit 1a and output matching circuit 1b.

[0013] 1, the metal wall 1e indicated by the dashed line is configured to include electrodes 1d-1 and 1d-2. This allows the metal wall 1e to sufficiently suppress mutual interference between the input matching circuit 1a and the output matching circuit 1b. Note that if the FET cells 1c-1, 1c-2, 1c-3, and 1c-4 are arranged without any gaps in the chip width direction of the high-frequency amplifier 1, i.e., in the direction in which the multiple FET cells are lined up between the input matching circuit 1a and the output matching circuit 1b, the electrodes 1d-1 and 1d-2 are not essential.

[0014] The electrode 1d-3 is a ground potential electrode provided in the output matching circuit 1b. The electrode 1d-3 is formed adjacent to the strip line in the output matching circuit 1b, and functions as the coplanar line 1b-1.

[0015] The metal wall 1e is a conductive wall at ground potential provided between the input matching circuit 1a and the output matching circuit 1b, and serves to suppress mutual interference between the input matching circuit 1a and the output matching circuit 1b.

[0016] For example, metal wall 1e includes a ground potential electrode 1d-1 provided adjacent to FET cell 1c-1, conductor portions (not shown in FIG. 1 ) of FET cells 1c-1, 1c-2, 1c-3, and 1c-4 provided side by side between input matching circuit 1a and output matching circuit 1b, and a ground potential electrode 1d-2 provided adjacent to FET cell 1c-4. In this manner, metal wall 1e is disposed perpendicular to the transmission direction of the high-frequency signal in high-frequency amplifier 1. This allows metal wall 1e to sufficiently suppress mutual interference between input matching circuit 1a and output matching circuit 1b.

[0017] Even if there are gaps between the FET cells 1c-1, 1c-2, 1c-3, and 1c-4, if the gaps are at ground potential, they can function as metal walls 1e.

[0018] 1 shows a case where there are four FET cells, but the present invention is not limited to this. For example, the number of FET cells may be one, two, or eight. When there is one FET cell, electrodes 1d-1 and 1d-2 are provided at both ends of the single FET cell in a direction perpendicular to the transmission direction of the high-frequency signal.

[0019] 1, in the high-frequency amplifier 1, the transmission line of the input matching circuit 1a is composed of a strip line 1a-1, and the transmission line of the output matching circuit 1b is composed of a coplanar line 1b-1. This makes it possible to achieve lower loss of high-frequency signals compared to when all transmission lines are strip lines, and to achieve higher output power, higher gain, and higher efficiency for the high-frequency amplifier 1.

[0020] However, when different transmission modes are used on the input and output sides, deterioration of the isolation between the input matching circuit 1 a and the output matching circuit 1 b can cause mutual interference, resulting in significant deterioration of characteristics. In contrast, in the high-frequency amplifier 1, the metal wall 1 e suppresses feedback between the FET cells and also suppresses deterioration of isolation, making it possible to suppress deterioration of characteristics due to mutual interference between the input matching circuit 1 a and the output matching circuit 1 b.

[0021] 1 shows the high-frequency amplifier 1 having one amplification stage of FET cells, the amplification stage of FET cells may be two or more. For example, when the amplification stage of FET cells is two, the input matching circuit 1a and the matching circuits between the first amplification stage and the second amplification stage may be configured with strip lines, and the output matching circuit 1b may be configured with a coplanar line.

[0022] Next, the structure of FET cells 1c-1 to 1c-4 will be described. FIG. 2 is a top view showing the configuration of FET cells 1c-1 to 1c-4. Although not shown in FIG. 2 for simplicity, a solid conductor on the top of the MMIC is formed on the top of FET cells 1c-1 to 1c-4. As shown in FIG. 2, FET cells 1c-1 to 1c-4 are each configured to include a gate electrode 11, source electrodes 12-1, 12-2, and 12-3, a drain electrode 13, via holes 14-1 and 14-2, and a pillar 15. The gate electrode 11 is a comb-shaped electrode and has finger electrodes 11-1 to 11-8. The drain electrode 13 is also a comb-shaped electrode and has finger electrodes 13-1 to 13-4.

[0023] The transmission line of the input matching circuit 1a is connected to the gate electrode 11, and the transmission line of the output matching circuit 1b is connected to the drain electrode 13. A finger electrode 13-1 of the drain electrode 13 is arranged between finger electrodes 11-1 and 11-2 of the gate electrode 11, and a source electrode 12-1 is arranged between finger electrodes 11-2 and 11-3 of the gate electrode 11. Similarly, a finger electrode 13-2 of the drain electrode 13 is arranged between finger electrodes 11-3 and 11-4 of the gate electrode 11, and a source electrode 12-2 is arranged between finger electrodes 11-4 and 11-5 of the gate electrode 11. A finger electrode 13-3 of the drain electrode 13 is arranged between finger electrodes 11-5 and 11-6 of the gate electrode 11, and a source electrode 12-3 is arranged between finger electrodes 11-6 and 11-7 of the gate electrode 11. The finger electrode 13-4 of the drain electrode 13 is disposed between the finger electrodes 11-7 and 11-8 of the gate electrode 11.

[0024] The via holes 14-1 and 14-2 are formed at both ends of the FET in the width direction. Furthermore, a pillar 15 is formed directly above the FET. For example, the pillar 15 is a member formed using copper and has conductivity. This allows the formation of a metal wall 1e including the pillar 15. Note that, for ease of explanation, FIG. 2 also shows the configuration of the FET covered from above by the pillar 15.

[0025] Fig. 3 is a cross-sectional arrow diagram showing a cross section of the FET cell shown in Fig. 2 taken along line CC in Fig. 2. As shown in Fig. 3, FET cells 1c-1 to 1c-4 each include finger electrodes 11-1 to 11-8 of gate electrode 11, source electrodes 12-1, 12-2, and 12-3, finger electrodes 13-1 to 13-4 of drain electrode 13, via holes 14-1 and 14-2, pillar 15, electrode 16 on the upper part of the FET, dielectric layer 17, solid conductor 18 on the upper part of the MMIC, solid conductor 19 on the lower part of the MMIC, and base substrate 20.

[0026] Electrode 16 is a conductor portion at ground potential provided in the intermediate portion between solid conductor 18 above the MMIC and solid conductor 19 below the MMIC. Electrode 16 is electrically connected to solid conductor 18 via pillar 15 and to solid conductor 19 via via holes 14-1 and 14-2, and is at ground potential. In the region surrounded by the dashed line in FIG. 3 , a metal at ground potential is formed over the entire region, and a metal wall 1e is formed including this metal and electrode 16. Source electrodes 12-1, 12-2, and 12-3 are connected to electrode 16 and are at ground potential.

[0027] For example, a mold is used for the dielectric layer 17. Polyimide or BCB (Benzocyclobutene) or the like is provided between the mold and the metal for the purpose of protecting the FET or the like.

[0028] The semiconductor material of the FET of the MMIC is, for example, GaN. However, this is not a limitation, and the FET may be made of materials such as GaAs, InP, Si, SiC, or diamond. For the base substrate 20, a substrate such as SiC is used. However, this is not a limitation, and the base substrate 20 may be made of materials such as Si, GaN, or diamond.

[0029] Next, the characteristics of the high-frequency amplifier 1 will be described. FIG. 4 is a graph showing the results of calculations of loss in the transmission lines of high-frequency signals provided in the high-frequency amplifier 1. In FIG. 4, the vertical axis represents loss (dB), and the horizontal axis represents frequency (GHz). The loss calculation result L1 for the coplanar line 1b-1 and the loss calculation result L2 for the strip line 1a-1 were both obtained with a characteristic impedance Zc of 43 Ω, a line length of λ / 4 at 18 GHz, an input terminated at Zc / 5, and an output of 5*Zc, taking into account the impedance transformation function that the circuit of the high-frequency amplifier 1 necessarily possesses.

[0030] As shown in Figure 4, the loss calculation result L1 for the coplanar waveguide is smaller than the loss calculation result L2 for the stripline. This difference is particularly noticeable when handling high-frequency signals, suggesting that coplanar waveguides are more useful as frequencies increase.

[0031] Next, the strip line 1a-1 and the coplanar line 1b-1 will be described. FIG. 5 is a cross-sectional arrow diagram showing a cross section of the strip line 1a-1 taken along line A-A in FIG. 1. As shown in FIG. 5, the strip line 1a-1 includes a dielectric layer 17, a solid conductor 18 above the MMIC, a solid conductor 19 below the MMIC, an underlying substrate 20, and a transmission line 21 for high-frequency signals. The strip line 1a-1 is a transmission line that constitutes the input matching circuit 1a, and electric field lines are formed not only in the solid conductor 19 below the MMIC via the underlying substrate 20 but also in the solid conductor 18 above the MMIC via the dielectric layer 17, resulting in increased loss.

[0032] 6 is a cross-sectional view of the coplanar line 1b-1 taken along line B-B in FIG. 1. As shown in FIG. 6, the coplanar line 1b-1 includes a ground potential electrode 1d-3, via holes 14-1 and 14-2, pillars 15, a dielectric layer 17, a solid conductor 18 above the MMIC, a solid conductor 19 below the MMIC, an undersubstrate 20, and a high-frequency signal transmission line 21. Coplanar line 1b-1 can reduce loss because some of the electric field lines formed in dielectric layer 17 are also formed in the ground potential electrode 1d-3. Furthermore, because coplanar line 1b-1 includes solid conductor 18 above the MMIC and solid conductor 19 below the MMIC, it is sometimes referred to as a grounded coplanar line.

[0033] The loss reduction associated with the change from the strip line 1a-1 to the coplanar line 1b-1 is largely dependent on the physical properties of the substrate 20 and the dielectric layer 17. For example, when the dielectric constant of the substrate 20 provided below the transmission line 21 is 1.5 times or more higher than the dielectric constant of the dielectric layer 17 provided above the transmission line 21, loss is reduced and effective loss reduction is possible. Furthermore, even when the dielectric loss tangent of the dielectric layer 17 provided above the transmission line 21 is more than twice as high as the dielectric loss tangent of the substrate 20 provided below the transmission line 21, loss is reduced and effective loss reduction is possible. Furthermore, even when the effective dielectric constant of the substrate 20 provided below the transmission line 21 is more than twice as high as the effective dielectric constant of the dielectric layer 17 provided above the transmission line 21, loss is reduced and effective loss reduction is possible.

[0034] (Variation 1) Variation 1 of the high-frequency amplifier 1 includes pillars 15 at ground potential arranged at both ends of the FET cell, and the electrodes 16 are electrically connected to a solid conductor 18 above the MMIC and a solid conductor 19 below the MMIC via the pillars 15. FIG. 7 is a top view showing an example configuration of FET cells 1c-1 to 1c-4 included in Variation 1 of the high-frequency amplifier 1. As shown in FIG. 7, the FET cell of Variation 1 includes a gate electrode 11, source electrodes 12-1, 12-2, and 12-3, a drain electrode 13, via holes 14-1 and 14-2, a pillar 15, and an electrode 16 at the top of the FET. In FIG. 7, in the FET of Variation 1, the pillars 15 are provided at both ends of the FET cell rather than at the top of the FET. The electrodes 16 shown in FIG. 7 are strip-shaped electrodes extending across the via holes 14-1 and 14-2 at both ends of the FET cell.

[0035] Electrode 16 is connected to solid conductor 18 on the top of the MMIC and via holes 14-1 and 14-2 via pillar 15, and is at ground potential. Source electrodes 12-1, 12-2, and 12-3 may be formed like bridge beams for electrode 16, and electrode 16 may be formed to have the same width as source electrodes 12-1, 12-2, and 12-3.

[0036] 8 is a cross-sectional view of FET cells 1c-1 to 1c-4 of Modification 1 taken along line D-D in FIG. As shown in FIG. 8, FET cells 1c-1 to 1c-4 each include finger electrodes 11-1 to 11-8 of gate electrode 11, source electrodes 12-1, 12-2, and 12-3, finger electrodes 13-1 to 13-4 of drain electrode 13, via holes 14-1 and 14-2, pillar 15, electrode 16 on the upper part of the FET, dielectric layer 17, solid conductor 18 on the upper part of the MMIC, solid conductor 19 on the lower part of the MMIC, and base substrate 20. By using source electrodes 12-1, 12-2, and 12-3 as bridges for electrode 16, a metal wall 1e at ground potential can be formed. This allows metal wall 1e to sufficiently suppress mutual interference between input matching circuit 1a and output matching circuit 1b.

[0037] (Variation 2) In Variation 2 of the high-frequency amplifier 1, the FET cells 1c-1 to 1c-4 are ISVs (Individual Source Vias) that include source electrodes 21-1 to 21-3 with via holes. The source electrodes 21-1 to 21-3 are electrically connected to an upper solid conductor 18 and a lower solid conductor 19, and include pillars 15 of a ground potential conductor disposed at both ends of the FET cells. The electrode 16 is electrically connected to the upper solid conductor 18 and the lower solid conductor 19 via the via holes and the pillars 15. FIG. 9 is a top view showing the configuration of the FET cells 1c-1 to 1c-4 included in Variation 2 of the high-frequency amplifier 1. As shown in FIG. 9, the FET cell of the second modification includes a gate electrode 11, source electrodes 21-1, 21-2, and 21-3, a drain electrode 13, via holes 14-1 and 14-2, a pillar 15, and an electrode 16 on the top of the FET.

[0038] Even when the FET cell has an ISV structure, pillars 15 are arranged at both ends of the FET cell, as in Modification 1. The arrangement of electrodes 16 shown in Fig. 9 is one example. As another configuration, for example, bridge beams may be formed at both ends of source electrodes 21-1, 21-2, 21-3, 21-4, and 21-5, or electrodes 16 may be formed to have the same width as source electrodes 21-1, 21-2, 21-3, 21-4, and 21-5.

[0039] Fig. 10 is a cross-sectional arrow diagram showing a cross section of FET cells 1c-1 to 1c-4 of Modification 2 taken along line E-E in Fig. 9. As shown in Fig. 10, electrode 16 is at ground potential because it is electrically connected to solid conductor 19 below the MMIC via source electrodes 21-1, 21-2, 21-3, 21-4, and 21-5 of the ISVs and to solid conductor 18 above the MMIC via pillar 15. As a result, electrode 16 is one of the elements constituting metal wall 1e.

[0040] 10, the FET cell includes a metal wall 1e at ground potential, finger electrodes 11-1, 11-2, 11-3, 11-4, 11-5, 11-6, 11-7, and 11-8 of a gate electrode 11, source electrodes 21-1, 21-2, 21-3, 21-4, and 21-5 of an ISV, finger electrodes 13-1, 13-2, 13-3, and 13-4 of a drain electrode 13, a pillar 15, an electrode 16 on the upper part of the FET, a dielectric layer 17, a solid conductor 18 on the upper part of the MMIC, a solid conductor 19 on the lower part of the MMIC, and an underlying substrate 20. This allows the metal wall 1e to sufficiently suppress mutual interference between the input matching circuit 1a and the output matching circuit 1b.

[0041] (Variation 3) Variation 3 of the high-frequency amplifier 1 includes pillars 15 of conductors at ground potential arranged on the input sides of both ends of the FET cell, which is an ISV. Electrode 16 is electrically connected to upper solid conductor 18 and lower solid conductor 19 via pillars 15. FIG. 11 is a top view showing the configuration of FET cells 1c-1 to 1c-4 included in Variation 3 of the high-frequency amplifier. The FET cell according to Variation 3 includes finger electrodes 11-1 and 11-2 of gate electrode 11, source electrodes 12-1, 12-2, 12-3, 12-4, 12-5, and 12-6, finger electrodes 13-1 and 13-2 of drain electrode 13, pillar 15, and FET upper electrodes 16-1 and 16-2.

[0042] 11 shows two FET cells. Pillar 15 is not disposed between the FET cells, but is shifted toward the gate side (input side) and connected to via holes 14-1, 14-2, 14-3, and 14-4. Electrodes 16-1 and 16-2 on the top of the FET are connected to solid conductor 18 above the MMIC and solid conductor 19 below the MMIC via via holes 14-1, 14-2, 14-3, and 14-4 and pillar 15, and are thus at ground potential. As a result, electrodes 16-1 and 16-2 become one of the elements constituting metal wall 1e.

[0043] The spacing between the pillars 15 must be λ / 4 or less, and preferably about λ / 8, where λ is the wavelength of the upper limit frequency of the band being used. The placement of the pillars 15 shown in FIG. 11 is just an example, and they can also be placed on the drain electrode side, for example.

[0044] (Variation 4) Variation 4 of high-frequency amplifier 1 includes via holes 14-1 and 14-2 disposed at both ends of FET cells 1c-1 to 1c-4 and electrically connected to upper solid conductor 18 and lower solid conductor 19, and pillars 15 of a conductor at ground potential disposed directly above via holes 14-1 and 14-2. Electrode 16 is electrically connected to the upper solid conductor and lower solid conductor via via holes 14-1 and 14-2 and pillar 15.

[0045] 12 is a top view showing the configuration of FET cells 1c-1 to 1c-4 included in Modification 4 of the high-frequency amplifier 1. Modification 4 shows an FET cell in which pillars 15 are formed on via holes 14-1 and 14-2. The FET cell shown in FIG. 12 includes a gate electrode 11, source electrodes 12-1, 12-2, and 12-3, a drain electrode 13, via holes 14-1 and 14-2, pillars 15, and an electrode 16 on the top of the FET.

[0046] Fig. 13 is a cross-sectional arrow view showing a cross section of FET cells 1c-1 to 1c-4 of Modification 4 taken along line F-F in Fig. 12. The FET cell of Fig. 13 includes a metal wall 1e at ground potential, finger electrodes 11-1, 11-2, 11-3, 11-4, 11-5, 11-6, 11-7, and 11-8 of gate electrode 11, source electrodes 12-1, 12-2, and 12-3, finger electrodes 13-1, 13-2, 13-3, and 13-4 of drain electrode 13, via holes 14-1 and 14-2, pillar 15, electrode 16 on the upper part of the FET, dielectric layer 17, solid conductor 18 on the upper part of the MMIC, solid conductor 19 on the lower part of the MMIC, and base substrate 20.

[0047] 12, in Modification 4, pillar 15 is disposed above the via hole, not above the FET. In this case, electrode 16 above the FET is also connected to solid conductor 18 above the MMIC and via holes 14-1 and 14-2 via pillar 15, and is at ground potential. Furthermore, source electrodes 12-1, 12-2, and 12-3 form a bridge beam, which becomes one of the elements constituting metal wall 1e at ground potential.

[0048] 12 is an example. As an alternative, for example, bridge beams may be formed at both ends of the source electrodes 12-1, 12-2, and 12-3, or the electrodes 16 may be formed to have the same width as the source electrodes 12-1, 12-2, and 12-3.

[0049] As described above, the high-frequency amplifier 1 according to the first embodiment is a high-frequency amplifier 1 configured with an MMIC having solid conductors at ground potential formed on the upper and lower parts thereof, and includes an input matching circuit 1a, an output matching circuit 1b, FET cells 1c-1 to 1c-4 connected to the input matching circuit 1a and the output matching circuit 1b, and a metal wall 1e at ground potential provided between the input matching circuit 1a and the output matching circuit 1b. By providing the metal wall 1e at ground potential provided between the input matching circuit 1a and the output matching circuit 1b, it is possible to suppress deterioration of characteristics due to mutual interference between the input matching circuit 1a and the output matching circuit 1b.

[0050] The high-frequency amplifier 1 according to the first embodiment includes electrodes 1d-1 and 1d-2 at ground potential that are provided adjacent to the FET cells 1c-1 and 1c-4 at both ends of the FET cells 1c-1 to 1c-4 that are arranged side by side. The metal wall 1e is configured to include the electrodes 1d-1 and 1d-2. This allows the metal wall 1e to sufficiently suppress mutual interference between the input matching circuit 1a and the output matching circuit 1b.

[0051] In the high-frequency amplifier 1 according to the first embodiment, the FET cells 1c-1 to 1c-4 have an electrode 16 at ground potential provided in an intermediate portion between the solid conductor above the MMIC and the solid conductor below the MMIC, and the metal wall 1e is configured to include the electrodes 16 of the FET cells 1c-1 to 1c-4. This allows the metal wall 1e to sufficiently suppress mutual interference between the input matching circuit 1a and the output matching circuit 1b.

[0052] In the high-frequency amplifier 1 according to the first embodiment, the input matching circuit 1a is configured to include a strip line 1a-1, and the output matching circuit 1b is configured with a coplanar line 1b-1 formed by a line arranged on the output side via a metal wall 1e and a grounded electrode 1d-3. This enables the high-frequency amplifier 1 to achieve high output power, high gain, and high efficiency.

[0053] The high-frequency amplifier 1 according to the first embodiment includes pillars 15 disposed directly above the FET cells 1c-1 to 1c-4, and the electrodes 16 are electrically connected to the upper and lower solid conductors via the pillars 15. This allows the formation of a metal wall 1e including the pillars 15.

[0054] Modification 1 of the high-frequency amplifier 1 according to the first embodiment includes pillars 15 disposed on both ends of the FET cells 1c-1 to 1c-4, and the electrodes 16 are electrically connected to the upper solid conductor 18 and the lower solid conductor 19 via the pillars 15. This allows the metal wall 1e to sufficiently suppress mutual interference between the input matching circuit 1a and the output matching circuit 1b.

[0055] Variation 2 of the high-frequency amplifier 1 according to the first embodiment includes conductor pillars 15 at ground potential arranged at both ends of the FET cells. FET cells 1c-1 to 1c-4 have source electrodes 21-1 to 21-3 with via holes. Source electrodes 21-1 to 21-3 are electrically connected to upper solid conductor 18 and lower solid conductor 19, and electrode 16 is electrically connected to upper solid conductor 18 and lower solid conductor 19 via the via holes and pillars 15. This allows metal wall 1e to sufficiently suppress mutual interference between input matching circuit 1a and output matching circuit 1b.

[0056] The third modification of the high-frequency amplifier 1 according to the first embodiment includes conductor pillars 15 of ground potential arranged on the input side of both ends of the FET cell. The electrode 16 is electrically connected to the upper solid conductor 18 and the lower solid conductor 19 via the pillars 15. This allows the metal wall 1e to sufficiently suppress mutual interference between the input matching circuit 1a and the output matching circuit 1b.

[0057] A fourth variation of the high-frequency amplifier 1 according to the first embodiment includes via holes 14-1 and 14-2 disposed at both ends of the FET cells 1c-1 to 1c-4 and electrically connected to the upper and lower solid conductors, and a pillar 15 of a ground potential conductor disposed directly above the via holes 14-1 and 14-2. An electrode 16 is electrically connected to the upper and lower solid conductors via the via holes 14-1 and 14-2 and the pillar 15. This allows the metal wall 1e to sufficiently suppress mutual interference between the input matching circuit 1a and the output matching circuit 1b.

[0058] In the high-frequency amplifier 1 according to the first embodiment, in the transmission line 21 of a high-frequency signal in each of the lines 1a-1 and 1b-1 constituting the input matching circuit 1a and the output matching circuit 1b, the dielectric constant of the base substrate 20 provided below the transmission line 21 is 1.5 times or more higher than the dielectric constant of the dielectric layer 17 provided above the transmission line 21. This reduces the loss in the transmission line 21, enabling effective loss reduction.

[0059] In the high-frequency amplifier 1 according to the first embodiment, in the transmission line 21 of a high-frequency signal in each of the lines 1a-1 and 1b-1 constituting the input matching circuit 1a and the output matching circuit 1b, the dielectric loss tangent of the dielectric layer 17 provided on the upper part of the transmission line 21 is at least twice as high as the dielectric loss tangent of the base substrate 20 provided on the lower part of the transmission line 21. This reduces the loss in the transmission line 21, enabling effective loss reduction.

[0060] In the high-frequency amplifier 1 according to the first embodiment, in the transmission line 21 of a high-frequency signal in each line constituting the input matching circuit 1a and the output matching circuit 1b, the effective dielectric constant of the base substrate 20 provided below the transmission line 21 is at least twice as high as the effective dielectric constant of the dielectric layer 17 provided above the transmission line 21. This reduces the loss in the transmission line 21, enabling effective loss reduction.

[0061] In the high-frequency amplifier 1 according to the first embodiment, the metal wall 1 e is disposed perpendicular to the transmission direction of the high-frequency signal, thereby enabling the metal wall 1 e to sufficiently suppress mutual interference between the input matching circuit 1 a and the output matching circuit 1 b.

[0062] Second Embodiment In the first embodiment, an example was shown in which the input matching circuit 1a and the output matching circuit 1b were formed only with transmission lines, but in the second embodiment, a high-frequency amplifier will be described in which a metal wall 1e is provided in the matching circuit.

[0063] FIG. 14 is a top view showing an outline of a configuration example of an input matching circuit 1a included in a high-frequency amplifier 1 according to a second embodiment. As shown in FIG. 14, the input matching circuit 1a of the high-frequency amplifier 1 according to the second embodiment includes matching circuits 1f-1 and 1f-2, a matching circuit 1g connected to the matching circuits 1f-1 and 1f-2, and a metal wall 1e at ground potential provided between the matching circuits 1f-1 and 1f-2. The matching circuit 1f-1 is a first matching circuit on the input side, and the matching circuit 1f-2 is a second matching circuit on the output side different from the matching circuit 1f-1. The matching circuit 1g is a third matching circuit connected to the matching circuits 1f-1 and 1f-2. The electrode 1d-1 is a ground potential electrode provided at one end of the matching circuit 1g. The electrode 1d-2 is a ground potential electrode provided at the other end of the matching circuit 1g. Although FIG. 14 shows an input matching circuit 1a, a similar configuration may be applied to an output matching circuit or an inter-stage matching circuit.

[0064] For example, metal wall 1e includes electrode 1d-1 at ground potential, matching circuit 1g, and electrode 1d-2 at ground potential. In this manner, metal wall 1e is arranged perpendicular to the transmission direction of the high-frequency signal in matching circuit 1g. This allows metal wall 1e to sufficiently suppress mutual interference between matching circuits 1f-1 and 1f-2.

[0065] In the second embodiment, it is also necessary to ensure isolation to prevent mutual interference when the transmission mode is changed. For this reason, the matching circuit also has a metal wall 1e at ground potential. Also, while Figure 14 shows a configuration in which grounded electrodes 1d-1 and 2d-2 are provided, there is no problem in omitting the matching circuit 1g if it is sufficiently large compared to the chip width.

[0066] Next, a specific configuration of the matching circuit 1g will be described. Fig. 15 is a cross-sectional arrow diagram showing a cross section of the matching circuit 1g taken along line G-G in Fig. 14. As shown in Fig. 15, the matching circuit 1g has an MIM (Metal-Insulator-Metal) formed on a via hole 14. The matching circuit 1g includes the via hole 14, a dielectric layer 17, a solid conductor 18 above the MMIC, a solid conductor 19 below the MMIC, a dielectric layer 22, and an upper electrode 23 of the MIM.

[0067] The via hole 14 shown in FIG. 15 is electrically connected to the electrodes 1d-1 and 2d-2 shown in FIG. 14. This forms a metal wall 1e at ground potential. The MIM upper electrode 23 is connected to the transmission lines of the matching circuits 1f-1 and 1f-2 in FIG. 14. The dielectric layer 22 is made of a material such as SiN. The upper electrode 23 and the electrode of the via hole 14 generate capacitance, which operates as a parallel MIM capacitor. This allows for low loss.

[0068] A first modification of the matching circuit 1g according to the second embodiment will now be described. FIG. 16 is a cross-sectional arrow diagram showing a cross section of the matching circuit 1g according to the first modification of the second embodiment taken along line G-G in FIG. 15. The matching circuit 1g according to the first modification includes a pillar 15, a solid conductor 18 above the MMIC, a solid conductor 19 below the MMIC, a base substrate 20, a dielectric layer 22, and an MIM top electrode 23. The top electrode 23 is connected to the solid conductor 18 above the MMIC via the pillar 15 and is therefore at ground potential. Furthermore, the top electrode 23 is electrically connected to the grounded electrodes 1d-1 and 1d-2 and can therefore be one of the elements constituting the metal wall 1e. The top electrode 23 and the base electrode 24 generate capacitance, functioning as a parallel MIM capacitor.

[0069] A second modification of the matching circuit 1g according to the second embodiment will now be described. FIG. 17 is a cross-sectional view of the matching circuit 1g according to the second modification of the second embodiment, taken along line G-G in FIG. 15 . The matching circuit 1g shown in FIG. 17 utilizes multiple wiring layers to form a thin-film microstrip line. This allows for low loss. For example, as shown in FIG. 17 , the matching circuit 1g includes a via hole 14, a pillar 15, a dielectric layer 17, a solid conductor 18 above the MMIC, a solid conductor 19 below the MMIC, a base substrate 20, a high-frequency signal transmission line 21, an MIM upper electrode 23, and a ground conductor 25 for the thin-film microstrip line.

[0070] The ground conductor 25 for the thin-film microstrip line is connected to the solid conductor 19 below the MMIC via the via hole 14 and to the solid conductor 18 above the MMIC via the pillar 15, and is at ground potential. The ground conductor 25 is electrically connected to the electrodes 1d-1 and 1d-2, and thereby becomes one of the elements constituting the metal wall 1e at ground potential.

[0071] 17 , either the via hole 14 or the pillar 15 is sufficient to set the ground conductor 25 to the ground potential, so either one may be omitted. Furthermore, since the distance between the high-frequency signal transmission line 21 and the ground conductor 25 is extremely small compared to the solid conductor 18 above the MMIC, almost no electric field lines are formed in the solid conductor 18 above the MMIC. Therefore, the distance between the transmission line 21 and the ground conductor 25 should be ⅕ or less.

[0072] A third modification of the matching circuit 1g according to the second embodiment will now be described. Fig. 18 is a cross-sectional arrow diagram showing a cross section of the matching circuit 1g according to the third modification of the second embodiment, taken along line G-G in Fig. 15. The matching circuit 1g shown in Fig. 18 forms a thin-film microstrip line by taking advantage of the presence of multiple wiring layers. In the matching circuit 1g shown in Fig. 18, the vertical relationship between the high-frequency signal transmission line 21 and the ground conductor 25 for the thin-film microstrip line is reversed compared to the second modification shown in Fig. 17.

[0073] The matching circuit 1g of the third modification includes a via hole 14, a pillar 15, a dielectric layer 17, a solid conductor 18 above the MMIC, a solid conductor 19 below the MMIC, an underlying substrate 20, a high-frequency signal transmission line 21, an MIM upper electrode 23, and a ground conductor 25 for the thin-film microstrip line. The ground conductor 25 is electrically connected to the solid conductor 19 below the MMIC via the via hole 14 and to the solid conductor 18 above the MMIC via the pillar 15, and is at ground potential. The ground conductor 25 is electrically connected to electrodes 1d-1 and 1d-2, thereby becoming one of the elements constituting the metal wall 1e at ground potential.

[0074] The distance between the high-frequency signal transmission line 21 and the ground conductor 25 for the thin-film microstrip line is extremely small compared to the solid conductor 18 above the MMIC, so electric lines of force are hardly formed in the solid conductor 19 below the MMIC. Therefore, the distance between the transmission line 21 and the ground conductor 25 should be 1 / 5 or less.

[0075] As described above, in the high-frequency amplifier 1 according to the second embodiment, at least one of the input matching circuit 1a and the output matching circuit 1b includes matching circuit 1f-1, matching circuit 1f-2, matching circuit 1g connected to matching circuit 1f-1 and matching circuit 1f-2, respectively, and metal wall 1e at ground potential provided between matching circuit 1f-1 and matching circuit 1f-2. By providing metal wall 1e at ground potential provided between matching circuit 1f-1 and matching circuit 1f-2, it is possible to suppress deterioration of characteristics due to mutual interference between matching circuit 1f-1 and matching circuit 1f-2.

[0076] High-frequency amplifier 1 according to the second embodiment includes electrodes 1d-1 and 1d-2 at ground potential provided at both ends of matching circuit 1g. Metal wall 1e is configured to include electrodes 1d-1 and 1d-2. This allows metal wall 1e to sufficiently suppress mutual interference between matching circuits 1f-1 and 1f-2.

[0077] In the high-frequency amplifier 1A according to the second embodiment, the matching circuit 1g is configured to include MIM capacitors connected in parallel, thereby enabling a reduction in loss.

[0078] In the high-frequency amplifier 1A according to the second embodiment, the matching circuit 1g is configured to include microstrip lines connected in parallel, thereby enabling a reduction in loss.

[0079] In the high-frequency amplifier 1A according to the second embodiment, the metal wall 1e is disposed perpendicular to the transmission direction of the high-frequency signal, thereby enabling the metal wall 1e to sufficiently suppress mutual interference between the matching circuits 1f-1 and 1f-2.

[0080] Various aspects of the present disclosure are summarized below as appendices.

[0081] (Supplementary Note 1) A high-frequency amplifier formed with a monolithic microwave integrated circuit having solid conductors at ground potential formed on its upper and lower parts, comprising: an input matching circuit; an output matching circuit; a transistor cell connected to the input matching circuit and the output matching circuit; and a conductive wall at ground potential provided between the input matching circuit and the output matching circuit. (Supplementary Note 2) The high-frequency amplifier according to Supplementary Note 1, further comprising: electrodes at ground potential provided on both ends of the transistor cell or adjacent to the transistor cell located at both ends of a plurality of the transistor cells arranged side by side, the conductive wall including the electrodes. (Supplementary Note 3) The high-frequency amplifier according to Supplementary Note 1 or Supplementary Note 2, further comprising: electrodes at ground potential provided on both ends of the transistor cell or adjacent to the transistor cell located at both ends of a plurality of the transistor cells arranged side by side, the conductive wall including the electrodes. (Supplementary Note 4) The high-frequency amplifier according to any one of Supplementary Note 1 to Supplementary Note 3, characterized in that the input matching circuit is configured to include a strip line, and the output matching circuit is configured to include a coplanar line formed by a line arranged on the output side via the conductor wall and a grounded electrode. (Supplementary Note 5) The high-frequency amplifier according to Supplementary Note 3, characterized in that it includes a conductor pillar of ground potential arranged directly above the transistor cell, and the conductor portion is electrically connected to the upper solid conductor and the lower solid conductor via the pillar. (Supplementary Note 6) The high-frequency amplifier according to Supplementary Note 3, characterized in that it includes a conductor pillar of ground potential arranged at both ends of the transistor cell, and the conductor portion is electrically connected to the upper solid conductor and the lower solid conductor via the pillar.(Supplementary Note 7) The high-frequency amplifier according to Supplementary Note 3, further comprising: a conductor pillar at ground potential arranged on both ends of the transistor cell, the transistor cell having an electrode with a via hole, the electrode with the via hole electrically connected to the upper solid conductor and the lower solid conductor, and the conductor portion electrically connected to the upper solid conductor and the lower solid conductor via the via hole and the pillar. (Supplementary Note 8) The high-frequency amplifier according to Supplementary Note 3, further comprising: a conductor pillar at ground potential arranged on the input side of both ends of the transistor cell, the conductor portion electrically connected to the upper solid conductor and the lower solid conductor via the pillar. (Supplementary Note 9) The high-frequency amplifier according to Supplementary Note 3, comprising: an electrical connection portion disposed at both ends of the transistor cell and electrically connected to the upper solid conductor and the lower solid conductor; and a conductor pillar of ground potential disposed directly above the electrical connection portion, wherein the conductor portion is electrically connected to the upper solid conductor and the lower solid conductor via the electrical connection portion and the pillar. (Supplementary Note 10) The high-frequency amplifier according to any one of Supplementary Notes 1 to 9, wherein, in a transmission line of a high-frequency signal in each of the lines constituting the input matching circuit and the output matching circuit, the dielectric constant of an underlying substrate provided below the transmission line is 1.5 times or more higher than the dielectric constant of a dielectric layer provided above the transmission line. (Supplementary Note 11) The high-frequency amplifier according to any one of Supplementary Note 1 to Supplementary Note 9, characterized in that, in the transmission lines of high-frequency signals in each of the lines constituting the input matching circuit and the output matching circuit, the dielectric loss tangent of the dielectric layer provided above the transmission line is at least twice as high as the dielectric loss tangent of the base substrate provided below the transmission line. (Supplementary Note 12) The high-frequency amplifier according to any one of Supplementary Note 1 to Supplementary Note 9, characterized in that, in the transmission lines of high-frequency signals in each of the lines constituting the input matching circuit and the output matching circuit, the effective dielectric constant of the base substrate provided below the transmission line is at least twice as high as the effective dielectric constant of the dielectric layer provided above the transmission line.(Supplementary Note 13) The high-frequency amplifier according to any one of Supplementary Notes 1 to 12, wherein the conductive wall is disposed perpendicular to the transmission direction of the high-frequency signal. (Supplementary Note 14) The high-frequency amplifier according to any one of Supplementary Notes 1 to 13, wherein at least one of the input matching circuit or the output matching circuit includes: a first matching circuit; a second matching circuit different from the first matching circuit; a third matching circuit connected to the first matching circuit and the second matching circuit, respectively; and the conductive wall at ground potential provided between the first matching circuit and the second matching circuit. (Supplementary Note 15) The high-frequency amplifier according to Supplementary Note 14, wherein the third matching circuit includes electrodes at ground potential provided on both ends thereof, and the conductive wall includes the electrodes. (Supplementary Note 16) The high-frequency amplifier according to Supplementary Note 14, wherein the third matching circuit includes MIM capacitors connected in parallel. (Supplementary Note 17) The high-frequency amplifier according to Supplementary Note 14, wherein the third matching circuit is configured to include microstrip lines connected in parallel. (Supplementary Note 18) The high-frequency amplifier according to any one of Supplementary Notes 14 to 17, wherein the conductor wall is disposed perpendicular to the transmission direction of the high-frequency signal.

[0082] It is possible to combine the embodiments, modify any of the components of the embodiments, or omit any of the components of the embodiments.

[0083] A high-frequency amplifier according to the present disclosure can be used, for example, in a high-frequency module with a flip-chip structure.

[0084] 1, 1A high frequency amplifier, 1a input matching circuit, 1a-1 strip line, 1b output matching circuit, 1b-1 coplanar line, 1c-1 to 1c-4 FET cells, 1d-1 to 1d-3, 16, 16-1, 16-2 electrodes, 1e metal wall, 1f-1, 1f-2, 1g matching circuit, 11 gate electrode, 11-1 to 11-7, 13-1 to 13-4 finger electrodes, 12-1 to 12-3, 21-1 to 21-5 source electrodes, 13 drain electrodes, 14, 14-1, 14-2 via holes, 15 pillars, 17, 22 dielectric layer, 18, 19 solid conductor, 20 base substrate, 21 transmission line, 23 top electrode, 24 bottom electrode, 25 ground conductor.

Claims

1. A high-frequency amplifier composed of a monolithic microwave integrated circuit with ground potential solid conductors formed on the upper and lower parts, Input matching circuit, Output matching circuit, A transistor cell connected to the input matching circuit and the output matching circuit, A ground potential conductor wall is provided between the input matching circuit and the output matching circuit, A pillar of ground potential conductor positioned directly above the transistor cell, Equipped with, The transistor cell has a ground potential conductor portion provided in the intermediate portion between the upper solid conductor and the lower solid conductor, The aforementioned conductor wall is composed of the conductor portion of the transistor cell, A high-frequency amplifier in which the conductor portion is electrically connected to the upper solid conductor and the lower solid conductor via the pillar.

2. A high-frequency amplifier composed of a monolithic microwave integrated circuit with ground potential solid conductors formed on the upper and lower parts, Input matching circuit, Output matching circuit, A transistor cell connected to the input matching circuit and the output matching circuit, A ground potential conductor wall is provided between the input matching circuit and the output matching circuit, Pillars of ground potential conductors arranged at both ends of the transistor cell, Equipped with, The transistor cell has a ground potential conductor portion provided in the intermediate portion between the upper solid conductor and the lower solid conductor, The aforementioned conductor wall is composed of the conductor portion of the transistor cell, A high-frequency amplifier in which the conductor portion is electrically connected to the upper solid conductor and the lower solid conductor via the pillar.

3. A high-frequency amplifier composed of a monolithic microwave integrated circuit with ground potential solid conductors formed on the upper and lower parts, Input matching circuit, Output matching circuit, A transistor cell connected to the input matching circuit and the output matching circuit, A ground potential conductor wall is provided between the input matching circuit and the output matching circuit, Pillars of ground potential conductors arranged at both ends of the transistor cell, Equipped with, The transistor cell has a ground potential conductor portion provided in the intermediate portion between the upper solid conductor and the lower solid conductor, The aforementioned conductor wall is composed of the conductor portion of the transistor cell, The transistor cell has electrodes having via holes, The electrode having the via hole electrically connects the upper solid conductor and the lower solid conductor. A high-frequency amplifier in which the conductor portion is electrically connected to the upper solid conductor and the lower solid conductor via the via holes and pillars.

4. A high-frequency amplifier composed of a monolithic microwave integrated circuit with ground potential solid conductors formed on the upper and lower parts, Input matching circuit, Output matching circuit, A transistor cell connected to the input matching circuit and the output matching circuit, A ground potential conductor wall is provided between the input matching circuit and the output matching circuit, A pillar of ground potential conductors positioned on the input side of both ends of the transistor cell, Equipped with, The transistor cell has a ground potential conductor portion provided in the intermediate portion between the upper solid conductor and the lower solid conductor, The aforementioned conductor wall is composed of the conductor portion of the transistor cell, A high-frequency amplifier in which the conductor portion is electrically connected to the upper solid conductor and the lower solid conductor via the pillar.

5. A high-frequency amplifier composed of a monolithic microwave integrated circuit with ground potential solid conductors formed on the upper and lower parts, Input matching circuit, Output matching circuit, A transistor cell connected to the input matching circuit and the output matching circuit, A ground potential conductor wall is provided between the input matching circuit and the output matching circuit, via holes are arranged at both ends of the transistor cell and electrically connected to the upper solid conductor and the lower solid conductor, A pillar of ground potential conductor positioned directly above the via hole, Equipped with, The transistor cell has a ground potential conductor portion provided in the intermediate portion between the upper solid conductor and the lower solid conductor, The aforementioned conductor wall is composed of the conductor portion of the transistor cell, A high-frequency amplifier in which the conductor portion is electrically connected to the upper solid conductor and the lower solid conductor via the via holes and pillars.

6. A high-frequency amplifier composed of a monolithic microwave integrated circuit with ground potential solid conductors formed on the upper and lower parts, Input matching circuit, Output matching circuit, A transistor cell connected to the input matching circuit and the output matching circuit, A ground potential conductor wall is provided between the input matching circuit and the output matching circuit, Equipped with, At least one of the input matching circuit or the output matching circuit is The first matching circuit and A second matching circuit, which is different from the first matching circuit, A third matching circuit connected to the first matching circuit and the second matching circuit, A high-frequency amplifier comprising: a ground-potential conductor wall provided between the first matching circuit and the second matching circuit.

7. The transistor cell is provided with ground potential electrodes located at both ends of the transistor cell, or adjacent to the transistor cell located at both ends of a plurality of transistor cells arranged side by side, The aforementioned conductor wall is configured to include an electrode at ground potential. A high-frequency amplifier according to any one of claims 1 to 6.

8. The transistor cell has a ground potential conductor portion provided in the intermediate portion between the upper solid conductor and the lower solid conductor, The conductor wall is configured to include the conductor portion of the transistor cell. The high-frequency amplifier according to claim 6.

9. The aforementioned input matching circuit is configured to include a strip line, The output matching circuit is configured to include a coplanar line formed by a line located on the output side via the conductive wall and a grounded electrode. A high-frequency amplifier according to any one of claims 1 to 6 and 8.

10. In the transmission lines of high-frequency signals in each of the lines constituting the input matching circuit and the output matching circuit, the dielectric constant of the substrate provided below the transmission line is 1.5 times or more higher than the dielectric constant of the dielectric layer provided above the transmission line. A high-frequency amplifier according to any one of claims 1 to 6 and 8.

11. In the transmission lines for high-frequency signals in each of the lines constituting the input matching circuit and the output matching circuit, the dielectric loss tangent of the dielectric layer provided on the upper part of the transmission line is at least twice as high as the dielectric loss tangent of the underlying substrate provided on the lower part of the transmission line. A high-frequency amplifier according to any one of claims 1 to 6 and 8.

12. In the transmission lines of high-frequency signals in each of the lines constituting the input matching circuit and the output matching circuit, the effective dielectric constant of the substrate provided below the transmission line is at least twice as high as the effective dielectric constant of the dielectric layer provided above the transmission line. A high-frequency amplifier according to any one of claims 1 to 6 and 8.

13. The aforementioned conductor wall is positioned perpendicular to the transmission direction of the high-frequency signal. A high-frequency amplifier according to any one of claims 1 to 6 and 8.

14. At least one of the input matching circuit or the output matching circuit is The first matching circuit and A second matching circuit, which is different from the first matching circuit, A third matching circuit connected to the first matching circuit and the second matching circuit, The system comprises a ground potential conductor wall provided between the first matching circuit and the second matching circuit. A high-frequency amplifier according to any one of claims 1 to 5.

15. The third matching circuit is provided with ground potential electrodes at both ends, The aforementioned conductor wall is configured to include an electrode at ground potential. The high-frequency amplifier according to claim 6.

16. The third matching circuit is configured to include MIM capacitors connected in parallel. The high-frequency amplifier according to claim 6.

17. The third matching circuit is configured to include microstrip lines connected in parallel. The high-frequency amplifier according to claim 6.

18. The aforementioned conductor wall is positioned perpendicular to the transmission direction of the high-frequency signal. The high-frequency amplifier according to claim 6 and any one of claims 15 to 17.