Doherty amplifier

Abstract

A Doherty amplifier (100) comprises: a carrier amplification unit (101) that includes a plurality of transistors; a peak amplification unit (102) that includes a plurality of transistors; and an output synthesis unit (203) that synthesizes the outputs of the plurality of transistors in the carrier amplification unit and the outputs of the plurality of transistors in the peak amplification unit. The output synthesis unit has a plurality of output-side electrodes (230) that synthesize the outputs of the plurality of transistors in the carrier amplification unit and the outputs of the plurality of transistors in the peak amplification unit for each combination of the transistors of the carrier amplification unit and the transistors of the peak amplification unit.

Description

Doherty Amplifier

[0001] The disclosed technology relates to a Doherty amplifier.

[0002] In recent years, the rapid spread of mobile wireless terminals such as mobile phones has led to the development of mobile communication infrastructure. Furthermore, in mobile communications where communication capacity and density are increasing, there is a growing demand for low power consumption not only in mobile wireless terminals but also in base stations. Therefore, amplifiers for mobile communications that can efficiently amplify signals with a large peak-to-average power ratio (PAPR) are desired. Doherty amplifiers are known as amplifiers that can efficiently amplify signals with a large PAPR. Doherty amplifiers can efficiently amplify signals at operating points with a large backoff amount from saturated output.

[0003] A Doherty amplifier includes a carrier amplifier (also called a main amplifier) ​​that operates in class AB and a peak amplifier (also called an auxiliary amplifier) ​​that operates in class C. During linear operation with a large back-off amount, only the carrier amplifier operates, but during saturated output, both the carrier amplifier and the peak amplifier operate, enabling highly efficient signal amplification from back-off to saturated output.

[0004] In amplifiers that require high output, for example, multiple transistors are connected in parallel on an integrated circuit chip to increase output power. Specifically, in the amplifier described in Patent Document 1, a single tapered input electrode and a single tapered output electrode are provided on the input and output sides of the amplifier, which is made up of multiple transistors connected in parallel.

[0005] Japanese Patent Application Laid-Open No. 2018-117214

[0006] In a high-output Doherty amplifier, in a configuration in which Doherty combining is performed using a single output electrode as disclosed in the above-mentioned Patent Document 1, there are many possible combinations of combining multiple transistors in the carrier amplification section and multiple transistors in the peak amplification section, which causes a problem that the paths vary significantly depending on the combination, resulting in differences in electrical length and degradation of amplification characteristics.

[0007] The present disclosure is intended to solve the above-mentioned problems, and aims to uniquely determine the combined combination of transistors in the carrier amplification section and transistors in the peak amplification section in a high-output Doherty amplifier.

[0008] A Doherty amplifier according to the present disclosure comprises: a carrier amplification section including a plurality of transistors; a peak amplification section including a plurality of transistors; and an output combining section that combines outputs of the plurality of transistors in the carrier amplification section and outputs of the plurality of transistors in the peak amplification section, wherein the output combining section has a plurality of output electrodes that combine the outputs of the plurality of transistors in the carrier amplification section and outputs of the plurality of transistors in the peak amplification section for each combination of transistors in the carrier amplification section and transistors in the peak amplification section.

[0009] According to the present disclosure, it is possible to provide an advantageous effect of configuring a high-output Doherty amplifier so that the combined combination of transistors in the carrier amplification section and transistors in the peak amplification section is uniquely determined.

[0010] FIG. 1 is a diagram illustrating a configuration of a Doherty amplifier 100 (100A) according to a first embodiment of the present disclosure. FIG. 2 is a diagram illustrating a configuration of a Doherty amplifier 100 (100B) according to a second embodiment of the present disclosure. FIG. 3 is a diagram illustrating a configuration of a Doherty amplifier 100 (100C) according to a third embodiment of the present disclosure. FIG. 4 is a diagram illustrating a configuration of a Doherty amplifier 100 (100D) according to a fourth embodiment of the present disclosure. FIG. 5 is a diagram illustrating a configuration of a Doherty amplifier 100 (100E) according to a fifth embodiment of the present disclosure. FIG. 6 is a diagram illustrating a reference configuration example of a Doherty amplifier 100′ that does not employ the configuration of the Doherty amplifier according to the present disclosure.

[0011] First, a reference configuration example that does not employ part of the configuration of the present disclosure will be described. Fig. 6 is a diagram showing a reference configuration example of a Doherty amplifier 100' that does not employ the configuration of the Doherty amplifier of the present disclosure. The Doherty amplifier 100' shown in Fig. 6 includes a carrier amplifier section 101, a peak amplifier section 102, an output combiner section 103, an input circuit section 104, and an output circuit section 105.

[0012] A Doherty amplifier 100′ (amplifier) ​​that requires high output and is installed in a mobile communication base station may be configured with a carrier amplification section 101 and a peak amplification section 102, each of which is composed of a plurality of transistors M01, M02, and M03, and a plurality of transistors A01, A02, and A03, connected in parallel. Specifically, in the carrier amplification section 101 shown in FIG. 6 , a transistor M01, a transistor M02, and a transistor M03 are arranged in parallel, and in the peak amplification section 102 shown in FIG. 6 , a transistor A01, a transistor A02, and a transistor A03 are arranged in parallel. These transistors M01, M02, and M03, and A01, A02, and A03 are connected to an output terminal (reference configuration example) 130 of an output combining section 103 in the subsequent stage.

[0013] The output side electrode 130 is, for example, a single solid electrode, and is connected to the source portions of the transistors M01, M02, and M03 of the carrier amplification section 101 by bonding wires 108, and to the source portions of the transistors A01, A02, and A03 of the peak amplification section 102 by bonding wires 109.

[0014] 6 , in the output electrode 130, which is a single solid electrode, the signals input from the input circuit unit 104 to the carrier amplification unit 101 and the peak amplification unit 102 through the bonding wires 106 and 107 have different lengths for, for example, a path Aout of Doherty combining between the output of the transistor M01 located at the top of the carrier amplification unit 101 and the output of the transistor A03 located at the bottom of the peak amplification unit 102, and a path Cout of Doherty combining between the output of the transistor M03 located at the bottom of the peak amplification unit 102 and the output of the transistor A01 located at the top of the peak amplification unit 102. In addition to the paths Aout and Cout in FIG. 6 , there are many other combinations of Doherty combining paths between the transistors M01, M02, and M03 of the carrier amplification unit 101 and the transistors A01, A02, and A03 of the peak amplification unit 102, and Doherty combining may occur with an electrical length unintended by the designer.

[0015] Furthermore, in a Doherty amplifier, when it is necessary to appropriately determine the impedance when looking at the load from the carrier amplifier and the peaking amplifier, the electrical length of the combining circuit (Doherty combining) that combines the output of the carrier amplifier and the output of the peaking amplifier significantly affects the performance of the Doherty amplifier.

[0016] That is, in a Doherty amplifier, if the electrical length of the Doherty combining path is not uniquely determined, it can cause degradation of the amplification characteristics of the Doherty amplifier (high-power Doherty amplifier), so it is preferable to strictly determine the electrical length of the Doherty combining path. Taking this concept into consideration, embodiments of the present disclosure will be described below.

[0017] In order to explain the present disclosure in more detail, embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0018] First Embodiment In the first embodiment, an example of a configuration in which a linear output electrode is provided for each combination of a transistor in a carrier amplification section and a transistor in a peak amplification section will be described.

[0019] 1 is a diagram illustrating the configuration of a Doherty amplifier 100 (100A) according to a first embodiment of the present disclosure. The Doherty amplifier 100 (100A) is a high-output Doherty amplifier capable of generating a higher output than a Doherty amplifier having a simple configuration including a carrier amplifier section and a peak amplifier section each composed of a single transistor. The Doherty amplifier 100A shown in FIG. 1 includes a carrier amplifier section 101, a peak amplifier section 102, an output combiner section 203, an input circuit section 104, and an output circuit section 105.

[0020] The input circuit unit 104 includes a circuit that inputs signals to the transistors (M01, M02, M03) of the carrier amplification unit 101 and the transistors (A01, A02, A03) of the peak amplification unit 102 in the Doherty amplifier 100A. Specifically, the input circuit unit 104 is connected to the gates of the transistors M01, M02, and M03 in the carrier amplification unit 101 via bonding wires 106. The input circuit unit 104 is also connected to the gates of the transistors A01, A02, and A03 in the peak amplification unit 102 via bonding wires 107.

[0021] The carrier amplification unit 101 includes a plurality of transistors (M01, M02, M03). Each of the plurality of transistors (M01, M02, M03) operates as a carrier amplifier. The transistors (M01, M02, M03) are, for example, silicon MOS transistors. The transistors (M01, M02, M03) may be not only silicon MOS transistors but also transistors such as GaN-HEMTs. The carrier amplification unit 101 shown in FIG. 1 includes a transistor M01, a transistor M02, and a transistor M03. The transistors M01, M02, and M03 are arranged in parallel and connected in the output combining unit 203 at the subsequent stage. That is, the plurality of transistors (M01, M02, M03) in the carrier amplification unit 101 are connected in parallel. Although the carrier amplification unit 101 shown in FIG. 1 includes three transistors, the number of transistors is not limited to three. The number of transistors in the carrier amplification section 101 is appropriately designed depending on the performance required of the Doherty amplifier 100A, and may be N (N≧2), as described below. The output electrode (source electrode) of each of the transistors (M01, M02, M03) in the carrier amplification section 101 is connected to a first end, which is one of both ends of the output electrodes 230 (230a, 230b, 230c), via a bonding wire 208. Specifically, the transistor M01 is connected to the first end of the output electrode 230a via the bonding wire 208. The transistor M02 is connected to the first end of the output electrode 230b via the bonding wire 208. The transistor M03 is connected to the first end of the output electrode 230c via the bonding wire 208.

[0022] The peak amplifier 102 includes a plurality of transistors (A01, A02, A03). Each of the plurality of transistors (A01, A02, A03) operates as a peak amplifier. The transistors (A01, A02, A03) are, for example, silicon MOS transistors. The transistors (A01, A02, A03) may be not only silicon MOS transistors but also transistors such as GaN-HEMTs. The peak amplifier 102 shown in FIG. 1 includes a transistor A01, a transistor A02, and a transistor A03. The transistors A01, A02, and A03 are arranged in parallel and connected in the output combiner 203 at the subsequent stage. That is, the plurality of transistors (A01, A02, A03) in the peak amplifier 102 are connected in parallel. Although the peak amplifier 102 shown in FIG. 1 includes three transistors (A01, A02, and A03), the number of transistors is not limited to three. The number of transistors in the peak amplifier 102 is appropriately designed depending on the performance required of the Doherty amplifier 100A, and may be N (N≧2), as described below. The output electrode (source electrode) of each of the transistors (A01, A02, and A03) in the peak amplifier 102 is connected to the second end, which is the other end of the output electrodes 230 (230a, 230b, and 230c), via a bonding wire 209. Specifically, the transistor A01 is connected to the second end of the output electrode 230a via the bonding wire 209. The transistor A02 is connected to the second end of the output electrode 230b via the bonding wire 209. The transistor A03 is connected to the second end of the output electrode 230c via the bonding wire 209.

[0023] The output combiner 203 combines the outputs of the plurality of transistors (M01, M02, M03) in the carrier amplifier 101 and the outputs of the plurality of transistors (A01, A02, A03) in the peak amplifier 102. The output combiner 203 is configured to uniquely determine the combined combination of the transistors (M01, M02, M03) in the carrier amplifier 101 and the transistors (A01, A02, A03) in the peak amplifier 102. Specifically, the output combiner 203 has a plurality of output electrodes 230 (230a, 230b, 230c). The multiple output electrodes 230 (230a, 230b, 230c) combine the outputs of the multiple transistors (M01, M02, M03) in the carrier amplification section 101 and the outputs of the multiple transistors (A01, A02, A03) in the peak amplification section 102 for each combination of the transistors (M01, M02, M03) in the carrier amplification section 101 and the transistors (A01, A02, A03) in the peak amplification section 102. In other words, the multiple output electrodes 230 are configured with the same number of output electrodes as the number of combinations of the transistors in the carrier amplification section 101 and the transistors in the peak amplification section 102. The output combining section 203 shown in FIG. 1 is configured to include an output electrode (first electrode) 230a, an output electrode (second electrode) 230b, and an output electrode (third electrode) 230c.

[0024] The output electrode (first electrode) 230a, the output electrode (second electrode) 230b, and the output electrode (third electrode) 230c are each a linearly extending rectangular electrode. The output electrode (first electrode) 230a has two longitudinal ends, one of which, a first end, is connected to the output electrode (source electrode) of the transistor M01 in the carrier amplification unit 101 via a bonding wire 208. The other of which, a second end, is connected to the output electrode (source electrode) of the transistor A01 in the peak amplification unit 102 via one of the bonding wires 209, and is also connected to the output circuit unit 105 via a bonding wire 210.

[0025] The output electrode (second electrode) 230b has a rectangular shape with a first end, which is one of the longitudinal ends, connected to the output electrode (source electrode) of the transistor M02 via a bonding wire 208. The other end, which is a second end, is connected to the output electrode (source electrode) of the transistor A02 in the peak amplifier 102 via one of the bonding wires 209, and is also connected to the output circuit 105 via a bonding wire 210.

[0026] The output electrode (third electrode) 230c has a rectangular shape with a first end, which is one of the longitudinal ends, connected to the output electrode (source electrode) of the transistor M03 via a bonding wire 208. The other end, which is a second end, is connected to the output electrode (source electrode) of the transistor A03 in the peak amplification unit 102 via one of the bonding wires 209, and is also connected to the output circuit unit 105 via a bonding wire 210. Other characteristic configurations of the Doherty amplifier 100A according to this embodiment will be described below.

[0027] The multiple output electrodes 230 (230a, 230b, 230c) are wired to have equal lengths. Specifically, the length of the output electrode 230a, the length of the output electrode 230b, and the length of the output electrode 230c are all equal. This makes it easy to configure the paths for Doherty combining between the transistors (M01, M02, M03) of the carrier amplification section 101 and the transistors (A01, A02, A03) of the peak amplification section 102 to have equal lengths. Note that in this embodiment, the output electrodes 230a, 230b, and 230c have the same or approximately the same shape.

[0028] The paths of the output electrodes 230 (230a, 230b, 230c) that connect the transistors (M01, M02, M03) of the carrier amplification section 101 and the transistors (A01, A02, A03) of the peak amplification section 102 are of equal length. Specifically, the path from the position where the bonding wire 208 is connected to the position where the bonding wires 209 and 210 are connected to the output electrode 230a, the path from the position where the bonding wire 208 is connected to the position where the bonding wires 209 and 210 are connected to the output electrode 230b, and the path from the position where the bonding wire 208 is connected to the position where the bonding wires 209 and 210 are connected to the output electrode 230c are of equal length. This makes it easier to equalize the electrical lengths in the Doherty combining circuits of the outputs of the transistors (M01, M02, M03) of the carrier amplification section 101 and the transistors (A01, A02, A03) of the peak amplification section 102.

[0029] The plurality of transistors (M01, M02, M03) in the carrier amplification unit 101 may be N (N≧2) or more transistors, and the plurality of transistors (A01, A02, A03) in the peak amplification unit 102 may be N (N≧2) or more transistors. The output of the Doherty amplifier can be set by adjusting the number and combination of transistors.

[0030] The transistors (M01, M02, M03) of the carrier amplification section 101 are connected to the output electrodes 230 (230a, 230b, 230c) via bonding wires 208, and the transistors (A01, A02, A03) of the peak amplification section 102 are connected to the output electrodes 230 (230a, 230b, 230c) via bonding wires 209. The length of each bonding wire 208, 209 is adjusted depending on the shape of the output electrodes 230 (230a, 230b, 230c) or the position of the output electrodes 230 (230a, 230b, 230c) in the output combining section 203. The length is not particularly specified, but is adjusted to a length such that the electrical lengths of the paths Dout (path Dout1, path Dout2, path Dout3) of the Doherty combination are equal, for example. By adjusting the lengths in this manner, the electrical lengths of the Doherty combining circuits for the outputs of the multiple transistors (M01, M02, M03) in the carrier amplification section 101 and the outputs of the transistors (A01, A02, A03) in the peak amplification section 102 can be set to be equal.

[0031] The output circuit unit 105 includes a circuit that outputs a signal amplified by the Doherty amplifier 100 (100A) to the outside of the Doherty amplifier 100 (100A). Specifically, the output circuit unit 105 is connected to output electrodes 230 (230a, 230b, 230c) via bonding wires 210, and is further connected to outputs of multiple transistors (M01, M02, M03) in the carrier amplification unit 101 via bonding wires 208. The output circuit unit 105 is also connected to outputs of transistors (A01, A02, A03) in the peak amplification unit 102 via bonding wires 209.

[0032] As described above, the Doherty amplifier according to the first embodiment divides the output electrodes into lines of physically equal length, and assigns one of the divided output electrodes to each combination of Doherty combining of each transistor in the carrier amplification section and each transistor in the peak amplification section, thereby realizing a high-output Doherty amplifier as a path for Doherty combining.

[0033] The configuration example shown in Fig. 1 will be described in comparison with the reference configuration example shown in Fig. 6. As is clear from a comparison between the configuration example shown in Fig. 1 and the reference configuration example shown in Fig. 6, in the configuration shown in this embodiment, the multiple output electrodes, output electrode 230a, output electrode 230b, and output electrode 230c, are divided into electrodes of equal length, compared to the single output electrode shown in Fig. 6.

[0034] 6 is divided into electrodes of equal length, such as output electrode 230a, output electrode 230b, and output electrode 230c, as shown in FIG. 1, thereby making it possible to uniquely determine the Doherty combined paths of the outputs of transistors M01, M02, and M03 in the carrier amplification section 101 and transistors A01, A02, and A03 in the peak amplification section 102, and to make the electrical lengths equal. For example, it can be said that the electrical lengths of path Dout1 of Doherty combined outputs of transistors M01 and A01, path Dout2 of Doherty combined outputs of transistors M02 and A02, and path Dout3 of Doherty combined outputs of transistors M03 and A03 are clearly equal because output electrodes 230a, 230b, and 230c are equal in length.

[0035] Furthermore, the output electrodes 230a, 230b, and 230c are made to be sufficiently thick so that the outputs of the transistors M01, M02, and M03 of the carrier amplifier 101 and the transistors A01, A02, and A03 of the peak amplifier 102 can be combined with as little loss as possible.

[0036] The division of the output side electrode changes the connection positions of the bonding wires 208, 209, and 210. Therefore, as described above, there is no regulation on the lengths of the bonding wires 208, 209, and 210, but they are connected so that the electrical lengths of the Doherty combining paths Dout1, Dout2, and Dout3 are equal.

[0037] The signals Doherty combined through the equal-length paths Dout1, Dout2, and Dout3 are delivered to the output circuit section 105 by the bonding wire 210.

[0038] Therefore, by combining the Doherty combining paths of the transistors M01, M02, and M03 in the carrier amplification section 101 and the transistors A01, A02, and A03 in the peak amplification section 102, as in the single output side electrode 130 in Figure 6, the combination will not occur with an electrical length that is not intended by the designer, and this can prevent degradation of the amplification characteristics of the high-power Doherty amplifier.

[0039] Furthermore, as described above, by adopting the structure of the present disclosure, all of the Doherty combining paths of the transistors in the carrier amplification section and the transistors in the peak amplification section are of equal length, which makes it possible to eliminate differences in electrical length between the Doherty combining paths, thereby preventing degradation of the amplification characteristics of the high-power Doherty amplifier.

[0040] This embodiment provides an example of the following configuration: a Doherty amplifier comprising: a carrier amplification section including a plurality of transistors; a peak amplification section including a plurality of transistors; and an output combining section that combines outputs of the plurality of transistors in the carrier amplification section and outputs of the plurality of transistors in the peak amplification section, wherein the output combining section has a plurality of output electrodes that combine the outputs of the plurality of transistors in the carrier amplification section and outputs of the plurality of transistors in the peak amplification section for each combination of transistors in the carrier amplification section and transistors in the peak amplification section. This advantageous effect of the present disclosure is that it is possible to provide a Doherty amplifier configured so that the combination of transistors in the carrier amplification section and transistors in the peak amplification section is uniquely determined. Furthermore, the present disclosure provides the same advantageous effect by employing the above configuration in a communication device, such as a mobile wireless terminal or a base station device.

[0041] This embodiment further provides the following exemplary configuration: A Doherty amplifier characterized in that the plurality of output electrodes are wired to have equal lengths. This provides an advantage of providing a Doherty amplifier that facilitates configuring the paths of the Doherty combination of the transistors in the carrier amplification section and the transistors in the peak amplification section to have equal lengths. Furthermore, since differences in electrical length are less likely to occur in each Doherty combination, it provides an advantage of preventing degradation of the amplification characteristics of the high-power Doherty amplifier. Furthermore, the present disclosure provides the same advantage as above by employing the above configuration in communication devices such as mobile wireless terminals and base station devices.

[0042] This embodiment provides an example of the following configuration: A Doherty amplifier characterized in that the paths in the output electrodes connecting the transistors in the carrier amplification section and the transistors in the peak amplification section are equal in length. This further provides an advantage of providing a Doherty amplifier that easily equalizes the electrical lengths in each Doherty combining circuit of the output of the transistors in the carrier amplification section and the output of the transistors in the peak amplification section. Furthermore, since differences in electrical length are less likely to occur in each Doherty combination, it is possible to prevent degradation of the amplification characteristics of a high-power Doherty amplifier. Furthermore, the present disclosure provides the same advantage as above by employing the above configuration in communication devices such as mobile wireless terminals and base station devices.

[0043] This embodiment provides an example of the following configuration: A Doherty amplifier characterized in that the number of transistors is N (N≧2) or more. This provides an advantageous effect of providing a Doherty amplifier that allows output setting based on the number and combination of transistors. Furthermore, the present disclosure provides the same advantageous effect as described above by employing the above configuration in communication devices such as mobile wireless terminals and base station devices.

[0044] This embodiment provides an exemplary configuration as follows: The transistor and the output electrode are connected via a bonding wire, and the length of the bonding wire is adjusted depending on the shape of the output electrode or the position of the output electrode in the output combining section. This further provides an advantage of providing a Doherty amplifier that can easily equalize the electrical lengths in the Doherty combining circuits for the output of the transistor in the carrier amplification section and the output of the transistor in the peak amplification section. Furthermore, since differences in electrical length are less likely to occur in each Doherty combination, deterioration of the amplification characteristics of the high-power Doherty amplifier can be prevented. Furthermore, the present disclosure provides the same advantage as above by employing the above configuration in communication devices such as mobile wireless terminals and base station devices.

[0045] Embodiment 2. In the above-described embodiment 1, an example of a configuration in which a linear output electrode is provided for each combination of a transistor in a carrier amplification section and a transistor in a peak amplification section is described. In embodiment 2, an example of a configuration in which a bent output electrode is provided for each combination of a transistor in a carrier amplification section and a transistor in a peak amplification section is described. In embodiment 2, duplicated descriptions of configurations according to embodiment 2 that are similar to the configuration according to embodiment 1 already described will be omitted as appropriate.

[0046] FIG. 2 is a diagram illustrating a configuration of a Doherty amplifier 100 (100B) according to a second embodiment of the present disclosure. FIG. 2 illustrates a configuration in which the lines of output electrodes 230a, 230b, and 230c provided in the output combining unit 203 of FIG. 1 have different shapes. Compared to the Doherty amplifier 100A already described, the Doherty amplifier 100B according to this embodiment employs output electrodes 330 (330a, 330b, and 330c) instead of the output electrodes 230 (230a, 230b, and 230c) in the Doherty amplifier 100A. Configurations already described or configurations described below can be applied to components other than the output electrodes 330 (330a, 330b, and 330c). In the description of this embodiment, the output electrodes 330 (330a, 330b, and 330c) will be mainly described.

[0047] The output combining unit 203 has a plurality of output electrodes 330 (330a, 330b, 330c). The plurality of output electrodes 330 (330a, 330b, 330c) combine the outputs of the plurality of transistors (M01, M02, M03) in the carrier amplification unit 101 and the outputs of the plurality of transistors (A01, A02, A03) in the peak amplification unit 102 for each combination of the transistors (M01, M02, M03) in the carrier amplification unit 101 and the transistors (A01, A02, A03) in the peak amplification unit 102. The output combining unit 203 shown in FIG. 2 is configured to include an output electrode (first bent electrode) 330a, an output electrode (second bent electrode) 330b, and an output electrode (third bent electrode) 330c. The output electrode (first bent electrode) 330a, the output electrode (second bent electrode) 330b, and the output electrode (third bent electrode) 330c each have a shape with one or more bends. Possible shapes of the output electrodes include, for example, an L-shape, an inverted L-shape, an M-shape, a V-shape, an inverted V-shape, and a W-shape. Although not shown, the output electrode (first bent electrode) 330a, the output electrode (second bent electrode) 330b, and the output electrode (third bent electrode) 330c may each have a curved portion. In this case, possible shapes of the output electrodes include, for example, a C-shape, an inverted C-shape, a J-shape, an inverted J-shape, an S-shape, an inverted S-shape, a U-shape, and an inverted U-shape.

[0048] The output electrode (first bent electrode) 330a has a first end, which is one of both longitudinal ends, connected to the output electrode (source electrode) of the transistor M01 in the carrier amplification unit 101 via one of the bonding wires 208. The other end, which is a second end, is connected to the output electrode (source electrode) of the transistor A01 in the peak amplification unit 102 via one of the bonding wires 209, and is also connected to the output circuit unit 105 via a bonding wire 210.

[0049] The output electrode (second bent electrode) 330b has a first end, which is one of both longitudinal ends, connected to the output electrode (source electrode) of the transistor M02 via one of the bonding wires 208. The other end, which is a second end, is connected to the output electrode (source electrode) of the transistor A02 in the peak amplifier 102 via one of the bonding wires 209, and is also connected to the output circuit 105 via a bonding wire 210.

[0050] The output electrode (third bent-shaped electrode) 330c has a first end, which is one of both longitudinal ends, connected to the output electrode (source electrode) of the transistor M03 via one of the bonding wires 208. The other end, which is a second end, is connected to the output electrode (source electrode) of the transistor A03 in the peak amplifier 102 via one of the bonding wires 209, and is also connected to the output circuit unit 105 via a bonding wire 210. Other characteristic configurations of the Doherty amplifier 100B according to this embodiment will be described below.

[0051] The multiple output electrodes 330 (330a, 330b, 330c) are wired to have equal lengths. Specifically, the length of the output electrode 330a, the length of the output electrode 330b, and the length of the output electrode 330c are all equal. This makes it easy to configure the paths for Doherty combining between the transistors (M01, M02, M03) of the carrier amplification section 101 and the transistors (A01, A02, A03) of the peak amplification section 102 to have equal lengths. Note that, although the figure shows the output electrodes 330a, 330b, and 330c as having different shapes, the output electrodes 330a, 330b, and 330c in this embodiment may have the same or substantially the same shape.

[0052] The paths are of equal length in each of the output electrodes 330 (330a, 330b, 330c) that connect the transistors (M01, M02, M03) of the carrier amplification section 101 and the transistors (A01, A02, A03) of the peak amplification section 102. Specifically, the path from the position where the bonding wire 208 is connected in the output electrode 330a to the positions where the bonding wires 209 and 210 are connected, the path from the position where the bonding wire 208 is connected in the output electrode 330b to the positions where the bonding wires 209 and 210 are connected, and the path from the position where the bonding wire 208 is connected in the output electrode 330c to the positions where the bonding wires 209 and 210 are connected are all of equal length. In this way, the configuration is such that the electrical lengths of the Doherty combining circuits for the outputs of the transistors (M01, M02, M03) of the carrier amplification section 101 and the transistors (A01, A02, A03) of the peak amplification section 102 are easily made equal.

[0053] As described above, the present disclosure achieves the same effects as those achieved when the output electrodes of Embodiment 1 are employed, even when the output electrodes have a shape different from that of Embodiment 1. Furthermore, by making the Doherty combining paths (Dout1, Dout2, Dout3) equal in length, it is possible to further prevent deterioration of the amplification characteristics.

[0054] This embodiment provides an example of the following configuration: a Doherty amplifier, wherein the output electrode has a shape having one or more bent portions. This provides an advantage of providing a Doherty amplifier with a configuration that improves design freedom. Furthermore, the present disclosure provides the same advantage as above by applying the above configuration to a communication device, such as a mobile wireless terminal or a base station device.

[0055] Embodiment 3. In the above-described embodiment 2, an example of a configuration in which an output electrode having a bent shape is provided for each combination of a transistor in a carrier amplification section and a transistor in a peak amplification section is described. In embodiment 3, an example of a configuration of a Doherty amplifier packaged including input and output terminals is described. In embodiment 3, duplicated descriptions of the configuration of embodiment 3 that is the same as the configuration of embodiment 1 or embodiment 2 already described will be omitted as appropriate.

[0056] FIG. 3 is a diagram illustrating a configuration of a Doherty amplifier 100 (100C) according to a third embodiment of the present disclosure. FIG. 3 illustrates a configuration example of the Doherty amplifier 100C in which the configuration of FIG. 1 is housed in a package 440. However, the Doherty amplifier 100C according to this embodiment may be one in which the configuration of FIG. 2 is housed in a package 440, or one in which a configuration according to an embodiment described below is housed in a package 440. In the following description of this embodiment, configurations that are different from those already described will be mainly described.

[0057] The Doherty amplifier 100C includes terminals such as an input terminal and an output terminal. The total number of terminals is appropriately designed depending on the performance required of the packaged Doherty amplifier 100C. The Doherty amplifier 100C shown in FIG. 3 includes an input signal terminal (first input signal terminal) 441, an input signal terminal (second input signal terminal) 442, a terminal 443, and an output signal terminal 444.

[0058] The first input signal terminal 441 is a terminal for inputting an external signal to the carrier amplification unit 101. The first input signal terminal 441 is connected to input a signal to a plurality of transistors in the carrier amplification unit 101. Specifically, the first input signal terminal 441 is connected to each transistor (M01, M02, M03) of the carrier amplification unit 101 via a bonding wire 106.

[0059] The second input signal terminal 442 is a terminal for inputting an external signal to the peak amplifier 102. The second input signal terminal 442 is connected to input a signal to a plurality of transistors in the peak amplifier 102. Specifically, the second input signal terminal 442 is connected to each transistor (A01, A02, A03) of the peak amplifier 102 via a bonding wire 107.

[0060] The terminal 443 may be used to supply power to the transistors (M01, M02, M03) (A01, A02, A03) in the carrier amplifier 101 and the peak amplifier 102, or for other purposes.

[0061] The output signal terminal 444 is a terminal for outputting the signal after Doherty combining to the outside. The output signal terminal 444 is connected to the plurality of output electrodes 230 (230a, 230b, 230c) so as to output the signal combined by the output combining unit 503. Specifically, the output signal terminal 444 is connected to the output electrodes 230 (230a, 230b, 230c) via bonding wires 210.

[0062] In the present embodiment, an example of a configuration in which the configuration of Fig. 1 is housed in package 440 has been shown, but a configuration in which the configuration of Fig. 2 is housed in a package may also be used. Alternatively, a configuration in which a configuration according to an embodiment described below is housed in a package may also be used.

[0063] This embodiment provides an example of the following configuration: a Doherty amplifier comprising: a first input signal terminal connected to input a signal to a plurality of transistors in the carrier amplification section; a second input signal terminal connected to input a signal to a plurality of transistors in the peak amplification section; and an output signal terminal connected to the plurality of output electrodes to output a signal combined by the output combining section. This provides an advantage of providing a packaged Doherty amplifier. Furthermore, the present disclosure provides the same advantage as above by applying the above configuration to a communication device such as a mobile wireless terminal or a base station device.

[0064] Fourth Embodiment In the third embodiment described above, an example of the configuration of a packaged Doherty amplifier has been described. In the fourth embodiment, an example of the configuration of a Doherty amplifier in which the inside of the output combiner is multi-layered will be described. In the fourth embodiment, duplicated descriptions of the configuration of the fourth embodiment that is the same as the configuration of the first embodiment, the second embodiment, or the third embodiment already described will be omitted as appropriate.

[0065] FIG. 4 is a diagram illustrating a configuration of a Doherty amplifier 100 (100D) according to a fourth embodiment of the present disclosure. Similar to FIG. 3 , FIG. 4 illustrates a packaged Doherty amplifier in which the configuration of the Doherty amplifier 100D according to the present embodiment is housed in a package 440. However, compared to the Doherty amplifiers 100 (100A, 100B, 100C) already described, the Doherty amplifier 100D according to the present embodiment only needs to have a multi-layered configuration inside the output combiner, and the following description will mainly focus on the configuration in which the output combiner is multi-layered inside.

[0066] 4 includes a carrier amplifier 101, a peak amplifier 102, an output combiner 503, an input circuit 104, and an output circuit 105. The carrier amplifier 101, the peak amplifier 102, the input circuit 104, and the output circuit 105 are configured in the same manner or substantially the same manner as the carrier amplifier 101, the peak amplifier 102, the input circuit 104, and the output circuit 105 already described.

[0067] The output combining section 503 is configured in multiple layers with output combining layer sections 510 (510a, 510b, 510c) for each output electrode 330 (330a, 330b, 330c). The output electrodes 330 (330a, 330b, 330c) are electrodes having a shape with one or more bent sections. The number of output combining layer sections 510 is the same as the number of combinations of transistors in the carrier amplification section 101 and transistors in the peak amplification section 102. The output combining section 503 shown in FIG. 4 is configured to include an output combining layer section (first output combining layer section) 510a, an output combining layer section (second output combining layer section) 510b, and an output combining layer section (third output combining layer section) 510c.

[0068] An output electrode 330a is disposed in the first output combining layer section 510a. The output electrode 330a is an electrode having a bent portion. A first end, which is one of both ends of the output electrode 330a, is connected to the output electrode (source electrode) of the transistor M01 in the carrier amplification section 101 via one of the bonding wires 208. The bent portion of the output electrode 330a is connected to the output electrode (source electrode) of the transistor A01 in the peak amplification section 102 via one of the bonding wires 209. A second end, which is the other of both ends of the output electrode 330a, is connected to the output circuit section 105 via one of the bonding wires 210 and the output signal terminal 444.

[0069] An output electrode 330b is disposed in the second output combining layer unit 510b. The output electrode 330b is an electrode having a bent portion. A first end, which is one of both ends of the output electrode 330b, is connected to the output electrode (source electrode) of the transistor M02 in the carrier amplification unit 101 via one of the bonding wires 208. The bent portion of the output electrode 330b is connected to the output electrode (source electrode) of the transistor A02 in the peak amplification unit 102 via one of the bonding wires 209. A second end, which is the other of both ends of the output electrode 330b, is connected to the output circuit unit 105 via one of the bonding wires 210 and the output signal terminal 444.

[0070] An output electrode 330c is disposed in the third output combining layer section 510c. The output electrode 330c is an electrode having a bent portion. A first end of the output electrode 330c, which is one of both ends, is connected to the output electrode (source electrode) of the transistor M03 in the carrier amplification section 101 via one of the bonding wires 208. The bent portion of the output electrode 330c is connected to the output electrode (source electrode) of the transistor A03 in the peak amplification section 102 via one of the bonding wires 209. A second end of the output electrode 330c, which is the other of both ends, is connected to the output circuit section 105 via one of the bonding wires 210 and the output signal terminal 444.

[0071] The multilayered output combining layer unit 510 (510a, 510b, 510c) is provided with output electrodes 230 (230a, 230b, 230c) of equal length. Since the output electrodes 230 (230a, 230b, 230c) are provided on the multilayered output combining layer unit 510 (510a, 510b, 510c), there are no wiring pattern restrictions such as overlapping of wires, which is the case when wiring is performed on the same plane. This makes it easy to wire the output electrodes 230 (230a, 230b, 230c) with equal lengths, and provides the same effects as those described in the first embodiment of the present disclosure. Furthermore, since the output electrodes 230 (230a, 230b, 230c) are provided in the multi-layered output combining section, the effect of mitigating the influence of the interaction between the output electrodes can be obtained compared to when the output electrodes 230 (230a, 230b, 230c) are provided on the same plane.

[0072] This embodiment provides an example of the following configuration: a Doherty amplifier, wherein the output combining section is configured in multiple layers with output combining layer sections for the respective output electrodes. This provides an advantage of providing a Doherty amplifier that can reduce wiring pattern constraints. Furthermore, the present disclosure provides the same advantage as described above by applying the above configuration to communication devices such as mobile wireless terminals and base station devices.

[0073] Embodiment 5. In the above-described embodiment 4, an example of the configuration of a Doherty amplifier in which multiple output electrodes are arranged in layers is described. In embodiment 5, an example of the configuration of a Doherty amplifier in which multiple output electrodes are crossed in a three-dimensional manner is described. In embodiment 5, duplicated descriptions of the configuration of embodiment 5 that is the same as the configuration of embodiment 1, embodiment 2, embodiment 3, or embodiment 4 already described will be omitted as appropriate.

[0074] FIG. 5 is a diagram illustrating a configuration of a Doherty amplifier 100 (100E) according to a fifth embodiment of the present disclosure. Similar to FIG. 3 , FIG. 5 illustrates a packaged Doherty amplifier in which the configuration of the Doherty amplifier 100E according to the present embodiment is housed in a package 440. However, compared to the Doherty amplifiers 100 (100A, 100B, 100C) already described, the Doherty amplifier 100E according to the present embodiment only needs to have a multi-layered internal output combiner and a plurality of output-side electrodes crossing each other three-dimensionally. Hereinafter, the configuration in which the internal output combiner is multi-layered will be mainly described.

[0075] The output combining unit 603 has a plurality of output combining layers 610 (610a, 610b), and is configured so that the plurality of output combining layers 610 intersect and arrange a plurality of output electrodes in a three-dimensional manner. The output combining unit 603 shown in FIG. 5 includes an output combining layer 610a and an output combining layer 610b. Output electrodes 330 (330a, 330b, 330c) are arranged in the output combining layer 610a and the output combining layer 610b. The output combining layer 610a includes connecting portions (620, 630). The output electrodes 330 (330a, 330b, 330c) shown in FIG. 5 are each shaped to have a bent portion (first bent portion, second bent portion) at the connecting portions (620, 630). The connecting portions (620, 630) structurally connect the output combining layer portion 610a and the output combining layer portion 610b. At the connecting portions (620, 630), the output electrodes 330 (330a, 330b, 330c) in the output combining layer portion 610a and the output electrodes 330 (330a, 330b, 330c) in the output combining layer portion 610b intersect three-dimensionally. That is, the multiple output electrodes 330 (330a, 330b, 330c) are arranged to intersect three-dimensionally.

[0076] 5 , the first output electrode 330a is disposed on the output combining layer 610a from a first end, which is one of the ends, to a second end, which is the other of the ends, via bent portions (first bent portion, second bent portion) at the connecting portion 620. The second output electrode 330b is disposed on the output combining layer 610a from the first end, which is one of the ends, to just before the position where it intersects with the first output electrode 330a, a portion of which is disposed on the output combining layer 610b at the connecting portion 620 and intersects with the first output electrode 330a in a three-dimensional manner, and is then disposed on the output combining layer 610a again at the first bent portion at the connecting portion 620. The second output electrode 330b is further arranged on the output combining layer 610a up to just before the position where it intersects with the first output electrode 330a, a portion of it is arranged on the output combining layer 610b at the connecting portion 630 and intersects the first output electrode 330a three-dimensionally, and at the connecting portion 630, from the second bent portion to the second end, which is the other of both ends, is arranged again on the output combining layer 610a. The third output electrode 330c is arranged on the output combining layer 610a from the first end, which is one of both ends, to just before the position where it intersects with the first output electrode 330a, a portion of it is arranged on the output combining layer 610b at the connecting portion 620 and intersects the first output electrode 330a and the second output electrode 330b three-dimensionally, and at the connecting portion 620, it is arranged again on the output combining layer 610a. The third output electrode 330c is further arranged in the output synthesis layer section 610a up to just before the position where it intersects with the first output electrode 330a, a portion of it is arranged in the output synthesis layer section 610b at the connecting section 630 so that it intersects the first output electrode 330a and the second output electrode 330b in a three-dimensional manner, and the portion of the connecting section 630 from the second bend to the second end, which is the other of the two ends, is again arranged in the output synthesis layer section 610a.

[0077] The effects of the configuration according to this embodiment will be described below. The output combining layer section 610a includes a connecting section 620 and a connecting section 630. The connecting sections 620 and 630 structurally connect the output combining layer section 610a and the output combining layer section 610b, and the output electrodes 230a, 230b, and 230c can be interconnected between the output combining layer sections via the connecting sections 620 and 630, such as from the output combining layer section 610a to the output combining layer section 610b, or from the output combining layer section 610b to the output combining layer section 610a. By providing connecting sections such as the connecting sections 620 and 630, it is possible to avoid overlapping of the output electrodes 230a, 230b, and 230c at the connecting sections 620 and 630, thereby easing restrictions on the wiring pattern. This makes it easy to wire the plurality of output electrodes 230a, 230b, and 230c to have equal lengths, and provides the same effects as those described in the first embodiment of the present disclosure.

[0078] This embodiment provides an example of the following configuration: a Doherty amplifier, wherein the plurality of output electrodes are arranged to intersect in a three-dimensional manner. This provides an advantage of providing a Doherty amplifier that enables reduction in wiring pattern constraints. Furthermore, the present disclosure provides the same advantage as described above by applying the above configuration to communication devices such as mobile wireless terminals and base station devices.

[0079] It should be noted that within the scope of this disclosure, the embodiments may be freely combined, any components of the embodiments may be modified, or any components of the embodiments may be omitted. Specifically, for example, a Doherty amplifier may be configured by combining at least two of the configurations described in Embodiments 1 to 5, or by including two or more configurations. Such a configuration further reduces the constraints on the wiring pattern in the Doherty amplifier.

[0080] The present disclosure enables a high-output Doherty amplifier to be configured so that the combined combination of transistors in the carrier amplification section and transistors in the peak amplification section is uniquely determined, and is therefore suitable for use in amplifiers for mobile communications, such as portable wireless terminals and base stations.

[0081] 100 (100A, 100B, 100C, 100D, 100E) Doherty amplifier, 100' Doherty amplifier (reference configuration example), 101 carrier amplifier section, 102 peak amplifier section, 103 output circuit section (reference configuration example), 104 input circuit section, 105 output circuit section, 106 bonding wire, 107 bonding wire, 108 bonding wire, 109 bonding wire, 110 bonding wire, 130 output side terminal (reference configuration example), 203 output combining section, 208 bonding wire, 209 bonding wire, 210 bonding wire, 230a output side electrode (first electrode), 230b output side electrode (second electrode), 230c output side electrode (third electrode), 330a output side electrode (first bent-shaped electrode), 330b Output electrode (second bent electrode), 330c output electrode (third bent electrode), 440 package, 441 input signal terminal (first input signal terminal), 442 input signal terminal (second input signal terminal), 443 output signal terminal, 444 terminal, 503 output combining section, 510a output combining layer section (first output combining layer section), 510b output combining layer section (second output combining layer section), 510c output combining layer section (third output combining layer section), 603 output combining section, 610a output combining layer section, 610b output combining layer section, 620 connection section, 630 connection section, M01 transistor, M02 transistor, M03 transistor, A01 transistor, A02 transistor, A03 transistor, Aout path, Cout path, Dout1 path, Dout2 Route, Dout3 route.

Claims

1. A carrier amplification section including multiple transistors, A peak amplification section including multiple transistors, An output combining unit that combines the outputs of multiple transistors in the carrier amplification unit and the outputs of multiple transistors in the peak amplification unit, Equipped with, The output combining unit has multiple output electrodes that combine the outputs of multiple transistors in the carrier amplification unit and the outputs of multiple transistors in the peak amplification unit for each combination of transistors in the carrier amplification unit and the peak amplification unit. A Doherty amplifier characterized by the following features.

2. The Doherty amplifier according to claim 1, characterized in that the plurality of output electrodes are wired to be of equal length.

3. The paths in the output electrodes connecting the transistor of the carrier amplification section and the transistor of the peak amplification section are of equal length. A Doherty amplifier according to claim 1 or 2.

4. The aforementioned plurality of transistors are three or more. A Doherty amplifier according to claim 1 or 2.

5. The transistor and the output electrode are connected via a bonding wire. The length of the bonding wire is adjusted according to the shape of the output electrode or the position of the output electrode in the output synthesis section. A Doherty amplifier according to claim 1 or 2.

6. The output electrode has a shape having one or more bent portions. A Doherty amplifier according to claim 1 or 2.

7. A first input signal terminal connected to a plurality of transistors in the carrier amplification section to input signals, A second input signal terminal connected to the multiple transistors in the peak amplification section to input signals, Output signal terminals connected to the plurality of output side electrodes to output the signal synthesized by the output synthesis unit, A Doherty amplifier according to claim 1 or 2, characterized by comprising:

8. The output combining unit is configured in multiple layers, each consisting of an output combining layer for each output electrode. A Doherty amplifier according to claim 1 or 2.

9. The aforementioned plurality of output electrodes are arranged to intersect in three dimensions. A Doherty amplifier according to claim 1 or 2.