Semiconductor device

Abstract

Provided is a semiconductor device comprising: an insulating plate; a semiconductor element provided above the insulating plate and having a first control electrode and a second control electrode; a plurality of first conductive patterns provided above the insulating plate and electrically connected to the first control electrode; and a plurality of second conductive patterns provided above the insulating plate and electrically connected to the second control electrode. The plurality of first conductive patterns and the plurality of second conductive patterns are alternately arranged in a predetermined arrangement direction, the plurality of first conductive patterns are electrically connected to each other, and the plurality of second conductive patterns are electrically connected to each other.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] A semiconductor module is described in Patent Document 1. [Prior art documents] [Patent documents] [Patent document 1] JP 2024-013924 A [Patent document 2] WO 2023 / 037809 General disclosure

[0003] A first aspect of the present invention provides a semiconductor device comprising: an insulating plate; a semiconductor element provided above the insulating plate and having a first control electrode and a second control electrode; a plurality of first conductive patterns provided above the insulating plate and electrically connected to the first control electrode; and a plurality of second conductive patterns provided above the insulating plate and electrically connected to the second control electrode, wherein the plurality of first conductive patterns and the plurality of second conductive patterns are alternately arranged in a predetermined arrangement direction, and the plurality of first conductive patterns are electrically connected to each other, and the plurality of second conductive patterns are electrically connected to each other.

[0004] In the semiconductor device, two adjacent first conductive patterns may be connected to each other across a second conductive pattern between the two adjacent first conductive patterns, and two adjacent second conductive patterns may be connected to each other across a first conductive pattern between the two adjacent second conductive patterns.

[0005] In any of the semiconductor devices described above, a main conductive pattern may be provided between the insulating plate and the semiconductor element, the main conductive pattern extending in the arrangement direction, and the insulating plate and the semiconductor element may be disposed adjacent to the main conductive pattern in a direction perpendicular to the arrangement direction.

[0006] In any of the above semiconductor devices, the plurality of first conductive patterns may be electrically connected to one another via a wire member, and the plurality of second conductive patterns may be electrically connected to one another via a wire member.

[0007] In any of the above semiconductor devices, the wire member electrically connecting the plurality of first conductive patterns to one another may connect the two adjacent first conductive patterns over a second conductive pattern between two adjacent first conductive patterns, and the wire member electrically connecting the plurality of second conductive patterns to one another may connect the two adjacent second conductive patterns over a first conductive pattern between two adjacent second conductive patterns.

[0008] In any of the above semiconductor devices, the plurality of first conductive patterns may be electrically connected to the first control electrode via a wire member.

[0009] In any of the above semiconductor devices, the plurality of second conductive patterns may be electrically connected to the second control electrode via a wire member.

[0010] In any of the above semiconductor devices, at least one of the plurality of first conductive patterns may have a first wiring portion that wires a wire member for connection to the first control electrode and a second wiring portion that wires a wire member for connection to another first conductive pattern, and at least one of the plurality of second conductive patterns may have a third wiring portion that wires a wire member for connection to the second control electrode and a fourth wiring portion that wires a wire member for connection to another second conductive pattern.

[0011] In any of the above semiconductor devices, the second wiring portion may have an area smaller than that of the first wiring portion, and the fourth wiring portion may have an area smaller than that of the third wiring portion.

[0012] In any of the semiconductor devices described above, the first wiring portion may be closer to the semiconductor element than the second wiring portion in a direction perpendicular to the arrangement direction, and the third wiring portion may be closer to the semiconductor element than the fourth wiring portion in a direction perpendicular to the arrangement direction.

[0013] In any of the above semiconductor devices, two adjacent first conductive patterns may each have the first wiring portion and the second wiring portion. The wire member for connecting to another first conductive pattern may connect the second wiring portion of one of the two adjacent first conductive patterns to the first wiring portion of the other of the two adjacent first conductive patterns. Two adjacent second conductive patterns may each have the third wiring portion and the fourth wiring portion. The wire member for connecting to another second conductive pattern may connect the fourth wiring portion of one of the two adjacent second conductive patterns to the third wiring portion of the other of the two adjacent second conductive patterns.

[0014] In any of the above semiconductor devices, at least one of the plurality of first conductive patterns may have a generally rectangular fifth wiring portion. A wire member for connecting to the first control electrode and a wire member for connecting to another first conductive pattern may be wired to the fifth wiring portion. At least one of the plurality of second conductive patterns may have a generally rectangular sixth wiring portion. A wire member for connecting to the second control electrode and a wire member for connecting to another second conductive pattern may be wired to the sixth wiring portion.

[0015] In any of the above semiconductor devices, the semiconductor element may include a plurality of semiconductor elements arranged in the arrangement direction, and two adjacent semiconductor elements may be asymmetrical with respect to a direction perpendicular to the arrangement direction.

[0016] In any of the above semiconductor devices, the semiconductor element may include a plurality of semiconductor elements arranged in the arrangement direction, and two adjacent semiconductor elements may be mirror-symmetric with respect to a direction perpendicular to the arrangement direction.

[0017] In any of the above semiconductor devices, the semiconductor element may include a plurality of semiconductor elements arranged in the arrangement direction, the plurality of first conductive patterns may include a first conductive pattern to which one semiconductor element is connected, and the plurality of second conductive patterns may include a second conductive pattern to which one semiconductor element is connected.

[0018] In any of the above semiconductor devices, the semiconductor element may include a plurality of semiconductor elements arranged in the arrangement direction, the plurality of first conductive patterns may include a first conductive pattern to which two semiconductor elements are connected, and the plurality of second conductive patterns may include a second conductive pattern to which two semiconductor elements are connected.

[0019] In any of the above semiconductor devices, the plurality of first conductive patterns may include first conductive patterns that are connected to adjacent first conductive patterns but not connected to the semiconductor element, and the plurality of second conductive patterns may include second conductive patterns that are connected to adjacent second conductive patterns but not connected to the semiconductor element.

[0020] In any of the above semiconductor devices, the semiconductor element may include a wide bandgap semiconductor.

[0021] In any of the above semiconductor devices, the wide bandgap semiconductor may include any of a silicon carbide semiconductor, a gallium nitride semiconductor, and a gallium oxide semiconductor.

[0022] Any of the above semiconductor devices may include a first external control terminal electrically connected to the plurality of first conductive patterns, a second external control terminal electrically connected to the plurality of second conductive patterns, and an external main terminal electrically connected to a main conductive pattern that carries a main current of the semiconductor element.

[0023] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0024] 1 shows an example of a perspective view of the semiconductor device 100. 2 shows an example of a plan view of the semiconductor device 100. 3 shows an example of a region R of the semiconductor device 100. 4 shows an example of a region R of a semiconductor device 500 according to a comparative example. 5 shows an example of a main current fluctuation in the semiconductor device 100. 6 shows an example of a main current fluctuation in the semiconductor device 500 according to a comparative example. 7 shows an example of magnetic flux interchange in the semiconductor device 100. 8 shows an example of magnetic flux interchange in the semiconductor device 500 according to the comparative example. 9 shows a region R of a modified example of the semiconductor device 100. 10 shows a region R of a modified example of the semiconductor device 100. 11 shows a region R of a modified example of the semiconductor device 100.

[0025] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0026] In this specification, one side of a semiconductor chip in a direction parallel to the depth direction of a semiconductor substrate is referred to as "top" and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other member, one is referred to as the top surface and the other as the bottom surface. The directions of "top," "bottom," "front," and "back" are not limited to the direction of gravity or the direction in which the semiconductor device is attached to a substrate or the like when mounted.

[0027] In this specification, technical matters may be explained using orthogonal coordinate axes of X, Y, and Z. In this specification, a plane parallel to the top surface of a semiconductor chip is defined as the XY plane, and the depth direction of a semiconductor substrate of the semiconductor chip is defined as the Z axis.

[0028] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0029] 1A shows an example of a perspective view of a semiconductor device 100. The semiconductor device 100 includes a case portion 110, a base portion 120, and a plurality of terminals. The semiconductor device 100 may function as a part of a power conversion device such as an inverter. The semiconductor device 100 may house a semiconductor chip or the like inside.

[0030] The case 110 accommodates the semiconductor chip and other components of the semiconductor device 100. The case 110 is molded from insulating resin. The case 110 is provided on the base 120.

[0031] The base portion 120 is fixed to the case portion 110 with screws, adhesive, or the like. The case portion 110 may be provided with holes for fixing the base portion 120. The base portion 120 may be set to a ground potential. The base portion 120 has a main surface in the XY plane.

[0032] A plurality of terminals may be provided on the upper surface of the case 110. In this example, an external main terminal 130, a first external control terminal 140, and a second external control terminal 142 are provided on the upper surface of the case 110. The external main terminal 130 may include an external output terminal 132, an external positive terminal 134, and an external negative terminal 136. The external output terminal 132, the external positive terminal 134, and the external negative terminal 136 may form a current path for a large current flowing through the power semiconductor element.

[0033] The external output terminal 132 is an AC output terminal. The external positive terminal 134 is a positive terminal of a DC power supply. The external negative terminal 136 is a negative terminal of the DC power supply. Each terminal may be electrically connected to a corresponding terminal of a semiconductor chip or the like included in the semiconductor device 100.

[0034] The first external control terminal 140 is a terminal that supplies a first control signal to the semiconductor element 10, which will be described later. The second external control terminal 142 is a terminal that supplies a second control signal to the semiconductor element 10. The first control signal and the second control signal will be described later.

[0035] 1B shows an example of a plan view of the semiconductor device 100. The figure shows an example of the layout of circuits provided on the base portion 120 inside the case portion 110. The semiconductor device 100 includes one or more insulating plates 20 on the base portion 120.

[0036] The semiconductor device 100 of this example includes two insulating plates 20 on a base portion 120. In this example, the two insulating plates 20 are arranged side by side in the X-axis direction on the base portion 120. A plurality of semiconductor elements 10 and a plurality of wiring patterns may be arranged on the insulating plates 20. The plurality of insulating plates 20 may be connected via a lead frame 22. In this example, a plurality of insulating plates 20 are arranged on the base portion 120, but a single insulating plate 20 may also be arranged on the base portion 120.

[0037] The insulating plate 20 is bonded to the base portion 120. The insulating plate 20 may be a ceramic (e.g., alumina) substrate with good thermal conductivity, with conductive patterns on both sides. For example, the insulating plate 20 is a DCB (Direct Copper Bond) substrate in which a copper circuit plate is directly bonded onto a ceramic substrate. The insulating plates 20 are connected in parallel.

[0038] A first connection portion 40 and a second connection portion 42 may be provided on the base portion 120. The first connection portion 40 is connected to a first external control terminal 140. The second connection portion 42 is connected to a second external control terminal 142.

[0039] The insulating plate 20 may have an output terminal 32, a positive terminal 34, and a negative terminal 36. In the semiconductor device 100 of this example, the insulating plate 20-1 has the output terminal 32, and the insulating plate 20-2 has the positive terminal 34 and the negative terminal 36. However, each of the insulating plates 20 of the semiconductor device 100 may have the output terminal 32, the positive terminal 34, and the negative terminal 36.

[0040] Each terminal may be electrically connected to each external terminal via a connecting member such as a lead frame. The output terminal 32 is electrically connected to an external output terminal 132. The positive terminal 34 is electrically connected to an external positive terminal 134. The negative terminal 36 is electrically connected to an external negative terminal 136.

[0041] A main conductive pattern 50, a plurality of first conductive patterns 60, and a plurality of second conductive patterns 70 are provided above the insulating plate 20. The main conductive pattern 50 is provided between the insulating plate 20 and the semiconductor element 10 and is a conductive pattern through which the main current of the semiconductor element 10 flows. The main conductive pattern 50 is provided with an output terminal 32, a positive terminal 34, and a negative terminal 36. Therefore, the main conductive pattern 50 may be electrically connected to each of the external output terminal 132, the external positive terminal 134, and the external negative terminal 136. In other words, the external main terminal 130 may be electrically connected to the main conductive pattern 50 through which the main current of the semiconductor element 10 flows. The main conductive patterns 50 of the plurality of insulating plates 20 may be electrically connected to each other via the lead frame 22.

[0042] The plurality of first conductive patterns 60 are electrically connected to each other. The plurality of first conductive patterns 60 may be electrically connected to the first connection portion 40. That is, the first external control terminal 140 may be electrically connected to the plurality of first conductive patterns 60.

[0043] The plurality of second conductive patterns 70 are electrically connected to one another. The plurality of second conductive patterns 70 may be electrically connected to the second connection portion 42. That is, the second external control terminal 142 may be electrically connected to the plurality of second conductive patterns 70.

[0044] The semiconductor element 10 is provided above the insulating plate 20. The semiconductor element 10 may be provided above the main conductive pattern 50. The semiconductor element 10 may be a power semiconductor element. For example, the semiconductor element 10 may be an IGBT or a MOSFET. The semiconductor element 10 may include a wide bandgap semiconductor. As an example, the wide bandgap semiconductor includes any of a silicon carbide semiconductor, a gallium nitride semiconductor, and a gallium oxide semiconductor. As another example, the wide bandgap semiconductor may include diamond.

[0045] 1C shows an example of a region R of the semiconductor device 100. The region R is the region shown in FIG.

[0046] The semiconductor element 10 has a first control electrode 12 and a second control electrode 14. For example, if the semiconductor element 10 is an IGBT, the first control electrode 12 may be a base electrode, and the second control electrode 14 may be an emitter electrode. As another example, if the semiconductor element 10 is a MOSFET, the first control electrode 12 may be a gate electrode, and the second control electrode 14 may be a source electrode. Although the semiconductor element 10 of this example has one first control electrode 12 and two second control electrodes 14 that are separated from each other, the number and arrangement of electrodes of the semiconductor element 10 are not limited to this example.

[0047] The plurality of first conductive patterns 60 are electrically connected to the first control electrode 12. The plurality of first conductive patterns 60 may be electrically connected to the first control electrode 12 via wire members 80. As described above, the plurality of first conductive patterns 60 are electrically connected to one another, the plurality of first conductive patterns 60 are electrically connected to the first connection portion 40, and the first external control terminal 140 is electrically connected to the plurality of first conductive patterns 60. The semiconductor element 10 is controlled by inputting a first control signal from the first external control terminal 140 to the first control electrode 12.

[0048] The plurality of second conductive patterns 70 are electrically connected to the second control electrode 14. The plurality of second conductive patterns 70 may be electrically connected to the second control electrode 14 via wire members 80. As described above, the plurality of second conductive patterns 70 are electrically connected to one another, the plurality of second conductive patterns 70 are electrically connected to the second connection portion 42, and the second external control terminal 142 is electrically connected to the plurality of second conductive patterns 70. The semiconductor element 10 is controlled by inputting a second control signal from the second external control terminal 142 to the second control electrode 14.

[0049] The plurality of first conductive patterns 60 and the plurality of second conductive patterns 70 are alternately arranged in a predetermined arrangement direction. In this example, the first conductive patterns 60 and the second conductive patterns 70 are alternately arranged in the X-axis direction. That is, the arrangement direction in this example is the X-axis direction.

[0050] In the semiconductor device 100 of this example, the first conductive patterns 60 and the second conductive patterns 70 are alternately arranged in a predetermined arrangement direction (e.g., the X-axis direction), so that the distance between each conductive pattern and the semiconductor element 10 can be made substantially the same in a direction perpendicular to the arrangement direction (e.g., the Y-axis direction). This makes it possible to minimize the lengths of both the wire members 80 connecting the first conductive patterns 60 and the first control electrode 12 and the wire members 80 connecting the second conductive patterns 70 and the second control electrode 14. This makes it possible to reduce the parasitic inductance of both the current path for controlling the first control electrode 12 and the current path for controlling the second control electrode 14.

[0051] Two adjacent first conductive patterns 60 may be connected to each other across a second conductive pattern 70 between the two adjacent first conductive patterns 60. For example, adjacent first conductive patterns 60a and 60b are connected to each other across a second conductive pattern 70a between first conductive patterns 60a and 60b.

[0052] The multiple first conductive patterns 60 may be electrically connected to one another via wire members 80. The wire members 80 electrically connecting the multiple first conductive patterns 60 to one another may connect two adjacent first conductive patterns 60 by extending over the second conductive pattern 70 between the two adjacent first conductive patterns 60. For example, the wire member 80a electrically connecting the adjacent first conductive patterns 60a and 60b connects the first conductive pattern 60a and the first conductive pattern 60b by extending over the second conductive pattern 70a between the first conductive pattern 60a and the first conductive pattern 60b.

[0053] Two adjacent second conductive patterns 70 may be connected to each other across the first conductive pattern 60 between the two adjacent second conductive patterns 70. For example, adjacent second conductive patterns 70a and 70b are connected to each other across the first conductive pattern 60b between second conductive patterns 70a and 70b.

[0054] The multiple second conductive patterns 70 may be electrically connected to one another via wire members 80. The wire members 80 electrically connecting the multiple second conductive patterns 70 to one another may connect two adjacent second conductive patterns 70 by extending over the first conductive pattern 60 between the two adjacent second conductive patterns 70. For example, the wire member 80b electrically connecting the adjacent second conductive patterns 70a and 70b connects the second conductive pattern 70a and the second conductive pattern 70b by extending over the first conductive pattern 60b between the second conductive patterns 70a and 70b.

[0055] In the semiconductor device 100 of this example, the first conductive patterns 60 are connected to each other across the second conductive patterns 70, and the second conductive patterns 70 are connected to each other across the first conductive patterns 60. As a result, a control signal path including a plurality of first conductive patterns 60 and a control signal path including a plurality of second conductive patterns 70 form a twisted current path. By forming each control signal path as a twisted current path, when magnetic flux crosses the control signal path, induced electromotive forces cancel each other out within the control signal path, thereby suppressing the effects of magnetic flux crossing. Details of suppressing the effects of magnetic flux crossing by twisted current paths will be described later.

[0056] The main conductive pattern 50 may be provided extending in the arrangement direction of the first conductive pattern 60 and the second conductive pattern 70. In this example, the main conductive pattern 50 is provided extending in the X-axis direction. The plurality of first conductive patterns 60 and the plurality of second conductive patterns 70 may be adjacent to the main conductive pattern 50 in a direction perpendicular to the arrangement direction. In this example, the plurality of first conductive patterns 60 and the plurality of second conductive patterns 70 are adjacent to the main conductive pattern 50 in the Y-axis direction.

[0057] In the semiconductor device 100 of this example, the main conductive pattern 50 is provided extending in the arrangement direction of the first conductive patterns 60 and the second conductive patterns 70, and the first conductive patterns 60 and the second conductive patterns 70 are provided adjacent to the main conductive pattern 50 in a direction perpendicular to the arrangement direction. This makes it possible to suppress imbalance in back electromotive force that occurs in a control signal path including the plurality of first conductive patterns 60 and a control signal path including the plurality of second conductive patterns 70 due to fluctuations in the main current flowing through the main conductive pattern 50. Suppressing imbalance in back electromotive force makes it possible to suppress imbalance in the potential difference between the first control electrode 12 and the second control electrode 14 of the semiconductor element 10. Details of suppressing imbalance in back electromotive force due to the arrangement relationship of each conductive pattern will be described later.

[0058] At least one of the multiple first conductive patterns 60 may have a first wiring portion 62 and a second wiring portion 64. In the semiconductor device 100 of this example, all of the first conductive patterns 60 have the first wiring portion 62 and the second wiring portion 64.

[0059] The first wiring portion 62 may have wire members 80 for connection to the first control electrode 12. The second wiring portion 64 may have wire members 80 for connection to other first conductive patterns 60. For example, the first wiring portion 62 of the first conductive pattern 60b has wire members 80c and 80d for connection to the first control electrode 12 wired thereto. The second wiring portion 64 of the first conductive pattern 60b has wire member 80a for connection to other first conductive patterns 60a wired thereto.

[0060] The area of ​​the second wiring portion 64 may be smaller than the area of ​​the first wiring portion 62. The first wiring portion 62 may be closer to the semiconductor element 10 in a direction perpendicular to the arrangement direction than the second wiring portion 64. In this example, the first wiring portion 62 is closer to the semiconductor element 10 in the Y-axis direction than the second wiring portion 64.

[0061] Each of two adjacent first conductive patterns 60 may have a first wiring portion 62 and a second wiring portion 64. For example, each of adjacent first conductive patterns 60a and first conductive patterns 60b has a first wiring portion 62 and a second wiring portion 64. A wire member 80 for connecting to another first conductive pattern 60 may connect the second wiring portion 64 of one of the two adjacent first conductive patterns 60 to the first wiring portion 62 of the other of the two adjacent first conductive patterns 60. In this example, the wire member 80a connects the second wiring portion 64 of the first conductive pattern 60b to the first wiring portion 62 of the first conductive pattern 60a.

[0062] At least one of the multiple second conductive patterns 70 may have a third wiring portion 72 and a fourth wiring portion 74. In the semiconductor device 100 of the present example, all of the second conductive patterns 70 have the third wiring portion 72 and the fourth wiring portion 74.

[0063] The third wiring portion 72 may have wire members 80 for connection to the second control electrode 14. The fourth wiring portion 74 may have wire members 80 for connection to other second conductive patterns 70. For example, the third wiring portion 72 of the second conductive pattern 70b has wire members 80e-80h for connection to the second control electrode 14 wired thereto. The fourth wiring portion 74 of the second conductive pattern 70b has wire members 80b for connection to other second conductive patterns 70a wired thereto.

[0064] The area of ​​the fourth wiring portion 74 may be smaller than the area of ​​the third wiring portion 72. The third wiring portion 72 may be closer to the semiconductor element 10 in a direction perpendicular to the arrangement direction than the fourth wiring portion 74. In this example, the third wiring portion 72 is closer to the semiconductor element 10 in the Y-axis direction than the fourth wiring portion 74.

[0065] Each of two adjacent second conductive patterns 70 may have a third wiring portion 72 and a fourth wiring portion 74. For example, each of adjacent second conductive patterns 70a and 70b has a third wiring portion 72 and a fourth wiring portion 74. A wire member 80 for connecting to another second conductive pattern 70 may connect the fourth wiring portion 74 of one of two adjacent second conductive patterns 70 to the third wiring portion 72 of the other of the two adjacent second conductive patterns 70. In this example, the wire member 80b connects the fourth wiring portion 74 of the second conductive pattern 70b to the third wiring portion 72 of the second conductive pattern 70a.

[0066] As described above, in the semiconductor device 100 of this example, the first conductive pattern 60 and the second conductive pattern 70 each have a wiring portion for wiring the wire member 80 for connection to the control electrode of the semiconductor element 10, and a wiring portion for wiring the wire member 80 for connection to another conductive pattern. This makes it possible to improve the bondability of the wire member 80 while minimizing the space required for the areas in which the first conductive pattern 60 and the second conductive pattern 70 are arranged.

[0067] In order to improve the bondability of the wire member 80, it is preferable to bond a certain area or more in the extension direction of the wire member 80. In the semiconductor device 100 of this example, the extension direction of the bonding portion of the wire member 80 for connecting the first conductive patterns 60 to each other and the second conductive patterns 70 to each other is the arrangement direction of the first conductive patterns 60 and the second conductive patterns 70, so the bonding area in the direction perpendicular to the arrangement direction can be reduced. In other words, the areas of the second wiring portion 64 and the fourth wiring portion 74 can be reduced. This makes it possible to improve the bondability of the wire member 80 while shortening the length in the direction perpendicular to the arrangement direction and reducing space.

[0068] The semiconductor element 10 may include a plurality of semiconductor elements 10 arranged in the arrangement direction. Two adjacent semiconductor elements 10 may be mirror-symmetric with respect to a direction perpendicular to the arrangement direction. For example, the semiconductor elements 10a and 10b adjacent to each other are mirror-symmetric with respect to the Y-axis direction. The semiconductor elements 10b and 10c adjacent to each other are mirror-symmetric with respect to the Y-axis direction. In this way, in the semiconductor device 100 of this example, the semiconductor elements 10 that are mirror-symmetric with each other are alternately arranged.

[0069] The plurality of first conductive patterns 60 may include first conductive patterns 60 in which two semiconductor elements 10 are connected. For example, the plurality of first conductive patterns 60 may include first conductive patterns 60a in which semiconductor elements 10a and 10b are connected. The plurality of second conductive patterns 70 may include second conductive patterns 70 in which two semiconductor elements 10 are connected. For example, the plurality of second conductive patterns 70 may include second conductive patterns 70a in which semiconductor elements 10b and 10c are connected.

[0070] The plurality of first conductive patterns 60 may include first conductive patterns 60 that are connected to adjacent first conductive patterns 60 but are not connected to the semiconductor element 10. For example, the plurality of first conductive patterns 60 include a first conductive pattern 60c that is connected to an adjacent first conductive pattern 60a but is not connected to the semiconductor element 10. Although not shown in the present example, the plurality of second conductive patterns 70 may similarly include a second conductive pattern 70 that is connected to adjacent second conductive patterns 70 but is not connected to the semiconductor element 10.

[0071] 2 shows an example of a region R of a semiconductor device 500 according to a comparative example. In the semiconductor device 500, a first control pattern 560 and a second control pattern 570 extending in the extension direction of the main conductive pattern 50 are provided.

[0072] In the semiconductor device 500 according to the comparative example, both the first control pattern 560 and the second control pattern 570 are provided in an elongated manner, so that one is adjacent to the semiconductor element 10 and the other is not adjacent to the semiconductor element 10. In the example of FIG. 2 , the first control pattern 560 is adjacent to the semiconductor element 10, and the second control pattern 570 is not adjacent to the semiconductor element 10. With this arrangement, the wire member 80 for connecting to the second control pattern 570 on the side farther from the semiconductor element 10 is longer than the wire member 80 for connecting to the first control pattern 560 on the side closer to the semiconductor element 10. As a result, it may not be possible to reduce the parasitic inductance of the current path that controls the second control electrode 14.

[0073] On the other hand, according to the semiconductor device 100 of the embodiment, the first conductive patterns 60 and the second conductive patterns 70 are alternately arranged in a predetermined arrangement direction (e.g., the X-axis direction), so that the distance between each conductive pattern and the semiconductor element 10 can be made substantially the same in a direction perpendicular to the arrangement direction (e.g., the Y-axis direction). This makes it possible to minimize the lengths of both the wire members 80 connecting the first conductive patterns 60 and the first control electrode 12 and the wire members 80 connecting the second conductive patterns 70 and the second control electrode 14. This makes it possible to reduce the parasitic inductance of both the current path for controlling the first control electrode 12 and the current path for controlling the second control electrode 14.

[0074] In the semiconductor device 500 according to the comparative example, both the first control pattern 560 and the second control pattern 570 are provided in an extended manner. In this case, in order to improve the bondability of the wire members 80 for connecting each control pattern to the control electrode of the semiconductor element 10, the width of each control pattern in the direction perpendicular to the extension direction needs to be at least a certain amount. As a result, it may not be possible to achieve both improved bondability of the wire members 80 and space saving at the same time.

[0075] On the other hand, in the semiconductor device 100 according to the embodiment, each of the first conductive pattern 60 and the second conductive pattern 70 has a wiring portion for wiring the wire member 80 for connection to the control electrode of the semiconductor element 10, and a wiring portion for wiring the wire member 80 for connection to another conductive pattern. This makes it possible to improve the bondability of the wire member 80 while minimizing the space required for the areas in which the first conductive pattern 60 and the second conductive pattern 70 are arranged.

[0076] 3A shows an example of a main current fluctuation in the semiconductor device 100. For example, when a main current fluctuation occurs in the −X-axis direction in the main conductive pattern 50, a counter electromotive force in the +X-axis direction is generated in each of the first conductive pattern 60 and the second conductive pattern 70.

[0077] In the semiconductor device 100 of this example, the main conductive pattern 50 is provided extending in the arrangement direction of the first conductive pattern 60 and the second conductive pattern 70, and the first conductive pattern 60 and the second conductive pattern 70 are provided adjacent to the main conductive pattern 50 in a direction perpendicular to the arrangement direction. This causes counter electromotive forces of approximately the same magnitude to be generated in the first conductive pattern 60 and the second conductive pattern 70. Therefore, it is possible to suppress imbalance in the potential difference between the first control electrode 12 and the second control electrode 14 of the semiconductor element 10.

[0078] 3B shows an example of main current fluctuation in the semiconductor device 500 according to the comparative example. For example, when a main current fluctuation occurs in the −X-axis direction in the main conductive pattern 50, a back electromotive force in the +X-axis direction is generated in each of the first control pattern 560 and the second control pattern 570.

[0079] In the semiconductor device 500 according to the comparative example, one of the first control pattern 560 and the second control pattern 570 is adjacent to the semiconductor element 10, and the other is not adjacent to the semiconductor element 10. In the example of FIG. 3B , the first control pattern 560 is adjacent to the semiconductor element 10, and the second control pattern 570 is not adjacent to the semiconductor element 10. With this arrangement, the counter electromotive force generated in the first control pattern 560 is larger than the counter electromotive force generated in the second control pattern 570. Therefore, an imbalance in the potential difference between the first control electrode 12 and the second control electrode 14 of the semiconductor element 10 may occur.

[0080] 4A shows an example of magnetic flux intersection in the semiconductor device 100. For example, when magnetic flux intersection occurs in the +Z-axis direction, a counterclockwise induced electromotive force is generated.

[0081] In the semiconductor device 100 of this example, a control signal path including a plurality of first conductive patterns 60 and a control signal path including a plurality of second conductive patterns 70 form a twisted current path. As a result, induced electromotive forces in opposite directions are generated between adjacent first conductive patterns 60, and the induced electromotive forces due to magnetic flux intersection cancel each other out between adjacent first conductive patterns 60. Similarly, induced electromotive forces cancel each other out between adjacent second conductive patterns 70. Therefore, when magnetic flux intersection occurs in the control signal path, the induced electromotive forces cancel each other out within the control signal path, thereby suppressing the effects of magnetic flux intersection.

[0082] 4B shows an example of magnetic flux intersection in the semiconductor device 500 according to the comparative example. For example, when magnetic flux intersection occurs in the +Z-axis direction, a counterclockwise induced electromotive force is generated.

[0083] In the semiconductor device 500 according to the comparative example, both the first control pattern 560 and the second control pattern 570 are provided in an elongated manner, so that an induced electromotive force is generated in one direction as a whole in each of the first control pattern 560 and the second control pattern 570. As a result, the induced electromotive forces are not canceled out within the control patterns. Therefore, when magnetic fluxes intersect in the control signal path, the effects of the magnetic flux intersect may not be suppressed.

[0084] As described above, the semiconductor device 100 according to the embodiment can reduce the parasitic inductance of the current path for controlling the semiconductor element 10 and suppress the effects of main current fluctuations and magnetic flux crossings, thereby suppressing the effects of electromagnetic radiation noise and reducing the risk of false firing of the semiconductor element 10.

[0085] 5 shows a region R of a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 1C in that the number of semiconductor elements 10 is different. In this example, differences from the embodiment of FIG. 1C will be particularly described, and the rest may be the same as the embodiment of FIG. 1C.

[0086] The semiconductor element 10 may include a plurality of semiconductor elements 10 arranged in an arrangement direction. Two adjacent semiconductor elements 10 may be asymmetrical with respect to a direction perpendicular to the arrangement direction. For example, the semiconductor elements 10a and 10b adjacent to each other are asymmetrical with respect to the Y-axis direction. The semiconductor elements 10b and 10c adjacent to each other are asymmetrical with respect to the Y-axis direction.

[0087] The plurality of first conductive patterns 60 may include a first conductive pattern 60 connected to one semiconductor element 10. For example, the plurality of first conductive patterns 60 includes a first conductive pattern 60a connected to one semiconductor element 10a. The plurality of second conductive patterns 70 may include a second conductive pattern 70 connected to one semiconductor element 10. For example, the plurality of second conductive patterns 70 includes a second conductive pattern 70a connected to one semiconductor element 10c.

[0088] The plurality of first conductive patterns 60 may include first conductive patterns 60 that are connected to adjacent first conductive patterns 60 but not connected to the semiconductor element 10. For example, the plurality of first conductive patterns 60 include a first conductive pattern 60b that is connected to an adjacent first conductive pattern 60a but not connected to the semiconductor element 10. The plurality of second conductive patterns 70 may include a second conductive pattern 70 that is connected to an adjacent second conductive pattern 70 but not connected to the semiconductor element 10. For example, the plurality of second conductive patterns 70 include a second conductive pattern 70b that is connected to an adjacent second conductive pattern 70a but not connected to the semiconductor element 10.

[0089] 6 shows region R of a modified example of semiconductor device 100. Semiconductor device 100 of this example differs from the embodiment of FIG. 1C in that the wiring positions of wire members 80 in first conductive pattern 60 and second conductive pattern 70 are different. In this example, differences from the embodiment of FIG. 1C will be particularly described, and the rest may be the same as the embodiment of FIG. 1C.

[0090] In the first wiring portion 62 of the first conductive pattern 60, the ends of the wire members 80 for connecting the first conductive patterns 60 to each other and the ends of the wire members 80 for connecting the first conductive patterns 60 to the semiconductor element 10 may be arranged in the arrangement direction. For example, in the first wiring portion 62 of the first conductive pattern 60a, the ends of the wire members 80a for connecting the first conductive patterns 60 to each other and the ends of the wire members 80b and 80c for connecting the first conductive pattern 60a to the semiconductor element 10 are arranged in the X-axis direction.

[0091] In the third wiring portion 72 of the second conductive pattern 70, the ends of the wire members 80 for connecting the second conductive patterns 70 to each other and the ends of the wire members 80 for connecting the second conductive patterns 70 to the semiconductor element 10 may be arranged in the arrangement direction. For example, in the third wiring portion 72 of the second conductive pattern 70a, the end of the wire member 80d for connecting the second conductive patterns 70 to each other and the ends of the wire members 80e-80h for connecting the second conductive pattern 70a to the semiconductor element 10 are arranged in the X-axis direction.

[0092] In semiconductor device 100 of the present example, the ends of wire members 80 for connecting conductive patterns to each other and the ends of wire members 80 for connecting conductive patterns to semiconductor element 10 are arranged in the arrangement direction. This allows the areas of first wiring portion 62 and third wiring portion 72 to be smaller than when the ends are not arranged, thereby achieving further space savings.

[0093] 7 shows a region R of a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 1C in that the shapes of the first conductive pattern 60 and the second conductive pattern 70 are different. In this example, differences from the embodiment of FIG. 1C will be particularly described, and the rest may be the same as the embodiment of FIG. 1C.

[0094] At least one of the multiple first conductive patterns 60 may have a substantially rectangular fifth wiring portion 66. In the semiconductor device 100 of the present example, all of the first conductive patterns 60 have the fifth wiring portion 66. The wire member 80 for connecting to the first control electrode 12 and the wire member 80 for connecting to other first conductive patterns 60 may be wired to the fifth wiring portion 66. For example, the wire member 80 for connecting the first conductive pattern 60a to the first control electrode 12 and the wire member 80 for connecting the first conductive pattern 60a to other first conductive patterns 60b are wired to the fifth wiring portion 66 of the first conductive pattern 60a.

[0095] At least one of the multiple second conductive patterns 70 may have a sixth wiring portion 76 having a substantially rectangular shape. In the semiconductor device 100 of the present example, all of the second conductive patterns 70 have the sixth wiring portion 76. The wire member 80 for connecting to the second control electrode 14 and the wire member 80 for connecting to other second conductive patterns 70 may be wired to the sixth wiring portion 76. For example, the wire member 80 for connecting the second conductive pattern 70a to the second control electrode 14 and the wire member 80 for connecting the second conductive pattern 70a to other second conductive patterns 70b are wired to the sixth wiring portion 76 of the second conductive pattern 70a.

[0096] The configurations described in each of Figures 1C and 5 to 7 may be used together with the configurations described in the other figures, i.e., the semiconductor device 100 according to the present invention may include all or any combination of the configurations described in Figures 1C and 5 to 7.

[0097] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0098] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0099] REFERENCE SIGNS LIST 10 Semiconductor element, 12 First control electrode, 14 Second control electrode, 20 Insulating plate, 22 Lead frame, 32 Output terminal, 34 Positive electrode terminal, 36 Negative electrode terminal, 40 First connection portion, 42 Second connection portion, 50 Main conductive pattern, 60 First conductive pattern, 62 First wiring portion, 64 Second wiring portion, 66 Fifth wiring portion, 70 Second conductive pattern, 72 Third wiring portion, 74 Fourth wiring portion, 76 Sixth wiring portion, 80 Wire member, 100 Semiconductor device, 110 Case portion, 120 Base portion, 130 External main terminal, 132 External output terminal, 134 External positive electrode terminal, 136 External negative electrode terminal, 140 First external control terminal, 142 Second external control terminal

Claims

1. A semiconductor device comprising: an insulating plate; a semiconductor element provided above the insulating plate and having a first control electrode and a second control electrode; a plurality of first conductive patterns provided above the insulating plate and electrically connected to the first control electrode; and a plurality of second conductive patterns provided above the insulating plate and electrically connected to the second control electrode, wherein the plurality of first conductive patterns and the plurality of second conductive patterns are alternately arranged in a predetermined arrangement direction, and the plurality of first conductive patterns are electrically connected to each other, and the plurality of second conductive patterns are electrically connected to each other.

2. The semiconductor device according to claim 1, wherein two adjacent first conductive patterns are connected to each other across a second conductive pattern between the two adjacent first conductive patterns, and two adjacent second conductive patterns are connected to each other across a first conductive pattern between the two adjacent second conductive patterns.

3. The semiconductor device according to claim 1, further comprising a main conductive pattern extending in the arrangement direction, provided between the insulating plate and the semiconductor element, and through which a main current of the semiconductor element flows, wherein the plurality of first conductive patterns and the plurality of second conductive patterns are adjacent to the main conductive pattern in a direction perpendicular to the arrangement direction.

4. The semiconductor device according to claim 1, wherein the plurality of first conductive patterns are electrically connected to one another via wire members, and the plurality of second conductive patterns are electrically connected to one another via wire members.

5. The semiconductor device described in claim 4, wherein the wire member electrically connecting the plurality of first conductive patterns to each other connects the two adjacent first conductive patterns beyond a second conductive pattern between two adjacent first conductive patterns, and the wire member electrically connecting the plurality of second conductive patterns to each other connects the two adjacent second conductive patterns beyond a first conductive pattern between two adjacent second conductive patterns.

6. The semiconductor device according to claim 1, wherein the plurality of first conductive patterns are electrically connected to the first control electrode via a wire member.

7. The semiconductor device according to claim 1, wherein the plurality of second conductive patterns are electrically connected to the second control electrode via a wire member.

8. The semiconductor device according to claim 1, wherein at least one of the plurality of first conductive patterns has a first wiring section that wires a wire member for connection to the first control electrode, and a second wiring section that wires a wire member for connection to other first conductive patterns; and at least one of the plurality of second conductive patterns has a third wiring section that wires a wire member for connection to the second control electrode, and a fourth wiring section that wires a wire member for connection to other second conductive patterns.

9. The semiconductor device according to claim 8, wherein the area of ​​the second wiring portion is smaller than the area of ​​the first wiring portion, and the area of ​​the fourth wiring portion is smaller than the area of ​​the third wiring portion.

10. The semiconductor device according to claim 8, wherein the first wiring portion is closer to the semiconductor element than the second wiring portion in a direction perpendicular to the arrangement direction, and the third wiring portion is closer to the semiconductor element than the fourth wiring portion in a direction perpendicular to the arrangement direction.

11. The semiconductor device of claim 8, wherein each of two adjacent first conductive patterns has the first wiring portion and the second wiring portion, the wire member for connection to another first conductive pattern connects the second wiring portion of one of the two adjacent first conductive patterns to the first wiring portion of the other of the two adjacent first conductive patterns, each of two adjacent second conductive patterns has the third wiring portion and the fourth wiring portion, and the wire member for connection to another second conductive pattern connects the fourth wiring portion of one of the two adjacent second conductive patterns to the third wiring portion of the other of the two adjacent second conductive patterns.

12. The semiconductor device according to claim 1, wherein at least one of the plurality of first conductive patterns has a fifth wiring portion having a substantially rectangular shape, and a wire member for connecting to the first control electrode and a wire member for connecting to other first conductive patterns are wired to the fifth wiring portion, and at least one of the plurality of second conductive patterns has a sixth wiring portion having a substantially rectangular shape, and a wire member for connecting to the second control electrode and a wire member for connecting to other second conductive patterns are wired to the sixth wiring portion.

13. A semiconductor device according to any one of claims 1 to 12, wherein the semiconductor elements include a plurality of semiconductor elements arranged in the arrangement direction, and two adjacent semiconductor elements are asymmetrical with respect to a direction perpendicular to the arrangement direction.

14. A semiconductor device according to any one of claims 1 to 12, wherein the semiconductor elements include a plurality of semiconductor elements arranged in the arrangement direction, and two adjacent semiconductor elements are mirror-symmetric with respect to a direction perpendicular to the arrangement direction.

15. A semiconductor device according to any one of claims 1 to 12, wherein the semiconductor element includes a plurality of semiconductor elements arranged in the arrangement direction, the plurality of first conductive patterns includes a first conductive pattern to which one semiconductor element is connected, and the plurality of second conductive patterns includes a second conductive pattern to which one semiconductor element is connected.

16. A semiconductor device according to any one of claims 1 to 12, wherein the semiconductor element includes a plurality of semiconductor elements arranged in the arrangement direction, the plurality of first conductive patterns include a first conductive pattern to which two semiconductor elements are connected, and the plurality of second conductive patterns include a second conductive pattern to which two semiconductor elements are connected.

17. A semiconductor device according to any one of claims 1 to 12, wherein the plurality of first conductive patterns include first conductive patterns that are connected to adjacent first conductive patterns but not connected to the semiconductor element, and the plurality of second conductive patterns include second conductive patterns that are connected to adjacent second conductive patterns but not connected to the semiconductor element.

18. The semiconductor device according to any one of claims 1 to 12, wherein the semiconductor element includes a wide bandgap semiconductor.

19. The semiconductor device according to claim 18, wherein the wide bandgap semiconductor includes any one of a silicon carbide semiconductor, a gallium nitride semiconductor, and a gallium oxide semiconductor.

20. A semiconductor device according to any one of claims 1 to 12, comprising: a first external control terminal electrically connected to the plurality of first conductive patterns; a second external control terminal electrically connected to the plurality of second conductive patterns; and an external main terminal electrically connected to a main conductive pattern through which a main current of the semiconductor element flows.