Voltage generating circuit

Abstract

A current source (10) includes a current generating circuit (MP02, MN02, R0) that is connected between a power supply node (Np) and a ground node (Ng) and generates a first current (I1) in a path from the power supply node (Np) to the ground node (Ng) in response to the supply of a power supply voltage (AVDD). The current source (10) supplies an output current (I2) proportional to the first current (I1) to an output node (No). A current-voltage conversion circuit (30) converts the output current (I2) into a reference voltage (VREF) generated in the output node (No). A startup current control circuit (20) is connected to the path of the first current (I1) and temporarily increases the conductance of the current generating circuit during an operation period that is provided when the power supply voltage (AVDD) rises.

Description

Voltage Generation Circuit

[0001] The present disclosure relates to a voltage generating circuit.

[0002] In recent years, with the advancement of IoT (Internet of Things) and AI (Artificial Intelligence) technologies, electronic devices that operate on power supplies have become more diverse. For example, electronic devices powered by energy harvesting or electronic devices that operate for long periods on small batteries include circuits that operate on the order of nanoamperes (nA). One such circuit is a reference voltage generation circuit that outputs a constant voltage.

[0003] Among reference voltage generation circuits, bandgap reference circuits are well known, which generate constant reference voltages and currents regardless of variations in power supply voltage, temperature, and process. Because bandgap reference circuits serve as reference voltage and current sources for electronic devices, it is desirable for them to be started up before the analog circuits to which they supply the reference voltage or reference current.

[0004] On the other hand, a bandgap reference circuit requires a certain static current during operation. However, if the static current is reduced to reduce power consumption, the time required to charge the load capacitance connected to the output of the bandgap reference circuit to the desired voltage, i.e., the startup time, increases.

[0005] Japanese Patent Laid-Open Publication No. 2010-160700 (Patent Document 1) describes a circuit configuration in which a power supply current supply circuit (current source) is connected between the power supply of a bandgap reference circuit and an output terminal to which a load capacitance is connected. According to the configuration of Patent Document 1, when the power supply is started, a current source formed of a diode-connected transistor supplies current from the power supply to the output terminal. This shortens the time required for the voltage at the output terminal to rise when the power supply is started, thereby improving the start-up characteristics.

[0006] JP 2010-160700 A

[0007] However, in the configuration of Patent Document 1, a current source is inserted between the power supply and the output terminal, which reduces the impedance between the power supply and the output of the bandgap reference circuit, which increases the fluctuation of the output voltage relative to the fluctuation of the power supply voltage, particularly at high frequencies, and this raises concerns about a deterioration in the power supply rejection ratio.

[0008] Furthermore, when the added current source is configured with a P-type MOS (Metal Oxide Semiconductor) transistor as in Patent Document 1, if the potential difference between the power supply voltage and the output voltage of the bandgap reference circuit becomes small, the PMOS transistor cannot operate in the saturation region and cannot supply a desired current, which may reduce the effect of improving start-up performance.

[0009] The present disclosure has been made to solve such problems, and an object of the present disclosure is to improve the start-up performance of a voltage generation circuit for generating a constant voltage without deteriorating the power supply rejection ratio.

[0010] In one aspect of the present disclosure, a voltage generation circuit is provided. The voltage generation circuit includes a current source, a current-to-voltage conversion circuit, and a startup current control circuit. The current source is connected between a power supply node supplying a power supply voltage and a ground node, and includes a first current generation circuit that generates a first current in a first path from the power supply node to the ground node in response to the supply of the power supply voltage, and is configured to supply an output current proportional to the first current to an output node. The current-to-voltage conversion circuit is connected between the output node and the ground node, and is configured to convert the output current into a reference voltage that is generated at the output node. The startup current control circuit is connected to the first path, and is configured to operate when the power supply voltage rises and temporarily increase the conductance of the first current generation circuit during the operation period.

[0011] According to the present disclosure, the output current supplied to the output node can be increased by temporarily increasing the first current generated by the current source when the power supply voltage rises, without placing an additional current supply element at the output node, thereby improving the start-up performance of the voltage generation circuit without deteriorating the power supply rejection ratio during steady state and without increasing current consumption.

[0012] FIG. 1 is a circuit diagram illustrating an example of the configuration of a voltage generation circuit according to a first embodiment. FIG. 2 is a circuit diagram illustrating an example of the configuration of a power-on reset circuit for generating a control signal for the startup current control circuit shown in FIG. 1. FIG. 3 is a conceptual waveform diagram for explaining the operation of the voltage generation circuit shown in FIG. 1 at startup. FIG. 4 is a circuit diagram illustrating an example of the configuration of a voltage generation circuit according to a modified example of the first embodiment. FIG. 5 is a circuit diagram illustrating an example of the configuration of a voltage generation circuit according to a modified example of the second embodiment. FIG. 6 is a circuit diagram illustrating an example of the configuration of a voltage generation circuit according to a third embodiment. FIG. 7 is a schematic block diagram illustrating an example of the overall system configuration of a BLE (Bluetooth Low Energy) module, which is one example of application of the voltage generation circuit according to the present embodiment.

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be denoted by the same reference numerals, and their description will not be repeated in principle.

[0014] First Embodiment (Circuit Configuration) Fig. 1 is a circuit diagram illustrating an example of the configuration of a voltage generating circuit 5A according to a first embodiment.

[0015] As shown in FIG. 1, the voltage generating circuit 5A includes a current source 10, a startup current control circuit 20, a current-voltage conversion circuit 30, and a load capacitance CL.

[0016] The current source 10 is configured to have temperature dependency (positive temperature coefficient) such that the generated current increases with increasing temperature. For example, the current source 10 is configured as a PTAT (Proportional To Absolute Temperature) current source, which generates a current that increases in proportion to an increase in absolute temperature. Therefore, hereinafter, the current source 10 is also referred to as a "PTAT current source 10."

[0017] The startup current control circuit 20 is provided to temporarily increase the current of the PTAT current source 10 only when the voltage generating circuit 5A is started up, which accompanies the rise of the power supply voltage AVDD. The current-voltage conversion circuit 30 is connected between an output node No, at which a reference voltage VREF is generated, and a GND node Ng, and converts the output current I2 supplied from the current source 10 to the output node No into the reference voltage VREF.

[0018] The PTAT current source 10 includes P-type transistors MP01 to MP03, N-type transistors MN01 and MN02, and a resistor element R0. Each of the P-type and N-type transistors can typically be configured using a MOS transistor. In the following description, the electrical resistance value of resistor element R0 will also be referred to as R0.

[0019] P-type transistors MP01 to MP03 are connected between a power supply node Np, to which a power supply voltage AVDD is supplied, and nodes N1 to N3, respectively, and each has its gate connected to node N2. Therefore, each of P-type transistors MP01 and MP03 forms a current mirror with P-type transistor MP02. Furthermore, P-type transistor MP02 has its gate and drain connected together, forming a diode-connected state. P-type transistor MP03 operates to supply output current I2, which is a proportional copy of currents I0 and I1 flowing through a path including P-type transistors MP01 and MP02, to output node No, where reference voltage VREF is generated.

[0020] In the following, as a representative example, the transistor sizes (ratio of gate width GW and gate length GL: GW / GL) of P-type transistors MP01, MP02, and MP03, i.e., the current ratio of the current mirror, will be described as 1:1:1, but this ratio is not limited to this example and can be changed.

[0021] N-type transistor MN01 is connected between node N1 and GND node Ng, which is supplied with ground voltage AGND. N-type transistor MN02 is connected between node N2 and node N3, and resistor element R0 is connected between node N3 and GND node Ng. The gates of N-type transistors MN01 and MN2 are connected to node N1. Therefore, N-type transistor MN01 has its gate and drain connected together, and is in a diode-connected state.

[0022] Furthermore, the N-type transistor MN02 is configured to have a transistor size that is L times (L≧1) that of the N-type transistor MN01. That is, as shown in the figure, the ratio of the transistor sizes (GW / GL) of the N-type transistors MN01 and MN02 is 1:L.

[0023] The startup current control circuit 20 is connected in parallel to the resistor element R0. That is, the startup current control circuit 20 has an N-type transistor MNsw and a resistor element R01 connected in series between the node N3 and the GND node Ng. In the voltage generating circuit 5A, the N-type transistor MNsw is connected between the node N3 and the resistor element R01, and the resistor element R01 is connected between the N-type transistor MNsw and the GND node Ng.

[0024] The N-type transistor MNsw operates as a switch that turns on and off in response to a control signal CNT. That is, when the N-type transistor MNsw is on, the startup current control circuit 20 operates, and a current I11 flows through the resistance element R01 from the node N3 to the GND node Ng. On the other hand, when the N-type transistor MNsw is off, the startup current control circuit 20 is stopped, and the current I11 is not generated.

[0025] The current-voltage conversion circuit 30 has a series-connected circuit of a resistance element R0 and a CTAT (Complementary to Absolute Temperature) conversion unit 31, which has a temperature dependency (negative temperature coefficient) of opposite polarity to that of the current source 10. Therefore, the electrical resistance value of the resistance element R0 decreases as the temperature rises. Hereinafter, the electrical resistance value of the resistance element R1 will also be referred to as R1.

[0026] The CTAT conversion unit 31 can be configured with an element having a CTAT characteristic in which the output voltage decreases with an increase in absolute temperature, in contrast to the PTAT current source 10. In the example of Fig. 1, the CTAT conversion unit 31 is configured with a diode-connected PNP bipolar transistor Q0. This allows the current-voltage conversion circuit 30 to be configured to have a negative temperature coefficient, in which the ratio of the reference voltage VREF to the output current I2 decreases with an increase in temperature.

[0027] The CTAT conversion unit 31 is not limited to the diode-connected PNP bipolar transistor Q0 shown in FIG. 1, but can be configured by diode-connecting an NPN bipolar transistor, an N-type MOS transistor, or a P-type MOS transistor, or by using a diode element.

[0028] (Circuit operation)

[0029] Next, the operation of the voltage generating circuit 5A will be described. First, the operation of generating the reference voltage VREF by the current source 10 and the current-voltage conversion circuit 30 when the control signal CNT is at L level and the N-type transistor MNsw is off, causing the startup current control circuit 20 to be in a stopped state, will be described in detail.

[0030] In the current source 10, by operating the N-type transistor MN01 in the subthreshold region by appropriately setting the electrical resistance value of the resistor element R0, the current I0 flowing between the drain and source of the N-type transistor MN01 is determined by the gate-source voltage VGS0, drain-source voltage VDS0, and threshold voltage V Ｔ Using the above, it can be expressed as equation (1).

[0031] In equation (1), Io is a process-dependent pre-factor, T is the absolute temperature, k is the Boltzmann constant, q is the elementary charge, and n is a constant representing a slope factor calculated from the ratio of the depletion layer capacitance and the gate oxide film capacitance.

[0032] In equation (1), when VDS0 > 3 (kT / q), the second term, exp(-(q VDS0) / kT), can approximate to zero, so the current I0 in equation (1) can approximate to equation (2) (3 (kT / q) = 0.078 [V]).

[0033] When equation (2) is transformed to solve for VGS0, the following equation (3) is obtained.

[0034] When the P-type transistors MP01 and MP02 constituting the current mirror operate so that the current I0=I1, and the N-type transistor MN01 operates in the subthreshold region, the N-type transistor MN02, whose gate-source voltage is smaller than that of the N-type transistor MN01 by the voltage drop across the resistor R0, also operates in the subthreshold region. The gate-source voltage VGS1 of the N-type transistor MN02 is determined so that I0=I1 is maintained even if the source potential of the N-type transistor MN01 increases due to the current I1. Therefore, the gate-source voltage VGS1 of the N-type transistor MN02 can be expressed by the following equation (4) using the ratio L of the N-type transistor sizes of the N-type transistors MN01 and MN02 described above.

[0035] Furthermore, according to Kirchhoff's voltage law, it can be seen that the voltage difference between the GND node Ng and the node N1 is VGS0=VGS1+I10·R0, where I10 is the current flowing through the resistance element R0. From this, it is possible to derive I10=(VGS0-VGS1) / R0. When the startup current control circuit 20 is in a stopped state and I0=I10, the current I0 is expressed by the following equation (5) using equations (1) to (4).

[0036] In equation (5), (n k ln(L)) / (q R0) is the element constant of N-type transistor MN0 and resistor element R0. Therefore, it can be understood that current I0 (= I1 = I2) generated by current source 10 operating N-type transistors MN01 and MN02 in the subthreshold region (weak inversion region) is proportional to absolute temperature T. In this way, current source 10 can operate as a PTAT current source of a self-bias circuit. It can also be understood that the value of current I0 (I1, I2) can be adjusted by the electrical resistance value of resistor element R1 and the transistor size ratio L (between N-type transistors MN01 and MN02).

[0037] In a steady state where the load capacitance CL is charged, the output current I2 is equal to the current I20 flowing through the current-voltage conversion circuit 30 (I2=I20). Therefore, the reference voltage VREF generated at the output node No by the voltage generation circuit 5A can be expressed by the following equation (6) using the base-emitter voltage VBE of the diode-connected bipolar transistor Q0 (PNP bipolar transistor): VREF=R1·I2+VBE (6)

[0038] On the other hand, the current I0 generated by the PTAT current source 10 is copied by a current mirror with a current ratio of 1:1 and supplied to the output node No where the reference voltage VREF is generated as an output current I2 from the P-type transistor MP03, so that I10 = I1 = I2 = I20 holds. As a result, by substituting equation (5) into the above equation (6), the reference voltage VREF can be expressed by the following equation (7).

[0039] The temperature dependency of the reference voltage VREF is expressed by the following equation (8) obtained by differentiating equation (7) with respect to absolute temperature T.

[0040] In equation (8), the second term on the right side is a negative constant determined by the constant of bipolar transistor Q0, while the value of the first term on the right side is a positive value that can be adjusted by the transistor size (GW / GL) of N-type transistor MN01 and the transistor size ratio L between N-type transistors MN01 and MN02.

[0041] Therefore, by determining the transistor size of N-type transistor MN01 and the transistor size ratio L between N-type transistors MN01 and MN02 so that the sum of the first and second terms on the right-hand side is zero, the reference voltage VREF can be made a constant value with respect to changes in absolute temperature T, with its temperature dependency eliminated.

[0042] When the voltage generating circuit 5A is started, the reference voltage VREF is generated according to equation (6) after the charging of the load capacitance CL of the output node No is completed. Therefore, the start-up time of the voltage generating circuit 5A depends on the time required to charge the load capacitance CL. The slew rate SR of the voltage rise when the load capacitance CL is charged can be expressed by the following equation (9) using the output current I2 (P-type transistor MP03) and current I20 (current-voltage conversion circuit 30) in FIG. 1: SR=(I2-I20) / CL (9)

[0043] Here, current I20 flows through diode-connected bipolar transistor Q0, and is therefore determined by the characteristic value of bipolar transistor Q0. Therefore, it can be seen that by increasing output current I2, i.e., current I1 generated by PTAT current source 10, the slew rate SR can be increased and the startup time can be shortened.

[0044] Next, the operation of the voltage generating circuit 5A when the control signal CNT is at H level and the N-type transistor MNsw is turned on, so that the startup current control circuit 20 is in an active state will be described.

[0045] When the N-type transistor MNsw is turned on, the resistance elements R0 and R01 are connected in parallel between the node N3 and the GND node Ng. As a result, it can be understood that the current I1 (P-type transistor MP02) in FIG. 1 changes from equation (5) to equation (10) below.

[0046] In equation (10), compared to equation (5), the resistance value that determines the current value changes from R0 (equation (5)) to (R0·R01) / (R0+R01), which is the combined resistance value of the parallel connection. For example, when R0=R01, (R0·R01) / (R0+R01)=R0 / 2, so it can be understood that the current I1 in equation (10) is twice that in equation (5). That is, it can be understood that the current value in equation (10) is larger than the current value in equation (5) due to the effect of increasing the conductance of the portion of the path (corresponding to the "first path") of current I1 (the "first current") that flows from power supply node Np to GND node Ng via node N1, which is caused by connecting resistive element R01 in parallel with resistive element R0.

[0047] As a result, when the startup current control circuit 20 is activated, the output current I2 supplied from the current source 10 to the node N3 also doubles, and the slew rate SR in equation (9) increases, thereby shortening the startup time of the voltage generating circuit 5A.

[0048] It is also possible to increase the output current I2 by increasing the transistor size of the P-type transistor MP03 and increasing the current ratio of the current mirror without changing the current I0. However, if the slew rate is increased by increasing the output current I2 in this way, the impedance of the P-type transistor MP03 will decrease during startup when the load capacitance CL is being charged and throughout steady-state operation after charging is complete, thereby reducing the impedance between the output node No and the power supply node Np.

[0049] Generally, the power supply rejection ratio (PSRR), which is an index showing the effect of fluctuations in the power supply voltage AVDD at the power supply node Np on fluctuations in the reference voltage VREF generated at the output node No, is proportional to (Zo+Zcs) / Zo, where Zo is the output impedance of the voltage generating circuit 5A and Zcs is the impedance of the P-type transistor MP03. Therefore, a decrease in the impedance of the P-type transistor MP03, i.e., the impedance between the power supply node Np and the output node No, reduces the PSRR, increasing the effect of fluctuations in the power supply voltage AVDD on fluctuations in the reference voltage VREF. While this shortens the startup time of the voltage generating circuit 5A, it raises concerns about a decrease in the stability of the reference voltage VREF during steady-state operation.

[0050] In contrast to this, in the present embodiment, the startup current control circuit 20 is used to temporarily increase the current I1 of the PTAT current source 10 only when the voltage generating circuit 5A is started up, thereby increasing the output current I2 from the P-type transistor MP03, thereby shortening the startup time of the voltage generating circuit 5A without impairing the stability of the reference voltage VREF during steady-state operation.

[0051] FIG. 2 is a circuit diagram illustrating an example of the configuration of a power-on reset (POR) circuit 100 for generating the control signal CNT of the startup current control circuit 20. As shown in FIG.

[0052] As shown in FIG. 2, the POR circuit 100 includes a rising edge detection circuit 110 for detecting the rising edge of the power supply voltage AVDD, a voltage divider circuit 115, a comparator 120, and an inverter 130.

[0053] The rise detection circuit 110 has N-type transistors MND0 and MN30. The N-type transistor MN30 is diode-connected by connecting its gate and drain, and is electrically connected between a node Nx, at which a detection voltage V1 reflecting the rise behavior of the power supply voltage AVDD is generated, and a GND node Ng. That is, the source of the N-type transistor MN30 is connected to the GND node Ng, and the drain and gate are connected to the node Nx.

[0054] The N-type transistor MND0 is connected between the power supply node Np and the node Nx. The source and gate of the N-type transistor MND0 are connected to the drain of the N-type transistor MN30, and the drain is connected to the power supply node Np.

[0055] The characteristics of both N-type transistors are designed so that the threshold voltage of N-type transistor MND0 is lower than that of N-type transistor MN30. For example, N-type transistor MN30 can be configured as an enhancement-type NMOS transistor, while N-type transistor MND0 can be configured as a depletion-type NMOS transistor. As another example, N-type transistor MND0 can be configured as a native NMOS transistor.

[0056] The voltage-dividing circuit 115 has resistor elements Rp0 and Rp1 connected in series between the power supply node Np and the GND node Ng via a node Ny. Therefore, a divided voltage V2 of the power supply voltage AVDD by the resistor elements Rp0 and Rp1 is generated at the node Ny. If the electrical resistance values ​​of the resistor elements Rp0 and Rp1 are also written as Rp0 and Rp1, then Vy=AVDD·(Rp1 / (Rp0+Rp1)).

[0057] The comparator 120 outputs a signal CNTB having a logic level indicating the result of comparison between the detected voltage V1 from the rise detection circuit 110 and the divided voltage V2 from the voltage divider circuit 115. Specifically, when V2≧V1, the signal CNTB is set to the H level (power supply voltage AVDD), whereas when V1>V2, the signal CNTB is set to the L level (AGND).

[0058] The inverter 130 inverts the logic level of the signal CNTB from the comparator 120 and outputs the control signal CNT. The control signal CNT is input to the gate of the N-type transistor MNsw in the startup current control circuit 20, as shown in FIG. 1. The control signal CNT is set to an H level (power supply voltage AVDD) when V1>V2, and is set to an L level (AGND) when V2≧V1.

[0059] 2, node Nx where detection voltage V1 is generated corresponds to the “fourth node,” diode-connected N-type transistor MN30 corresponds to an example of the “eighth transistor,” and N-type transistor MND0 with a low threshold voltage corresponds to an example of the “ninth transistor.” POR circuit 100 can be shared with other circuits (not shown) as an external element of voltage generating circuit 5A.

[0060] FIG. 3 shows a schematic waveform diagram for explaining the operations of the POR circuit 100 shown in FIG. 2 and the voltage generating circuit 5A shown in FIG.

[0061] 3, when voltage generating circuit 5A is started, power supply voltage AVDD rises from 0 V (corresponding to AGND), reaches the minimum operating voltage VDDmin of N-type transistors at time t1, and then continues to rise until it reaches a steady value (corresponding to the standard value) at time t3. The minimum operating voltage VDDmin corresponds to the minimum value of the voltage region in which N-type transistors MN30 and MND0, and the transistor group (not shown) included in comparator 120 and inverter 130 in POR circuit 100 of FIG. 2 can operate in the saturated region.

[0062] The divided voltage V2 in the POR circuit 100 in FIG. 2 is represented by the product of the voltage division ratio and the power supply voltage AVDD at that time, and therefore rises in proportion to the power supply voltage AVDD at startup.

[0063] In contrast, the detection voltage V1 output by the rise detection circuit 110 is such that, immediately after the rise of the power supply voltage AVDD, the electrical resistance of the N-type transistor MND0 is lower than the electrical resistance of the N-type transistor MN30 because the threshold voltage of the N-type transistor MND0 is lower than the threshold voltage of the N-type transistor MN30. Thereafter, as the power supply voltage AVDD rises, the electrical resistances of the N-type transistors MND0 and MN30 become equal. As a result, immediately after the rise of the power supply voltage AVDD, the rate of rise of the detection voltage V1 is higher than the rate of rise of the divided voltage V2, which rises in proportion to the power supply voltage AVDD. Meanwhile, as the power supply voltage AVDD rises, the rise of the detection voltage V1 becomes more gradual, and the rate of rise of the detection voltage V1 becomes slower than the rate of rise of the divided voltage V2.

[0064] Therefore, by designing the voltage division ratio of the voltage divider circuit 115 so that the steady-state value after the power supply voltage AVDD rises is V2>V1, the operation of the POR circuit 100 is realized as shown in FIG. 3, in which V1>V2 immediately after power-on, but V2>V1 after the power supply voltage AVDD rises.

[0065] In the example of FIG. 3, after the comparator 120 and the inverter 130 become operable at time t1, the relationship between the detected voltage V1 and the divided voltage V2 changes from V1>V2 to V2>V1 at time t2.

[0066] In response to this, the control signal CNT is set to H level, which is a voltage level equivalent to the power supply voltage AVDD, during the period V1>V2 (i.e., until time t2), and is set to AVDD (L level) after time t2. Conversely, the signal CNTB is set to AVDD (L level) until time t2, but is set to H level, which is a voltage level equivalent to the power supply voltage AVDD after time t2.

[0067] 1, during the period before time t1 when control signal CNT is higher than the threshold voltage of N-type transistor MNsw, and during the period from time t1 to t2, N-type transistor MNsw is turned on, causing current I1 generated by PTAT current source 10 to temporarily increase from the value of equation (5) to the value of equation (10). Then, after time t2, N-type transistor MNsw is turned off, and current I1 returns to the value of equation (5).

[0068] 3, the waveform of the reference voltage VREF when the power supply voltage AVDD rises and the voltage generating circuit 5A starts up is shown by a dotted line. On the other hand, for comparison, the waveform when the N-type transistor MNsw is kept off, i.e., when the startup current control circuit 20 is not provided, is shown by a dotted line.

[0069] When the voltage generating circuit 5A is started up, the startup current control circuit 20 is activated by the N-type transistor MNsw, and the current I1 generated by the PTAT current source 10 increases during the period up to time t2. The output current I2 of the P-type transistor MP03 also increases accordingly, and the rate of rise of the reference voltage VREF increases compared to a configuration (dotted line) in which the startup current control circuit 20 is not provided. It can be seen that this shortens the time until the reference voltage VREF is generated, improving startup performance.

[0070] Furthermore, after time t2, the N-type transistor MNsw is turned off, and the current I1 is maintained at the value of equation (5), thereby suppressing the current consumption of the voltage generating circuit 5A during steady state (for example, on the order of nanoamperes). Furthermore, since the improvement in startup performance does not involve a decrease in impedance during steady state (between the power supply node Np and the output node No), a decrease in the PSRR of the voltage generating circuit 5A can be avoided. In other words, startup performance can be improved without impairing the stability of the reference voltage VREF during steady state.

[0071] 3, the timing (time t2) at which the detected voltage V1 and the divided voltage V2 switch between high and low can be freely adjusted within the range of times t1 to t3 by adjusting the voltage division ratio of voltage divider circuit 115 (the resistance values ​​of resistor elements Rp0 and Rp1). As shown in FIG. 3, delaying the timing of time t2 significantly improves startup performance, but also causes a slight overshoot in reference voltage VREF. Therefore, the timing of time t2, i.e., the current increase period by startup current control circuit 20, can be appropriately set depending on the characteristics of the circuit to which reference voltage VREF is supplied, specifically, the tolerance for overshoot and the required startup characteristics.

[0072] The timing at which the detection voltage V1 and the divided voltage V2 switch between high and low is equivalent to the timing at which the power supply voltage AVDD at startup exceeds a predetermined determination voltage Vt. In other words, by adjusting the voltage division ratio of the voltage divider circuit 115, it is possible to arbitrarily adjust the determination voltage Vt within a voltage range lower than the steady-state value of the power supply voltage AVDD.

[0073] Thus, according to the voltage generating circuit of the first embodiment, at startup when the power supply voltage AVDD rises, the startup current control circuit 20 temporarily increases the current I1 generated by the current source (PTAT current source) 10, thereby temporarily increasing the output current I2 to the output node No at which the reference voltage VREF is generated.

[0074] As a result, the reference voltage VREF is quickly increased by the temporarily increased output current I2 without causing a decrease in impedance between the power supply node Np and the output node No, thereby improving the start-up performance of the voltage generating circuit without deteriorating the PSRR. Furthermore, unlike Patent Document 1, the current I1 of the PTAT current source 10 can be increased even when the difference between the power supply voltage AVDD and the reference voltage VREF is small, so the effect of improving the start-up performance is not reduced.

[0075] In current source 10, as described above, the current path from power supply node Np to the ground node (GND node Ng) via node N2 corresponds to an example of the "first path," while the current path from power supply node Np to the ground node via node N1 corresponds to an example of the "second path." That is, current I1 corresponds to the "first current," and current I0 corresponds to the "second current." Furthermore, node N2 corresponds to the "first node," node N3 corresponds to the "second node," and node N1 corresponds to the "third."

[0076] Furthermore, in the current source 10, the P-type transistor MP02, the N-type transistor MN02, and the resistor element R0, which are the generating parts of the current I1, constitute an embodiment of a "first current generating circuit." The P-type transistor MP02 corresponds to the "first transistor," the N-type transistor MN02 corresponds to the "second transistor," and the resistor element R01 corresponds to the "second resistor element." Similarly, the P-type transistor MP01 and the N-type transistor MN01, which are the generating parts of the current I0, constitute an embodiment of a "second current generating circuit," with the P-type transistor MP01 corresponding to the "third transistor" and the N-type transistor MN01 corresponding to the "fourth transistor." The P-type transistor MP03, which generates the output current I2, corresponds to the "fifth transistor." Furthermore, in the startup current control circuit 20, the N-type transistor MNsw corresponds to the "switch element" or the "sixth transistor," and the resistor element R01 corresponds to the "second resistor element."

[0077] Modification of First Embodiment FIG. 4 is a circuit diagram illustrating an example of the configuration of a voltage generating circuit 5B according to a modification of the first embodiment.

[0078] 4, voltage generating circuit 5B differs from voltage generating circuit 5A (FIG. 1) according to the first embodiment in that it includes a startup current control circuit 21 instead of startup current control circuit 20. In the modification of the first embodiment, the same points as those in the first embodiment will not be described repeatedly.

[0079] Compared to the startup current control circuit 20, the startup current control circuit 21 is connected in parallel to the resistance element R0 like the startup current control circuit 20, but the connection order of the resistance element R01 and the N-type transistor MNsw is different. Specifically, in the startup current control circuit 21, the resistance element R01 is connected between the node N3 and the N-type transistor MNsw, and the N-type transistor MNsw is connected between the resistance element R01 and the GND node Ng. A control signal CNT is input to the gate of the N-type transistor MNsw, as in FIG. 1.

[0080] In the startup current control circuit 21 as well, the N-type transistor MNsw corresponds to the "switch element" or the "sixth transistor", and the resistance element R01 corresponds to the "second resistance element".

[0081] The configuration of other parts of voltage generating circuit 5B is similar to that of voltage generating circuit 5A, and therefore detailed description thereof will not be repeated. Therefore, the circuit operation involving the on / off of N-type transistor MNsw in response to control signal CNT is also similar between voltage generating circuits 5A and 5B.

[0082] 1, when the back gate of the N-type transistor MNsw is connected to the GND node Ng (AGND), a potential difference occurs between the source and the back gate. Therefore, there is a concern that the threshold voltage of the N-type transistor MNsw may increase due to the substrate bias effect. When the threshold voltage increases due to the substrate bias effect, the on-resistance of the N-type transistor MNsw increases during the period when the control signal CNT is at the H level, thereby reducing the current I1 during that period.

[0083] As a result, in the voltage generating circuit 5A including the startup current control circuit 20, there is a concern that the effect of shortening the startup time, i.e., the effect of improving startup performance, will be suppressed due to the decrease in output current I2 as the current I1 decreases. Furthermore, in the startup current control circuit 20, there is a concern that the layout area will increase because the well needs to be separated in order to connect the back gate of the N-type transistor MNsw to the GND node Ng.

[0084] 4, the back gate and source of N-type transistor MNsw can be set to the same potential. Therefore, the voltage generating circuit according to the modification of the first embodiment is expected to avoid the above-mentioned increase in layout area and to enhance the effect of improving startability, compared to the configuration of FIG.

[0085] Second Embodiment Fig. 5 is a circuit diagram illustrating an example of the configuration of a voltage generating circuit 5C according to a second embodiment.

[0086] 5, voltage generating circuit 5C differs from voltage generating circuit 5A (FIG. 1) according to the first embodiment in that it includes startup current control circuit 22 instead of startup current control circuit 20. In the second embodiment, the same points as those in the first embodiment will not be described repeatedly.

[0087] The startup current control circuit 22 is connected in parallel to the N-type transistor MN02. That is, the startup current control circuit 22 has N-type transistors MNsw and MN22 connected in series between nodes N2 and N3. In the voltage generating circuit 5C, the N-type transistor MNsw is connected between the node N2 and the N-type transistor MN22, and the N-type transistor MN22 is connected between the N-type transistor MNsw and the node N3.

[0088] That is, the source of N-type transistor MN22 is connected to node N3, the drain of N-type transistor MN22 is connected to node N2 via N-type transistor MNsw, and the gate of N-type transistor MN22 is connected to the gates of N-type transistors MN01 and MN02.

[0089] Furthermore, the transistor size (GW / GL) of the N-type transistor MN22 is designed to be M times (M≧1) the transistor size of the N-type transistor MN01. That is, the transistor size ratio among the N-type transistors MN01, MN02, and MN22 is MN01:MN02:MN22=1:L:M.

[0090] In the startup current control circuit 22, the N-type transistor MNsw corresponds to the "switch element," and the N-type transistor MN22 corresponds to the "seventh transistor."

[0091] The configuration of other parts of voltage generating circuit 5C is the same as that of voltage generating circuit 5A, and therefore detailed description thereof will not be repeated. That is, N-type transistor MNsw is on / off controlled in response to control signal CNT, as in the first embodiment.

[0092] Therefore, in voltage generating circuit 5C, during the ON period of N-type transistor MNsw, a parallel-connected circuit of N-type transistors MN02 and MN03 is connected in series with resistive element R0 between node N2 and GND node Ng. Therefore, current I1 generated by PTAT current source 10 is the sum of current I12 flowing through N-type transistor MN02 and current I13 flowing through N-type transistor MN02 (I1 = I12 + I13). Considering the transistor size ratio (1:L:M) described above, it can be understood that current I1 during the ON period of N-type transistor MNsw in voltage generating circuit 5C is expressed by the following equation (11), not equation (10).

[0093] From a comparison of equations (5) and (11), it can be seen that in the second embodiment, the parallel connection of N-type transistor MN22 to N-type transistor MN02 increases the conductance of the portion of the path (corresponding to the "first path") through which current I1 (the "first current") flows from power supply node Np to GND node Ng via node N1, thereby increasing the current I1 during the on-period of N-type transistor MNsw compared to the off-period of N-type transistor MNsw. Specifically, current I0 during the on-period of N-type transistor MNsw increases by ln(L+M) / ln(L) times the current I0 during the off-period of N-type transistor MNsw.

[0094] Therefore, in the voltage generating circuit according to the second embodiment, as in the voltage generating circuit according to the first embodiment, the output current I2 of the P-type transistor MP03 can be increased by increasing the current I1 of the PTAT current source 10 only when the voltage generating circuit is started up, thereby achieving the same effect as in the first embodiment in terms of improved start-up performance. That is, the start-up performance of the voltage generating circuit can be improved without lowering the PSRR, even when the difference between the power supply voltage AVDD and the reference voltage VREF is small.

[0095] Modification of Second Embodiment FIG. 6 is a circuit diagram illustrating an example of the configuration of a voltage generating circuit 5D according to a modification of the second embodiment.

[0096] As shown in FIG. 6, the voltage generating circuit 5D differs from the voltage generating circuit 5C (FIG. 5) according to the second embodiment in that it includes a startup current control circuit 23 instead of the startup current control circuit 22.

[0097] Compared to the startup current control circuit 22, the startup current control circuit 23 is connected in parallel to the N-type transistor MN02 like the startup current control circuit 22, but the connection order of the N-type transistors MNsw and MN22 is different. Specifically, in the startup current control circuit 23, the N-type transistor MN22 is connected between the node N2 and the N-type transistor MNsw, and the N-type transistor MNsw is connected between the N-type transistor MN22 and the node N3. A control signal CNT is input to the gate of the N-type transistor MNsw, as in FIG. 5 .

[0098] In the startup current control circuit 23 as well, the N-type transistor MNsw corresponds to the "switch element," and the N-type transistor MN22 corresponds to the "seventh transistor."

[0099] The configuration of other parts of voltage generating circuit 5D is similar to that of voltage generating circuit 5C, and therefore detailed description thereof will not be repeated. Therefore, the current I1 during the on period and the off period of N-type transistor MNsw in response to control signal CNT is also similar between voltage generating circuits 5C and 5D.

[0100] Therefore, the voltage generating circuit according to the modification of the second embodiment can also achieve the same effect as the voltage generating circuit according to the second embodiment in terms of startability.

[0101] Third Embodiment Fig. 7 is a circuit diagram illustrating a configuration example of a voltage generating circuit 5E according to a third embodiment. As shown in Fig. 7, voltage generating circuit 5C differs from voltage generating circuit 5A (Fig. 1) according to the first embodiment in that it includes current source 11 instead of current source 10 and in that it includes a startup current control circuit 25 instead of startup current control circuit 20. In the third embodiment, the same points as those in the first embodiment will not be described again.

[0102] Current source 11 differs from current source 10 in the connection position of resistor element R0. Specifically, resistor element R0 is connected between node N1 and node N4 connected to the drain of N-type transistor MN01. The gate of N-type transistor MN01 is connected to node N1 as in FIG. 1, while the gate of N-type transistor MN02 is connected to node N4.

[0103] The startup current control circuit 25 is connected in parallel to the resistor element R0. That is, the startup current control circuit 25 has an N-type transistor MNsw and a resistor element R01 connected in series between nodes N1 and N4. The gate of the N-type transistor MNsw receives a control signal CNT similar to that in the first embodiment.

[0104] 7, the current I0 flowing through the node N1 and the N-type transistor MN01 is represented by the sum of the current I00 flowing through the startup current control circuit 25 and the current I01 flowing through the resistance element R0. During the period when the control signal CNT is at the L level and the N-type transistor MNsw is turned off, I00=0, and therefore I1=I01.

[0105] It is understood that in the current source 11 as well, VGS0=VGS1+I01·R0 holds between the gate-source Vgs0 of the N-type transistor MN01 and the gate-source Vgs1 of the N-type transistor MN02, similarly to the current source 10 (i.e., I01=(VGS0−VGS1) / R0). Therefore, similarly to the current source 10, the current source 11 can operate as a PTAT current source in accordance with the equations (1) to (5).

[0106] As a result, during the period when the control signal CNT is at L level and the N-type transistor MNsw is turned off (the period when the startup current control circuit 25 is stopped), the current I0 flows only through the resistance element R0, and the current I1 (I1 = I0) is expressed by the above equation (5).

[0107] Furthermore, during the period when the control signal CNT is at H level and the N-type transistor MNsw is turned on (the operation period of the startup current control circuit 25), a current I0 flows through the parallel circuit of the resistance elements R0 and R01, similar to the voltage generating circuit 5A (FIG. 1). Therefore, the current I1 (I1=I0) is expressed by the above-mentioned equation (10).

[0108] P-type transistor MP03 and current-voltage conversion circuit 30 (resistance element R1 and CTAT switching unit 31) are configured in the same manner as in Fig. 1 (voltage generation circuit 5A). Therefore, the relationship between current I1 generated by current source 11 and output current I2 to node N3 is the same as the relationship between current I1 generated by current source 10 in embodiment 1 (voltage generation circuit 5A) and output current I2.

[0109] As a result, the voltage generating circuit according to the third embodiment can also improve the start-up performance based on the same principle as the voltage generating circuit according to the first embodiment. That is, the rate of rise of the reference voltage VREF at start-up can be increased without deteriorating the PSRR in the steady state, even when the difference between the power supply voltage AVDD and the reference voltage VREF is small.

[0110] In the example of Figure 7, the startup current control circuit 25 is configured so that the resistance element R01 is connected between the node N1 and the N-type transistor MNsw, and the N-type transistor MNsw is connected between the resistance element R01, the node N4, and the resistance element R01. However, even if the connection order of the N-type transistor MNsw and the resistance element R01 is reversed from the example of Figure 7, the voltage generation circuit 5E can achieve the same effect.

[0111] In current source 11, the current path from power supply node Np to the ground node (GND node Ng) via node N1, to which startup current control circuit 25 is connected, corresponds to an example of a "first path," while the current path from power supply node Np to the ground node via node N2 corresponds to an example of a "second path." That is, current I0 corresponds to the "first current," and current I1 corresponds to the "second current." Furthermore, node N1 corresponds to the "first node," node N4 corresponds to the "second node," and node N2 corresponds to the "third node."

[0112] Furthermore, in the current source 11, the P-type transistor MP01, the N-type transistor MN01, and the resistor element R0, which are the parts that generate the current I0, constitute an embodiment of a "first current generating circuit." The P-type transistor MP01 corresponds to the "first transistor," the N-type transistor MN01 corresponds to the "second transistor," and the resistor element R01 corresponds to the "second resistor element." Similarly, the P-type transistor MP02 and the N-type transistor MN02, which are the parts that generate the current I1, constitute an embodiment of a "second current generating circuit," with the P-type transistor MP02 corresponding to the "third transistor" and the N-type transistor MN02 corresponding to the "fourth transistor." Also in the current source 11, the P-type transistor MP03 that generates the output current I2 corresponds to the "fifth transistor." Furthermore, in the startup current control circuit 25, the N-type transistor MNsw corresponds to the "switch element," and the resistor element R01 corresponds to the "second resistor element."

[0113] In the above-described embodiments of the present disclosure, the field-effect transistors shown as components of the voltage generating circuits 5A to 5E can be replaced with bipolar transistors. That is, the P-type transistors corresponding to the "first conductivity type" can also be configured with PNP-type bipolar transistors, and the N-type transistors corresponding to the "second conductivity type" can also be configured with NPN-type bipolar transistors. In this case, the drain, source, and gate (corresponding to the "control electrode") in the description of each configuration example can be appropriately replaced with the collector, emitter, and base.

[0114] Furthermore, the resistor elements R0, R1, and R01 shown as components of the voltage generating circuits 5A to 5E are not limited to resistor elements and can be replaced with other elements such as active loads using transistors, as long as they are loads with negative temperature coefficients. For example, in FIG. 1, it is possible to configure a "load" that functions similarly to the resistor element R1 in FIG. 1 by connecting the source, body, and drain of an NMOS transistor to ground and connecting the gate to the gate of an N-type transistor, and utilizing the gate leakage current of the NMOS transistor.

[0115] Although the present embodiment shows an example in which the output of the POR circuit 100 for detecting power supply startup is used as the control signal CNT, the configuration of the POR circuit is not limited to the example shown in Fig. 2, and any configuration can be applied as long as it can define similar timing in accordance with the rise in the power supply voltage AVDD at startup. Furthermore, the control signal CNT is not limited to the output signal from the POR circuit, and can be generated by any analog circuit, digital circuit, or microcomputer from inside or outside the voltage generating circuit 5A and provided to the startup current control circuit 20.

[0116] FIG. 8 is a schematic block diagram illustrating an example of the overall system configuration of a BLE module, which is one application example of the voltage generating circuit according to this embodiment.

[0117] As shown in FIG. 8 , a voltage generation circuit 5 (collectively referring to 5A to 5E) according to this embodiment is mounted on a BLE module 2 and supplies a reference voltage VREF corresponding to a constant bias voltage to a circuit group 6 within the BLE module 2. The circuit group 6 uses the reference voltage VREF for the operation of each circuit as a constant voltage that is not affected by the power supply voltage, temperature, manufacturing process, etc. The BLE module 2 may also be mounted with a POR circuit 100 illustrated in FIG. 2 as an external element of the voltage generation circuit 5. The circuit group 6 includes, for example, a power supply regulator such as an LDO (Low Drop Out), a D / A (Digital to Analog) converter, or an A / D (Analog to Digital) converter.

[0118] The voltage generating circuit according to this embodiment is not limited to being mounted on a BLE module, but can be applied to any electronic device for generating a reference voltage.

[0119] Furthermore, the present disclosure is not limited to the above-described embodiments, and can be freely modified and changed within the scope of the claims.

[0120] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0121] 2 BLE module, 5, 5A to 5E voltage generation circuit, 6 circuit group, 10, 11 current source, 20 to 23, 25 startup current control circuit, 30 current-voltage conversion circuit, 31 CTAT conversion unit, 100 POR circuit, 110 rise detection circuit, 115 voltage divider circuit, 120 comparator, 130 inverter, AGND ground voltage, AVDD power supply voltage, CL load capacitance, CNT control signal, MN0 to MN02, MN22, MN30, MND0, MNsw N-type transistor, MP01 to MP03 P-type transistor, N1 to N4, Nx, Ny node, Ng GND node, No output node, Np power supply node, Q0 bipolar transistor, R0, R01, R1, Rp0, Rp1 resistive element, SR slew rate, T Absolute temperature, V1 detection voltage, V2 divided voltage, VREF reference voltage, Vt judgment voltage.

Claims

1. A current source is connected between a power supply node that supplies a power supply voltage and a ground node, and includes a first current generation circuit that generates a first current in a first path from the power supply node to the ground node in response to the supply of the power supply voltage, and is configured to supply an output current proportional to the first current to an output node. A current-voltage conversion circuit connected between the output node and the ground node, configured to convert the output current into a reference voltage generated at the output node, A voltage generation circuit comprising a startup current control circuit connected to the first path and configured to operate when the power supply voltage rises, and to temporarily increase the conductance of the first current generation circuit during the operating period.

2. The current source is configured to have a positive temperature dependence such that the first current increases in response to the rise in temperature. The voltage generation circuit according to claim 1, wherein the current-voltage conversion circuit is configured to have a negative temperature dependence in which the ratio of the reference voltage to the first current decreases in response to the rise in temperature.

3. The current source is configured such that the first current changes in proportion to the absolute temperature with a positive proportionality constant. The voltage generation circuit according to claim 2, wherein the current-voltage conversion circuit includes a conversion unit in which the voltage obtained by converting the first current changes in proportion to the absolute temperature with a negative proportionality constant.

4. The current source is A second path formed in parallel with the first path between the power node and the ground node further includes a second current generating circuit that generates a current proportional to the first current. The first current generation circuit is, A first transistor of a first conductivity type is connected between the power supply node and the first node, A second transistor of second conductivity type connected between the first node and the second node, The system includes a first resistive element connected between the second node and the ground node, The second current generation circuit is, Connected between the power supply node and the third node, the third transistor of the first conductivity type that constitutes a current mirror with the first transistor, The system includes a fourth transistor of the second conductivity type connected between the third node and the ground node, The control electrodes of the second and fourth transistors are commonly connected to the third node. The current source is The system further includes a fifth transistor of first conductivity type connected between the power supply node and the output node, which constitutes a current mirror with the first transistor and the third transistor. The voltage generation circuit according to any one of claims 1 to 3, wherein the startup current control circuit is connected in parallel with the second transistor or the first resistor.

5. The startup current control circuit includes a switch element and a second resistor element connected in series between the second node and the ground node. The voltage generating circuit according to claim 4, wherein the switch element is turned on during the operation period of the startup current control circuit and turned off during the shutdown period of the startup current control circuit.

6. The switching element is composed of the sixth transistor of the second conductivity type, The second resistive element is connected between the second node and the sixth transistor, The voltage generating circuit according to claim 5, wherein the sixth transistor is connected between the second resistive element and the ground node.

7. The startup current control circuit includes a switch element and a seventh transistor of the second conductivity type, which are connected in series between the first node and the second node. The control electrode of the seventh transistor is connected to the control electrode of the second transistor. The voltage generating circuit according to claim 4, wherein the switch element is turned on during the operation period of the startup current control circuit and turned off during the shutdown period of the startup current control circuit.

8. The current source is A second path formed in parallel with the first path between the power node and the ground node further includes a second current generating circuit that generates a current proportional to the first current. The first current generation circuit is, A first transistor of a first conductivity type is connected between the power supply node and the first node, A first resistive element connected between the first node and the second node, The system includes a second transistor of a second conductivity type having a control electrode connected between the second node and the ground node and connected to the first node, The second current generation circuit is, Connected between the power supply node and the third node, the third transistor of the first conductivity type constitutes a current mirror with the first transistor, It includes a fourth transistor of second conductivity type connected between the third node and the ground node, and to which the control electrode is connected to the second node, The current source is The system further includes a fifth transistor of first conductivity type connected between the power supply node and the output node, which constitutes a current mirror with the first transistor and the third transistor. The startup current control circuit is connected in parallel with the first resistive element, and is a voltage generation circuit according to any one of claims 1 to 3.

9. The startup current control circuit includes a switch element and a second resistor element connected in series between the first node and the second node. The voltage generating circuit according to claim 8, wherein the switch element is turned on during the operation period of the startup current control circuit and turned off during the shutdown period of the startup current control circuit.

10. The voltage generation circuit according to any one of claims 1 to 3, wherein the operating period of the startup current control circuit is provided for the period from when the power supply voltage rises from the ground voltage to a steady state value until the power supply voltage reaches a determination voltage set lower than the steady state value, and the startup current control circuit is stopped when the power supply voltage exceeds the determination voltage.

11. The aforementioned operating period is set during a period in which the detection voltage indicating the rising behavior of the power supply voltage is higher than the divided voltage of the power supply voltage based on a predetermined voltage division ratio. The detection voltage is generated such that the voltage rise rate at startup of the power supply voltage is higher than that of the voltage divider voltage, while the voltage rise rate becomes lower than that of the voltage divider voltage as the power supply voltage increases. The voltage generation circuit according to claim 10, wherein the voltage division ratio is determined such that when the power supply voltage is lower than the determination voltage, the detection voltage is higher than the voltage division voltage, and when the power supply voltage is higher than the determination voltage, the voltage division voltage is higher than the detection voltage.

12. A diode-connected eighth transistor is connected between the fourth node where the detection voltage is generated and the ground node. A ninth transistor with a lower threshold voltage than the eighth transistor is connected between the fourth node and the power supply node. The voltage generating circuit according to claim 11, wherein the control electrode of the ninth transistor is connected to the fourth node.