Antenna control device, antenna control method, and array antenna device

Abstract

An antenna control device (1) is configured to comprise: a signal conversion unit (12) that converts a multi-bit signal into 1-bit signals and outputs the 1-bit signals; and a plurality of output switching units (13-1 to 13-K) that each delay a 1-bit signal outputted from the signal conversion unit (12) and output the delayed 1-bit signal to, among a plurality of antenna elements (6-1 to 6-K) included in an array antenna (6), a corresponding antenna element (6-k) (k=1,..., K). Each output switching unit (13-k) has: a first delay processing unit (31-1) that delays a 1-bit signal outputted from the signal conversion unit (12) by a first delay time; a second delay processing unit (31-2) that delays a 1-bit signal outputted from the signal conversion unit (12) by a second delay time; and a switching unit (32) that outputs, to a corresponding antenna element (6-k), either a first signal that is the 1-bit signal having been delayed by the first delay processing unit (31-1) or a second signal that is the 1-bit signal having been delayed by the second delay processing unit (31-2), on the basis of the ratio of outputting the first signal or the second signal.

Description

Antenna control device, antenna control method, and array antenna device

[0001] The present disclosure relates to an antenna control device, an antenna control method, and an array antenna device.

[0002] There is an array antenna device that includes an array antenna including a plurality of antenna elements. For example, Patent Document 1 discloses an array antenna system as such an array antenna device, which includes a plurality of signal conversion units that convert multi-bit signals into 1-bit signals and output the 1-bit signals, and an array antenna that radiates radio waves in a desired direction based on the 1-bit signals output from the plurality of signal conversion units.

[0003] JP 2017-17421 A

[0004] The array antenna system disclosed in Patent Document 1 has a problem in that it is not possible to radiate radio waves from the array antenna in a desired direction unless it is provided with a plurality of signal conversion units.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to obtain an antenna control device that can radiate radio waves from an array antenna in a desired direction by simply having one signal conversion unit.

[0006] The antenna control device according to the present disclosure includes a signal conversion unit that converts a multi-bit signal into a 1-bit signal and outputs the 1-bit signal, and a plurality of output switching units that delay the 1-bit signal output from the signal conversion unit and output the delayed 1-bit signal to a corresponding antenna element among a plurality of antenna elements included in an array antenna. Each output switching unit has a first delay processing unit that delays the 1-bit signal output from the signal conversion unit by a first delay time, a second delay processing unit that delays the 1-bit signal output from the signal conversion unit by a second delay time, and a switching unit that outputs either the first signal, which is the 1-bit signal delayed by the first delay processing unit, or the second signal, which is the 1-bit signal delayed by the second delay processing unit, to the corresponding antenna element based on an output ratio of the first signal, which is the 1-bit signal delayed by the first delay processing unit, or the second signal, which is the 1-bit signal delayed by the second delay processing unit.

[0007] According to the present disclosure, radio waves can be emitted from an array antenna in a desired direction by simply providing one signal conversion unit.

[0008] 1 is a configuration diagram showing an array antenna device including an antenna control device 1 according to a first embodiment. FIG. 2 is a hardware configuration diagram showing hardware of the antenna control device 1 according to the first embodiment. FIG. 3 is a hardware configuration diagram of a computer in the case where the antenna control device 1 is realized by software, firmware, or the like. FIG. 4 is a configuration diagram showing a signal conversion unit 12 of the antenna control device 1 according to the first embodiment. FIG. 5 is a configuration diagram showing an output switching unit 13-k (k=1, ..., K) of the antenna control device 1 according to the first embodiment. FIG. 6 is a flowchart showing an antenna control method, which is a processing procedure of the antenna control device 1. FIG. 7 is an explanatory diagram showing waveform images of a first signal, a second signal, a third signal, and a fourth signal. FIG. 8 is an explanatory diagram showing the relationship between a switching ratio and the phase of an output signal. FIG. 9 is an explanatory diagram showing the relationship between a first signal, a second signal, a third signal, and a fourth signal.

[0009] In order to explain the present disclosure in more detail, embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0010] First Embodiment Fig. 1 is a configuration diagram showing an array antenna device including an antenna control device 1 according to a first embodiment. The array antenna device shown in Fig. 1 includes the antenna control device 1, amplifiers 4-1 to 4-K, filters 5-1 to 5-K, and an array antenna 6, where K is an integer equal to or greater than 2. The antenna control device 1 includes an FPGA (Field Programmable Gate Array) 2 and a control unit 3. The FPGA 2 includes a signal generation unit 11, a signal conversion unit 12, and output switching units 13-1 to 13-K. The array antenna 6 includes antenna elements 6-1 to 6-K.

[0011] The signal generation unit 11 is realized by, for example, a signal generation circuit 41 shown in Fig. 2. The signal generation unit 11 is, for example, an RF (Radio Frequency) signal generator. The signal generation unit 11 generates a multi-bit signal in the RF band and outputs the multi-bit signal to the signal conversion unit 12. In the antenna control device 1 shown in Fig. 1, the FPGA 2 includes the signal generation unit 11. However, this is merely an example, and the signal generation unit 11 may be provided outside the FPGA 2.

[0012] The signal conversion unit 12 is realized by, for example, the signal conversion circuit 42 shown in FIG. 2. The signal conversion unit 12 has, for example, a delta-sigma modulation unit or a pulse-width modulation unit. The signal conversion unit 12 acquires a multi-bit signal from the signal generation unit 11. The signal conversion unit 12 converts the multi-bit signal into a 1-bit signal and outputs the 1-bit signal to each of the K output switching units 13-1 to 13-K. The 1-bit signal is a signal having an H (High) level voltage or an L (Low) level voltage. The signal conversion unit 12 outputs the 1-bit signal to each of the K output switching units 13-1 to 13-K at, for example, a sampling rate four times the frequency of the multi-bit signal.

[0013] The output switching unit 13-k (k = 1, ..., K) is realized by, for example, the output switching circuit 43 shown in FIG. 2. As shown in FIG. 5, the output switching unit 13-k includes a first delay processing unit 31-1, a second delay processing unit 31-2, a switching unit 32, and an amplitude adjustment unit 33. The output switching unit 13-k acquires a 1-bit signal from the signal conversion unit 12. The output switching unit 13-k delays the 1-bit signal and outputs the delayed 1-bit signal to the amplifier 4-k included in the series of the corresponding antenna element 6-k among the K antenna elements 6-1 to 6-K.

[0014] The control unit 3 is realized by, for example, the control circuit 44 shown in Fig. 2. The control unit 3 controls a switching ratio, which is the ratio at which the first signal or the second signal is output from the output switching unit 13-k (k = 1, ..., K). The control unit 3 also controls the first delay time in the first delay processing unit 31-1 and the second delay time in the second delay processing unit 31-2.

[0015] The amplifier 4-k (k=1, . . . , K) receives the delayed 1-bit signal from the output switching unit 13-k, amplifies the delayed 1-bit signal, and outputs the amplified 1-bit signal to the filter 5-k.

[0016] Filter 5-k (k = 1, ..., K) acquires the amplified 1-bit signal from amplifier 4-k. By passing through filter 5-k, the 1-bit signal returns to an RF band signal waveform similar to that of the multi-bit signal generated by signal generator 11. Antenna element 6-k (k = 1, ..., K) radiates into space a radio wave corresponding to the signal that has passed through filter 5-k.

[0017] 1, it is assumed that each of the components of the antenna control device 1, namely, the signal generation unit 11, the signal conversion unit 12, the output switching units 13-1 to 13-N, and the control unit 3, is realized by dedicated hardware as shown in Fig. 2. That is, it is assumed that the antenna control device 1 is realized by a signal generation circuit 41, a signal conversion circuit 42, an output switching circuit 43, and a control circuit 44. Each of the signal generation circuit 41, the signal conversion circuit 42, the output switching circuit 43, and the control circuit 44 is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination thereof.

[0018] The components of the antenna control device 1 are not limited to those realized by dedicated hardware, and the antenna control device 1 may be realized by software, firmware, or a combination of software and firmware. The software or firmware is stored as a program in the memory of a computer. The computer refers to hardware that executes a program, and includes, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a central processing unit, a processing unit, an arithmetic unit, a microprocessor, a microcomputer, a processor, or a DSP (Digital Signal Processor).

[0019] 3 is a hardware configuration diagram of a computer when the antenna control device 1 is realized by software, firmware, etc. When the antenna control device 1 is realized by software, firmware, etc., a program for causing a computer to execute the respective processing procedures of the signal generation unit 11, the signal conversion unit 12, the output switching units 13-1 to 13-N, and the control unit 3 is stored in a memory 51. Then, a processor 52 of the computer executes the program stored in the memory 51.

[0020] 2 shows an example in which each of the components of the antenna control device 1 is realized by dedicated hardware, while Fig. 3 shows an example in which the antenna control device 1 is realized by software, firmware, etc. However, this is merely an example, and some of the components in the antenna control device 1 may be realized by dedicated hardware, and the remaining components may be realized by software, firmware, etc.

[0021] Fig. 4 is a configuration diagram showing the signal conversion unit 12 of the antenna control device 1 according to the first embodiment. Fig. 4 shows an example of the configuration of first-order delta-sigma modulation when the signal conversion unit 12 is realized by a delta-sigma modulation unit. The signal conversion unit 12 shown in Fig. 4 includes a loop filter 21 and a 1-bit quantizer 25. The loop filter 21 includes a subtractor 22, an integrator 23, and a delay unit 24. The integrator 23 includes an adder 23a and a delay unit 23b.

[0022] The subtractor 22 subtracts the 1-bit signal delayed by the delay unit 24 from the multi-bit signal output from the signal generating unit 11, and outputs a subtraction signal indicating the result of the subtraction to the adder 23a. The adder 23a adds the subtraction signal output from the subtractor 22 to the sum signal delayed by the delay unit 23b, and outputs a sum signal indicating the result of the addition to the delay unit 23b and the 1-bit quantizer 25. The delay unit 23b delays the sum signal output from the adder 23a, and outputs the delayed sum signal to the adder 23a.

[0023] The delay unit 24 delays the 1-bit signal output from the 1-bit quantizer 25 and outputs the delayed 1-bit signal to the subtractor 22. The 1-bit quantizer 25 quantizes the sum signal output from the adder 23 a to generate a 1-bit signal, and outputs the 1-bit signal to each of the K output switching units 13-1 to 13-K.

[0024] 5 is a configuration diagram showing an output switching unit 13-k (k=1, ..., K) of the antenna control device 1 according to the first embodiment. The output switching unit 13-k shown in FIG. 5 has a first delay processing unit 31-1, a second delay processing unit 31-2, a switching unit 32, and an amplitude adjustment unit 33. The first delay processing unit 31-1 acquires a 1-bit signal from the signal conversion unit 12. The first delay processing unit 31-1 delays the 1-bit signal by a first delay time and outputs the first signal, which is a 1-bit signal after the delay, to the switching unit 32.

[0025] The second delay processing unit 31-2 acquires a 1-bit signal from the signal conversion unit 12. The second delay processing unit 31-2 delays the 1-bit signal by a second delay time and outputs the delayed 1-bit signal, which is a second signal, to the switching unit 32. In the antenna control device 1 according to the first embodiment, the signal conversion unit 12 outputs a 1-bit signal at a sampling rate four times the frequency of the multi-bit signal, and the second delay time is a delay time that delays the signal by one bit longer than the first delay time. If the 1-bit signal is output at a sampling rate faster than four times the frequency of the multi-bit signal, the circuit size would become large and this would be unrealistic. Here, the second delay time is assumed to be a delay time that delays the signal by one bit longer than the first delay time. However, this is merely an example, and the second delay time may be longer than the first delay time by one clock or more.

[0026] The switching unit 32 outputs either the first signal output from the first delay processing unit 31-1 or the second signal output from the second delay processing unit 31-2 as a third signal to the amplitude adjustment unit 33 based on the ratio controlled by the control unit 3. When the second delay time is longer than the first delay time by one clock or more, the switching unit 32 outputs either the first signal or the second signal to the amplitude adjustment unit 33 in units of one clock.

[0027] The amplitude adjustment unit 33 acquires the third signal from the switching unit 32. The amplitude adjustment unit 33 adjusts the amplitude of the third signal based on the amplitude adjustment amount controlled by the control unit 3. The amplitude adjustment unit 33 outputs the signal after the amplitude adjustment to the amplifier 4-k included in the series of the corresponding antenna element 6-k.

[0028] Next, the operation of the array antenna device shown in Fig. 1 will be described. Fig. 6 is a flowchart showing an antenna control method, which is a processing procedure of the antenna control device 1. The signal generation unit 11 generates, for example, a multi-bit signal in the RF band (step ST1 in Fig. 6). The process of generating the multi-bit signal itself is a well-known technique, so a detailed description will be omitted. The signal generation unit 11 outputs the multi-bit signal to the signal conversion unit 12.

[0029] The signal conversion unit 12 acquires a multi-bit signal from the signal generation unit 11. The signal conversion unit 12 converts the multi-bit signal into a 1-bit signal (step ST2 in FIG. 6). The 1-bit signal is, for example, an RF band signal. The conversion into a 1-bit signal by the signal conversion unit 12 is performed under the control of the control unit 3. However, if the frequency, sampling rate, etc. are fixed, control by the control unit 3 is not necessary.

[0030] The output switching unit 13-k acquires a 1-bit signal from the signal conversion unit 12. The output switching unit 13-k outputs either the first signal or the second signal to the amplifier 4-k based on the ratio controlled by the control unit 3 (step ST3 in FIG. 6). The signal switching process performed by the output switching unit 13-k will be specifically described below.

[0031] The first delay processing unit 31-1 acquires a 1-bit signal from the signal conversion unit 12. The first delay processing unit 31-1 delays the 1-bit signal by a first delay time controlled by the control unit 3. The first delay processing unit 31-1 outputs a first signal, which is a delayed 1-bit signal, to the switching unit 32.

[0032] The second delay processing unit 31-2 acquires a 1-bit signal from the signal conversion unit 12. The second delay processing unit 31-2 delays the 1-bit signal by a second delay time controlled by the control unit 3. The second delay processing unit 31-2 outputs a second signal, which is a delayed 1-bit signal, to the switching unit 32. In the array antenna device shown in FIG. 1, the second delay time is, for example, a delay time that delays the signal by one bit more than the first delay time. Therefore, as shown in FIG. 7, the second signal is delayed by one bit more than the first signal. FIG. 7 is an explanatory diagram showing waveform images of the first signal, second signal, third signal, and fourth signal. The fourth signal is the signal shown in FIG. 9 and will be described later.

[0033] Based on the ratio controlled by the control unit 3, the switching unit 32 outputs either the first signal output from the first delay processing unit 31-1 or the second signal output from the second delay processing unit 31-2 as a third signal to the amplitude adjustment unit 33. FIG. 8 is an explanatory diagram showing the relationship between the switching ratio and the phase of the output signal. If the phase of the signal to the antenna element 6-k, which corresponds to the radiation direction of the radio wave, is, for example, 18.0 [deg.], the switching ratio between the first signal and the second signal is controlled to 3:1 by the control unit 3, and the switching unit 32 outputs either the first signal or the second signal at a switching ratio of 3:1. If the phase of the signal to the antenna element 6-k, which corresponds to the radiation direction of the radio wave, is, for example, 26.7 [deg.], the switching unit 32 outputs either the first signal or the second signal at a switching ratio of 3:1. ], the switching ratio between the first signal and the second signal is controlled to 2:1 by the control unit 3, and the switching unit 32 outputs either the first signal or the second signal at a switching ratio of 2:1. If the phase of the signal to the antenna element 6-k, which corresponds to the radiation direction of the radio wave, is, for example, 45.0 [deg.], the switching ratio between the first signal and the second signal is controlled to 1:1 by the control unit 3, and the switching unit 32 outputs either the first signal or the second signal at a switching ratio of 1:1.

[0034] If the phase of the signal to antenna element 6-k, which corresponds to the radiation direction of the radio waves, is, for example, 63.3 degrees, the switching ratio between the first signal and the second signal is controlled by the control unit 3 to 1:2, and the switching unit 32 outputs either the first signal or the second signal at a switching ratio of 1:2. If the phase of the signal to antenna element 6-k, which corresponds to the radiation direction of the radio waves, is, for example, 72.0 degrees, the switching ratio between the first signal and the second signal is controlled by the control unit 3 to 1:3, and the switching unit 32 outputs either the first signal or the second signal at a switching ratio of 1:3. If the phase of the signal to antenna element 6-k, which corresponds to the radiation direction of the radio waves, is, for example, 0.0 degrees, the switching unit 32 always outputs the first signal. If the phase of the signal to antenna element 6-k, which corresponds to the radiation direction of the radio waves, is, for example, 90.0 degrees, ], the switching unit 32 always outputs the second signal.

[0035] The amplitude adjustment unit 33 acquires the third signal from the switching unit 32. The amplitude adjustment unit 33 adjusts the amplitude of the third signal based on the amplitude adjustment amount controlled by the control unit 3. The amplitude adjustment unit 33 outputs the signal after the amplitude adjustment to the amplifier 4-k included in the series of the corresponding antenna element 6-k.

[0036] The amplifier 4-k (k=1, . . . , K) receives the third signal from the output switching unit 13-k, amplifies the third signal, and outputs the amplified third signal to the filter 5-k.

[0037] The filter 5-k (k = 1, ..., K) acquires the amplified third signal from the amplifier 4-k. The amplified third signal passes through the filter 5-k to become a fourth signal having a signal waveform similar to that of the multi-bit signal generated by the signal generator 11, as shown in FIG. 7. The antenna element 6-k (k = 1, ..., K) radiates into space a radio wave corresponding to the fourth signal output from the filter 5-k. FIG. 9 is an explanatory diagram showing the relationship between the first signal, the second signal, and the fourth signal. In FIG. 9, the horizontal axis represents Ich and the vertical axis represents Qch. The example in FIG. 9 shows the fourth signal when the switching ratio between the first signal and the second signal is 1:1.

[0038] In the above-described first embodiment, the antenna control device 1 is configured to include a signal conversion unit 12 that converts a multi-bit signal into a 1-bit signal and outputs the 1-bit signal, and a plurality of output switching units 13-1 to 13-K that delay the 1-bit signal output from the signal conversion unit 12 and output the delayed 1-bit signal to a corresponding antenna element 6-k (k = 1, ..., K) among a plurality of antenna elements 6-1 to 6-K included in the array antenna 6. Each output switching unit 13-k has a first delay processing unit 31-1 that delays the 1-bit signal output from the signal conversion unit 12 by a first delay time, a second delay processing unit 31-2 that delays the 1-bit signal output from the signal conversion unit 12 by a second delay time, and a switching unit 32 that outputs either the first signal, which is a 1-bit signal delayed by the first delay processing unit 31-1, or the second signal, which is a 1-bit signal delayed by the second delay processing unit 31-2, to the corresponding antenna element 6-k based on the output ratio. Therefore, the antenna control device 1 can radiate radio waves from the array antenna 6 in a desired direction by simply having one signal conversion unit 12.

[0039] In the first embodiment, the antenna control device 1 is configured to include a control unit 3 that controls the ratio at which the first signal or the second signal is output from the output switching unit 13-k (k=1, ..., K). Therefore, the antenna control device 1 can control the radiation direction of the radio waves radiated from the array antenna 6 to a target direction.

[0040] In the first embodiment, the antenna control device 1 is configured so that the output switching unit 13-k (k=1, ..., K) has an amplitude adjustment unit 33 that adjusts the amplitude of the signal output from the switching unit 32 and outputs the amplitude-adjusted signal to the corresponding antenna element 6-k. Therefore, the antenna control device 1 can control the radiation direction of the radio waves radiated from the array antenna 6 to a target direction.

[0041] In addition, in the present disclosure, any of the components of the embodiments may be modified or omitted.

[0042] The present disclosure enables an array antenna to emit radio waves in a desired direction by simply including one signal conversion unit, and can be used in an antenna control device, an antenna control method, and an array antenna device.

[0043] 1 Antenna control device, 2 FPGA, 3 Control unit, 4-1 to 4-K Amplifiers, 5-1 to 5-K, Filter, 6 Array antenna, 6-1 to 6-K Antenna elements, 11 Signal generation unit, 12 Signal conversion unit, 13-1 to 13-N Output switching unit, 21 Loop filter, 22 Subtractor, 23 Integrator, 23a Adder, 23b Delay unit, 24 Delay unit, 25 1-bit quantizer, 31-1 First delay processing unit, 31-2 Second delay processing unit, 32 Switching unit, 33 Amplitude adjustment unit, 41 Signal generation circuit, 42 Signal conversion circuit, 43 Output switching circuit, 44 Control circuit, 51 Memory, 52 Processor.

Claims

1. A signal conversion unit that converts a multi-bit signal into a 1-bit signal and outputs the 1-bit signal, The system includes multiple output switching units that delay the 1-bit signal output from the signal conversion unit and output the delayed 1-bit signal to the corresponding antenna element among the multiple antenna elements included in the array antenna, Each output switching unit is: A first delay processing unit delays the 1-bit signal output from the signal conversion unit by a first delay time, A second delay processing unit delays the 1-bit signal output from the signal conversion unit by a second delay time, An antenna control device comprising: a switching unit that outputs either the first signal or the second signal to the corresponding antenna element based on a ratio of outputting either the first signal, which is a 1-bit signal delayed by the first delay processing unit, or the second signal, which is a 1-bit signal delayed by the second delay processing unit.

2. Each output switching unit is: The antenna control device according to claim 1, further comprising an amplitude adjustment unit that adjusts the amplitude of the signal output from the switching unit and outputs the amplitude-adjusted signal to the corresponding antenna element.

3. The second delay time is at least one clock cycle longer than the first delay time. The switching unit is The antenna control device according to claim 1 or 2, characterized in that it outputs either the first signal or the second signal to the corresponding antenna element in units of one clock cycle.

4. The signal conversion unit is The 1-bit signal is output at a sampling rate four times the frequency of the multi-bit signal. The antenna control device according to claim 1 or 2, characterized in that the second delay time is a delay time that is delayed by 1 bit more than the first delay time.

5. The antenna control device according to claim 1 or 2, further comprising a control unit for controlling the ratio.

6. The signal conversion unit converts a multi-bit signal into a 1-bit signal and outputs the 1-bit signal. Multiple output switching units delay the 1-bit signal output from the signal conversion unit and output the delayed 1-bit signal to the corresponding antenna element among the multiple antenna elements included in the array antenna. Each output switching unit, The 1-bit signal output from the signal conversion unit is delayed by a first delay time, and the 1-bit signal output from the signal conversion unit is delayed by a second delay time. An antenna control method characterized by outputting either the first signal or the second signal to the corresponding antenna element based on a ratio of outputting either a first signal, which is a 1-bit signal delayed by the first delay time, or a second signal, which is a 1-bit signal delayed by the second delay time.

7. An array antenna containing multiple antenna elements, A signal conversion unit that converts a multi-bit signal into a 1-bit signal and outputs the 1-bit signal, The system includes a plurality of output switching units that delay the 1-bit signal output from the signal conversion unit and output the delayed 1-bit signal to the corresponding antenna element among the plurality of antenna elements. Each output switching unit is: A first delay processing unit delays the 1-bit signal output from the signal conversion unit by a first delay time, A second delay processing unit delays the 1-bit signal output from the signal conversion unit by a second delay time, An array antenna device characterized by having a switching unit that outputs either the first signal or the second signal to the corresponding antenna element based on a ratio of outputting a first signal, which is a 1-bit signal delayed by the first delay processing unit, or a second signal, which is a 1-bit signal delayed by the second delay processing unit.