Semiconductor device

Abstract

The present invention increases the surge energy rating of a semiconductor device. A semiconductor device (1) comprises: a semiconductor element (3); and a plurality of wires (44) joined to an electrode (302) exposed on the surface of the semiconductor element. The plurality of wires include wires (44A) having a first wire diameter, and the sum of the bonding areas of the electrode and the plurality of wires having the first wire diameter is greater than or equal to 0.123 mm2 per 1 mm2 of the electrode on the semiconductor element.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] 2. Description of the Related Art Some semiconductor devices used in power conversion devices have electrodes of semiconductor elements such as insulated gate bipolar transistors (IGBTs) connected to conductor patterns on wiring boards or the like by wires (see, for example, Patent Documents 1 and 2).

[0003] JP 2005-166854 A JP 2008-186957 A

[0004] The above-mentioned semiconductor devices are required to have a high surge energy resistance in order to prevent the semiconductor elements from being destroyed by a suddenly generated high current.

[0005] One of the objects of the present invention is to increase the surge energy resistance of a semiconductor device.

[0006] A semiconductor device according to one aspect includes a semiconductor element and a plurality of wires joined to electrodes exposed on a surface of the semiconductor element. The plurality of wires includes wires having a first wire diameter, and the wires are joined to the electrodes of the semiconductor element within 1 mm of the electrodes. ２ The sum of the bonding areas between the electrode and the plurality of wires is 0.123 mm ２ That's all.

[0007] According to the above-described embodiment, the surge energy resistance of the semiconductor device can be increased.

[0008] FIG. 1 is a plan view of a semiconductor device according to an embodiment; FIG. 2 is a cross-sectional view illustrating an example of the configuration inside a case of the semiconductor device of FIG. 1; and FIG. 3 is a circuit diagram of an inverter circuit formed in the semiconductor device of FIG. 1. FIGS. 4A and 4B are plan views illustrating an example of the relationship between wire diameters and junction points of wires. FIGS. 5A and 5B are side views illustrating an example of the relationship between wire diameters and junction points of wires. A table illustrating an example of the relationship between the number of junction points and junction area for each wire diameter of wires. A graph illustrating an example of the relationship between the number of wires and surge energy withstand capacity for each wire diameter. A graph illustrating an example of the relationship between the number of junction points and surge energy withstand capacity for each wire diameter. A graph illustrating an example of the relationship between the junction area and surge energy withstand capacity for each wire diameter. A graph illustrating an example of the relationship between the number of wires per unit area for each wire diameter and surge energy withstand capacity for each wire diameter. A graph illustrating an example of the relationship between the number of wires per unit area for each wire diameter and surge energy withstand capacity for each wire diameter. A graph illustrating an example of the relationship between the number of junction points per unit area for each wire diameter and surge energy withstand capacity for each wire diameter.

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The X-axis, Y-axis, and Z-axis in the drawings are shown for the purpose of defining planes and directions in the illustrated semiconductor device. The X-axis, Y-axis, and Z-axis are orthogonal to each other and form a right-handed system. In the following description, the direction parallel to the X-axis is referred to as the X-direction, the direction parallel to the Y-axis is referred to as the Y-direction, and the direction parallel to the Z-axis is referred to as the Z-direction. Furthermore, when each of the X-direction, Y-direction, and Z-direction is associated with the direction of the arrows (positive and negative) of the X-axis, Y-axis, and Z-axis shown in the drawings, it is referred to as the "positive side" or "negative side."

[0010] In this specification, the Z direction may be referred to as the up-down direction. In this specification, "up" and "above" refer to the positive side of the Z direction relative to a reference surface, component, position, etc., and "down" and "below" refer to the negative side of the Z direction relative to a reference surface, component, position, etc. For example, when describing "component B is placed on component A," component B is placed on the positive side of component A in the Z direction. Furthermore, when describing "the top surface of component A," this surface includes the surface located at the end of component A on the positive side of the Z direction and facing the positive side of the Z direction. These directions and surfaces associated with these directions are terms used for convenience of explanation, and their correspondence with the X-axis, Y-axis, and Z-axis directions may change depending on the mounting orientation of the semiconductor device, etc. For example, in this specification, the surface of a semiconductor element facing a wiring board is referred to as the bottom surface, and the surface opposite the bottom surface is referred to as the top surface. However, this is not limited thereto, and the surface facing the wiring board may be referred to as the top surface, and the surface opposite the top surface may be referred to as the bottom surface.

[0011] The aspect ratios and relative sizes of components in each drawing are merely schematic representations and do not necessarily correspond to the relationships in an actually manufactured semiconductor device. For the sake of convenience, the relative sizes of components may be exaggerated or may differ from the external shapes of components used in an actual semiconductor device. Furthermore, for the sake of convenience, some of the cross-sectional views show the cross-sectional configuration of a semiconductor device cut along an imaginary cutting line that cannot be accurately shown in a plan view.

[0012] In this specification, the terms "not shown," "not shown," "not shown," and the like are intended to mean that the components to which these terms are attached, or the reference symbols and leading lines that clearly indicate the components, are not shown in the figures. For example, "first main electrode not shown" is intended to mean both that a part (e.g., a shape, a line, etc.) representing the first main electrode is not shown in the figures, and that a reference symbol and leading line that clearly indicates a part corresponding to the first main electrode in the figures are not included in the figures. Also, underlined reference symbols in the figures indicate the entire component, including multiple parts that are distinguished by multiple reference symbols.

[0013] The semiconductor device exemplified in the following description may be applied to, for example, a power conversion device such as an inverter device for industrial or electrical equipment (e.g., for an in-vehicle motor). Therefore, in the following description, detailed descriptions of configurations, functions, operations, manufacturing methods, etc. identical or similar to those of known semiconductor devices will be omitted. In this specification, a "semiconductor device" refers to a semiconductor element, sometimes called a semiconductor chip or die, sealed with an insulating material, and may also be referred to as a "semiconductor module." Furthermore, the "surge energy tolerance" in the present invention may be a value expressed as the product of the surge current tolerance IFSM and the voltage VFSM. The surge current tolerance IFSM is the maximum value of a non-repetitive forward surge current in a half cycle of a commercial frequency sine wave (pulse width tp = 10 ms), and the voltage VFSM is the value of the forward voltage Vf of the diode element when measuring the surge current tolerance IFSM.

[0014] Fig. 1 is a plan view of a semiconductor device according to one embodiment. Fig. 2 is a cross-sectional view illustrating an example of the configuration inside a case of the semiconductor device of Fig. 1. Fig. 3 is a circuit diagram of an inverter circuit formed in the semiconductor device of Fig. 1. The cross-sectional view of Fig. 2 may be an example of a cross-sectional configuration when the semiconductor device 1 of Fig. 1 is cut along the dashed dotted line A-A'.

[0015] The semiconductor device 1 according to the present embodiment includes wiring boards 2A and 2B, semiconductor elements 3A-3D, wires 40-49, a case 5, a sealant (not shown), and a heat sink 6. In this specification, when referring to components referenced by a symbol consisting of a number followed by a letter, the number and letter are used to distinguish between components assigned the same number, and only the number is used when no distinction is required. For example, when referring to a specific semiconductor element among multiple semiconductor elements 3A-3D, the symbol assigned to that specific semiconductor element in FIG. 1 is used (e.g., "semiconductor element 3A"). Otherwise, the symbol is simply referred to as "semiconductor element 3." Furthermore, when referring to multiple elements with the same designation, the modifiers "first" and "second" may be used. For example, wiring board 2A and wiring board 2B may be referred to as "first wiring board 2A" and "second wiring board 2B." It should be noted that the modifiers "first" and "second" are used only to distinguish between multiple identical components and are not intended to specify the order of those components.

[0016] The wiring board 2 is an element-mounting component that mounts a semiconductor element 3, which may also be called a semiconductor chip, die, or the like. The semiconductor element 3 may be, for example, an RC (Reverse Conducting)-IGBT element that combines the functions of a switching element such as an IGBT (Insulated Gate Bipolar Transistor) element and the functions of a diode element such as an FWD (Free Wheeling Diode). The wiring board 2 and the semiconductor element 3 are circuit components for forming a half-bridge inverter circuit 10 illustrated in FIG. 3 .

[0017] The first wiring board 2A includes an insulating substrate 200, conductor patterns 201 to 207 arranged on the upper surface of the insulating substrate 200, and a heat dissipation pattern arranged on the lower surface of the insulating substrate 200. The second wiring board 2B includes an insulating substrate 200, conductor patterns 201, 202, 204 to 207 arranged on the upper surface of the insulating substrate 200, and a heat dissipation pattern 208 arranged on the lower surface of the insulating substrate 200. The wiring board 2 may be, but is not limited to, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazing) substrate. The first wiring board 2A and the second wiring board 2B may be integrated.

[0018] The insulating substrate 200 is made of, for example, aluminum oxide (Al ２ O ３ ), aluminum nitride (AlN), silicon nitride (Si ３ N ４ ), or aluminum oxide (Al ２ O ３ ) and zirconium oxide (ZrO ２ The insulating substrate 200 may be a substrate formed of a ceramic material such as a composite material with a metal core. The insulating substrate 200 may be a substrate formed by molding an insulating resin such as an epoxy resin into a sheet shape, a substrate formed by impregnating a base material such as glass fiber with an insulating resin, or a substrate formed by coating the surface of a flat metal core with an insulating resin.

[0019] Conductor patterns 201 to 207 arranged on the upper surface of insulating substrate 200 are used as wiring in electronic circuits such as an inverter circuit formed within semiconductor device 1. Heat dissipation pattern 208 arranged on the lower surface of insulating substrate 200 is used as a heat dissipation component that conducts heat generated by semiconductor element 3 to heat sink 6 during operation of semiconductor device 1. Conductor patterns 201 to 207 and heat dissipation pattern 208 are formed from, for example, a metal foil such as copper or aluminum.

[0020] The wiring board 2 is disposed on the upper surface of the heat sink 6. The heat dissipation pattern 208 of the wiring board 2 is connected in close contact with the upper surface of the heat sink 6 by a bonding material such as solder (not shown) or a heat transfer material such as thermal grease or thermal compound. The heat sink 6 may be a metal plate made of, for example, copper or aluminum. The heat sink 6 may have a plurality of fins on its lower surface. The heat sink 6 may be a part of the cooler 7 or may be a component connected to the cooler 7. In other words, the cooler 7 is an optional component of the semiconductor device 1 of this embodiment. The cooler 7 is not limited to a specific cooling method or a specific structure.

[0021] 1 and 2, a case 5 is disposed on the upper surface of a heat sink 6. The case 5 includes a frame-shaped insulating member 500 having openings on the upper and lower surfaces, and a plurality of terminals 501-507 integrated with the insulating member 500. When placed on the upper surface of the heat sink 6, the insulating member 500 of the case 5 can be shaped to accommodate the wiring board 2, semiconductor element 3, wires 40-49, etc., and to define a space that can be filled with a sealant to seal them. The open end on the upper surface of the insulating member 500 may be covered, for example, with a lid (not shown) formed of an insulating material.

[0022] The terminals 501-507 of the case 5 are broadly divided into main terminals 501-503 and control terminals 504-507. The main terminals 501-503 are connected to electrodes that pass a main current through switching elements, such as IGBT elements, in the semiconductor element 3. In the case of the semiconductor device 1 having the half-bridge inverter circuit 10 illustrated in FIG. 3 , the first main terminal 501 may be a P terminal connected to the positive electrode of a DC power supply and connected to the collector electrodes of the IGBT elements 310 in the semiconductor elements 3A and 3B arranged on the upper surface of the first wiring board 2A. The second main terminal 502 may be an N terminal connected to the negative electrode of a DC power supply and connected to the emitter electrodes of the IGBT elements 310 in the semiconductor elements 3C and 3D arranged on the upper surface of the second wiring board 2B. The third main terminal 503 is an intermediate terminal (M terminal) connected to a load, and is connected to the emitter electrodes of the IGBT elements 310 of the semiconductor elements 3A and 3B arranged on the upper surface of the first wiring board 2A, and the collector electrodes of the semiconductor elements 3C and 3D arranged on the upper surface of the second wiring board 2B. The semiconductor element 3, which is the RC-IGBT element described above, includes the IGBT element 310 and a diode element 311 connected in anti-parallel to the IGBT element 310. The semiconductor element 3 in the semiconductor device 1 illustrated in FIGS. 1 and 2 is arranged on the wiring board 2 with the collector electrode arranged on the lower surface and the emitter electrode 302 and the gate electrode 303 arranged on the upper surface.

[0023] Collector electrodes of semiconductor elements 3A and 3B on first wiring board 2A are joined to first conductor pattern 201 of wiring board 2 by a bonding material such as solder. First conductor pattern 201 of first wiring board 2A is electrically connected to first main terminal 501 by wire 40. Emitter electrodes 302 of semiconductor elements 3A and 3B on first wiring board 2A are electrically connected to second conductor pattern 202 of first wiring board 2A by wire 41. Second conductor pattern 202 of first wiring board 2A is electrically connected to first conductor pattern 201 of second wiring board 2B by wire 42. First conductor pattern 201 of second wiring board 2B is joined to collector electrodes of semiconductor elements 3C and 3D, and is electrically connected to third main terminal 503 by wire 43. Emitter electrodes 302 of semiconductor elements 3C and 3D are electrically connected to second conductor pattern 202 of second wiring board 2B by wire 44. Second conductor pattern 202 of second wiring board 2B is electrically connected to third conductor pattern 203 of first wiring board 2A by wire 45, and third conductor pattern 203 of first wiring board 2A is electrically connected to second main terminal 502 by wire 46.

[0024] Gate electrodes 303 of semiconductor elements 3A and 3B are electrically connected to fourth conductor pattern 204 of first wiring board 2A by wire 47. Fourth conductor pattern 204 of first wiring board 2A is electrically connected to first control terminal 504 via wire and sixth conductor pattern 206 of second wiring board 2B. Gate electrodes 303 of semiconductor elements 3C and 3D are electrically connected to fourth conductor pattern 204 of second wiring board 2B by wire 48. Fourth conductor pattern 204 of second wiring board 2B is electrically connected to second control terminal 505 via wire and sixth conductor pattern 206 of first wiring board 2A.

[0025] 3 also has auxiliary control terminals 506 and 507, also referred to as auxiliary emitter terminals, sense-emitter terminals, emitter-sense terminals, etc. The first auxiliary control terminal 506 is electrically connected to the emitter electrodes 302 of the semiconductor elements 3A and 3B and is connected to a control circuit (not shown) that generates control signals to be applied to the gate electrodes 303 of the semiconductor elements 3A and 3B. The second auxiliary control terminal 507 is electrically connected to the emitter electrodes 302 of the semiconductor elements 3C and 3D and is connected to a control circuit (not shown) that generates control signals to be applied to the gate electrodes 303 of the semiconductor elements 3C and 3D. In the case of a semiconductor device 1 having auxiliary emitter terminals, the second conductor pattern 202 of the first wiring board 2A is electrically connected to the first auxiliary control terminal 506 via wires, the fifth conductor pattern 205 of the first wiring board 2A, and the seventh conductor pattern 207 of the second wiring board 2B, etc. Similarly, the second conductor pattern 202 of the second wiring board 2B is electrically connected to the second auxiliary control terminal 507 via the wire 49, the fifth conductor pattern 205 of the second wiring board 2B, and the seventh conductor pattern 207 of the first wiring board 2A, etc.

[0026] 1 to 3 are merely examples of semiconductor devices to which the present invention can be applied. The wiring board 2, semiconductor element 3, case 5, etc. in the semiconductor device 1 are not limited to those with specific configurations. The electronic circuit formed in the semiconductor device 1 to which the present invention can be applied is not limited to the half-bridge inverter circuit 10 described above.

[0027] In the semiconductor device 1 of this embodiment, the emitter electrode 302 of one semiconductor element 3 is electrically connected to the conductor pattern 202 of the wiring board 2 by multiple wires 41 or 44. This connection increases the bonding area of ​​the emitter electrode 302 with the wire 41 or 44, thereby increasing the surge energy resistance of the semiconductor element 3. However, the bonding area of ​​the emitter electrode 302 of the semiconductor element 3 with the wire 41 or 44 is limited by the combination of the dimensions of the exposed region of the emitter electrode 302 on the top surface of the semiconductor element 3 and the wire diameter (diameter) of the wire 41 or 44. The wires 41 and 44 may be made of aluminum, an aluminum alloy, or the like, but are not limited to a specific material. Furthermore, although the present specification describes the wires 41 and 44 bonded to the emitter electrode 302 of the semiconductor element 3 as having a circular cross section, the cross-sectional shape of the wires 41 and 44 is not limited to a circular shape.

[0028] 4A and 4B are plan views illustrating the relationship between the wire diameter and the bonding points. FIGS. 5A and 5B are side views illustrating the relationship between the wire diameter and the bonding points. FIG. 6 is a table illustrating the relationship between the number of bonding points and the bonding area for each wire diameter. The side view of FIG. 5A may be the left side view of FIG. 4A, and the side view of FIG. 5B may be the left side view of FIG. 4B. The emitter electrode 302 of the semiconductor element 3 illustrated in FIGS. 4A and 4B is divided into two in the extension direction (Y direction) of the wire 44, but the emitter electrode 302 may be a single electrode without being divided, or may be divided according to a different division pattern.

[0029] 4A and 5A show an example of the wire spacing D2 and the number of junctions with the emitter electrode 302 when the emitter electrode 302 of the semiconductor element 3 is connected to the conductor pattern 202 of the wiring board 2 using a wire 44B having a wire diameter R2 of 400 μm (hereinafter referred to as the "second diameter wire 44B"). In wire bonding using the second diameter wire 44B, the spacing L2 between the junctions when two points on one wire 44B are bonded to a conductor so as to form a loop therebetween may be, for example, approximately 3.3 mm. Therefore, for example, if the dimension ERy of the wire 44B in the extension direction (Y direction) of the exposed region ER of the emitter electrode 302 on the top surface of the semiconductor element 3 is approximately 5.0 mm, the number of junctions with the emitter electrode 302 for one second diameter wire 44B is two. Therefore, when the emitter electrode 302 of the semiconductor element 3, whose region ER has a dimension ERy of 5.0 mm, is electrically connected to the conductor pattern 202 of the wiring board 2 by the wire 44B having the second wire diameter, the relationship between the number of wires, the number of bonding points, and the bonding area is as shown in Fig. 6. The bonding area of ​​the wire 44B having the second wire diameter (R2 = 400 µm) shown in Fig. 6 is 0.323 mm, which is the bonding area of ​​one bonding point when bonding is performed using a general bonding tool. ２ In reality, the wire and the electrode are connected to each other by a junction over a predetermined finite area in a plan view. In this specification, the term "junction point" refers to the center of the area where the wire and the electrode are connected to each other by a junction. For example, in a junction point between a wire and an electrode having a junction area that is close to an ellipse, the intersection of the major and minor axes of the ellipse is the junction point. In this specification, the distance between these junction points and the like are specified.

[0030] Furthermore, when multiple wires 44B of the second diameter are bonded to the emitter electrode 302 of the semiconductor element 3 in a direction (X direction) perpendicular to the wire extension direction (Y direction), the minimum value of the wire spacing D2 in the X direction (minimum spacing D2min) depends on the dimension of the bonding tool in the X direction (in other words, the gap G2 between the bonding points of adjacent wires 44B illustrated in FIG. 4A). Since the minimum spacing D2min of the wires 44B of the second diameter can be 0.8 mm, when the dimension ERx in the X direction of the region ER illustrated in FIG. 4A is 5.0 mm, the maximum number of wires 44B of the second diameter that can be used for bonding to the emitter electrode 302 of the semiconductor element 3 is 6 to 7.

[0031] 4B and 5B show an example of the wire spacing D1 and the number of junctions with the emitter electrode 302 when the emitter electrode 302 of the semiconductor element 3 is connected to the conductor pattern 202 of the wiring board 2 using a wire 44A having a wire diameter R1 of 200 μm (hereinafter referred to as the "first diameter wire 44A"). In wire bonding using the first diameter wire 44A, the spacing L1 between the junctions when two points on one wire 44A are bonded to a conductor so as to form a loop therebetween can be, for example, approximately 1.1 mm. Therefore, for example, if the dimension ERy of the wire 44A in the extension direction (Y direction) at the exposed region ER of the emitter electrode 302 on the top surface of the semiconductor element 3 is approximately 5.0 mm, the number of junctions with the emitter electrode 302 for one first diameter wire 44A is four. Depending on the performance of the bonding tool and the device, the distance L1 can be set to 1.0 mm or 0.9 mm. Furthermore, when multiple wires 44A of the first diameter are bonded to the emitter electrode 302 of the semiconductor element 3 in a direction (X direction) perpendicular to the extension direction (Y direction) of the wires 44A, the minimum distance D1 (minimum distance D1min) between the wires 44A of the first diameter, which may depend on the gap G1 between adjacent bonding points in the X direction, can be 0.4 mm. Therefore, when the X-direction dimension ERx of the region ER illustrated in FIG. 4B is 5.0 mm (i.e., the same as the dimension of the region ER illustrated in FIG. 4A), the maximum number of wires 44A of the first diameter that can be used for bonding to the emitter electrode 302 of the semiconductor element 3 is 12 to 13. Therefore, when the emitter electrode 302 of the semiconductor element 3 having the region ER of the above dimensions is electrically connected to the conductor pattern 202 of the wiring board 2 by the wires 44A having the first wire diameter, the relationship between the number of wires 44A and the bonding area is as shown in Fig. 6. Note that the bonding area of ​​the wires 44A having the first wire diameter (R1 = 200 µm) shown in Fig. 6 is 0.085 mm, which is the bonding area of ​​one bonding point when bonding is performed using a general bonding tool. ２ It is derived as:

[0032] As described above, the minimum spacing D1min (=0.4 mm) of the wires 44A having the first wire diameter (200 μm) can be half the minimum spacing D2min (=0.8 mm) of the wires 44B having the second wire diameter (400 μm). Therefore, for example, by changing the wires bonded to the emitter electrode 302 of the semiconductor element 3 from the wires 44B having a wire diameter of 400 μm to the wires 44A having a wire diameter of 200 μm and doubling the number of wires, the bonding area can be increased. However, as will be described below with reference to FIGS. 7 to 9 , simply selecting wires having a smaller wire diameter to increase the bonding area may not necessarily increase the surge energy resistance of the semiconductor element 3.

[0033] FIG. 7 is a graph illustrating the relationship between the number of wires for each wire diameter and surge energy withstand capability. FIG. 8 is a graph illustrating the relationship between the number of junctions for each wire diameter and surge energy withstand capability. FIG. 9 is a graph illustrating the relationship between the junction area for each wire diameter and surge energy withstand capability. The surge energy withstand capability for each bluff in FIGS. 7 to 9 is the product of the surge current withstand capability IFSM and the voltage VFSM. As described above, the surge current withstand capability IFSM is the maximum value of a non-repetitive forward surge current in a half cycle of a sine wave at a commercial frequency (pulse width tp = 10 ms), and the voltage VFSM is the value of the forward voltage Vf of the diode element when measuring the surge current withstand capability IFSM.

[0034] As can be seen from the graphs of Figures 7 to 9, whether the wire 44A with the first wire diameter (200 μm) is joined to the emitter electrode 302 of the semiconductor element 3 or the wire 44B with the second wire diameter (400 μm) is joined to the emitter electrode 302 of the semiconductor element 3, the surge energy resistance increases as the number of wires, the number of joining points, and the joining area increase.

[0035] However, for example, the surge energy withstand capability when eight wires 44A of the first wire diameter are joined to the emitter electrode 302 of the semiconductor element 3 is smaller than the surge energy withstand capability when four wires 44A of the first wire diameter are joined to the emitter electrode 302 of the semiconductor element 3. When eight wires 44A of the first wire diameter are joined to the emitter electrode 302 of the semiconductor element 3, the joining area is 2.74 mm ２ The bonding area (2.584 mm ) when four wires 44B having the second wire diameter are bonded to the emitter electrode 302 of the semiconductor element 3 is ２ However, in the graph of FIG. 9, the bonded area of ​​the wire with a wire diameter of 200 μm is 2.74 mm ２ The surge energy withstand capacity in this case is 2.584 mm2 for a wire with a wire diameter of 400 μm. ２ When ten wires 44A of the first wire diameter are bonded to the emitter electrode 302 of the semiconductor element 3, the bonding area of ​​the emitter electrode 302 is larger than when five wires 44B of the second wire diameter are bonded to the emitter electrode 302 of the semiconductor element 3, but the surge energy resistance can be approximately the same. In contrast, when twelve wires 44A of the first wire diameter are bonded to the emitter electrode 302 of the semiconductor element 3, the bonding area of ​​the emitter electrode 302 is 3.876 mm 2 when compared to when six wires 44B of the second wire diameter are bonded to the emitter electrode 302 of the semiconductor element 3. ２ From 4.08 mm ２ Therefore, the dimensions (Y direction x X direction) of the exposed region ER of the emitter electrode 302 of the semiconductor element 3 are 5.0 x 5.0 mm ２In this case, joining twelve wires 44A having the first wire diameter to the emitter electrode 302 can increase the surge energy tolerance compared to joining wires 44B having the second wire diameter. The graphs illustrated in FIGS. 7 to 9 show that the surge energy tolerance when twelve wires 44A having the first wire diameter are joined to the emitter electrode 302 is approximately 10% greater than the surge energy tolerance when six wires 44B having the second wire diameter are joined. Specifically, as illustrated in FIG. 9, the maximum surge energy tolerance when wires 44B having the second wire diameter (400 μm) are joined is approximately 6.0 kW, whereas the maximum surge energy tolerance when wires 44A having the first wire diameter (200 μm) are joined is approximately 6.6 kW.

[0036] The dimensions (Y direction x X direction) of the exposed region ER of the emitter electrode 302 are 5.0 x 5.0 mm ２ In this case, the number of wires 44B with a wire diameter of 400 μm that can be joined to the emitter electrode 302 can be a maximum of 6 to 7, as described above. In the graph of Figure 7, the number of wires 44A with a wire diameter of 200 μm that can have a greater surge energy resistance than when seven wires 44B with a wire diameter of 400 μm can be joined can be 11 or more. The dimensions (Y direction x X direction) of the region ER are 5.0 x 5.0 mm ２ When eleven wires 44A having a wire diameter of 200 μm are joined to the emitter electrode 302 having a diameter of 1.5 μm, the number of junction points becomes 44 as shown in FIG. 8, and the surge energy resistance is greater than when seven wires 44B having a wire diameter of 400 μm are joined (when the number of junction points is 14). ２ When joining wires 44A with a wire diameter of 200 μm to emitter electrode 302, using 12 or more wires can increase the surge energy resistance, while using 11 wires can suppress an increase in the time required for wire bonding (takt time).

[0037] The dimensions (Y direction x X direction) of the exposed region ER of the emitter electrode 302 are 5.0 x 5.0 mm ２6, nine wires with a wire diameter of 300 μm can be bonded to the emitter electrode 302. In this example, each wire can be bonded to the emitter electrode 302 at three junctions, resulting in 27 junctions and a bonded area of ​​4.077 mm ２ An example of the surge energy withstand capability when nine wires each having a diameter of 300 μm are joined to the emitter electrode 302 of the semiconductor element 3 is shown by the black diamonds in FIGS. 7 and 9 , which is smaller than the surge energy withstand capability when twelve wires 44A each having a diameter of 200 μm are joined, but is greater than the surge energy withstand capability when six wires 44B each having a diameter of 400 μm are joined.

[0038] Considering the above points, in the semiconductor device 1 of the present embodiment, the surge energy tolerance of the semiconductor element 3 can be increased by selecting the number of wires such that the sum of the bonding areas when the wires 44A having a wire diameter of 200 μm are bonded to the emitter electrode 302 of the semiconductor element 3 is larger than the sum of the bonding areas at which the surge energy tolerance is maximized when a wire having a larger wire diameter than the wires 44A (e.g., a wire having a wire diameter of 400 μm or 300 μm) is bonded to the emitter electrode 302. Furthermore, when a wire having a wire diameter of 300 μm is bonded to the emitter electrode 302 of the semiconductor element 3, the surge energy tolerance of the semiconductor element 3 can be increased by selecting the number of wires such that the sum of the bonding areas is larger than the sum of the bonding areas at which the surge energy tolerance is maximized when a wire having a larger wire diameter than the wires 44A (e.g., a wire 44B having a wire diameter of 400 μm) is bonded to the emitter electrode 302. That is, in the semiconductor device 1 of this embodiment, the multiple wires connected to the emitter electrode 302 of the semiconductor element 3 include wires of a first wire diameter, and are selected so that the sum of the bonding areas of the emitter electrode 302 is greater than the sum of the bonding areas at which the surge energy tolerance is maximized when a wire of a second wire diameter that is thicker than the first wire diameter is bonded to the emitter electrode.

[0039] The relationship between the wire diameter and surge energy resistance described above with reference to FIGS. 6 and 7 to 9 is as follows: when the dimensions (Y direction×X direction) of the exposed region ER of the emitter electrode 302 are 5.0×5.0 mm ２ The above-described relationship can be interpreted as a relationship that is independent of the dimensions of the exposed region ER of the emitter electrode 302 by converting it into the number of junctions and the junction area per unit area of ​​the emitter electrode 302.

[0040] FIG. 10 is a graph illustrating the relationship between the number of wires per unit area and surge energy withstand for each wire diameter. FIG. 11 is a graph illustrating the relationship between the number of junctions per unit area and surge energy withstand for each wire diameter. FIG. 12 is a graph illustrating the relationship between the junction area per unit area and surge energy withstand for each wire diameter. The horizontal axes in the graphs of FIGS. 10, 11, and 12 are plotted against the dimensions of the exposed region ER of the emitter electrode 302 (5.0×5.0 mm) based on the values ​​on the horizontal axis in the graphs of FIGS. 7, 8, and 9. ２ ) That is, the unit area is 1 mm ２ The "six wires" written on the top sides of the graphs in Figures 10 and 11 are intended to correspond to the values ​​when six wires 44B with a wire diameter of 400 µm are used in the graphs in Figures 7 and 8, respectively.

[0041] In the graph shown in Fig. 10, line Q1, which represents the relationship between the number of wires per unit area and surge energy withstand capability when wire 44A with a wire diameter of 200 µm is used, suggests that when the number of wires per unit area is 0.380 or more, the surge energy withstand capability is greater than the surge energy withstand capability (approximately 6.0 kW) when six wires 44B with a wire diameter of 400 µm are used. Also, line Q2, which represents the relationship between the number of junctions per unit area and surge energy withstand capability when wire 44A with a wire diameter of 200 µm is used, suggests that when the number of junctions per unit area is 0.153 or more, the surge energy withstand capability is greater than the surge energy withstand capability (approximately 6.0 kW) when six wires 44B with a wire diameter of 400 µm are used.

[0042] 12 with the graph of FIG. 10, when six wires 44B with a wire diameter of 400 μm are joined to the electrodes 302 of the semiconductor element 3, the surge energy withstand capacity is maximized (for example, about 6.0 kW). ２ When twelve wires 44A having a wire diameter of 200 μm are joined to the electrodes 302 of the semiconductor element 3, the electrode 1 mm ２ The contact area is larger.

[0043] Furthermore, in the graph shown in FIG. 12, a line Q3 showing the relationship between the bonded area per unit area and the surge energy withstand capacity when a wire with a wire diameter of 200 μm is used is ２ ) The bonding area per ２ When the bonding area per unit area is about 0.150 mm, the surge energy withstand capacity becomes larger than that when a wire with a wire diameter of 400 μm is used, as shown by the line Q4. ２ When the wire diameter is 200 μm and 300 μm, the surge energy withstand capability is larger when the wire diameter is 200 μm. That is, when a wire with a diameter of 200 μm or more and less than 400 μm is joined to the emitter electrode 302 of the semiconductor element 3, the surge energy withstand capability is larger when the wire diameter is 200 μm and 300 μm. ２ The bonding area per ２ More than 0.18 mm ２ If the wire diameter, number of wires, and number of junctions are set as follows, the electrode 1 mm ２ The point showing the relationship between the bonding area per unit area and the surge energy is within region S1, and the surge energy tolerance can be increased compared to when a wire with a wire diameter of 400 μm or more is bonded to the emitter electrode 302 of the semiconductor element 3. Note that region S1 in FIG. ２ The upper limit of the bonding area per ２ Any value less than or equal to 0.18 mm ２ The area may be any value above. ２The minimum value of the bonding area per unit area is a value (for example, 0.13 mm) that is greater than the maximum value (about 6.0 kW) of the actual measured values ​​of surge energy withstand capacity when a wire with a wire diameter of 400 μm is used on the line Q3 in FIG. ２ ) may also be used.

[0044] 12 suggests that the relationship between the bonded area per unit area and surge energy when a wire with a diameter of less than 200 μm is used is shown by a straight line Q5. ２ When the above values ​​are the same, the thinner the wire diameter, the greater the surge energy resistance. Note that reducing the wire diameter and increasing the number of bonding points increases the time (takt time) required to connect the emitter electrode 302 of the semiconductor element 3 to the wire, and increases the energy required for bonding, which may increase the manufacturing cost of the semiconductor device 1. Therefore, it is preferable to determine the wire diameter and bonding area per unit area within the ranges of regions S1 and S2 in FIG. 12 , which are set based on the surge energy resistance required for the semiconductor device 1.

[0045] In a semiconductor device 1 applied to a power conversion device, the switching operation of switching elements such as IGBT elements in the semiconductor element 3 is high speed, and therefore high surge currents and surge voltages may occur suddenly (for example, at the start of operation, etc.). If the suddenly occurring surge current or surge voltage exceeds an expected value (rated value), the semiconductor element 3 will be destroyed, making it impossible to supply power to a load connected to the power conversion device (for example, a motor for a vehicle, elevator, etc.). For this reason, the semiconductor device 1 is required to have as high a surge energy tolerance as possible for the semiconductor element 3.

[0046] In the semiconductor device described in Patent Document 1, the portion of a wire between two junctions is aligned with the surface of the emitter electrode of the semiconductor element 3, thereby reducing the wiring length (resistance) of the portion between the junctions and increasing the surge current resistance. However, the semiconductor device described in Patent Document 1 does not determine the optimal wire diameter by comparing the relationship between the junction area and the surge current resistance calculated for each wire diameter. Therefore, as described above with reference to Figures 7 to 9, reducing the wire diameter may result in a decrease in the surge current resistance. Furthermore, the semiconductor device described in Patent Document 2 bonds multiple wires to the electrodes of the semiconductor element in a non-uniform distribution, making it difficult to increase the junction area and increase the surge current resistance. In contrast, the semiconductor device 1 of the present embodiment can determine the optimal wire diameter that increases the surge energy resistance by comparing the relationship between the junction area and the surge energy resistance calculated for each wire diameter.

[0047] In the semiconductor device 1 of this embodiment, the wire diameter of the wire bonded to the emitter electrode 302 of the semiconductor element 3 is not limited to the above-described 200 μm or 300 μm. The wire diameter may be, for example, 100 μm, 150 μm, 250 μm, etc. The number of junctions of a single wire with the emitter electrode 302 of the semiconductor element 3 can be changed depending on the combination of the dimensions of the exposed region ER of the emitter electrode 302 and the wire diameter. For example, the number of junctions of a wire 44B with the emitter electrode 302 having a wire diameter of 400 μm may be three or more. Furthermore, the junctions of adjacent wires may be aligned in a direction different from the wire arrangement direction (X direction) as illustrated in FIGS. 4A and 4B . For example, the junctions of adjacent wires may be offset in the wire extension direction (Y direction) by a distance that is a non-integer multiple (e.g., ½) of the distance between the junctions of a single wire (e.g., the distance L1 in FIG. 4B ). Furthermore, the wires bonded to the emitter electrode 302 of one semiconductor element 3 are not limited to those having the same wire diameter. For example, the wires may include a wire with a diameter of 200 μm and a wire with a diameter of 400 μm. Furthermore, the wires bonded to the emitter electrode 302 of one semiconductor element 3 may have different wire diameters from the wires bonded to the third electrode (gate electrode).

[0048] In the semiconductor device 1 of the present embodiment, a semiconductor element including a switching element such as an IGBT element and a semiconductor element including a diode element such as an FWD element may be connected in parallel by a conductor pattern on a wiring board and a bonding wire. The switching element of the semiconductor element is not limited to an IGBT element, and may be, for example, a power metal oxide semiconductor field effect transistor (MOSFET) element, a bipolar junction transistor (BJT) element, or the like. When the switching element is a power MOSFET, the collector and emitter of the IGBT element described above may be replaced with the drain and source, and the auxiliary emitter with the auxiliary source. Furthermore, the diode element connected in anti-parallel to the switching element may be, for example, a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a merged PN Schottky diode (MPS), a PN diode, or the like. The semiconductor element is not limited to one formed using silicon (Si), but may be one formed using a wide band gap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), diamond, etc. The semiconductor device 1 may include a semiconductor element other than the switching element and the diode element.

[0049] In the above-described embodiment, the emitter electrode 302 of the switching element (IGBT element) of the semiconductor element 3 is connected to a plurality of wires. However, the electrode of the semiconductor element 3 to which the plurality of wires are connected is not limited to this. For example, the semiconductor element 3 may be disposed so that the surface on which the emitter electrode 302 and the gate electrode 303 are formed faces the wiring board 2. In this case, the electrode of the semiconductor element 3 to which the plurality of wires are connected may be the collector electrode of the IGBT element. Furthermore, if the semiconductor element on which the switching element is formed and the semiconductor element on which the diode element is formed are separate semiconductor elements, the above-described plurality of wires may be connected to, for example, the electrodes of the semiconductor element on which the diode element is formed. Furthermore, if the switching element of the semiconductor element 3 is a power MOSFET element, the electrode 302 of the semiconductor element 3 connected to the wire 41 or 44 (see FIG. 1 ) may be a source electrode.

[0050] The semiconductor device 1 according to the above-described embodiment is not limited to a specific application, but may be applied to high-output power conversion devices, such as industrial power conversion devices, such as inverter devices that drive motors in elevators, escalators, building air conditioning systems, etc., and power conversion devices for vehicles. The vehicle may be, for example, an electric vehicle that drives the wheels with a motor, or a hybrid vehicle that uses power from an internal combustion engine in addition to a motor. The vehicle is not limited to a four-wheeled vehicle, but may also be a two-wheeled vehicle, a railroad car, etc.

[0051] The features of the above-described embodiment are summarized below. The semiconductor device according to the above-described embodiment includes a semiconductor element and a plurality of wires joined to electrodes exposed on a surface of the semiconductor element, the plurality of wires including wires having a first wire diameter, and a first diameter of the electrodes of the semiconductor element. ２ The sum of the bonding areas between the electrode and the plurality of wires is 0.123 mm ２ That's all.

[0052] In the semiconductor device according to the above embodiment, the wires having the first wire diameter have a distance between joints of 1.1 mm or less.

[0053] In the semiconductor device according to the above embodiment, the wire having the first wire diameter is joined to the electrode at a plurality of joining points, and a loop spaced apart from the electrode is formed between the joining points.

[0054] In the semiconductor device according to the above embodiment, ２ The sum of the bonding areas between the electrode and the plurality of wires is 0.13 mm ２ That's all.

[0055] In the semiconductor device according to the above embodiment, the first wire diameter is 200 μm or 300 μm.

[0056] In the semiconductor device according to the above embodiment, the semiconductor element is formed of a semiconductor substrate made of any one of silicon, silicon carbide, and gallium nitride, and the electrode of the semiconductor element is an emitter electrode of an IGBT (Insulated Gate Bipolar Transistor) element or a source electrode of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) element.

[0057] The semiconductor device according to the above embodiment has a structure in which the electrode is ２ In this case, a first sum, which is the sum of the bonding areas between the electrode and the multiple wires of the first wire diameter, becomes larger than a second sum, which is the sum of the bonding areas between the electrode and the multiple wires of a second wire diameter thicker than the first wire diameter, at which the surge energy resistance is at its maximum value.

[0058] The semiconductor device according to the above embodiment has a structure in which the electrode is ２ In this case, when the first sum, which is the sum of the bonding areas between the electrode and the multiple wires of the first wire diameter, and the second sum, which is the sum of the bonding areas between the electrode and the multiple wires of a second wire diameter that is thicker than the first wire diameter, are the same, a semiconductor element having an electrode bonded with the multiple wires of the first wire diameter has a greater surge energy resistance than a semiconductor element having an electrode bonded with the multiple wires of the second wire diameter.

[0059] The present invention is not limited to the above-described embodiments, and may be variously modified, substituted, or altered without departing from the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way due to technological advances or other derived technologies, it may be implemented using that method. Therefore, the claims cover all embodiments that may fall within the scope of the technical idea.

[0060] As described above, the present invention has the effect of increasing the surge energy resistance of semiconductor elements in semiconductor devices and preventing the semiconductor elements from being destroyed by a suddenly generated high current, and is particularly useful when applied to semiconductor devices for industrial or vehicle use used as power conversion devices.

[0061] This application is based on Japanese Patent Application No. 2024-091877, filed on June 6, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor element and a plurality of wires joined to electrodes exposed on a surface of the semiconductor element, the plurality of wires including wires having a first wire diameter, the plurality of wires being joined to electrodes of the semiconductor element within 1 mm ２ The sum of the bonding areas between the electrode and the plurality of wires is 0.123 mm ２ That is the semiconductor device.

2. The semiconductor device according to claim 1, wherein the wires of said first wire diameter have a spacing between joints of 1.1 mm or less.

3. The semiconductor device according to claim 2, wherein said wire of said first wire diameter is joined to said electrode at a plurality of joining points, and a loop spaced apart from said electrode is formed between said joining points.

4. 1 mm of the electrode of the semiconductor element ２ The sum of the bonding areas between the electrode and the plurality of wires is 0.13 mm ２ 4. The semiconductor device according to claim 3.

5. The semiconductor device according to claim 4, wherein the first wire diameter is 200 μm or 300 μm.

6. The semiconductor device according to claim 5, wherein the semiconductor element is formed from a semiconductor substrate of any one of silicon, silicon carbide, and gallium nitride, and the electrode of the semiconductor element is an emitter electrode of an IGBT (Insulated Gate Bipolar Transistor) element or a source electrode of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) element.

7. 1 mm of the electrode ２ 7. The semiconductor device according to claim 6, wherein a first sum, which is the sum of the bonding areas between the electrode and the plurality of wires of the first wire diameter, is greater than a second sum, which is the sum of the bonding areas between the electrode and the plurality of wires of a second wire diameter thicker than the first wire diameter, at which the surge energy resistance is at its maximum.

8. 1 mm of the electrode ２ 8. The semiconductor device according to claim 7, wherein, when the first sum, which is the sum of the bonding areas between the electrode and the plurality of wires having the first wire diameter, and the second sum, which is the sum of the bonding areas between the electrode and the plurality of wires having a second wire diameter that is thicker than the first wire diameter, are the same, a semiconductor element having the electrode bonded with the plurality of wires having the first wire diameter has a higher surge energy tolerance than a semiconductor element having the electrode bonded with the plurality of wires having the second wire diameter.