Switching control circuit and semiconductor device

Abstract

The present invention provides a switching control circuit that includes a power supply-side first switching element and a ground-side second switching element connected in series, and a freewheeling diode connected in parallel to the first switching element, in which the switching control circuit switches the second switching element, which constitutes a load driving circuit for driving a load, wherein: the switching control circuit additionally includes a charging circuit that, when a drive signal reaches a first level, charges the capacitance of a control electrode of the second switching element for a first period with a first current which increases as the current flowing after a sufficient amount of time has elapsed from the beginning of the on period of the second switching element increases, then charges the capacitance with a second current smaller than the first current for a second period, and an off circuit for turning off the second switching element when the drive signal reaches a second level; and the second period includes a period in which a reverse recovery current flows through the freewheeling diode when the load current flowing through the load is maximized.

Description

Switching control circuit and semiconductor device

[0001] The present invention relates to a switching control circuit and a semiconductor device.

[0002] In a general voltage-driven switching control circuit, the gate resistance of the switching element is adjusted to adjust power loss and surge voltage.

[0003] Furthermore, a current-driven switching control circuit is known as a switching control circuit that improves the trade-off between power loss and surge voltage (see, for example, Patent Document 1).

[0004] JP 2016-073052 A

[0005] However, the invention described in Patent Document 1 has the problem of being complicated and expensive, since it requires a conversion circuit such as an A / D converter.

[0006] The present invention has been made in view of the above-mentioned problems, and has an object to provide a switching control circuit that can improve the relationship between power loss and surge voltage with a simple configuration.

[0007] A first aspect that achieves the above object is a switching control circuit that switches the second switching element of a load drive circuit that drives a load, the switching control circuit including a first switching element on the power supply side and a second switching element on the ground side that are connected in series, and a freewheeling diode that is connected in parallel to the first switching element, the switching control circuit including: a charging circuit that, when a drive signal reaches a first level, charges a capacitance of a control electrode of the second switching element for a first period with a first current that increases as a current that flows after a sufficient amount of time has passed from the start of an on period of the second switching element increases, and then charges the capacitance for a second period with a second current that is smaller than the first current; and an off circuit that turns off the second switching element when the drive signal reaches a second level, the second period including a period during which a reverse recovery current flows through the freewheeling diode when the load current flowing through the load is at its maximum.

[0008]

[0013] A second aspect of the present invention is a semiconductor device including a load drive circuit for driving a load, the load drive circuit including a first switching element on a power supply side, a second switching element on a ground side, and a freewheeling diode connected in parallel to the first switching element, a resistor for generating a voltage corresponding to the current of the second switching element, and a switching control circuit for switching the second switching element, wherein the switching control circuit includes: a charging circuit for charging a capacitance of a control electrode of the second switching element for a first period with a first current that increases as the voltage of the resistor increases, when a drive signal reaches a first level, and then charging the capacitance for a second period with a second current that is smaller than the first current, and an off circuit for turning off the second switching element when the drive signal reaches a second level, the second period including a period during which a reverse recovery current flows through the freewheeling diode when the load current is at a maximum. Other features of the present invention will become apparent from the description of this specification.

[0009] According to the present invention, it is possible to provide a switching control circuit that can improve the relationship between power loss and surge voltage with a simple configuration.

[0010] 1 is a diagram illustrating the configuration of a power module 10 according to an embodiment and a general power module 50; FIG. 2 is a diagram illustrating the configuration of a general voltage-driven LVIC 60; FIG. 3 is a diagram illustrating numerical simulation results for the voltage-driven LVIC 60; FIG. 4 is a diagram illustrating an example of the configuration of an LVIC 22 according to an embodiment; FIG. 5 is a diagram illustrating a low current output circuit 25 according to an embodiment; FIG. 6 is a diagram illustrating a high current output circuit 27 according to an embodiment; FIG. 7 is a diagram illustrating an example of the configuration of a sample-and-hold circuit 44; FIG. 8 is a diagram illustrating the operation of a charging circuit 23 according to an embodiment; ＳＥ Current I Ｃ Dependency and temperature dependence, current I Ｇ Current I Ｃ1 is a diagram illustrating power supply dependency and temperature dependency. FIG. 1 is a diagram illustrating switching by the LVIC 22 of an embodiment. FIG. 2 is a diagram illustrating switching by the LVIC 22 of an embodiment. FIG. 3 is a diagram illustrating switching by the LVIC 22 of an embodiment. FIG. 4 is a diagram illustrating switching by the LVIC 22 of an embodiment. FIG. 5 is a diagram illustrating periods T1 and T2. FIG. 6 is a diagram illustrating periods T1 and T2. A numerical simulation result of the LVIC 22 of an embodiment and the LVIC 60 of the comparative example. A numerical simulation result of the LVIC 22 of an embodiment and the LVIC 60 of the comparative example. A numerical simulation result of the LVIC 22 of an embodiment and the LVIC 60 of the comparative example. A numerical simulation result of the LVIC 22 of an embodiment and the LVIC 60 of the comparative example.

[0011] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to Japanese Patent Application No. 2024-096758, filed on June 14, 2024, the contents of which are incorporated by reference.

[0012] At least the following matters will become clear from the description of this specification and the accompanying drawings.

[0013] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. The same or equivalent components, members, etc. shown in each drawing are designated by the same reference numerals, and redundant explanations will be omitted where appropriate.

[0014] 1 is a diagram showing the configuration of a power module 10 (corresponding to a "semiconductor device") according to one embodiment of the present invention. The power module 10 is a semiconductor device that drives an inductor 11, which is, for example, a load, and includes a half-bridge circuit 20, an HVIC 21, an LVIC 22, and terminals IN1, IN2, COM, P, U, N, and S.

[0015] The half-bridge circuit 20 drives an inductor 11 (described later) which is a load. The half-bridge circuit 20 includes IGBTs (Insulated Gate Bipolar Transistors) 30 and 31 and FWDs (Free Wheeling Diodes) 32 and 33. The half-bridge circuit 20 corresponds to a "load drive circuit."

[0016] The IGBT 30 is an upper arm switching element provided on the power supply side, and the IGBT 31 is a lower arm switching element provided on the ground side and connected in series to the IGBT 30. The IGBT 30 corresponds to the "first switching element," and the IGBT 31 corresponds to the "second switching element."

[0017] The FWD 32 is a freewheeling diode connected in parallel to the IGBT 30 and circulating the energy of the inductor 11. The cathode of the FWD 32 is connected to the collector electrode of the IGBT 30, and the anode is connected to the emitter electrode of the IGBT 30.

[0018] The FWD 33 is a free wheel diode connected in parallel to the IGBT 31. The cathode of the FWD 33 is connected to the collector electrode of the IGBT 31, and the anode is connected to the emitter electrode of the IGBT 31.

[0019] The FWD 32 and the FWD 33 may be formed as parts of the IGBT 30 and the IGBT 31, respectively. In this case, the IGBT 30 and the IGBT 31 may be, for example, RC-IGBTs.

[0020] A predetermined power supply voltage is applied to terminal P, and an inductor 11, which serves as a load, is provided between terminal P and terminal U. Therefore, the inductor 11 and the half-bridge circuit 20 form a chopper circuit. The inductor 11 corresponds to the "load."

[0021] A collector current I flows through the IGBT 31 between the terminal S and the ground. Ｃ A resistor 13 is connected to detect the voltage.

[0022] The IGBT 31 described above is an element including a large-sized IGBT for controlling the inductor current IL and a small-sized IGBT for current detection, and a current from the current detection IGBT is supplied to the resistor 13. Therefore, V according to the inductor current IL and the current flowing through the IGBT 31, which is a load, is ＳＥ is generated at the resistor 13. In this embodiment, the voltage generated at the resistor 13 is referred to as "voltage V ＳＥ "

[0023] Here, no load is connected between the terminal U and the terminal N, but if an inductor is connected between the terminal U and the terminal N, the FWD 33 operates as a freewheeling diode.

[0024] The HVIC 21 (High Voltage Integrated Circuit) is an integrated circuit for switching the upper arm IGBT 30. The HVIC 21 switches the IGBT 30 based on, for example, a drive signal Vdr1 input from a microcomputer (not shown) via a terminal IN1.

[0025] The LVIC 22 (Low Voltage Integrated Circuit) is an integrated circuit for switching the lower arm IGBT 31. The LVIC 22 switches the IGBT 31 based on, for example, a drive signal Vdr2 input from a microcomputer (not shown) via a terminal IN2.

[0026] The terminal COM is a terminal to which a ground voltage is applied, and is connected to, for example, a housing (not shown) of the power module 10 or the like.

[0027] <<Switching of IGBT 31 by General Voltage-Driven LVIC>> Here, switching of the IGBT 31 by a general voltage-driven LVIC 60 will be described with reference to FIGS.

[0028] 2 is a diagram illustrating the configuration of the LVIC 60 in the general power module 50 shown in FIG. 1. The LVIC 60 includes a buffer circuit B1 and a resistor R ＧＯＮ In the following, switching of the IGBT 31 in the lower arm will be particularly described.

[0029] For example, when the drive signal Vdr2 becomes high level (hereinafter referred to as "H level"), the gate electrode of the IGBT 31 is connected to the resistor R ＧＯＮ A predetermined voltage Vcc (for example, 15 V) is applied via

[0030] On the other hand, when the drive signal Vdr2 becomes low level (hereinafter referred to as "L level"), the gate electrode of the IGBT 31 is connected to the resistor R ＧＯＮ A ground voltage (here, "0 V") is applied via

[0031] 3A and 3B are diagrams showing the results of a numerical simulation of the LVIC 60. The horizontal axis of FIG. 3A represents time, and the vertical axis represents the collector-emitter voltage V ＣＥ , the gate-emitter voltage V of the IGBT 31 ＧＥ , the collector current I flowing through the IGBT 31 Ｃ , the voltage V between both ends of the FWD 32 ＡＫ is.

[0032] Also, FIG. 3 shows the resistance R ＧＯＮ The results are shown for two conditions (large and small) for the resistance R ＧＯＮ The solid line shows the results for small resistance R ＧＯＮ The dashed line shows the results for the large

[0033] In addition, the resistance R ＧＯＮ When is small, the drive signal Vdr2 becomes H level at the time 0.0E+00 [sec], and the resistor R ＧＯＮ When is large, the drive signal Vdr2 becomes H level at the time 1.0E+00 [sec].

[0034] The current I in FIG. Ｃ As can be seen, the resistance R ＧＯＮ The smaller the value, the greater the current that flows through the load after the drive signal Vdr2 becomes H level (the current I Ｃ In this example, it is 600 A.) ＧＯＮ The smaller the value, the faster the switching speed.

[0035] The switching loss derived from the results of FIG. 3(a) is ＧＯＮ is small, it is 25.2 mJ, and the resistance R ＧＯＮ When the resistance R ＧＯＮ The larger the value, the larger the switching loss.

[0036] Also, the voltage V in FIG. ＡＫ As can be seen, the resistance R ＧＯＮ Surge voltage when is small (voltage V ＡＫ The peak value of the resistance R ＧＯＮ When the resistance R ＧＯＮ The smaller the voltage, the larger the surge voltage.

[0037] As the above results show, in switching by the LVIC 60, the resistance R ＧＯＮ If the resistance R is reduced, the switching loss will be reduced but the surge voltage will be increased. ＧＯＮ Increasing V V reduces the surge voltage but increases the switching loss. In other words, in a typical voltage-driven LVIC 60, there is a trade-off between the switching loss and the surge voltage.

[0038] 4 is a diagram showing an example of the configuration of the LVIC 22 (corresponding to a "switching control circuit") of this embodiment. The LVIC 22 is an integrated circuit that turns the IGBT 31 on and off based on the drive signal Vdr2 while improving the trade-off between switching loss and surge voltage.

[0039] 2, the LVIC 22 is a current-driven LVIC (details will be described later). The LVIC 22 includes a buffer circuit B2, a charging circuit 23, and an off circuit 24.

[0040] The buffer circuit B2 receives the drive signal Vdr2 and outputs a signal S1, the logic level of which is equal to that of the drive signal Vdr2, to the charging circuit 23 and the off circuit 24. The charging circuit 23 is a circuit for charging the capacitance of the gate electrode of the IGBT 31 in order to turn on the IGBT 31 in response to the drive signal Vdr2. At this time, the charging circuit 23 supplies a gate current I Ｇ is supplied to the gate electrode of the IGBT 31.

[0041] 4, the charging circuit 23 includes a low current output circuit 25, a timer circuit 26, and a high current output circuit 27. The charging circuit 23 will be described with reference to FIGS.

[0042] FIG. 5 is a diagram for explaining the low current output circuit 25. FIG. 6 is a diagram for explaining the high current output circuit 27. FIG. 7 is a diagram showing an example of the configuration of the sample-and-hold circuit 44. FIG. 8 is a diagram for explaining the operation of the charging circuit 23. In FIG. 8, the horizontal axis represents time, and the vertical axis represents the drive signal Vdr2, signals S1 and S2 (described in detail later), and the gate current I of the IGBT 31. Ｇ is.

[0043] The low current output circuit 25 receives a current I from a high current output circuit 27 (described later). ＧＯＮ２ A smaller current I ＧＯＮ１ The low current output circuit 25 receives the signal S1 and a predetermined voltage V, and outputs a current I ＧＯＮ１ Output.

[0044] As shown in FIG. 5, the low current output circuit 25 includes transistors T11 to T13, m transistors T14, and an operational amplifier OP1.

[0045] The transistor T11 controls the current I output from the low current output circuit 25 based on the signal S1. ＧＯＮ１ The transistor T11 is a switch for switching between setting the value of 0 or a predetermined value (described later). In this embodiment, the transistor T11 is a p-channel MOS transistor. The transistor T11 is connected between a power supply and the gate electrode of a transistor T12 (described later).

[0046] The transistors T12 and T13, the resistor 41, and the operational amplifier OP1 generate a current I ＧＯＮ１ The current I ＲＥＦ１ In this embodiment, the transistors T12 and T13 are p-channel MOS transistors.

[0047] The transistors T12 and T13 and the resistor 41 are connected in series in this order between the power supply and the ground. The resistance value of the resistor 41 is R ＲＥＦ１ and the resistor 41 is connected to a voltage V ＲＥＦ１ occurs.

[0048] Here, the operational amplifier OP1 controls the transistor T13 so that the voltage of the source electrode of the transistor T13 coincides with a predetermined voltage V1.

[0049] A predetermined voltage V1 is applied to the non-inverting input terminal of the operational amplifier OP1. The inverting input terminal of the operational amplifier OP1 is connected between the transistor T13 and the resistor 41. The output terminal of the operational amplifier OP1 is connected to the gate electrode of the transistor T13.

[0050] As a result, when the signal S1 input to the transistor T11 is at an L level, the current I ＲＥＦ１ The value of V1 / R ＲＥＦ１ On the other hand, when the signal S1 is at H level, the current I ＲＥＦ１ The value of is zero.

[0051] The m transistors T14 are connected to the current I ＧＯＮ１ The value of I ＲＥＦ１ In this embodiment, the m transistors T14 are p-channel MOS transistors.

[0052] The m transistors T14 are connected in parallel with one another, and each of the m transistors T14 has a drain electrode connected to a power supply and a gate electrode connected to the gate electrode of the transistor T12.

[0053] Therefore, when the signal S1 input to the transistor T11 is at L level, the transistor T12 is in a diode-connected state, and the transistor T12 and the m number of transistors T14 form a current mirror circuit. As a result, the output current I ＧＯＮ１ The value of is m×I ＲＥＦ１ This becomes:

[0054] As a result, when the signal S1 input to the transistor T11 is at an L level, the output current I ＧＯＮ１ The value of is m×I ＲＥＦ１ On the other hand, when the signal S1 is at the H level, the output current I ＧＯＮ１ The value of is zero.

[0055] The predetermined voltage V1 and the number m of transistors 14 are ＧＯＮ１ The value of may be adjusted appropriately to a desired value.

[0056] 4 is a circuit that outputs a signal S2 that defines periods T1 to T3 shown in Fig. 8 based on the drive signal Vdr2 to the high current output circuit 27. The periods T1 to T3 will be described in detail later.

[0057] Specifically, when the signal S1 goes low, the timer circuit 26 outputs a low-level signal S2 for a period T1. When the period T1 ends, the timer circuit 26 outputs a high-level signal S2 for a period T2. When the period T2 ends, the timer circuit 26 outputs a low-level signal S2 for a period T3.

[0058] The high current output circuit 27 outputs a current I ＧＯＮ２ As will be described in detail later, when the high current output circuit 27 receives an L-level signal S2 from the timer circuit 26 for a period T1, the high current output circuit 27 outputs a current value I １ Current I ＧＯＮ２ When the timer circuit 26 inputs the H-level signal S2 for the period T2, the high current output circuit 27 outputs a current value I ２ Current I ＧＯＮ２ When the timer circuit 26 inputs the signal S3 at an L level for a period T3, the high current output circuit 27 outputs a current value I ３Current I ＧＯＮ２ Output.

[0059] 6, the high current output circuit 27 differs from the low current output circuit 25 in that the number of transistors T24 is n, and that the high current output circuit 27 further includes an amplifier circuit 43 and a sample-and-hold circuit 44. In the following, a description of the parts that overlap with the low current output circuit 25 will be omitted, and the description will focus on the differences.

[0060] The amplifier circuit 43 is a circuit that amplifies, by a predetermined gain, a voltage corresponding to a current that flows after a sufficient time has elapsed from the beginning of the on-period of the IGBT 31. Note that the "current that flows after a sufficient time has elapsed from the beginning of the on-period of the IGBT 31" is, for example, a current that becomes substantially constant after the IGBT 31 is turned on, and is also referred to as a "load current." Note that in this embodiment, after a sufficient time has elapsed since the IGBT 31 was turned on, the current that flows through the IGBT 31 increases and then decreases to become substantially constant (for example, a current of 600 A shown by the solid line in FIG. 3A).

[0061] The amplifier circuit 43 amplifies the voltage V applied to the resistor 13 (FIG. 4). ＳＥ is used as input, and the amplified voltage V ＳＥ１ is output to the sample-and-hold circuit 44.

[0062] FIG. 9 shows the voltage V ＳＥ (Figure 4) current I Ｃ Dependency and temperature dependence, current I Ｇ Current I Ｃ 1 is a diagram illustrating the dependence of the voltage V ＳＥ is the current I of the IGBT 31 generated in the resistor 13 Ｃ The voltage corresponds to

[0063] As shown in FIG. 9(a), the voltage V ＳＥ Since the resistor 13 has a positive temperature coefficient, the voltage V increases as the temperature increases. ＳＥ is also the current I Ｃ The amplifier circuit 43 has a characteristic that the larger the voltage V ＳＥ Current I Ｃ Depending on the dependence and temperature dependence, the voltage V ＳＥ By amplifying the current I ＧWhereas, voltage V ＳＥ and the same current I Ｃ Dependence and temperature dependence can be given.

[0064] The sample-and-hold circuit 44 is a circuit that samples and holds the output of the amplifier circuit 43 based on a predetermined timing.

[0065] For example, the sample-and-hold circuit 44 samples the output of the amplifier circuit 43 at the timing when the IGBT 31 switches from on to off, and holds the sampled output until the next period when the IGBT 31 is on.

[0066] The sample-and-hold circuit 44 generates a voltage V ＳＥ１ and is configured to include a delay circuit 45, an edge detection circuit 46, a switch 47, a capacitor 48, and a unity gain buffer 49 (FIG. 7).

[0067] The delay circuit 45 and the edge detection circuit 46 are connected to the voltage V ＳＥ１ Specifically, the delay circuit 45 delays the drive signal Vdr2 by a "predetermined time Tx" and outputs the signal Vd. The "predetermined time Tx" delayed by the delay circuit 45 is, for example, the time from when the drive signal Vdr2 goes to "L" level to turn off the IGBT 31 until the IGBT 31 actually turns off. As will be described in detail later, by sampling the current of the IGBT 31 at such timing, the sample-and-hold circuit 44 generates a timing for sampling the load current I Ｃ You can get the maximum value of

[0068] The edge detection circuit 46 detects the falling edge of the signal Vd and outputs a pulse signal Vp to the switch 47 .

[0069] The switch 47 has a voltage V ＳＥ１ is applied to the capacitor 48, and the capacitor 48 is turned on only during the period when the pulse signal Vp is input. As a result, when the switch 47 is turned on, the voltage of the capacitor 48 becomes equal to the voltage V ＳＥ１ This becomes:

[0070] The unity gain buffer 49 converts the voltage on the capacitor 48 to a voltage VＳＥ２ It is a buffer circuit that outputs the voltage V ＳＥ２ An adjustment circuit (not shown) may be added to adjust the gain and offset of the amplifier.

[0071] The operation of the charging circuit 23 described above will be described with reference to Fig. 8. When the drive signal Vdr2 becomes one logic level (in this embodiment, it is "L level", and "one logic level" corresponds to "first level"), the charging circuit 23 first increases the gate current I Ｇ The value of I １ The capacitance of the gate electrode of the IGBT 31 is charged over a period T1 (FIG. 8).

[0072] At this time, since the signal S1 is at the L level, the current I output from the low current output circuit 25 is ＧＯＮ１ The value of is m×I ＲＥＦ１ Furthermore, since the signal S2 is also at the L level, the current I output from the high current output circuit 27 is ＧＯＮ２ The value of is n × I ＲＥＦ２ Therefore, the gate current I Ｇ The value of I １ is m × I ＲＥＦ１ + n × I ＲＥＦ２ is.

[0073] According to this embodiment, the gate current I Ｇ is the current that increases as the temperature increases. Ｇ is a current corresponding to the output of the amplifier circuit 43. The gate current I Ｇ is a current corresponding to the voltage held in the sample-and-hold circuit 44.

[0074] After the period T1, the charging circuit 23 supplies the gate current I Ｇ The value of I ２ The capacitance of the gate electrode of the IGBT 31 is charged over a period T2 (FIG. 8).

[0075] At this time, since the signal S1 is at the L level, the current I output from the low current output circuit 25 is ＧＯＮ１ The value of is m×I ＲＥＦ１ Furthermore, since the signal S2 is at the H level, the current I output from the high current output circuit 27 is ＧＯＮ２The value of is zero. Therefore, the gate current I Ｇ The value of I ２ is m × I ＲＥＦ１ That is, the gate current I Ｇ The value of I ２ I １ Smaller than.

[0076] After the period T2, the charging circuit 23 supplies the gate current I Ｇ The value of I ３ The capacitance of the gate electrode of the IGBT 31 is charged over a period T3.

[0077] At this time, since the signal S1 is at the L level, the current I output from the low current output circuit 25 is ＧＯＮ１ The value of is m×I ＲＥＦ１ Furthermore, since the signal S2 is also at the L level, the current I generated by the high current output circuit 27 is ＧＯＮ２ The value of is n × I ＲＥＦ２ Therefore, the gate current I Ｇ The value of I ３ is m × I ＲＥＦ１ + n × I ＲＥＦ２ and I in the period T1 １ is equal to.

[0078] Also, the gate current I Ｇ The value of I １ and I ３ The larger the current that flows after a sufficient time has elapsed from the beginning of the on-period of the IGBT 31, the larger I ２ In this embodiment, I ２ is set to a value at which the charging of the capacitance of the gate electrode of the IGBT 31 is substantially stopped during the period T2.

[0079] The gate electrode corresponds to the "control electrode." １ Gate current I Ｇ corresponds to the "first current". ２ Gate current I Ｇ corresponds to the "second current". ３ Gate current I Ｇ corresponds to the "third current."

[0080] The period T1 corresponds to the "first period." The period T2 corresponds to the "second period." The period T3 corresponds to the "third period." In this embodiment, the periods T1 and T3 are each set to be longer than the period T2.

[0081] The off circuit 24 in FIG. 4 turns off the IGBT 31 when the drive signal Vdr2 becomes the other logic level ("H level" in this embodiment, and the "other logic level" corresponds to the "second level").

[0082] The off circuit 24 includes a switch 28. When the drive signal Vdr2 goes high, the switch 28 becomes conductive and discharges the capacitance of the gate electrode of the IGBT 31, thereby turning the IGBT 31 off.

[0083] <<Switching of IGBT 31 by LVIC 22>> A detailed description will be given of switching of the IGBT 31 by the LVIC 22. Figures 10 to 14 are diagrams for explaining switching of the IGBT 31 by the LVIC 22 of this embodiment.

[0084] 10, the horizontal axis represents time, and the vertical axis represents the gate current I of the IGBT 31. Ｇ , the gate-emitter voltage V of the IGBT 31 ＧＥ , the voltage V across the FWD 32 ＡＫ , the collector-emitter voltage V of the IGBT 31 ＣＥ , the collector current I flowing through the IGBT 31 Ｃ is.

[0085] 11 to 14 show an equivalent circuit of the half-bridge circuit 20 during a period when the drive signal Vdr2 is at an L level. That is, the IGBT 30 of the upper arm is omitted because it is off. Also, the FWD 33 of the lower arm is omitted because the IGBT 31 is on and no current flows in a reverse bias state.

[0086] In addition, the wiring inductance is L Ｓ The DC voltage V applied to the half-bridge circuit 20 is shown as ＤＣ is shown.

[0087] FIG. 11 shows the time t ０From time t １ 8 is a diagram illustrating a state during a period from time t ０ is the time when the period T1 starts and charging of the capacitance of the gate electrode of the IGBT 31 starts. １ The capacitance of the gate electrode of the IGBT 31 is charged, and the voltage V between the gate and emitter of the IGBT 31 increases. ＧＥ is the threshold voltage V of the IGBT 31 ｔｈ This is the time when

[0088] During this period, a forward current I flows through the FWD 32. Ｌ Furthermore, since the IGBT 31 is off, the current Ic flowing through the IGBT 31 is substantially zero.

[0089] FIG. 12 shows the time t １ From time t ２ 8 is a diagram illustrating the state during the period from time t ２ is the time when the period T1 ends. As will be described later in detail, the end of the period T1 (here, time t ２ ) is set to the time when the current Ic reaches the current flowing through the inductor 11.

[0090] Time t １ From this point on, charging of the capacitance of the gate electrode of the IGBT 31 further progresses, and the voltage V between the gate and emitter of the IGBT 31 ＧＥ is the threshold voltage V ｔｈ Even during this period, the forward current I Ｌ is playing.

[0091] In addition, the current Ic flowing through the IGBT 31 increases, and the voltage V ＣＥ Here, the current I for charging the capacitance of the gate electrode of the IGBT 31 is １ The larger the current Ic is, the faster the voltage V ＣＥ This reduces the switching loss of the IGBT 31.

[0092] FIG. 13 shows the time t ２ From time t ３8 is a diagram illustrating a state during a period from the time T1 to the time T2 (period T2 in FIG. 8). This period corresponds to period T2. Period T2 is set to be shorter than period T1.

[0093] During this period, the voltage applied to the FWD 32 is switched in the reverse direction, and a reverse recovery current I ｒｒ This reverse recovery current I ｒｒ is added to the current Ic, and during the period when the IGBT 31 is on, ０ Current I after a sufficient time has passed Ｃ and a peak value appears during period T2.

[0094] Furthermore, the period T2 starts and the voltage V ＣＥ This is because the inductance L of the wiring increases as explained below. Ｓ This is due to the voltage drop.

[0095] First, in the period T1, a current I is supplied to charge the capacitance of the gate electrode of the IGBT 31. Ｃ As a result, the inductance L of the wiring during the period T1 Ｓ A voltage drop of occurs.

[0096] On the other hand, during the period T2, the charging of the capacitance of the gate electrode of the IGBT 31 is stopped, so that the current I Ｃ The increase in the inductance L of the wiring is slower than that in the period T1. Ｓ The voltage drop of the voltage V ＣＥ Therefore, the period T2 starts and the voltage drop of the voltage V ＣＥ increases.

[0097] In addition, the reverse recovery current I flowing through the FWD 32 ｒｒ Thus, the voltage V across the FWD 32 ＡＫ rises. Here, the voltage V ＡＫ The peak value of the surge voltage V ＡＫｐｅａｋ can be expressed by the following equation:

[0098] In this equation, the voltage V ＣＥAs described above, the voltage V increases during the period T2. ＣＥ From the above formula, the rise in surge voltage V ＡＫｐｅａｋ It acts to reduce

[0099] That is, by providing a period T2 in which the charging speed of the capacitance of the gate electrode of the IGBT 31 is reduced, the surge voltage V ＡＫｐｅａｋ can be reduced.

[0100] FIG. 14 shows the time t ３ From time t ４ 8 is a diagram illustrating a state during a period from time t ３ is the time when the period T3 starts, and time t ４ is the time when the period T3 ends. During this period, the current I Ｃ and voltage V ＡＫ remains at a steady value.

[0101] << Current for charging I １ Regarding >> In the switching control circuit of this embodiment, as described above, the current I for charging the capacitance of the gate electrode of the IGBT 31 during the period T1 is Ｇ (The current value is I １ ) is the current that flows after a sufficient time has elapsed from the beginning of the on-period of the IGBT 31 ("current I Ｃ The larger the steady-state value (also referred to as "constant value at which the current is approximately constant") of

[0102] Here, unlike this embodiment, if the current I Ｇ is the current I Ｃ The case where the constant value is set independent of the steady-state value of , and the effect of this embodiment will be described.

[0103] FIG. 15 shows the current I for charging the capacitance of the gate electrode of the IGBT 31. Ｇ is the current I Ｃ 1 is a diagram illustrating a period T1 and a period T2 when the current I is constant regardless of the steady-state value. Ｃ The steady-state values ​​are shown for 300 A (solid line) and 600 A (dashed line).

[0104] In this example, in either case, time t ０ In the period T1, in either case, the current I Ｃ begin to flow at roughly the same time and rise at roughly the same speed.

[0105] current I Ｃ If the steady-state value of is 300 A, the current I Ｃ The time when reaches a steady value is time t １ and at time t ０ From time t １ is set as the period T1 (shown as "T1 (300 A)" in FIG. 15). Meanwhile, the current I Ｃ If the steady-state value of is 600 A, the current I Ｃ The time when reaches a steady value is time t ２ and at time t ０ From time t ２ is set as the period T1 (shown as "T1 (600A)" in FIG. 15).

[0106] Also, in this example, the current I Ｃ When the steady-state value of is 300 A, the period during which the reverse recovery current flows is １ From time t ３ This period is set as period T2 (shown as "T2 (300 A)" in FIG. 15). On the other hand, the current I Ｃ When the steady-state value of is 600 A, the period during which the reverse recovery current flows is ２ From time t ４ This period is set as period T2 (shown as "T2 (600A)" in FIG. 15).

[0107] That is, the current I for charging the capacitance of the gate electrode of the IGBT 31 Ｇ The value of I １ is the current I Ｃ If the steady-state value of is assumed to be constant, the current I Ｃ The periods T1 and T2 must be set according to the steady-state value of

[0108] In this embodiment, the period T2 is set so as to include a period during which a reverse recovery current flows through the FWD 32 when the load current flowing through the inductor 11 reaches a maximum.

[0109] FIG. 16 is a diagram illustrating the period T1 and the period T2 in this embodiment. In this diagram, the current I Ｃ The steady-state values ​​of are 300 A and 600 A. In this example, the maximum value of the load current flowing through the inductor 11 is 600 A.

[0110] As described above, in this embodiment, the current I for charging the capacitance of the gate electrode of the IGBT 31 is Ｇ The value of I １ The larger the current that flows, the larger the

[0111] In the example of FIG. 16, the current I Ｃ When the steady-state value of Ｇ The value of I １ is the current I Ｃ When the steady state value is 300A, the value I １ (FIG. 16(a)). Ｃ When the steady-state value of is 600 A, the period during which the reverse recovery current flows through the FWD 32 is t １ From time t ２ In this embodiment, this period is set as period T2 (FIG. 16B).

[0112] As can be seen from FIG. 16, the current I Ｃ When the steady-state value of is 300 A, the period during which the reverse recovery current flows through the FWD 32 is included in the period T2 set as described above.

[0113] That is, in this embodiment, the current I Ｃ Regardless of the steady-state value of the period T1, the common periods T1 to T3 are set.

[0114] <<Numerical Simulation Results>> FIGS. 17 to 20 show the results of numerical simulations of the LVIC 22 of this embodiment and a typical voltage-driven LVIC 60 as a comparative example.

[0115] 17A shows the results of the simulation of the comparative example, and FIG. 17B shows the results of the simulation of this embodiment. In these figures, the horizontal axis represents time, and the vertical axis represents the current I Ｃ , voltage V ＣＥ , voltage V ＡＫ , voltage V ＧＥFIG. 18 summarizes the results of FIG.

[0116] The comparative example is a switching control circuit using the voltage-driven LVIC 60 shown in FIG. 2. Here, as shown in FIG. ＧＯＮ was set to 3.9 ohms.

[0117] In addition, in the comparative example, the gate-emitter voltage V ＧＥ is +15V, and the voltage V when turning off the IGBT31 ＧＥ was set to 0V.

[0118] In this embodiment, a current I for charging the capacitance of the gate electrode of the IGBT 31 is Ｇ The value of I １ was set to 3.92 [A], period T1 was set to 300 [nsec], and period T2 was set to 100 [nsec].

[0119] FIG. 18 shows the surge voltage V ＡＫｐｅａｋ and the switching loss E due to the IGBT 31 ＯＮ and the switching loss E due to the IGBT 31 ＯＮ and the switching loss E due to the FWD ｒｒ The combined switching loss E ＯＮ +E ｒｒ The results are shown.

[0120] According to this embodiment, the surge voltage V ＡＫｐｅａｋ was reduced by 48 V compared to the comparative example. ＯＮ The switching loss E ＯＮ +E ｒｒ was reduced by 41% compared to the comparative example.

[0121] That is, according to this embodiment, the surge voltage V ＡＫｐｅａｋ , switching loss E ＯＮ , switching loss E ＯＮ +E ｒｒ All of these can be improved.

[0122] FIG. 19 shows the surge voltage V ＡＫｐｅａｋ and switching loss EＯＮ +E ｒｒ 10 shows the results of a numerical simulation conducted to examine the dependency of the relationship between the period T1 and the frequency of the power supply voltage Vp and the power supply voltage Vt. In this figure, the comparative example is indicated by black circles, and the present embodiment is indicated by white circles.

[0123] In the comparative example (black circle), the resistance R ＧＯＮ The graph shows the results when the period T1 is changed from 2.2 [ohm] to 10 [ohm]. In this embodiment (white circles), the results are shown when the period T1 is changed from 260 [nsec] to 320 [nsec].

[0124] From the results of the comparative example, the surge voltage V ＡＫｐｅａｋ and switching loss E ＯＮ +E ｒｒ It can be seen that there is a trade-off relationship between

[0125] From the results of this embodiment, it can be seen that an improvement is achieved compared to the trade-off relationship in the comparative example when the period T1 is between 280 [nsec] and 320 [nsec].

[0126] FIG. 20 shows the surge voltage V ＡＫｐｅａｋ and switching loss E ＯＮ +E ｒｒ 10 shows the results of a numerical simulation that investigated the dependency of the relationship between the period T2 and the temperature of the battery 10. In this figure, the comparative example is shown by a black circle, and the present embodiment is shown by a white circle.

[0127] The comparative example (black circles) is the same as that in FIG. 19, and in this embodiment (white circles), the results are shown when the period T2 is changed from 60 [nsec] to 200 [nsec].

[0128] The results of this embodiment show that there is almost no effect on the results if the period T2 is between 60 [nsec] and 200 [nsec]. In other words, it is clear that strict setting of the period T2 is not necessary.

[0129] As described above, according to the power module 10 of this embodiment, the trade-off between the switching loss of the half-bridge circuit 20 and the surge voltage is improved.

[0130] Summary The LVIC 22 of the embodiment described above is a switching control circuit that switches the IGBT 31 of a load drive circuit that drives a load, including an IGBT 30 on the power supply side and an IGBT 31 on the ground side that are connected in series, and an FWD 32 that is connected in parallel to the IGBT 30. When the drive signal becomes one of the logical levels, a current I increases as the current that flows after a sufficient time has passed from the beginning of the on-period of the IGBT 31. １ After the capacitance of the gate electrode of the IGBT 31 is charged for a period T1, the current I １ A smaller current I ２ The circuit includes a charging circuit 23 that charges the capacitance over a period T2, and an off circuit 24 that turns off the IGBT 31 when the drive signal becomes the other logical level, and the period T2 includes a period during which a reverse recovery current flows through the FWD 32 when the load current flowing through the load becomes maximum.

[0131] According to this configuration, the capacitance of the gate electrode of the IGBT 31 is charged with a large current during the period T1. Ｃ increases rapidly until it reaches the load current. ＶＣＥ decreases rapidly, thus reducing switching losses.

[0132] Furthermore, during a period T2 immediately before the reverse recovery current flows through the FWD 32, the charging of the capacitance of the gate electrode of the IGBT 31 by the large current is stopped, and accordingly, the voltage V ＣＥ Therefore, the surge voltage is reduced. As a result, the relationship between switching loss and surge voltage is improved with a simple configuration.

[0133] In the LVIC 22, the charging circuit 23 receives a current I that increases as the temperature increases. １ The capacitance of the gate electrode of the IGBT 31 is charged for the period T1. ＳＥ The temperature dependence of the current I Ｃ This allows for optimization of switching losses and surge voltages.

[0134] Furthermore, in the LVIC 22, the period T2 is shorter than the period 1. With this configuration, when the IGBT 31 is turned on, the capacitance of the gate electrode of the IGBT 31 can be sufficiently charged.

[0135] The LVIC 22 also includes an amplifier circuit 43 that amplifies, by a predetermined gain, a voltage corresponding to a current that flows after a sufficient time has elapsed from the beginning of the on-period of the IGBT 31, and the charging circuit 23 supplies a current I １ The capacitance of the gate electrode of the IGBT 31 is charged for the period T1, which makes it easier for the LVIC 22 to operate under optimal conditions for switching loss and surge voltage.

[0136] The LVIC 22 also includes a sample-and-hold circuit 44 that samples and holds the output of the amplifier circuit 43 based on a predetermined timing, and the charging circuit 23 supplies a current I １ With this configuration, the capacitance of the gate electrode of the IGBT 31 is charged for the period T1. １ This makes it easier for the LVIC 22 to operate under optimal conditions for switching loss and surge voltage.

[0137] In the LVIC 22, the charging circuit 23 supplies a current I ２ Larger current I ３ With this configuration, when the IGBT 31 is turned on, the capacitance of the gate electrode of the IGBT 31 can be sufficiently charged.

[0138] The charging circuit 23 generates a current I that increases as the current that flows after a sufficient time has passed from the beginning of the on-period of the IGBT 31 increases. ３ With this configuration, when the IGBT 31 is turned on, the capacitance of the gate electrode of the IGBT 31 can be sufficiently charged.

[0139] The power module 10 of the embodiment includes a load drive circuit that drives a load, the load drive circuit including an IGBT 30 on the power supply side, an IGBT 31 on the ground side, and an FWD 32 connected in parallel to the IGBT 30, a resistor 13 that generates a voltage according to the current of the IGBT 31, and an LVIC 22 that switches the IGBT 31. When a drive signal is at one logic level, the LVIC 22 generates a current I that increases as the voltage of the resistor 13 increases. １ After the capacitance of the gate electrode of the IGBT 31 is charged for a period T1, the current I １ A smaller current I ２ The circuit includes a charging circuit 23 that charges the capacitance over a period T2, and an off circuit 24 that turns off the IGBT 31 element when the drive signal becomes the other logic level, and period T2 includes a period during which a reverse recovery current flows through the freewheeling diode when the load current flowing through the load becomes maximum.

[0140] According to this configuration, the capacitance of the gate electrode of the IGBT 31 is charged with a large current during the period T1. Ｃ increases rapidly until it reaches the load current. ＶＣＥ decreases rapidly, thus reducing switching losses.

[0141] Furthermore, during a period T2 immediately before the reverse recovery current flows through the FWD 32, charging of the capacitance of the gate electrode of the IGBT 31 by the large current is stopped, and the voltage V ＣＥ Therefore, the surge voltage is reduced. As a result, the relationship between switching loss and surge voltage is improved with a simple configuration.

[0142] Power module 10, 50 Inductor 11 Half-bridge circuit 20 HVIC 21 LVIC 22, 60 Resistor 13, 41 Terminals IN1, IN2, COM, P, U, N IGBT 30, 31 FWD 32, 33 Charging circuit 23 Off circuit 24 Low current output circuit 25 Timer circuit 26 High current output circuit 27 Resistor 28 Amplifier circuit 43 Sample and hold circuit 44 Delay circuit 45 Edge detection circuit 46 Switch 47 Capacitor 48 Unity gain buffer 49

Claims

1. A switching control circuit for switching the second switching element of a load drive circuit that drives a load, the switching control circuit including a first switching element on the power supply side and a second switching element on the ground side that are connected in series, and a freewheeling diode connected in parallel to the first switching element, the switching control circuit including: a charging circuit that, when a drive signal reaches a first level, charges a capacitance of a control electrode of the second switching element for a first period with a first current that increases the larger the current that flows after a sufficient amount of time has passed since the second switching element is turned on, and then charges the capacitance for a second period with a second current that is smaller than the first current; and an off circuit that, when the drive signal reaches a second level, turns off the second switching element, the second period including a period during which a reverse recovery current flows through the freewheeling diode when the load current flowing through the load is at its maximum.

2. A switching control circuit according to claim 1, wherein said charging circuit charges said capacitance for said first period with said first current which increases as the temperature increases.

3. A switching control circuit according to claim 1, wherein the second period is shorter than the first period.

4. A switching control circuit according to any one of claims 1 to 3, comprising an amplifier circuit that amplifies a voltage corresponding to the current flowing through the second switching element by a predetermined gain, and the charging circuit charges the capacitor for a first period with the first current corresponding to the output of the amplifier circuit.

5. A switching control circuit according to claim 4, comprising a sample-and-hold circuit that samples and holds the output of said amplifier circuit based on a predetermined timing, and said charging circuit charges said capacitor for a first period with said first current corresponding to the voltage held in said sample-and-hold circuit.

6. A switching control circuit according to claim 1, wherein the charging circuit charges the capacitance for the third period with a third current greater than the second current after the second period.

7. A switching control circuit according to claim 6, wherein the charging circuit charges the capacitor during the third period with the third current, which increases as the current that flows after a sufficient time has elapsed from the beginning of the on-period of the second switching element increases.

8. A semiconductor device comprising: a load drive circuit for driving a load, the load including a first switching element on the power supply side, a second switching element on the ground side, and a freewheeling diode connected in parallel to the first switching element; a resistor for generating a voltage according to the current of the second switching element; and a switching control circuit for switching on and off the second switching element, wherein the switching control circuit comprises: a charging circuit for charging a capacitance of a control electrode of the second switching element for a first period with a first current that increases as the voltage of the resistor increases when a drive signal reaches a first level, and then charging the capacitance for a second period with a second current that is smaller than the first current; and an off circuit for turning off the second switching element when the drive signal reaches a second level, wherein the second period includes a period during which a reverse recovery current flows through the freewheeling diode when the load current flowing through the load reaches a maximum.