Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device comprising: a plurality of transistor parts and a plurality of diode parts alternately arranged; a plurality of trench parts extending in a predetermined trench extension direction on a front surface of a semiconductor substrate; an emitter electrode provided above the front surface of the semiconductor substrate; and a protective layer provided above the emitter electrode. The semiconductor device comprises a protective structure in which a plurality of protective regions provided with the protective layer and a plurality of opening regions not provided with the protective layer are alternately provided.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Conventionally, semiconductor devices provided with a protective film such as polyimide are known (see, for example, Patent Documents 1 to 3). [Prior Art Documents] [Patent Document 1] JP 2009-38140 A [Patent Document 2] JP 2015-177116 A [Patent Document 3] JP 2015-26683 A General disclosure

[0003] (Problem to be Solved) It is preferable to provide a protective film having a structure that does not impair the characteristics of a semiconductor device.

[0004] (Means for Solving the Problems) A first aspect of the present invention provides a semiconductor device, the semiconductor device comprising: a plurality of transistor portions and a plurality of diode portions arranged alternately; a plurality of trench portions extending in a predetermined trench extension direction on a front surface of a semiconductor substrate; an emitter electrode provided above the front surface of the semiconductor substrate; and a protective layer provided above the emitter electrode, the semiconductor device comprising a protective structure in which a plurality of protective regions provided with the protective layer and a plurality of opening regions not provided with the protective layer are alternately provided.

[0005] The width of each of the plurality of opening regions may be 400 μm or more and 800 μm or less.

[0006] The thickness of the protective layer may be 5 μm or more and 15 μm or less.

[0007] The width of the protective layer of the protective structure in the trench extension direction may be 30 μm or more and 90 μm or less.

[0008] The semiconductor device may include a lifetime control region provided on the front surface side of the semiconductor substrate, each of the plurality of transistor portions having a boundary region on the side of an adjacent diode portion, the lifetime control region extending from each of the plurality of diode portions to the adjacent boundary region, and the boundary region including a plurality of mesa portions.

[0009] The edge of the protective layer may be provided in the boundary region.

[0010] The plurality of diode sections may not be provided with the protective layer.

[0011] Each of the plurality of opening regions may be provided in a corresponding one of the plurality of diode sections.

[0012] The protective layer may have a peripheral protective portion provided above a peripheral region of the semiconductor substrate, and the protective layer of the protective structure may be in contact with the peripheral protective portion provided above an auxiliary pad.

[0013] The protective layer may have a peripheral protective portion provided above a peripheral region of the semiconductor substrate, and the protective layer of the protective structure may be spaced apart from the peripheral protective portion provided above an auxiliary pad.

[0014] The semiconductor device may include auxiliary pads provided between the ends of the plurality of transistor portions and the plurality of diode portions in the trench extension direction and an edge of the semiconductor substrate, the protective layer having a peripheral protective portion provided above the auxiliary pad, and the protective structure may be provided between the peripheral protective portion and a central opening that exposes a portion of the upper surface of the emitter electrode.

[0015] The protective structure may be provided at the end portions of the plurality of transistor portions and the plurality of diode portions in the trench extension direction.

[0016] The protective layer may have an end-side opening between the protective structure and the outer periphery protective portion, the end-side opening exposing a portion of the upper surface of the emitter electrode.

[0017] A second aspect of the present invention provides a semiconductor device comprising: a plurality of transistor portions and a plurality of diode portions alternately arranged in a predetermined element arrangement direction; an emitter electrode provided above a front surface of a semiconductor substrate; and a protective layer provided above the emitter electrode, the protective layer extending in the element arrangement direction across the plurality of transistor portions and the plurality of diode portions.

[0018] The semiconductor device may include auxiliary pads provided between ends of the plurality of transistor portions and the plurality of diode portions in a predetermined element extension direction and a first end edge of the semiconductor substrate, and the protective layer may be provided closer to the first end edge in the element extension direction than a second end edge opposite to the first end edge.

[0019] The plurality of diode portions may have lifetime control regions with different peak concentration depths.

[0020] The peak concentration position of the lifetime control region below the protective layer may be shallower than the peak concentration position of the lifetime control region in an area where the protective layer is not provided.

[0021] In a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method comprising the steps of forming a plurality of transistor portions and a plurality of diode portions arranged alternately, forming a plurality of trench portions in a front surface of a semiconductor substrate, the trench portions extending in a predetermined trench extension direction, forming an emitter electrode above the front surface of the semiconductor substrate, forming a protective layer above the emitter electrode, and forming a protective structure in which a plurality of protective regions provided with the protective layer and a plurality of opening regions not provided with the protective layer are alternately provided.

[0022] The method for manufacturing a semiconductor device includes the steps of placing a resist above the semiconductor substrate, and irradiating the semiconductor substrate with a particle beam using the resist as a mask to form a lifetime control region, and the film thickness of the resist may be 30 μm or more and 70 μm or less.

[0023] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0024] 7A is a diagram showing an example of the top surface of the semiconductor device 100. It is a top view showing an enlarged view of region A in FIG. 1. It is a diagram showing the a-a cross section of FIG. 2. It is a top view showing an example of the arrangement of the protective layer 150. It is a diagram showing the b1-b1 cross section of FIG. 4A. It is a diagram showing the b2-b2 cross section of FIG. 4A. It is a top view showing another example of the arrangement of the protective layer 150. It is a diagram showing the c1-c1 cross section of FIG. 5A. It is a diagram showing the c2-c2 cross section of FIG. 5A. It is a top view showing another example of the arrangement of the protective layer 150. It is a diagram showing the d1-d1 cross section of FIG. 6A. It is a diagram showing the d2-d2 cross section of FIG. 6A. It is a flowchart showing an example of a manufacturing process of the semiconductor device 100. It is a diagram showing an example in which step S110 of FIG. 7 is applied to the a-a cross section of FIG. 2.

[0025] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0026] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the front surface, and the other surface is referred to as the back surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0027] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0028] In this specification, orthogonal axes parallel to the front and back surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the front and back surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the front and back surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0029] The region from the center of the semiconductor substrate in the depth direction to the front surface of the semiconductor substrate may be referred to as the front surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the back surface of the semiconductor substrate may be referred to as the back surface side.

[0030] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0031] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity or a P-type conductivity.

[0032] Fig. 1 is a diagram showing an example of the top surface of a semiconductor device 100. Fig. 1 shows the positions of each component as projected onto the front surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0033] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 has edges 102 in a top view. In this specification, the term "top view" simply refers to a view from the front surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two pairs of edges 102 that face each other in a top view. In FIG. 1 , the X-axis and the Y-axis are parallel to one of the edges 102. The Z-axis is perpendicular to the front surface of the semiconductor substrate 10.

[0034] Semiconductor substrate 10 has an active region 160, a peripheral region 180, and an edge termination region 190. Active region 160 is a region through which a main current flows in the depth direction between the front and back surfaces of semiconductor substrate 10 when semiconductor device 100 is in operation. An emitter electrode is provided above active region 160, but is omitted in FIG.

[0035] The active region 160 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of FIG. 1 , a plurality of transistor sections 70 and a plurality of diode sections 80 are alternately arranged in stripes along a predetermined element arrangement direction (X-axis direction in this specification) on the front surface of the semiconductor substrate 10. In another example, the active region 160 may have the diode sections 80 arranged in a lattice pattern within the transistor section 70.

[0036] A temperature sensing section, which is a PN junction diode made of polysilicon or the like, may be provided in the center of the active region 160 .

[0037] In FIG. 1 , the region where the transistor section 70 is disposed is marked with the symbol "I," and the region where the diode section 80 is disposed is marked with the symbol "F." In this specification, the direction perpendicular to the element arrangement direction in a top view may be referred to as the element extension direction (herein, the Y-axis direction). The transistor section 70 and the diode section 80 may each have their longitudinal direction in a predetermined trench extension direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction.

[0038] The width of the transistor section 70 in the X-axis direction is larger than the width of the diode section 80 in the X-axis direction. Furthermore, the width of the transistor section 70 in the X-axis direction may be the same as the width of the diode section 80 in the X-axis direction. In one example, the width of the transistor section 70 in the X-axis direction is 1200 μm or more and 1500 μm or less, and the width of the diode section 80 in the X-axis direction is 300 μm or more and 500 μm or less. The element extension direction of the transistor section 70 and the diode section 80 may be the same as the trench extension direction of each trench section. The element arrangement direction of the transistor section 70 and the diode section 80 may be the same as the trench arrangement direction of each trench section, which will be described later.

[0039] The diode section 80 has an N+ type cathode region in a region that contacts the back surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region other than the cathode region on the back surface of the semiconductor substrate 10. In this specification, an extension region of the diode section 80 that extends in the Y-axis direction to a gate runner, which will be described later, may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region.

[0040] The transistor section 70 has a P+ type collector region in a region in contact with the back surface of the semiconductor substrate 10. In addition, the transistor section 70 has a gate structure, which has an N+ type emitter region, a P- type base region, a gate conductive portion, and a gate insulating film, periodically arranged on the front surface side of the semiconductor substrate 10.

[0041] The semiconductor device 100 includes a gate runner 48 that electrically connects the conductive portion of the gate trench portion to the gate pad. The gate runner 48 is disposed between the active region 160 and the edge 102 of the semiconductor substrate 10 in a top view. The gate runner 48 in this example surrounds the active region 160 in a top view. The region surrounded by the gate runner 48 in a top view may be the active region 160, and the region from the gate runner 48 toward the edge 102 may be the peripheral region 180.

[0042] The gate runner 48 is disposed above the semiconductor substrate 10. In this example, the gate runner 48 may be formed of polysilicon doped with impurities or the like. The gate runner 48 is electrically connected to a gate conductive portion provided inside the gate trench portion via a gate insulating film.

[0043] The peripheral region 180 surrounds the active region 160 in a top view. The peripheral region 180 may have one or more auxiliary pads provided above the semiconductor substrate 10. As an example, the semiconductor device 100 has auxiliary pads such as an anode pad, a cathode pad, and a current detection pad. Each auxiliary pad may be connected to an external circuit via wiring such as a wire.

[0044] The peripheral region 180 may include a current sensing section 210. The current sensing section 210 detects the current flowing through the transistor section 70. The peripheral region 180 may further include a temperature sensing section and a protection diode, which are PN junction diodes formed of polysilicon or the like.

[0045] In this example, edge termination region 190 is disposed between periphery region 180 and edge 102. Edge termination region 190 alleviates electric field concentration on the front surface side of semiconductor substrate 10.

[0046] Edge termination region 190 may include guard ring 92. Guard ring 92 is a P-type region in contact with the front surface of semiconductor substrate 10. Note that edge termination region 190 in this example includes multiple guard rings 92, but only one guard ring 92 is shown in FIG. 1 for clarity. By providing multiple guard rings 92, the depletion layer on the upper surface side of active region 160 can be extended outward, improving the breakdown voltage of semiconductor device 100. Edge termination region 190 may further include at least one of a field plate and a resurf annularly disposed around periphery region 180.

[0047] 1, a protective layer 150 is provided above the semiconductor substrate 10. The protective layer 150 is a protective film formed of polyimide or the like, and covers the entire front surface side of the semiconductor substrate 10. The protective layer 150 may have openings at positions corresponding to the auxiliary pads, wires, etc. provided in the peripheral region 180.

[0048] Fig. 2 is an enlarged top view of region A in Fig. 1. The semiconductor device 100 includes a semiconductor substrate having a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a free wheel diode (FWD).

[0049] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15, which are provided on the front surface of a semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion.

[0050] The semiconductor device 100 of this example also includes an emitter electrode 52 provided above the front surface of the semiconductor substrate 10. An interlayer insulating film is provided between the emitter electrode 52 and the front surface of the semiconductor substrate 10, but this is omitted in Figure 2. Contact holes 54 and 56 are provided in the interlayer insulating film of this example, penetrating the interlayer insulating film. In Figure 2, each contact hole is hatched with diagonal lines.

[0051] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 is electrically connected to the emitter region 12, the base region 14, and the contact region 15 on the front surface of the semiconductor substrate 10 via contact holes 54.

[0052] The emitter electrode 52 is connected to a dummy conductive portion in the dummy trench portion 30 by a contact hole 56. A connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is provided on the front surface of the semiconductor substrate 10 via an insulating film such as an interlayer insulating film and a dummy insulating film in the dummy trench portion 30.

[0053] The gate runner 48 may be formed of polysilicon doped with impurities, etc. The gate runner 48 is connected to the gate conductive portion in the gate trench portion 40 on the front surface of the semiconductor substrate 10. The gate runner 48 is not electrically connected to the dummy conductive portion in the dummy trench portion 30 or the emitter electrode 52.

[0054] The gate runner 48 and the emitter electrode 52 are electrically isolated by an insulating material such as an interlayer insulating film and an oxide film. At the tip of the gate trench portion 40, the gate conductive portion is exposed on the front surface of the semiconductor substrate 10 and is connected to the gate runner 48.

[0055] The emitter electrode 52 is made of a conductive material containing metal. For example, the emitter electrode 52 is made of aluminum or an aluminum-silicon alloy. The emitter electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like below the region made of aluminum or the like.

[0056] Furthermore, a plating layer (not shown) may be provided on the upper surface of the emitter electrode 52 .

[0057] The emitter electrode 52 may have a plug formed of tungsten or the like in the contact hole 54. The plug may have a barrier metal on the side in contact with the semiconductor substrate 10, with tungsten buried so as to be in contact with the barrier metal, and may be formed of aluminum or the like on the tungsten.

[0058] The plug is provided in a contact hole 54 that contacts the contact region 15 or the base region 14. A P++-type plug region having a higher doping concentration than the contact region 15 may be formed below the contact hole 54 in which the plug is provided. The plug region can improve the contact resistance between the barrier metal and the contact region 15. The depth of the plug region may be approximately 0.1 μm or less, and may have an area that is 10% or less smaller than the depth of the contact region 15.

[0059] The plug region improves the contact resistance, thereby improving the latch-up resistance in the operation of the transistor section 70. On the other hand, in the operation of the diode section 80, increases in conduction loss and switching loss can be suppressed.

[0060] The well region 11 extends from the gate runner 48, overlapping with the peripheral region 180, and is provided in a ring shape in top view. The well region 11 also extends to the active region 160 inside the gate runner 48 by a predetermined width, and is provided in a ring shape in top view. In this example, the well region 11 is provided in a range that is farther toward the gate runner 48 than the end of the contact hole 54 in the Y-axis direction. The well region 11 is a region of the second conductivity type that has a doping concentration higher than that of the base region 14. The doping concentration of the well region 11 may be the same as or lower than the doping concentration of the contact region 15. The gate runner 48 is electrically insulated from the well region 11.

[0061] In this example, the base region 14 is P- type, and the well region 11 is P+ type. The well region 11 is formed from the front surface of the semiconductor substrate to a position deeper than the bottom end of the base region 14. The base region 14 is provided in contact with the well region 11 in the transistor section 70 and the diode section 80. The well region 11 is electrically connected to the emitter electrode 52.

[0062] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the trench arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the trench arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the trench arrangement direction.

[0063] The gate trench portion 40 in this example may have two extension portions 39 (portions of the trench that are linear along the trench extension direction) extending along the trench extension direction perpendicular to the trench arrangement direction, and a connection portion 41 connecting the two extension portions 39.

[0064] At least a part of the connection portion 41 may be curved in top view. The connection portion 41 connects the ends of the two extension portions 39 in the Y-axis direction to the gate runner 48, thereby functioning as a gate electrode to the gate trench portion 40. On the other hand, by making the connection portion 41 curved, electric field concentration at the ends can be alleviated more effectively than if the connection portion 41 were completed at the extension portion 39.

[0065] In the transistor section 70, the dummy trench section 30 is provided between the extension portions 39 of the gate trench section 40. In the example of Fig. 2, one dummy trench section 30 is provided between the extension portions 39, but two dummy trench sections 30 may be provided, or more than two dummy trench sections 30 may be provided.

[0066] Furthermore, the dummy trench portion 30 may not be provided between the extension portions 39, and the gate trench portion 40 may be provided instead. With such a structure, the electron current from the emitter region 12 can be increased, thereby reducing the on-voltage.

[0067] The dummy trench portion 30 may have a linear shape extending in the trench extension direction, and may have an extension portion 29 and a connection portion 31, similar to the gate trench portion 40. In the semiconductor device 100 shown in FIG. 2 , only dummy trench portions 30 having connection portions 31 are arranged, but in other examples, the semiconductor device 100 may include linear dummy trench portions 30 without connection portions 31.

[0068] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction (positive side in the Z-axis direction) is covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0069] A mesa portion 60 is provided between each trench portion in the trench arrangement direction. The mesa portion 60 refers to a region sandwiched between the trench portions inside the semiconductor substrate 10. As an example, the depth position of the mesa portion 60 is from the front surface of the semiconductor substrate 10 to the bottom end of the trench portion.

[0070] The mesa portion 60 in this example is sandwiched between adjacent trench portions in the X-axis direction, and is provided on the front surface of the semiconductor substrate 10 so as to extend along the trench in the trench extension direction (Y-axis direction).

[0071] Each mesa portion 60 has a base region 14. In each mesa portion 60, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in a region sandwiched between the base regions 14 in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the front surface of the semiconductor substrate 10 in the depth direction.

[0072] The mesa portion 60 of the transistor section 70 has an emitter region 12 exposed on the front surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 has a contact region 15 exposed on the front surface of the semiconductor substrate 10.

[0073] The contact regions 15 and the emitter regions 12 in the mesa portion 60 are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and the emitter regions 12 in the mesa portion 60 are alternately arranged along the trench extension direction (Y-axis direction).

[0074] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the trench extension direction (Y-axis direction). For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0075] The mesa portion 60 of the diode portion 80 does not have an emitter region 12. A base region 14 may be provided on the upper surface of the mesa portion 60 of the diode portion 80. The base region 14 may be disposed over the entire mesa portion 60 of the diode portion 80.

[0076] A contact hole 54 is provided above each mesa portion. The contact holes 54 are arranged in a region sandwiched between the base regions 14 in the trench extension direction (Y-axis direction). In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 may be arranged in the center of the mesa portion in the trench arrangement direction (X-axis direction).

[0077] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the back surface of the semiconductor substrate 10. A P+ type collector region 22 may be provided in a region of the back surface of the semiconductor substrate 10 where the cathode region 82 is not provided. In Figure 2, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0078] The cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 11) that has a relatively high doping concentration and is formed deep, thereby suppressing hole injection from the well region 11 and reducing reverse recovery loss. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0079] The transistor section 70 has a boundary region 90 on the side of the adjacent diode section 80. The boundary region 90 includes a plurality of mesa sections 60. In FIG. 2, the boundary region 90 includes two mesa sections 60, but may include more than two mesa sections 60. In this example, the boundary region 90 is provided with a dummy trench section 30, but is not provided with a gate trench section 40.

[0080] 3 is a diagram showing the aa cross section of Fig. 2. The aa cross section is an XZ plane passing through the contact region 15, the base region 14, the gate trench portion 40, and the dummy trench portion 30. In the aa cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0081] The interlayer insulating film 38 is provided on the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 may be an insulating film such as silicate glass doped with impurities such as boron or phosphorus. The interlayer insulating film 38 may be in contact with the front surface 21, or another film such as an oxide film may be provided between the interlayer insulating film 38 and the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 has a contact hole 54, as described with reference to FIG. 2 .

[0082] The emitter electrode 52 is provided on the front surface 21 of the semiconductor substrate 10 and on the upper surface of the interlayer insulating film 38. The emitter electrode 52 is electrically connected to the front surface 21 of the semiconductor substrate 10 via a contact hole 54 in the interlayer insulating film 38. A plug (not shown) made of tungsten (W) or the like may be embedded inside the contact hole 54 via a barrier metal film. A P++-type plug region may be provided in the surface layer of the semiconductor substrate 10 where the contact hole 54 is provided. The doping concentration of the plug region is higher than the doping concentration of the contact region 15.

[0083] Furthermore, the contact hole 54 may be a trench contact in which the bottom of the contact hole 54 is provided deeper than the front surface 21 of the semiconductor substrate 10 .

[0084] The collector electrode 24 is provided on the rear surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 may be formed of a material containing a metal or a laminated film thereof.

[0085] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0086] The semiconductor substrate 10 has a drift region 18 of a first conductivity type. In this example, the drift region 18 is N-type. The drift region 18 may be a remaining region of the semiconductor substrate 10 without other doped regions being provided therein.

[0087] One or more accumulation regions 16 may be provided in the Z-axis direction above the drift region 18. The accumulation region 16 is a region in which the same dopant as the drift region 18 is accumulated at a higher concentration than the drift region 18. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18.

[0088] The accumulation region 16 in this example is N+ type. The accumulation region 16 may be provided only in the transistor section 70, or may be provided in both the transistor section 70 and the diode section 80. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 in this example is provided only in the transistor section 70, and is not provided in the diode section 80.

[0089] In the transistor section 70, an emitter region 12 is provided above the base region 14 in contact with the front surface 21 of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench section 40. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. Examples of dopants for the emitter region 12 include arsenic (As), phosphorus (P), and antimony (Sb).

[0090] The diode section 80 is provided with a base region 14 exposed on the front surface 21 of the semiconductor substrate 10. The base region 14 of the diode section 80 operates as an anode.

[0091] A buffer region 20 of the first conductivity type may be provided below the drift region 18. In this example, the buffer region 20 is N+ type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0092] In the transistor section 70, a collector region 22 is provided below the buffer region 20. The collector region 22 may be provided in contact with the cathode region 82 on the rear surface 23 of the semiconductor substrate 10.

[0093] In the diode section 80, a cathode region 82 is provided below the buffer region 20. The cathode region 82 may be provided at the same depth as the collector region 22 of the transistor section 70. The diode section 80 may function as a freewheeling diode (FWD) that conducts a freewheeling current in the reverse direction when the transistor section 70 is turned off.

[0094] The semiconductor substrate 10 is provided with a gate trench portion 40 and a dummy trench portion 30. The gate trench portion 40 and the dummy trench portion 30 are provided so as to pass from the front surface 21 of the semiconductor substrate 10 through the base region 14 and the accumulation region 16 to reach the drift region 18. The trench portion passing through the doped region is not limited to a case where the trench portion is formed after the doped region is formed. A case where the doped region is formed between the trench portions after the trench portions are formed is also included in the case where the trench portion passes through the doped region.

[0095] The gate trench portion 40 has a gate trench provided in the front surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed of an oxide film or a nitride film. The gate conductive portion 44 is provided so as to fill the inside of the gate trench more inward than the gate insulating film 42. The upper surface of the gate conductive portion 44 may be located in the same XY plane as the front surface 21 of the semiconductor substrate 10. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 may be formed of impurity-doped polysilicon or the like.

[0096] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 is covered with an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0097] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the XZ cross section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the front surface 21 of the semiconductor substrate 10. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy insulating film 32 may be formed of an oxide film or a nitride film. The dummy conductive portion 34 is provided so as to fill the inside of the dummy trench more inward than the dummy insulating film 32. The upper surface of the dummy conductive portion 34 may be located in the same XY plane as the front surface 21 of the semiconductor substrate 10. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.

[0098] The gate trench portion 40 and the dummy trench portion 30 in this example are covered with an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may have a downwardly convex curved shape (a curved shape in cross section).

[0099] In the diode section 80, a lifetime control region 72 including a lifetime killer is locally provided in the drift region 18. The lifetime killer is a crystal defect formed at a predetermined depth in the semiconductor substrate 10 by implanting, for example, helium ions, hydrogen ions (protons, deuterons), etc. The lifetime control region 72 promotes recombination between holes generated in the base region 14 and electrons injected from the cathode region 82 when the diode section 80 is turned off, and suppresses peak current during reverse recovery.

[0100] The lifetime control region 72 may be formed by irradiating the semiconductor substrate 10 with a proton or helium particle beam from the front surface 21 or the back surface 23 using a mask. As an example, the proton or helium particle beam is irradiated onto the transistor section 70 and the diode section 80 through openings in a resist mask, with the region where the lifetime control region 72 is not to be formed being shielded by the resist mask formed above the front surface 21 of the semiconductor substrate 10. The proton or helium particle beam is not irradiated onto the region shielded by the mask.

[0101] 3, the peak position in the Z-axis direction of the lifetime killer concentration distribution is indicated by an "x" symbol. The peak position in the Z-axis direction of the lifetime control region 72 in this example may be the same as the position in the Z-axis direction of the lower surface of the well region 11, or may be located lower than the position in the Z-axis direction of the lower surface of the well region 11. Furthermore, the lifetime control region 72 may be formed so that the lifetime killer concentration distribution has multiple peaks in the Z-axis direction.

[0102] In this example, the lifetime control region 72 is provided continuously from the diode portion 80 to at least a portion of the transistor portion 70 on the front surface 21 side of the semiconductor substrate 10. The region of the transistor portion 70 where the lifetime control region 72 is provided is referred to as a boundary region 90. When the diode portion 80 is conductive, hole current is generated not only in the base region 14 of the diode portion 80 but also from the base region 14 of the transistor portion 70 toward the cathode region 82. The transistor portion 70 has the boundary region 90 where the lifetime control region 72 is provided, which promotes carrier annihilation and reduces reverse recovery loss during turn-off.

[0103] However, in the trench portion of the boundary region 90, when a particle beam of helium or protons is irradiated from the front surface 21 or the back surface 23 of the semiconductor substrate 10, damage occurs in the gate insulating film 42, causing a change in the interface state. When a gate voltage is applied to the irradiated gate insulating film 42, an inversion layer is more likely to form in the adjacent base region 14 than in the unirradiated gate insulating film 42. Therefore, the threshold voltage in the boundary region 90 is lower than in the region of the transistor section 70 other than the boundary region 90. Therefore, in this example, a dummy trench portion 30 is provided in the boundary region 90, and no gate trench portion 40 is provided. Furthermore, in this example, an accumulation region 16 is not provided in the boundary region 90.

[0104] It is sufficient that the end 72 a of the lifetime control region 72 is within the boundary region 90 , and it is not necessary to provide the lifetime control region 72 over the entire boundary region 90 .

[0105] 4A is a top view showing an example of the arrangement of the protective layer 150. In FIG. 4A, the region where the protective layer 150 is arranged is indicated by diagonal hatching. The protective layer 150 may be provided above the emitter electrode 52. The protective layer 150 may be provided above the semiconductor substrate 10. In other words, the protective layer 150 may be provided above the semiconductor substrate 10 in a region where the emitter electrode 52 is not formed. The protective layer 150 may be in contact with the upper surface of the emitter electrode 52.

[0106] In this example, the protective layer 150 has peripheral protective portions 150-1 to 150-4 provided above the peripheral region 180. In FIG. 4A , the region of the protective layer 150 provided above the auxiliary pad is referred to as peripheral protective portion 150-1, and the region facing peripheral protective portion 150-1 is referred to as peripheral protective portion 150-2. Peripheral protective portion 150-1 and peripheral protective portion 150-2 may be provided extending parallel to edge 102 extending in the X-axis direction. Peripheral protective portion 150-3 and peripheral protective portion 150-4 may be provided facing each other and extending in the Y-axis direction. Peripheral protective portion 150-1 may have an opening that exposes a portion of the upper surface of the auxiliary pad. This allows a wire or the like to be connected to the upper surface of the auxiliary pad.

[0107] The protective layer 150 in this example has a central opening 150-6 that exposes a portion of the upper surface of the emitter electrode 52. The central opening 150-6 is surrounded by peripheral protective portions 150-1 to 150-4. By providing the central opening 150-6, wiring such as a lead frame can be connected to the upper surface of the emitter electrode 52 via a bonding material such as solder. The wiring may also be connected by wire bonding.

[0108] The protective layer 150 in this example has end-side protective portions 150-5 provided adjacent to the ends of the transistor section 70 and the diode section 80 in the Y-axis direction. In the example of FIG. 4A , a plurality of end-side protective portions 150-5 are arranged in the X-axis direction. In this example, a plurality of protective regions 153 in which the end-side protective portions 150-5 are provided and a plurality of opening regions 151 in which the end-side protective portions 150-5 are not provided constitute a protective structure 152. The protective structure 152 is provided between the central opening 150-6 and the peripheral protective portion 150-1. In the protective structure 152, a plurality of protective regions 153 and a plurality of opening regions 151 are provided alternately in the X-axis direction.

[0109] Each end side protection portion 150-5 is provided in the transistor section 70. In this example, the end side protection portion 150-5 is provided in contact with the outer periphery protection portion 150-1 provided above the auxiliary pad in the Y-axis direction. The end of the end side protection portion 150-5 in the X-axis direction is provided in the boundary region 90. In other words, the end side protection portion 150-5 is not provided in the diode section 80. The width of the end side protection portion 150-5 in the X-axis direction is equal to or less than the width of the transistor section 70 in the X-axis direction.

[0110] Each opening region 151 is provided in the diode section 80. The width Wo of the opening region 151 in the X-axis direction may be 400 μm or more and 800 μm or less. The width Wo of the opening region 151 in the X-axis direction may be smaller than the width of the protection region 153 in the X-axis direction. The width Wo of the opening region 151 in the X-axis direction may be larger than the width of the diode section 80 in the X-axis direction. The opening region 151 may extend in the X-axis direction from the diode section 80 to at least a portion of the adjacent boundary region 90. In other words, the opening region 151 may be provided corresponding to the lifetime control region 72. The opening region 151 exposes a portion of the upper surface of the emitter electrode 52. The opening region 151 may be connected to the central opening 150-6 in the Y-axis direction.

[0111] Fig. 4B is a diagram showing the b1-b1 cross section of Fig. 4A. Fig. 4C is a diagram showing the b2-b2 cross section of Fig. 4A. The b1-b1 cross section of Fig. 4B is a YZ plane that passes through the protection region 153 of the transistor section 70 along the Y-axis direction, and the b2-b2 cross section of Fig. 4C is a YZ plane that passes through the opening region 151 of the diode section 80 along the Y-axis direction.

[0112] In this example, the lifetime control region 72 is not formed in the transistor portion 70 other than the boundary region 90. Therefore, while the transistor portion 70 not having the lifetime control region 72 is shielded by a resist mask formed above the front surface 21 of the semiconductor substrate 10, a proton or helium particle beam is irradiated onto the diode portion 80 and boundary region 90 through openings in the resist mask. As a result, the proton or helium particle beam does not pass through the transistor portion 70 other than the boundary region 90, thereby suppressing fluctuations in the threshold voltage. Meanwhile, as shown in FIG. 4C , the lifetime control region 72 is formed in the diode portion 80 not shielded by the resist mask.

[0113] In conventional semiconductor devices, in order to prevent the solder for placing a lead frame on the upper surface of the emitter electrode exposed by the central opening in the protective layer from spreading to the auxiliary pad, the protective layer extends from above the auxiliary pad toward the active region 160 and is provided up to above the transistor section and diode section. As a result, in the region of the diode section 80 where the protective layer is provided, the injection depth of the helium or proton particle beam is shallower than in the region where the protective layer is not provided, and the peak concentration position in the lifetime control region becomes shallower.

[0114] The semiconductor device of this example has a protective structure 152 in which protective regions 153 and opening regions 151 are alternately arranged, and by making the opening regions 151 correspond to the range of the lifetime control region 72, it is possible to irradiate a particle beam of helium or protons without being blocked by the protective layer, and to make the peak concentration position of the lifetime control region constant.

[0115] Since the width of the protective region 153 is greater than the width Wo of the opening region 151, the protective structure 152 of this example can prevent the solder spreading from the central opening 150-6 from reaching the auxiliary pad.

[0116] Furthermore, by extending the end side protection portion 150-5 and the protection region 153 in the Y-axis direction into the active region 160, the lifetime control region 72 is not shielded by the protection layer, and solder spreading from the central opening 150-6 can be prevented from reaching the auxiliary pad.

[0117] FIG. 5A is a top view showing another example of the arrangement of the protective layer 150. Here, elements common to those in FIG. 4A are given the same reference numerals, and descriptions thereof will be omitted. The protective layer 150 shown in FIG. 5A has an end-side opening 150-7 between the protective structure 152 and the peripheral protective portion 150-1, which exposes a portion of the upper surface of the emitter electrode 52. The end-side protective portion 150-5 of the protective structure 152 is provided between the central opening 150-6 and the end-side opening 150-7. In other words, unlike the example in FIG. 4A, the end-side protective portion 150-5 in this example is spaced apart from the peripheral protective portion 150-1 provided above the auxiliary pad.

[0118] Fig. 5B is a diagram showing the c1-c1 cross section of Fig. 5A. Fig. 5C is a diagram showing the c2-c2 cross section of Fig. 5A. The c1-c1 cross section of Fig. 5B is a YZ plane passing through the protection region 153 of the transistor section 70 along the Y-axis direction, and the c2-c2 cross section of Fig. 5C is a YZ plane passing through the opening region 151 of the diode section 80 along the Y-axis direction.

[0119] As shown in FIG. 5B , the edge protection portion 150-5 of the protection region 153 has a trapezoidal cross section. The width Wp of the edge protection portion 150-5 in the Y-axis direction may be 30 μm or more and 90 μm or less. The thickness Dp of the edge protection portion 150-5 may be 5 μm or more and 15 μm or less. By having the width Wp in this range, the edge protection portion 150-5 of the protection region 153 can have a thickness Dp sufficient to block solder spreading from the central opening 150-6. Furthermore, by providing an edge opening 150-7 between the edge protection portion 150-5 and the peripheral protection portion 150-1, warpage of the chip can be suppressed.

[0120] Furthermore, the end protection portion 150-5 may be spaced apart from the outer periphery protection portion 150-1 by a greater distance in the Y-axis direction, which makes it easier to block solder spreading from the central opening 150-7.

[0121] 6A is a top view showing another example of the arrangement of the protective layer 150. Here, elements common to those in FIG. 5A are given the same reference numerals, and description thereof will be omitted. The protective structure 152 shown in FIG. 6A does not have an opening region, but only has a protective region 153 in which an edge-side protective portion 150-5 is provided. The edge-side protective portion 150-5 in this example extends in the X-axis direction across the active region 160. The edge-side protective portion 150-5 in this example is provided in the Y-axis direction close to the edge on which the auxiliary pad is provided.

[0122] Figure 6B is a diagram showing the d1-d1 cross section of Figure 6A. Figure 6C is a diagram showing the d2-d2 cross section of Figure 6A. The d1-d1 cross section of Figure 6B is a YZ plane passing through the protection region 153 of the transistor section 70 along the Y-axis direction, and the d2-d2 cross section of Figure 6C is a YZ plane passing through the protection region 153 of the diode section 80 along the Y-axis direction. This example differs from the examples of Figures 4A and 5A in that an end-side protection section 150-5 is also provided in the diode section 80 in which the lifetime control region 72 is formed.

[0123] As described above, in the region where the protective layer 150 is provided, the injection depth of the helium or proton particle beam is shallower than in the region where the protective layer 150 is not provided, and the peak concentration position of the lifetime control region is shallower. As shown in Figure 6C, the peak concentration position of the lifetime control region 72 below the end side protection portion 150-5 is shallower than the peak concentration position of the lifetime control region 72 in the region (central opening 150-6 and end side opening 150-7) where the end side protection portion 150-5 of the diode section 80 is not provided.

[0124] 5A, the width Wp of the end protection portion 150-5 in the Y-axis direction may be 30 μm or more and 90 μm or less, and the thickness Dp of the end protection portion 150-5 may be 5 μm or more and 15 μm or less. In this example, the end protection portion 150-5 is also provided in the diode portion 80, so that the peak concentration position of the lifetime control region 72 formed in the diode portion 80 varies. However, because the width Wp of the end protection portion 150-5 is sufficiently small relative to the dimensions of the element, it is possible to block the solder spreading from the central opening 150-6 while minimizing the effect on the characteristics of the diode portion 80.

[0125] Fig. 7 is a flowchart showing an example of a manufacturing process for the semiconductor device 100. Fig. 8 is a diagram showing an example in which step S110 in Fig. 7 is applied to the aa cross section in Fig. 2. Here, an example of a manufacturing process for a 1200V breakdown voltage RC-IGBT will be described as the semiconductor device 100.

[0126] In step S100, a device structure is formed on the front surface 21 side of the semiconductor substrate 10. Here, a low-resistivity P-type silicon wafer is used as the semiconductor substrate 10. Impurities are implanted into the front surface 21 of the semiconductor substrate 10 and thermally diffused to form the emitter region 12 and other regions. Step S100 may include a step of forming the base region 14, the emitter region 12, the contact region 15, and other regions as the device structure on the front surface 21 side of the semiconductor substrate 10 by ion implantation into the semiconductor substrate 10. Step S100 may include a step of forming a dummy trench portion 30 and a gate trench portion 40 as the device structure on the front surface 21 side.

[0127] In step S102, an interlayer insulating film 38 is formed above the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 may be a silicon oxide film such as BPSG. The interlayer insulating film 38 may be formed by stacking a plurality of insulating films. Step S102 may include a process of forming contact holes by etching the interlayer insulating film 38.

[0128] In step S104, an emitter electrode 52 is formed above the front surface 21 of the semiconductor substrate 10. For example, the emitter electrode 52 may be formed by depositing a film of aluminum or an alloy containing aluminum as a main component (e.g., an aluminum-silicon alloy, an aluminum-silicon-copper alloy, etc.) on the front surface 21 of the semiconductor substrate 10 and the interlayer insulating film 38.

[0129] Step S104 may include a step of forming a barrier metal between the interlayer insulating film 38 and the emitter electrode 52. It may also include a step of burying a plug made of tungsten or the like in the contact hole via the barrier metal.

[0130] Step S104 may also include a process of forming a plating layer on the emitter electrode 52 .

[0131] In step S106, an element structure is formed on the back surface 23 side of the semiconductor substrate 10. Step S106 may include a process of forming the buffer region 20, the collector region 22, the cathode region 82, etc. by ion implantation into the semiconductor substrate 10 after the semiconductor substrate 10 has been made to a desired thickness by back grinding.

[0132] In step S108, a protective layer 150 is formed above the front surface 21 of the semiconductor substrate 10. The protective layer 150 is patterned to have the protective structure 152 described with reference to FIGS. 4A, 5A, and 6A. In this example, the protective layer 150 is made of polyimide. After the polyimide applied to the upper surface of the emitter electrode 52 is spin-coated and cured, the polyimide in the opening region 151, the central opening 150-6, and the end openings 150-7 may be removed to form the protective layer 150.

[0133] In step S110, a proton or helium particle beam is irradiated from the front surface 21 side of the semiconductor substrate 10 in the diode portion 80 and the boundary region 90 to form a lifetime control region 72. The end portion 72a of the lifetime control region 72 may be formed within the boundary region 90.

[0134] In this example, a resist 200 is disposed above the protective layer 150, and helium ions are irradiated using the resist 200 as a mask. The resist 200 is disposed in the transistor section 70. In this example, the implantation depth of the helium ions is approximately 17 μm, and the film thickness Dr of the resist 200 is 30 μm or more and 70 μm or less. After the lifetime control region 72 is formed, the resist 200 may be removed by an ashing and stripping process.

[0135] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0136] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0137] DESCRIPTION OF SYMBOLS 10: Semiconductor substrate, 11: Well region, 12: Emitter region, 14: Base region, 15: Contact region, 16: Accumulation region, 18: Drift region, 20: Buffer region, 21: Front surface, 22: Collector region, 23: Back surface, 24: Collector electrode, 25: Connection portion, 29: Extension portion, 30: Dummy trench portion, 31: Connection portion, 32: Dummy insulating film, 34: Dummy conductive portion, 38: Interlayer insulating film, 40: Gate trench portion, 39: Extension portion, 42: Gate insulating film, 41: Connection portion, 44: Gate conductive portion , 48...gate runner, 52...emitter electrode, 54...contact hole, 56...contact hole, 60...mesa portion, 70...transistor portion, 72...lifetime control region, 72a...end portion, 80...diode portion, 82...cathode region, 90...boundary region, 92...guard ring, 100...semiconductor device, 102...edge, 150...protective layer, 151...opening region, 152...protective structure, 153...protective region, 160...active region, 180...peripheral region, 190...edge termination region, 200...resist, 210...current sense portion

Claims

1. Multiple transistor sections and multiple diode sections arranged alternately, On the front surface of the semiconductor substrate, there are multiple trenches extended in a predetermined trench extension direction, An emitter electrode provided above the front surface of the semiconductor substrate, A protective layer provided above the emitter electrode, Equipped with, The protective structure comprises a plurality of protective regions provided with the protective layer and a plurality of open regions not provided with the protective layer, which are arranged alternately. Semiconductor equipment.

2. The width of each of the aforementioned multiple opening regions is between 400 μm and 800 μm. The semiconductor device according to claim 1.

3. The thickness of the protective layer is 5 μm or more and 15 μm or less. The semiconductor device according to claim 1.

4. The width of the protective layer of the protective structure in the trench extension direction is 30 μm or more and 90 μm or less. The semiconductor device according to claim 1.

5. The semiconductor substrate is provided with a lifetime control region on the front side, Each of the plurality of transistor sections has a boundary region on the adjacent diode section side, and the lifetime control region extends from each of the plurality of diode sections to the adjacent boundary region. The boundary region includes a plurality of mesa portions. The semiconductor device according to claim 1.

6. The end of the protective layer is provided in the boundary region. The semiconductor device according to claim 5.

7. The aforementioned plurality of diode sections are not provided with the protective layer. The semiconductor device according to claim 6.

8. Each of the multiple opening regions is provided in each of the multiple diode sections. The semiconductor device according to claim 1.

9. The protective layer has an outer peripheral protective portion provided above the outer peripheral region of the semiconductor substrate, The protective layer of the protective structure is in contact with the outer peripheral protective portion, which has auxiliary pads provided on the inside, when viewed from above the semiconductor substrate. The semiconductor device according to claim 8.

10. The protective layer has an outer peripheral protective portion provided above the outer peripheral region of the semiconductor substrate, The protective layer of the protective structure is spaced apart from the outer peripheral protective portion on which the auxiliary pads are provided when viewed from above the semiconductor substrate. The semiconductor device according to claim 8.

11. The system includes auxiliary pads provided between the ends of the plurality of transistor sections and the plurality of diode sections in the trench extension direction and the edge of the semiconductor substrate, The protective layer has an outer peripheral protective portion provided above the outer peripheral region of the semiconductor substrate, and in a top view of the semiconductor substrate, the auxiliary pad is provided inside the outer peripheral protective portion. The protective structure is provided between the central opening that exposes a portion of the upper surface of the emitter electrode and the outer peripheral protective portion. The semiconductor device according to claim 1.

12. The protective structure is provided at the ends of the plurality of transistor sections and the plurality of diode sections in the trench extension direction. The semiconductor device according to claim 11.

13. The protective layer is provided with an end-side opening between the protective structure and the outer peripheral protective portion, which exposes a portion of the upper surface of the emitter electrode. The semiconductor device according to claim 11.

14. Multiple transistor sections and multiple diode sections arranged alternately in a predetermined element arrangement direction, An emitter electrode located above the front surface of the semiconductor substrate, A protective layer provided above the emitter electrode, Equipped with, The protective layer extends across the plurality of transistor portions and the plurality of diode portions in the direction of the element arrangement. Semiconductor equipment.

15. The system includes an auxiliary pad provided between the ends of the plurality of transistor sections and the plurality of diode sections in a predetermined element extension direction and the first edge of the semiconductor substrate, The protective layer is provided in the element's extending direction closer to the first end than the second end opposite to the first end. The semiconductor device according to claim 14.

16. The plurality of diode sections have lifetime control regions with different peak concentration depths. The semiconductor device according to claim 15.

17. The peak concentration position of the lifetime control region below the protective layer is shallower than the peak concentration position of the lifetime control region in the region where the protective layer is not provided. The semiconductor device according to claim 16.

18. The steps include forming multiple transistor sections and multiple diode sections arranged alternately, The steps include forming multiple trenches on the front surface of a semiconductor substrate, extending in a predetermined trench extension direction, The steps include forming an emitter electrode on the upper surface of the semiconductor substrate, The steps include forming a protective layer above the emitter electrode, The step of forming a protective structure in which a plurality of protective regions provided with the protective layer and a plurality of open regions not provided with the protective layer are alternately provided. A method for manufacturing a semiconductor device comprising the same equipment.

19. The steps include placing a resist on top of the semiconductor substrate, The steps include: irradiating the semiconductor substrate with a particle beam using the resist as a mask to form a lifetime control region; Equipped with, The thickness of the resist is 30 μm or more and 70 μm or less. The method for manufacturing a semiconductor device according to claim 18.

20. The plurality of transistor sections and the plurality of diode sections are provided with an auxiliary pad between the end of each section in a predetermined element extension direction and the edge of the semiconductor substrate, The aforementioned protective layer is An end-side protective portion extending in the direction of the element arrangement across the plurality of transistor sections and the plurality of diode sections, An outer peripheral protection portion is provided above the outer peripheral region of the semiconductor substrate, and the auxiliary pad is provided on the inside when viewed from above the semiconductor substrate, A central opening that exposes a portion of the upper surface of the emitter electrode, Adjacent to the outer peripheral protective portion is an end-side opening smaller than the central opening, It has, The end-side protective portion is provided between the central opening and the end-side opening. The semiconductor device according to claim 14.

21. The semiconductor device comprises an auxiliary pad provided between the ends of the plurality of transistor portions and the plurality of diode portions in the trench extension direction and the edge of the semiconductor substrate, The protective layer has an outer peripheral protective portion provided above the outer peripheral region of the semiconductor substrate, and in a top view of the semiconductor substrate, the auxiliary pad is provided inside the outer peripheral protective portion. The protective structure is provided between the central opening that exposes a portion of the upper surface of the emitter electrode and the outer peripheral protective portion. The method for manufacturing a semiconductor device according to claim 18.