Semiconductor device

Abstract

This semiconductor device (1) comprises: a semiconductor layer (40) which has a semiconductor substrate (32) that has a first conductivity type and contains an impurity of a first concentration, and a low-concentration impurity layer (33) that is formed to be in contact with the upper surface of the semiconductor substrate (32), has the first conductivity type, and contains an impurity of a second concentration that is lower than the first concentration; a first vertical MOS transistor (10) and a second vertical MOS transistor (20) which use the semiconductor substrate (32) as a common drain region; and a first Schottky barrier diode (81) which uses the low-concentration impurity layer (33) as a cathode in a case where the first conductivity type is N-type, and uses the low-concentration impurity layer (33) as an anode in a case where the first conductivity type is P-type, the first Schottky barrier diode (81) being connected in parallel in the same forward direction with a body diode of the first vertical MOS transistor (10).

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device including a vertical MOS (Metal Oxide Semiconductor) transistor.

[0002] 2. Description of the Related Art Conventionally, a semiconductor device is known that includes two vertical MOS transistors that share a semiconductor substrate as a common drain region.

[0003] Furthermore, a conventional technique is known in which a Schottky barrier diode having the same forward direction as the body diode of a vertical MOS transistor is connected in parallel to the body diode of the vertical MOS transistor, thereby making the forward voltage between the node connected to the anode of the body diode of the vertical MOS transistor and the node connected to the cathode lower than the forward voltage of the body diode of the vertical MOS transistor alone.

[0004] Japanese Patent Application Laid-Open No. 2002-203966

[0005] Conventionally, in a semiconductor device having two vertical MOS transistors that share a semiconductor substrate as a common drain region (hereinafter also referred to as a "conventional dual-configuration semiconductor device"), if it is desired to reduce the forward voltage between the node connected to the anode of the body diode of one of the vertical MOS transistors and the node connected to the cathode, it is necessary to connect a Schottky barrier diode, which is a discrete component, in parallel to the body diode of one of the vertical MOS transistors, and which has the same forward direction as the body diode of that vertical MOS transistor.

[0006] For this reason, it is necessary to separately arrange a Schottky barrier diode, which is a discrete product, near the conventional dual-structure semiconductor device.

[0007] Therefore, the number of elements increases compared to when a conventional dual-structure semiconductor device is used alone.

[0008] Therefore, an object of the present disclosure is to provide a semiconductor device that can reduce the forward voltage between a node connected to the anode of the body diode of one of two vertical MOS transistors that share a semiconductor substrate as a common drain region, and a node connected to the cathode, without increasing the number of elements compared to when a conventional dual-configuration semiconductor device is used alone.

[0009] A semiconductor device according to one aspect of the present disclosure includes a semiconductor layer having a semiconductor substrate of a first conductivity type containing an impurity at a first concentration, and a low-concentration impurity layer of the first conductivity type formed in contact with an upper surface of the semiconductor substrate and containing an impurity at a second concentration lower than the first concentration; a first vertical MOS transistor and a second vertical MOS transistor each having the semiconductor substrate as a common drain region; and a first Schottky barrier diode having the low-concentration impurity layer as a cathode when the first conductivity type is N-type and the low-concentration impurity layer as an anode when the first conductivity type is P-type, the first Schottky barrier diode being connected in parallel to a body diode of the first vertical MOS transistor in the same forward direction.

[0010] According to one aspect of the present disclosure, a semiconductor device is provided that can reduce the forward voltage between a node connected to the anode of the body diode of one of two vertical MOS transistors that share a semiconductor substrate as a common drain region, and a node connected to the cathode, without increasing the number of elements compared to when a conventional dual-configuration semiconductor device is used alone.

[0011] FIG. 1 is a plan view schematically showing an example of the structure of a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view schematically showing an example of the structure of a semiconductor device according to the first embodiment. FIG. 3 is a circuit diagram of the semiconductor device according to the first embodiment. FIG. 4 is an enlarged cross-sectional perspective view schematically showing an example of the structure around a first gate trench according to the first embodiment. FIG. 5 is an enlarged cross-sectional perspective view schematically showing an example of the structure around a second gate trench according to the first embodiment. FIG. 6 is a plan view schematically showing a positional relationship between a first body region, a second body region, and a first Schottky junction region according to the first embodiment. FIG. 7A is a plan view schematically showing a positional relationship between a first body region, a second body region, and a first Schottky junction region according to the first embodiment. FIG. 7B is a plan view schematically showing a positional relationship between a first body region, a second body region, and a first Schottky junction region according to the first embodiment. 7C is a plan view schematically showing the positional relationship between a first body region, a second body region, and a first Schottky junction region according to the first embodiment. FIG. 8 is a plan view schematically showing an example of the structure of a first electrode according to the first embodiment. FIG. 9 is a plan view schematically showing an example of the structure of a semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view schematically showing an example of the structure of a semiconductor device according to the second embodiment. FIG. 11 is a circuit diagram of the semiconductor device according to the second embodiment. FIG. 12 is a plan view schematically showing an example of the structure of a semiconductor device according to the second embodiment.

[0012] (Background to Achieving One Aspect of the Present Disclosure) The inventors came up with the idea that if a Schottky barrier diode having the same forward direction as the body diode of one of the vertical MOS transistors can be mounted inside the semiconductor device in addition to two vertical MOS transistors that share a semiconductor substrate as a common drain region, it is possible to realize a semiconductor device that can reduce the forward voltage between a node connected to the anode and a node connected to the cathode of the body diode of one of the two vertical MOS transistors that share a semiconductor substrate as a common drain region, without increasing the number of elements compared to when a conventional dual-configuration semiconductor device is used alone.

[0013] Then, based on this idea, the inventors conducted experiments and studies and arrived at the semiconductor device according to the present disclosure described below.

[0014] A semiconductor device according to one aspect of the present disclosure includes a semiconductor layer having a semiconductor substrate of a first conductivity type containing an impurity at a first concentration, and a low-concentration impurity layer of the first conductivity type formed in contact with an upper surface of the semiconductor substrate and containing an impurity at a second concentration lower than the first concentration; a first vertical MOS transistor and a second vertical MOS transistor each having the semiconductor substrate as a common drain region; and a first Schottky barrier diode having the low-concentration impurity layer as a cathode when the first conductivity type is N-type and the low-concentration impurity layer as an anode when the first conductivity type is P-type, the first Schottky barrier diode being connected in parallel to a body diode of the first vertical MOS transistor in the same forward direction.

[0015] The semiconductor device having the above configuration includes therein two vertical MOS transistors each having a semiconductor substrate as a common drain region, a body diode of one of the vertical MOS transistors, and a Schottky barrier diode connected in parallel in the same forward direction.

[0016] Therefore, according to the semiconductor device having the above configuration, it is possible to provide a semiconductor device that can reduce the forward voltage between the node connected to the anode of the body diode of one of two vertical MOS transistors that share a semiconductor substrate as a common drain region, and the node connected to the cathode, without increasing the number of elements compared to when a conventional dual-configuration semiconductor device is used alone.

[0017] Also, it is possible to omit the Schottky barrier diode connected in parallel to the body diode of the second vertical MOS transistor in the same forward direction.

[0018] This makes it possible to suppress an increase in the size of the semiconductor device compared to a configuration that further includes a Schottky barrier diode connected in parallel in the same forward direction as the body diode of the other vertical MOS transistor.

[0019] The total gate width of the first vertical MOS transistor and the total gate width of the second vertical MOS transistor may be equal.

[0020] This makes it possible to make the characteristics of the first vertical MOS transistor and the characteristics of the second vertical MOS transistor equal to each other relatively easily.

[0021] The semiconductor device may further include a first electrode that functions as a source electrode of the first vertical MOS transistor, and that functions as an anode electrode of the first Schottky barrier diode when the first conductivity type is N-type, and that functions as a cathode electrode of the first Schottky barrier diode when the first conductivity type is P-type, and a second electrode that functions as a source electrode of the second vertical MOS transistor, wherein an area of ​​the first electrode is larger than an area of ​​the second electrode in a plan view of the semiconductor device.

[0022] This makes it possible to suppress an increase in the size of the semiconductor device compared to a configuration in which the electrode that functions as the source electrode of the first vertical MOS transistor and the electrode that functions as the anode electrode or cathode electrode of the first Schottky barrier diode are provided as mutually different electrodes.

[0023] Furthermore, the semiconductor device may further include, on its upper surface, one or more first source pads functioning as source pads of the first vertical MOS transistor, and one or more second source pads functioning as source pads of the second vertical MOS transistor, the number of which is equal to the one or more first source pads, wherein the semiconductor device is rectangular in plan view having first and second sides parallel to each other, and the one or more first source pads and the one or more second source pads are positioned point-symmetrically with the center of the semiconductor device as the center of symmetry, or positioned line-symmetrically with a straight line connecting the midpoint of the first side and the midpoint of the second side as the axis of symmetry.

[0024] This makes it possible to prevent problems such as poor contact when mounting the semiconductor device on a mounting substrate. Also, in the bidirectional conduction from the first vertical MOS transistor to the second vertical MOS transistor and from the second vertical MOS transistor to the first vertical MOS transistor, it is possible to prevent current concentration and / or heat concentration from occurring biasedly in either one of the vertical MOS transistors.

[0025] Furthermore, the semiconductor device may further include a first body region of a second conductivity type different from the first conductivity type formed in the low-concentration impurity layer, the first body region functioning as a body region of the first vertical MOS transistor, wherein the first electrode has a Schottky junction region forming a Schottky junction with an upper surface of the semiconductor layer in a region that does not include even a part of the first body region in the planar view, and an ohmic junction region forming an ohmic junction with the upper surface of the semiconductor layer in a region that does not include even a part of the portion that does not include the first body region in the planar view, and the first electrode may be made of a plurality of conductive layers including a Schottky junction layer forming a Schottky junction with the upper surface of the semiconductor layer in the Schottky junction region, and an ohmic junction layer forming an ohmic junction with the upper surface of the semiconductor layer in the ohmic junction region, and a metal contained in the Schottky junction layer may be the same as a metal contained in the ohmic junction layer.

[0026] This makes it possible to simplify the manufacturing process compared to a configuration in which the metal contained in the Schottky junction layer and the metal contained in the ohmic junction layer are different from each other.

[0027] Furthermore, the semiconductor device may further include a first body region of a second conductivity type different from the first conductivity type formed in the low-concentration impurity layer, the first body region functioning as a body region of the first vertical MOS transistor, wherein the first electrode has a Schottky junction region forming a Schottky junction with an upper surface of the semiconductor layer in a region that does not include even a part of the first body region in the planar view, and an ohmic junction region forming an ohmic junction with the upper surface of the semiconductor layer in a region that does not include even a part of the portion that does not include the first body region in the planar view, and the first electrode is made of a plurality of conductive layers including a Schottky junction layer forming a Schottky junction with the upper surface of the semiconductor layer in the Schottky junction region, and an ohmic junction layer forming an ohmic junction with the upper surface of the semiconductor layer in the ohmic junction region, and a metal contained in the Schottky junction layer and a metal contained in the ohmic junction layer may be different from each other.

[0028] This makes it possible to make the characteristics of the Schottky barrier diode, particularly the forward voltage, leakage current, and other characteristics, more favorable than in a configuration in which the metal contained in the Schottky junction layer and the metal contained in the ohmic junction layer are the same.

[0029] Furthermore, the semiconductor device may be rectangular in shape in the plan view having first and second sides parallel to each other, and further include: a first body region of a second conductivity type different from the first conductivity type formed in the low-concentration impurity layer, the first body region functioning as the body region of the first vertical MOS transistor; a second body region of the second conductivity type formed in the low-concentration impurity layer, the second body region functioning as the body region of the second vertical MOS transistor; and a facing region that includes a center of the semiconductor device, a midpoint of the first side, and a midpoint of the second side, and is continuous with a constant width from the first side to the second side in the plan view, is located between the first body region and the second body region, and does not include even a part of the first body region or the second body region; and the entire Schottky junction region in the first Schottky barrier diode in the plan view may be included in the facing region.

[0030] This makes it possible to make the characteristics of the first vertical MOS transistor and the characteristics of the second vertical MOS transistor equal to each other relatively easily.

[0031] The semiconductor device is a rectangle having a first side and a second side parallel to each other in the plan view, and further includes a first body region of a second conductivity type different from the first conductivity type formed in the low-concentration impurity layer, the first body region functioning as a body region of the first vertical MOS transistor, a second body region of the second conductivity type formed in the low-concentration impurity layer, the second body region functioning as a body region of the second vertical MOS transistor, and a center of the semiconductor device, a midpoint of the first side, and a midpoint of the second side in the plan view. and an opposing region that is continuous with a finite width from the first side to the second side, the opposing region being located between the first body region and the second body region and not including even a part of the first body region or the second body region, wherein the opposing region includes a continuous central region that, in the planar view, has a width in a direction parallel to the first side and the second side that is the maximum width of the opposing region in the direction, and the entire Schottky junction region in the first Schottky barrier diode may be included in the central region in the planar view.

[0032] This makes it possible to make the characteristics of the first vertical MOS transistor and the characteristics of the second vertical MOS transistor equal to each other relatively easily.

[0033] Furthermore, the semiconductor device may further include: a first body region of a second conductivity type different from the first conductivity type formed in the low-concentration impurity layer, the first body region functioning as a body region of the first vertical MOS transistor; a second body region of the second conductivity type formed in the low-concentration impurity layer, the second body region functioning as a body region of the second vertical MOS transistor; and a guard ring region of the second conductivity type formed in the low-concentration impurity layer, the guard ring region functioning as a guard ring of the first Schottky barrier diode, wherein the first body region, the second body region, and the guard ring regions are isolated from each other.

[0034] This makes it relatively easy to make the breakdown voltage of the first vertical MOS transistor and the breakdown voltage of the second vertical MOS transistor equal.

[0035] Furthermore, the semiconductor device may further include a second Schottky barrier diode having the low-concentration impurity layer as a cathode when the first conductivity type is N-type and the low-concentration impurity layer as an anode when the first conductivity type is P-type, the second Schottky barrier diode being connected in parallel to the body diode of the second vertical MOS transistor in the same forward direction.

[0036] As a result, compared to when a conventional dual-structure semiconductor device is used alone, it is possible to reduce the forward voltage between the node connected to the anode and the node connected to the cathode of the body diode of the other of two vertical MOS transistors that share the semiconductor substrate as a common drain region, without increasing the number of elements.

[0037] In addition, in a plan view of the semiconductor device, an area of ​​a Schottky junction region in the first Schottky barrier diode and an area of ​​a Schottky junction region in the second Schottky barrier diode may be different from each other.

[0038] This allows the characteristics of the first Schottky barrier diode and the characteristics of the second Schottky barrier diode to be different from each other.

[0039] Specific examples of semiconductor devices according to an embodiment of the present disclosure will be described below with reference to the drawings. Each embodiment shown here illustrates a specific example of the present disclosure. Therefore, the numerical values, shapes, components, component arrangements and connection configurations, steps (processes), and step sequences shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. In each figure, substantially identical components are assigned the same reference numerals, and redundant explanations are omitted or simplified.

[0040] First Embodiment Hereinafter, a semiconductor device according to a first embodiment will be described, which is a chip-size package type semiconductor device that can be mounted face-down and includes two vertical MOS transistors that share a semiconductor substrate as a common drain region.

[0041] Here, the semiconductor device according to the first embodiment will be described as a chip-size package type semiconductor device that can be mounted face-down, but the semiconductor device according to the first embodiment does not necessarily have to be limited to a semiconductor device that can be mounted face-down, nor does it necessarily have to be limited to a chip-size package type semiconductor device.

[0042] <Configuration of Semiconductor Device> FIG. 1 is a plan view schematically showing an example of the structure of a semiconductor device 1 according to a first embodiment.

[0043] In FIG. 1 , the outlines of a first electrode 11 (described later), a second electrode 21 (described later), a first gate electrode 19 (described later), a second gate electrode 29 (described later), a first body region 18 (described later), a second body region 28 (described later), and a first Schottky junction region 73 (described later) are shown by dashed lines as if they were directly visible from outside the semiconductor device 1, but in reality, these outlines cannot be directly seen from outside the semiconductor device 1.

[0044] In the first embodiment, as shown in FIG. 1, the semiconductor device 1 will be described as having a rectangular shape having a first side 61 and a second side 62 that are parallel to each other in a plan view of the semiconductor device 1.

[0045] However, the semiconductor device 1 does not necessarily have to be limited to a rectangular configuration having a first side 61 and a second side 62 that are parallel to each other in a plan view of the semiconductor device 1. Note that the rectangular configuration having a first side 61 and a second side 62 that are parallel to each other in a plan view of the semiconductor device 1 also includes a square configuration in which the length of the first side 61 and the length of the second side 62 are equal.

[0046] 2 is a cross-sectional view schematically showing an example of the structure of the semiconductor device 1. FIG. 2 shows a cross section taken along line II in FIG.

[0047] FIG. 3 is a circuit diagram of the semiconductor device 1.

[0048] As shown in FIGS. 1 to 3, the semiconductor device 1 includes a semiconductor layer 40, a metal layer 30, an oxide film 34, a protective film 35, a first electrode 11, a second electrode 21, a first gate electrode 19, a second gate electrode 29, a first vertical MOS transistor 10, a second vertical MOS transistor 20, and a first Schottky barrier diode 81.

[0049] The semiconductor device 1 also has, on the upper surface thereof, one or more first source pads 111 (corresponding to the first source pads 111a to 111f in FIG. 1 . Hereinafter, when it is not necessary to explicitly distinguish between the individual pads, the first source pads 111a to 111f will also be simply referred to as “first source pads 111”) functioning as source pads of the first vertical MOS transistor 10, and a first gate pad 112 functioning as a gate pad of the first vertical MOS transistor 10. The second vertical MOS transistor 20 includes a gate pad 119, one or more second source pads 121 (corresponding to the second source pads 121a to 121f in FIG. 1 ) functioning as source pads of the second vertical MOS transistor 20, and a second gate pad 129 functioning as a gate pad of the second vertical MOS transistor 20.

[0050] As an example that does not necessarily need to be limited, the one or more first source pads 111 may have an oval shape in a plan view of the semiconductor device 1 .

[0051] Moreover, as an example that does not necessarily need to be limited, the first gate pad 119 may be circular in plan view of the semiconductor device 1 .

[0052] Furthermore, the one or more second source pads 121 may have an oval shape in a plan view of the semiconductor device 1, as an example that is not necessarily limited to this.

[0053] Moreover, the second gate pad 129 may be circular in plan view of the semiconductor device 1, as an example that does not necessarily need to be limited to this.

[0054] Here, as shown in FIG. 1, the semiconductor device 1 is described as having a configuration in which, when viewed in a plane, one or more first source pads 111 and one or more second source pads 121 are positioned point-symmetrically with the center 65 of the semiconductor device 1 as the center of symmetry.

[0055] However, the semiconductor device 1 does not necessarily have to be limited to a configuration in which, when viewed in a plane, one or more first source pads 111 and one or more second source pads 121 are positioned point-symmetrically with the center 65 of the semiconductor device 1 as the center of symmetry.

[0056] As another configuration example, the semiconductor device 1 may be configured such that, when viewed in a plane, one or more first source pads 111 and one or more second source pads 121 are positioned symmetrically with respect to a line 90 connecting the midpoint 611 of the first side 61 and the midpoint 621 of the second side 62 as the axis of symmetry.

[0057] In a planar view of the semiconductor device 1, the semiconductor device 1 is configured such that one or more first source pads 111 and one or more second source pads 121 are positioned in point symmetry with the center 65 of the semiconductor device 1 as the center of symmetry, or are positioned in line symmetry with the straight line 90 connecting the midpoint 611 of the first side 61 and the midpoint 621 of the second side 62 as the axis of symmetry, thereby making it possible to suppress the occurrence of problems such as poor contact when the semiconductor device 1 is mounted on a mounting substrate.

[0058] As an example of the semiconductor device 1, which is not necessarily limited to this example, in order to uniformly control the conduction in both directions, that is, from the first vertical MOS transistor 10 to the second vertical MOS transistor 20 and from the second vertical MOS transistor 20 to the first vertical MOS transistor 10, it is desirable to arrange the first vertical MOS transistor 10 and the second vertical MOS transistor 20 symmetrically in a plan view of the semiconductor device 1. In order to realize the above-described symmetrical arrangement of the first vertical MOS transistor 10 and the second vertical MOS transistor 20, as an example that is not necessarily limited to this example, the first Schottky barrier diode 81 may be arranged in a region that includes a center 65 of the semiconductor device 1 and is sandwiched between the first vertical MOS transistor 10 and the second vertical MOS transistor 20 in a plan view of the semiconductor device 1, as shown in FIGS.

[0059] Furthermore, in order to configure the semiconductor device 1 such that, in a plan view of the semiconductor device 1 as described above, the one or more first source pads 111 and the one or more second source pads 121 are positioned in point symmetry with the center 65 of the semiconductor device 1 as the center of symmetry, or in line symmetry with the straight line 90 connecting the midpoint 611 of the first side 61 and the midpoint 621 of the second side 62 as the axis of symmetry, as an example that does not necessarily need to be limited, as shown in FIGS. 1 and 2 , the first Schottky barrier diode 81 is disposed in a region that includes the center 65 of the semiconductor device 1 and is sandwiched between the first vertical MOS transistor 10 and the second vertical MOS transistor 20, and further, as shown in FIGS. 1 and 2 , it is desirable that the one or more first source pads 111 and the one or more second source pads 121 be positioned so as to avoid a region directly above the first Schottky barrier diode 81 (this directly above means directly above when the positive direction of the Z axis in FIG. 1 is defined as up).

[0060] In this specification, the center in a planar view refers to the intersection of the diagonals of a rectangular structure in a planar view, such as the semiconductor device 1; for a structure having an oval shape in a planar view, such as the first source pad 111 and the second source pad 121, refers to the intersection of the axis of symmetry extending in the longitudinal direction of the oval and the axis of symmetry extending in the lateral direction of the oval; for a structure having a circular shape in a planar view, such as the first gate pad 119 and the second gate pad 129, refers to the center of the circle; and for a structure having an elliptical shape in a planar view, refers to the intersection of the major axis and minor axis of the ellipse.

[0061] The semiconductor layer 40 is configured by stacking a semiconductor substrate 32 and a low-concentration impurity layer 33 .

[0062] The semiconductor substrate 32 is made of silicon of a first conductivity type containing impurities at a first concentration.

[0063] The low-concentration impurity layer 33 is made of silicon of the first conductivity type containing impurities at a second concentration lower than the first concentration, and is formed in contact with the upper surface of the semiconductor substrate 32. The low-concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth.

[0064] Generally, there are two types of conductivity types for semiconductors: P type and N type. The first conductivity type may be P type or N type. For convenience of explanation, the first conductivity type will be described as N type and the second conductivity type described below as P type. However, the first conductivity type may be P type and the second conductivity type may be N type.

[0065] The metal layer 30 is formed in contact with the back surface of the semiconductor layer 40. As an example, the metal layer 30 is not necessarily limited to a specific material, and may be composed of one or more layers including a layer made of silver or copper. Note that the metal layer 30 may contain trace amounts of elements other than metals that are mixed in as impurities during the manufacturing process of the semiconductor device 1.

[0066] The oxide film 34 is formed in contact with the upper surface of the low concentration impurity layer 33 .

[0067] The protective film 35 is a protective film that covers the upper surfaces of the oxide film 34 , the first electrode 11 , the second electrode 21 , the first gate electrode 19 , and the second gate electrode 29 .

[0068] The protective film 35 has one or more openings that expose a portion of the upper surface of the first electrode 11 to the outside of the protective film 35, one or more openings that expose a portion of the upper surface of the second electrode 21 to the outside of the protective film 35, an opening that exposes a portion of the upper surface of the first gate electrode 19 to the outside of the protective film 35, and an opening that exposes a portion of the upper surface of the second gate electrode 29 to the outside of the protective film 35.

[0069] The upper surface of the first electrode 11 is exposed to the outside of the protective film 35 through one or more openings in the protective film 35. The upper surface of the first electrode 11 exposed to the outside of the protective film 35 through one or more openings in the protective film 35 serves as one or more first source pads 111.

[0070] That is, the one or more first source pads 111 are portions of the upper surface of the first electrode 11 that are exposed to the outside of the protective film 35 through one or more openings.

[0071] The upper surface of the second electrode 21 is exposed to the outside of the protective film 35 through one or more openings in the protective film 35. The upper surface of the second electrode 21 exposed to the outside of the protective film 35 through one or more openings in the protective film 35 serves as one or more second source pads 121, respectively.

[0072] That is, the one or more second source pads 121 are portions of the upper surface of the second electrode 21 that are exposed to the outside of the protective film 35 through one or more openings.

[0073] The upper surface of the first gate electrode 19 is exposed to the outside of the protective film 35 through the opening of the protective film 35. The upper surface of the first gate electrode 19 exposed to the outside of the protective film 35 through the opening of the protective film 35 serves as a first gate pad 119.

[0074] That is, the first gate pad 119 is a portion of the upper surface of the first gate electrode 19 that is exposed to the outside of the protective film 35 at the opening.

[0075] The upper surface of the second gate electrode 29 is exposed to the outside of the protective film 35 through the opening of the protective film 35. The upper surface of the second gate electrode 29 exposed to the outside of the protective film 35 through the opening of the protective film 35 serves as a second gate pad 129.

[0076] That is, the second gate pad 129 is a portion of the upper surface of the second gate electrode 29 that is exposed to the outside of the protective film 35 at the opening.

[0077] In a region of the low-concentration impurity layer 33 that is contained within the first electrode 11 in a planar view of the semiconductor device 1, a first body region 18 of a second conductivity type different from the first conductivity type and containing impurities of a third concentration is formed.

[0078] Furthermore, in a region of the low-concentration impurity layer 33 that is contained within the first electrode 11 in a planar view of the semiconductor device 1, a plurality of first gate trenches 17 are formed, extending in a first direction (the X-axis direction in Figures 1 and 2) parallel to the upper surface of the semiconductor substrate 32 and in a second direction (the Y-axis direction in Figures 1 and 2) that is perpendicular to the first direction, and that is equally spaced in the second direction parallel to the upper surface of the semiconductor substrate 32, penetrating the first body region 18 from the upper surface of the low-concentration impurity layer 33 to a depth that reaches a portion of the low-concentration impurity layer 33.

[0079] A first gate conductor 15 is formed inside each of the plurality of first gate trenches 17 and extends in a first direction and is surrounded by a first gate insulating film 16 .

[0080] The first gate conductor 15 is electrically connected to a first gate electrode 19 .

[0081] The first gate conductor 15 is, by way of example and not necessarily by way of limitation, polysilicon containing impurities.

[0082] FIG. 4 is an enlarged perspective cross-sectional view schematically illustrating an example of the structure around the first gate trench 17 of the semiconductor device 1. As shown in FIG.

[0083] In FIG. 4, the first electrode 11 is illustrated as if it were transparent, but in reality, the first electrode 11 is not transparent, and structures present on the other side of the first electrode 11 cannot be directly viewed through the first electrode 11.

[0084] As shown in FIG. 4 , the low-concentration impurity layer 33 includes a plurality of first source regions 14 and a plurality of first body contact regions 13 formed alternately at a first period in the first direction (the X-axis direction in FIG. 4 ) in each of a plurality of first mesa portions 41 sandwiched between a plurality of first gate trenches 17 in the second direction (the Y-axis direction in FIG. 4 ), the plurality of first source regions 14 of the first conductivity type containing impurities at a fourth concentration formed in the first mesa portion 41 including the upper surface of the first mesa portion 41, and a plurality of first body contact regions 13 of the second conductivity type containing impurities at a fifth concentration higher than the third concentration formed in the first mesa portion 41 including the upper surface of the first mesa portion 41.

[0085] That is, the semiconductor device 1 further includes a plurality of first source regions 14 and a plurality of first body contact regions 13 .

[0086] As shown in Figures 2 and 4, the first electrode 11 is in contact with and connected to the multiple first source regions 14 and the multiple first body contact regions 13 in a region that does not include even a portion that does not include the first body region 18 in a plan view of the semiconductor device 1.

[0087] Here, the fourth concentration, which is the impurity concentration of the first source region 14, is a concentration adjusted so that the first electrode 11 and the first source region 14 form an ohmic junction, and the fifth concentration, which is the impurity concentration of the first body contact region 13, is a concentration adjusted so that the first electrode 11 and the first body contact region 13 form an ohmic junction.

[0088] Therefore, an ohmic junction is formed between the first electrode 11 and the first source region 14, and between the first electrode 11 and the first body contact region 13.

[0089] That is, as shown in FIG. 2 , the first electrode 11 has a first ohmic junction region 71 that forms an ohmic junction with the upper surface of the semiconductor layer 40 in a region that does not include even a part that does not include the first body region 18 in a plan view of the semiconductor device 1.

[0090] With the above configuration, the semiconductor device 1 includes the first vertical MOS transistor 10 .

[0091] Furthermore, with the above-described configuration, the first electrode 11 functions as the source electrode of the first vertical MOS transistor 10 .

[0092] Furthermore, with the above configuration, the first gate electrode 19 functions as the gate electrode of the first vertical MOS transistor 10 .

[0093] As shown in FIGS. 2 and 4, the junction surface between the first body region 18 and the low-concentration impurity layer 33 in the first vertical MOS transistor 10 is a PN junction surface.

[0094] In this way, the first vertical MOS transistor 10 includes a body diode whose forward direction is the direction of the electrical path from the first body region 18 to the low-concentration impurity layer 33 .

[0095] Furthermore, a second body region 28 of the second conductivity type containing impurities of a third concentration is formed in a region of the low concentration impurity layer 33 that is included in the second electrode 21 in a plan view of the semiconductor device 1.

[0096] In addition, in the region of the low-concentration impurity layer 33 that is contained within the second electrode 21 in a planar view of the semiconductor device 1, a plurality of second gate trenches 27 are formed, extending in the first direction and equally spaced in the second direction, penetrating the second body region 28 from the upper surface of the low-concentration impurity layer 33 to a depth that reaches a portion of the low-concentration impurity layer 33.

[0097] Then, inside each of the plurality of second gate trenches 27, a second gate conductor 25 is formed, which is surrounded by a second gate insulating film 26 and extends in the first direction.

[0098] The second gate conductor 25 is electrically connected to a second gate electrode 29 .

[0099] The second gate conductor 25 is, by way of example and not necessarily by way of limitation, polysilicon containing impurities.

[0100] FIG. 5 is an enlarged perspective cross-sectional view schematically illustrating an example of the structure around the second gate trench 27 of the semiconductor device 1. As shown in FIG.

[0101] In Figure 5, the second electrode 21 is illustrated as if it were transparent, but in reality, the second electrode 21 is not transparent, and structures present on the other side of the second electrode 21 cannot be directly viewed through the second electrode 21.

[0102] As shown in FIG. 5 , the low-concentration impurity layer 33 includes a plurality of second source regions 24 and a plurality of second body contact regions 23 formed alternately at a first period in a first direction (X-axis direction in FIG. 5 ) in each of a plurality of second mesa portions 42 sandwiched between a plurality of second gate trenches 27 in a second direction (Y-axis direction in FIG. 5 ), the plurality of second source regions 24 of the first conductivity type containing impurities of a fourth concentration formed in the second mesa portion 42 including the upper surface of the second mesa portion 42, and a plurality of second body contact regions 23 of the second conductivity type containing impurities of a fifth concentration formed in the second mesa portion 42 including the upper surface of the second mesa portion 42.

[0103] That is, the semiconductor device 1 further includes a plurality of second source regions 24 and a plurality of second body contact regions 23 .

[0104] As shown in Figures 2 and 5, the second electrode 21 is in contact with and connected to the multiple second source regions 24 and the multiple second body contact regions 23 in a region that does not include even a portion that does not include the second body region 28 in a planar view of the semiconductor device 1.

[0105] Here, the fourth concentration, which is the impurity concentration of the second source region 24, is a concentration adjusted so that the second electrode 21 and the second source region 24 form an ohmic junction, and the fifth concentration, which is the impurity concentration of the second body contact region 23, is a concentration adjusted so that the second electrode 21 and the second body contact region 23 form an ohmic junction.

[0106] Therefore, the second electrode 21 and the second source region 24 and the second electrode 21 and the second body contact region 23 form an ohmic junction.

[0107] That is, as shown in FIG. 2 , the second electrode 21 has a second ohmic junction region 72 that forms an ohmic junction with the upper surface of the semiconductor layer 40 in a region that does not include even a part that does not include the second body region 28 in a plan view of the semiconductor device 1.

[0108] With the above configuration, the semiconductor device 1 includes the second vertical MOS transistor 20 .

[0109] Furthermore, with the above configuration, the second electrode 21 functions as the source electrode of the second vertical MOS transistor 20 .

[0110] Moreover, with the above configuration, the second gate electrode 29 functions as the gate electrode of the second vertical MOS transistor 20 .

[0111] As shown in FIGS. 2 and 5, the junction surface between the second body region 28 and the low-concentration impurity layer 33 in the second vertical MOS transistor 20 is a PN junction surface.

[0112] In this way, the second vertical MOS transistor 20 includes a body diode whose forward direction is the direction of the electrical path from the second body region 28 to the low-concentration impurity layer 33 .

[0113] Furthermore, with the above-described configuration, the semiconductor substrate 32 functions as a common drain region in which the drain region of the first vertical MOS transistor 10 and the drain region of the second vertical MOS transistor 20 are shared.

[0114] That is, the first vertical MOS transistor 10 and the second vertical MOS transistor 20 share the semiconductor substrate 32 as a common drain region.

[0115] In the following description, the semiconductor device 1 is assumed to have a configuration in which the total gate width of the first vertical MOS transistor 10 is equal to the total gate width of the second vertical MOS transistor 20 .

[0116] For example, by making the structure of the first vertical MOS transistor 10 and the structure of the second vertical MOS transistor 20 similar, it is possible to realize a configuration in which the total gate width of the first vertical MOS transistor 10 and the total gate width of the second vertical MOS transistor 20 are equal to each other.

[0117] In order to make the total gate width of the first vertical MOS transistor 10 and the total gate width of the second vertical MOS transistor 20 equal, as an example that does not necessarily need to be limited, it is desirable that the area of ​​the first vertical MOS transistor 10 and the area of ​​the second vertical MOS transistor 20 are the same in a plan view of the semiconductor device 1.

[0118] Therefore, as an example that does not necessarily need to be limited, it is desirable that the semiconductor device 1 be configured such that, in a plan view of the semiconductor device 1, the area remaining after subtracting the area in which the first Schottky barrier diode 81 is disposed is divided into two equal parts in terms of area, and the first vertical MOS transistor 10 is disposed in one of the two halves, and the second vertical MOS transistor 20 is disposed in the other of the two halves.

[0119] However, the semiconductor device 1 does not necessarily have to be limited to a configuration in which the total gate width of the first vertical MOS transistor 10 and the total gate width of the second vertical MOS transistor 20 are equal.

[0120] In the semiconductor device 1, the total gate width of the first vertical MOS transistor 10 is equal to the total gate width of the second vertical MOS transistor 20, so that the characteristics of the first vertical MOS transistor 10 and the characteristics of the second vertical MOS transistor 20 can be made equal relatively easily. Furthermore, in the conduction direction from the first vertical MOS transistor 10 to the second vertical MOS transistor 20 and the conduction direction from the second vertical MOS transistor 20 to the first vertical MOS transistor 10, current concentration and / or heat concentration can be prevented from occurring unevenly in either one of the vertical MOS transistors.

[0121] As shown in FIGS. 1 and 2 , the first electrode 11 is in contact with and connected to the low-concentration impurity layer 33 in a region that does not include even a part of the first body region 18 and does not include even a part of the second body region 28 in a plan view of the semiconductor device 1.

[0122] Here, the second concentration, which is the concentration of the impurity in the low concentration impurity layer 33, is adjusted so that the first electrode 11 and the low concentration impurity layer 33 form a Schottky junction.

[0123] Therefore, the first electrode 11 and the low concentration impurity layer 33 form a Schottky junction.

[0124] That is, as shown in FIGS. 1 and 2 , the first electrode 11 has a first Schottky junction region 73 that forms a Schottky junction with the upper surface of the semiconductor layer 40 in a region that does not include even a part of the first body region 18 and does not include even a part of the second body region 28 in a plan view of the semiconductor device 1.

[0125] With the above configuration, the semiconductor device 1 includes the first Schottky barrier diode 81 .

[0126] The first Schottky barrier diode 81 is a Schottky barrier diode in which the low concentration impurity layer 33 serves as a cathode and the first electrode 11 serves as an anode.

[0127] In this way, the first Schottky barrier diode 81 is a Schottky barrier diode connected in parallel to the body diode of the first vertical MOS transistor 10 in the same forward direction.

[0128] With the above configuration, the first electrode 11 functions as the source electrode of the first vertical MOS transistor 10 and also functions as the anode electrode of the first Schottky barrier diode 81 .

[0129] When the first conductivity type is P-type, the first electrode 11 functions as a source electrode of the first vertical MOS transistor 10 and also functions as a cathode electrode of the first Schottky barrier diode 81.

[0130] Here, as described above, the semiconductor device 1 will be described as having a configuration in which the first electrode 11 functions as the source electrode of the first vertical MOS transistor 10 and also functions as the anode electrode or cathode electrode of the first Schottky barrier diode 81.

[0131] However, the semiconductor device 1 does not need to be limited to a configuration in which the first electrode 11 functions as the source electrode of the first vertical MOS transistor 10 and also functions as the anode electrode or cathode electrode of the first Schottky barrier diode 81.

[0132] As another configuration example, the semiconductor device 1 may be configured to include an electrode that functions as the source electrode of the first vertical MOS transistor 10 and an electrode that functions as the anode electrode or cathode electrode of the first Schottky barrier diode 81 as mutually different electrodes.

[0133] However, in such a configuration, it becomes necessary to provide a new pad for connecting the anode electrode or the electrode functioning as the cathode electrode of the first Schottky barrier diode 81 to the outside, which increases the size of the semiconductor device 1.

[0134] The semiconductor device 1 is configured such that the first electrode 11 functions as the source electrode of the first vertical MOS transistor 10 and also functions as the anode electrode or cathode electrode of the first Schottky barrier diode 81. This makes it possible to suppress an increase in the size of the semiconductor device 1 compared to a configuration in which the electrode that functions as the source electrode of the first vertical MOS transistor 10 and the electrode that functions as the anode electrode or cathode electrode of the first Schottky barrier diode 81 are provided as mutually different electrodes.

[0135] As shown in FIG. 2 , in a plan view of the semiconductor device 1, the outer periphery of the first Schottky junction region 73 is surrounded by a guard ring region 91 of the second conductivity type formed in the low-concentration impurity layer 33 and functioning as a guard ring for the first Schottky barrier diode 81.

[0136] That is, the semiconductor device 1 further includes a guard ring region 91 .

[0137] Here, as shown in FIG. 2 , the semiconductor device 1 will be described as having a configuration in which a first body region 18 of the second conductivity type, a second body region 28 of the second conductivity type, and a guard ring region 91 of the second conductivity type are separated from each other by a low-concentration impurity layer 33 of the first conductivity type.

[0138] However, the semiconductor device 1 does not necessarily have to be limited to a configuration in which the first body region 18 of the second conductivity type, the second body region 28 of the second conductivity type, and the guard ring region 91 of the second conductivity type are separated from each other by the low-concentration impurity layer 33 of the first conductivity type.

[0139] In the semiconductor device 1, the first body region 18 of the second conductivity type, the second body region 28 of the second conductivity type, and the guard ring region 91 of the second conductivity type are separated from one another by the low-concentration impurity layer 33 of the first conductivity type, so that the breakdown voltage of the first vertical MOS transistor 10 and the breakdown voltage of the second vertical MOS transistor 20 can be made equal relatively easily.

[0140] If the first body region 18 of the second conductivity type, the second body region 28 of the second conductivity type, and the guard ring region 91 of the second conductivity type are not separated from one another by the low-concentration impurity layer 33 of the first conductivity type, that is, if there is a portion where the first body region 18 of the second conductivity type and the guard ring region 91 of the second conductivity type overlap, the concentration of the impurity of the second conductivity type in the overlapping portion will be higher than the concentration of the impurity of the second conductivity type in the non-overlapping portion.

[0141] For this reason, an electric field is concentrated in the overlapping portions, and the withstand voltage in the overlapping portions becomes weaker than the withstand voltage in the non-overlapping portions.

[0142] Therefore, the breakdown voltage of both the first vertical MOS transistor 10 and the first Schottky barrier diode 81 will decrease.

[0143] FIG. 6 is a plan view schematically showing the positional relationship between the first body region 18, the second body region 28, and the first Schottky junction region 73. As shown in FIG.

[0144] In FIG. 6 , the outlines of the first body region 18, the second body region 28, and the first Schottky junction region 73 are shown by hatched solid lines as if they were directly visible from outside the semiconductor device 1, but in reality, these outlines cannot be directly seen from outside the semiconductor device 1.

[0145] Here, as shown in FIG. 6 , the semiconductor device 1 will be described as having a configuration in which, in a plan view of the semiconductor device 1, the semiconductor device 1 includes a center 65 of the semiconductor device 1, a midpoint 611 of the first side 61, and a midpoint 621 of the second side 62, and the semiconductor device 1 includes a facing region 50 that is continuous with a constant width from the first side 61 to the second side 62, the facing region 50 being located between the first body region 18 and the second body region 28 and not including even a part of the first body region 18 or the second body region 28, and the first Schottky junction region 73 is entirely included in the facing region 50, that is, the entire Schottky junction region in the first Schottky barrier diode 81 is entirely included in the facing region 50.

[0146] However, the semiconductor device 1 does not necessarily have to be limited to a configuration in which, in a plan view of the semiconductor device 1, the semiconductor device 1 includes a center 65 of the semiconductor device 1, a midpoint 611 of the first side 61, and a midpoint 621 of the second side 62, and the facing region 50 is continuous with a constant width from the first side 61 to the second side 62, is located between the first body region 18 and the second body region 28, and does not include even a portion of the first body region 18 or the second body region 28, and the entire first Schottky junction region 73 is included in the facing region 50.

[0147] The semiconductor device 1 includes, in a plan view of the semiconductor device 1, a center 65 of the semiconductor device 1, a midpoint 611 of the first side 61, and a midpoint 621 of the second side 62, and the facing region 50 is continuous with a constant width from the first side 61 to the second side 62, and is located between the first body region 18 and the second body region 28 and does not include even a part of the first body region 18 or the second body region 28. By configuring the first Schottky junction region 73 to be entirely included in the facing region 50, it is possible to make the characteristics of the first vertical MOS transistor 10 and the characteristics of the second vertical MOS transistor 20 equal to each other relatively easily.

[0148] As another configuration example, the semiconductor device 1 may be configured to include a facing region 50A instead of the facing region 50, as shown in FIGS. 7A and 7B.

[0149] 7A and 7B are plan views schematically showing the positional relationship between the first body region 18, the second body region 28, and the first Schottky junction region 73 in another configuration example of the semiconductor device 1.

[0150] 7A and 7B, similarly to FIG. 6, the contours of the first body region 18, the second body region 28, and the first Schottky junction region 73 are shown by hatched solid lines as if they were directly visible from outside the semiconductor device 1; however, in reality, these contours cannot be directly visible from outside the semiconductor device 1.

[0151] 7A and 7B , the semiconductor device 1 may include a facing region 50A that includes a center 65 of the semiconductor device 1, a midpoint 611 of the first side 61, and a midpoint 621 of the second side 62 in a plan view of the semiconductor device 1, and that is continuous with a finite width from the first side 61 to the second side 62, the facing region 50A being located between the first body region 18 and the second body region 28 and not including even a part of the first body region 18 or the second body region 28, and that includes a continuous central region 51 whose width in a direction parallel to the first side 61 and the second side 62 is the maximum width of the facing region 50A in that direction, and the entire first Schottky junction region 73 is included in the central region 51, i.e., the entire Schottky junction region in the first Schottky barrier diode 81 is included in the central region 51.

[0152] The semiconductor device 1 includes, in a plan view of the semiconductor device 1, a facing region 50A that includes a center 65 of the semiconductor device 1, a midpoint 611 of the first side 61, and a midpoint 621 of the second side 62, and that is continuous with a finite width from the first side 61 to the second side 62, the facing region 50A being located between the first body region 18 and the second body region 28 and not including even a part of the first body region 18 or the second body region 28, and that includes a continuous central region 51 whose width in a direction parallel to the first side 61 and the second side 62 is the maximum width of the facing region 50A in that direction, and the entire first Schottky junction region 73 is configured to be included in the central region 51, thereby making it relatively easy to equalize the characteristics of the first vertical MOS transistor 10 and the second vertical MOS transistor 20. In addition, the width of the central region 51 in a direction parallel to the first side 61 and the second side 62 may be equal to the width of the semiconductor device 1 in a direction parallel to the first side 61 and the second side 62, as shown in Figure 7C, for example.

[0153] FIG. 7C is a plan view schematically showing the positional relationship between the first body region 18, the second body region 28, and the first Schottky junction region 73 in another configuration example of the semiconductor device 1.

[0154] 7C , similarly to FIGS. 6 , 7A, and 7B , the contours of the first body region 18, the second body region 28, and the first Schottky junction region 73 are shown by hatched solid lines as if they were directly visible from outside the semiconductor device 1; however, in reality, these contours cannot be directly visible from outside the semiconductor device 1.

[0155] FIG. 8 is an enlarged cross-sectional view schematically showing an example of the structure of the first electrode 11. As shown in FIG.

[0156] Here, as shown in Figure 8, the first electrode 11 will be described as having a configuration in which the first conductive layer 112A, the second conductive layer 112B, and the third conductive layer 112C are stacked in this order.

[0157] However, the semiconductor device 1 does not necessarily have to be limited to a configuration in which the first electrode 11 has a first conductive layer 112A, a second conductive layer 112B, and a third conductive layer 112C, and the first conductive layer 112A, the second conductive layer 112B, and the third conductive layer 112C are stacked in this order.

[0158] The third conductive layer 112C is a main component that occupies most of the first electrode 11, and is made of metal.

[0159] A non-limiting example of the metal is aluminum containing a small amount of copper.

[0160] The first conductive layer 112A includes silicide and is in contact with and connected to the upper surface of the semiconductor layer 40 .

[0161] The thickness of the first conductive layer 112A is, for example, 5 to 50 nm, but is not necessarily limited thereto.

[0162] As shown in FIG. 8 , the first conductive layer 112A may be composed of, as an example that is not necessarily limited to, a Schottky junction layer 112AA that is in contact with and connected to the upper surface of the semiconductor layer 40 (low-concentration impurity layer 33 in FIG. 8 ) in the first Schottky junction region 73, and an ohmic junction layer 112AB that is in contact with and connected to the upper surface of the semiconductor layer 40 (low-concentration impurity layer 33 in FIG. 8 ) in the first ohmic junction region 71.

[0163] That is, the first electrode 11 may be made of a plurality of metal layers including the Schottky contact layer 112AA and the ohmic contact layer 112AB.

[0164] In this case, the metal contained in the Schottky junction layer 112AA and the metal contained in the ohmic junction layer 112AB may be the same or different from each other.

[0165] When the semiconductor device 1 is configured such that the metal contained in the Schottky junction layer 112AA and the metal contained in the ohmic junction layer 112AB are the same, the manufacturing process of the semiconductor device 1 can be made simpler than when the semiconductor device 1 is configured such that the metal contained in the Schottky junction layer 112AA and the metal contained in the ohmic junction layer 112AB are different from each other.

[0166] Conversely, in the semiconductor device 1, when the metal contained in the Schottky junction layer 112AA and the metal contained in the ohmic junction layer 112AB are different from each other, the characteristics of the first Schottky barrier diode 81 can be made more favorable compared to a configuration in which the metal contained in the Schottky junction layer 112AA and the metal contained in the ohmic junction layer 112AB are the same.

[0167] The second conductive layer 112B is a conductive layer sandwiched between the first conductive layer 112A and the third conductive layer 112C, and includes a barrier layer that prevents components of the third conductive layer 112C from diffusing into the semiconductor layer 40.

[0168] The barrier layer may be made of, but is not necessarily limited to, titanium nitride, tantalum nitride, tungsten-titanium, tungsten-titanium nitride, ruthenium, cobalt, or the like.

[0169] The thickness of the second conductive layer 112B is, for example, 10 to 100 nm, but is not necessarily limited thereto.

[0170] <Consideration> The semiconductor device 1 configured as described above includes therein two vertical MOS transistors (here, the first vertical MOS transistor 10 and the second vertical MOS transistor 20) that share the semiconductor substrate 32 as a common drain region, and a body diode of one of the vertical MOS transistors (here, the first vertical MOS transistor 10) and a first Schottky barrier diode 81 connected in parallel in the same forward direction.

[0171] Therefore, according to the semiconductor device 1 having the above configuration, it is possible to provide a semiconductor device that can reduce the forward voltage between the node connected to the anode of the body diode of one of two vertical MOS transistors that share a semiconductor substrate as a common drain region, and the node connected to the cathode, without increasing the number of elements compared to when a conventional dual-configuration semiconductor device is used alone.

[0172] In the first embodiment, the semiconductor device 1 does not include a Schottky barrier diode connected in parallel to the body diode of the second vertical MOS transistor 20 in the same forward direction.

[0173] This configuration can suppress an increase in chip size compared to a configuration that further includes a Schottky barrier diode connected in parallel in the same forward direction as the body diode of the second vertical MOS transistor 20 .

[0174] The first Schottky barrier diode 81 included in the semiconductor device 1 may be a junction barrier Schottky diode.

[0175] As a result, the semiconductor device 1 can suppress the leakage current in the first Schottky barrier diode 81 .

[0176] Second Embodiment Hereinafter, a semiconductor device according to a second embodiment will be described, which is configured by partially modifying the configuration of the semiconductor device 1 according to the first embodiment.

[0177] The semiconductor device 1 according to the first embodiment is configured to include a first Schottky barrier diode 81 connected in parallel to the body diode of the first vertical MOS transistor 10 in the same forward direction, but not to include a Schottky barrier diode connected in parallel to the body diode of the second vertical MOS transistor 20 in the same forward direction.

[0178] In contrast to this, the semiconductor device according to the second embodiment is configured to include a first Schottky barrier diode 81 connected in parallel to the body diode of the first vertical MOS transistor 10 in the same forward direction, and further includes a Schottky barrier diode connected in parallel to the body diode of the second vertical MOS transistor 20 in the same forward direction.

[0179] FIG. 9 is a plan view schematically showing an example of the structure of a semiconductor device 1A according to the second embodiment.

[0180] In FIG. 9 , the outlines of the first electrode 11, the second electrode 21A (described later), the first gate electrode 19, the second gate electrode 29, the first body region 18, the second body region 28, the first Schottky junction region 73, and the second Schottky junction region 74 (described later) are shown by dashed lines as if they were directly visible from outside the semiconductor device 1A, but in reality, these outlines cannot be directly seen from outside the semiconductor device 1A.

[0181] 10 is a cross-sectional view showing a schematic example of the structure of the semiconductor device 1A, taken along line II-II in FIG.

[0182] FIG. 11 is a circuit diagram of the semiconductor device 1A.

[0183] As shown in Figures 9 to 11, the semiconductor device 1A is configured by changing the second electrode 21 of the semiconductor device 1 according to the first embodiment to a second electrode 21A, and by adding a second Schottky barrier diode 82 and a guard ring region 92.

[0184] As shown in Figures 9 and 10, the second electrode 21A, like the second electrode 21, is in contact with and connected to a plurality of second source regions 24 and a plurality of second body contact regions 23 in a region that does not include even a portion that does not contain the second body region 28 in a planar view of the semiconductor device 1.

[0185] That is, like the second electrode 21, the second electrode 21A has a second ohmic junction region 72 that forms an ohmic junction with the upper surface of the semiconductor layer 40 in a region that does not include even a part that does not contain the second body region 28 in a planar view of the semiconductor device 1A, as shown in FIG. 10 .

[0186] The second electrode 21A is further in contact with and connected to the low-concentration impurity layer 33 in a region that does not include even a portion of the first body region 18 and does not include even a portion of the second body region 28 in a planar view of the semiconductor device 1A.

[0187] Here, the second concentration, which is the concentration of the impurity in the low concentration impurity layer 33, is adjusted so that the second electrode 21 and the low concentration impurity layer 33 form a Schottky junction.

[0188] Therefore, the second electrode 21A and the low concentration impurity layer 33 form a Schottky junction.

[0189] That is, as shown in FIGS. 9 and 10 , the second electrode 21A has a second Schottky junction region 74 that forms a Schottky junction with the upper surface of the semiconductor layer 40 in a region that does not include even a part of the first body region 18 and does not include even a part of the second body region 28 in a plan view of the semiconductor device 1A.

[0190] With the above configuration, the semiconductor device 1A includes the second Schottky barrier diode 82.

[0191] The second Schottky barrier diode 82 is a Schottky barrier diode in which the low concentration impurity layer 33 serves as a cathode and the second electrode 21A serves as an anode.

[0192] In this way, the second Schottky barrier diode 82 is a Schottky barrier diode connected in parallel to the body diode of the second vertical MOS transistor 20 in the same forward direction.

[0193] With the above configuration, the second electrode 21A functions as the source electrode of the second vertical MOS transistor 20 and also functions as the anode electrode of the second Schottky barrier diode 82 .

[0194] As shown in FIG. 9 , in a plan view of the semiconductor device 1A, the outer periphery of the second Schottky junction region 74 is surrounded by a guard ring region 92 of the second conductivity type formed in the low-concentration impurity layer 33, which functions as a guard ring for the second Schottky barrier diode 82.

[0195] That is, the semiconductor device 1A further includes a guard ring region 92.

[0196] <Consideration> The semiconductor device 1A having the above configuration includes therein two vertical MOS transistors (here, the first vertical MOS transistor 10 and the second vertical MOS transistor 20) that share the semiconductor substrate 32 as a common drain region, a first Schottky barrier diode 81 connected in parallel in the same forward direction to the body diode of one of the vertical MOS transistors (here, the first vertical MOS transistor 10), and a second Schottky barrier diode 82 connected in parallel in the same forward direction to the body diode of the other vertical MOS transistor (here, the second vertical MOS transistor 20).

[0197] Therefore, according to the semiconductor device 1A having the above configuration, it is possible to provide a semiconductor device that can not only reduce the forward voltage between the node connected to the anode of the body diode of one vertical MOS transistor and the node connected to the cathode of the two vertical MOS transistors that share a semiconductor substrate as a common drain region, but also reduce the forward voltage between the node connected to the anode of the body diode of the other vertical MOS transistor and the node connected to the cathode, without increasing the number of elements compared to when a conventional dual-configuration semiconductor device is used alone.

[0198] 9, the semiconductor device 1A is illustrated as if the area of ​​the first Schottky junction region 73 and the area of ​​the second Schottky junction region 74 are equal in plan view of the semiconductor device 1A, that is, the area of ​​the Schottky junction region in the first Schottky barrier diode 81 and the area of ​​the Schottky junction region in the second Schottky barrier diode 82 are equal.

[0199] In contrast to this, the semiconductor device 1A may be configured such that, in a plan view of the semiconductor device 1A, the area of ​​the Schottky junction region in the first Schottky barrier diode 81 and the area of ​​the Schottky junction region in the second Schottky barrier diode 82 are equal to each other, or such that the area of ​​the Schottky junction region in the first Schottky barrier diode 81 and the area of ​​the Schottky junction region in the second Schottky barrier diode 82 are different from each other.

[0200] FIG. 12 is a plan view schematically illustrating an example of the structure of the semiconductor device 1A in a configuration in which the area of ​​the first Schottky junction region 73 and the area of ​​the second Schottky junction region 74 are different from each other in a plan view of the semiconductor device 1A, that is, the area of ​​the Schottky junction region in the first Schottky barrier diode 81 and the area of ​​the Schottky junction region in the second Schottky barrier diode 82 are different from each other.

[0201] In the semiconductor device 1A, the area of ​​the Schottky junction region in the first Schottky barrier diode 81 and the area of ​​the Schottky junction region in the second Schottky barrier diode 82 are different from each other in a plan view of the semiconductor device 1A, so that the characteristics of the first Schottky barrier diode 81 and the characteristics of the second Schottky barrier diode 82 can be made different from each other.

[0202] The characteristics of the Schottky barrier diodes can also be controlled by adjusting the area of ​​the Schottky junction region, which is convenient when the desired characteristics of the Schottky barrier diodes for the first Schottky barrier diode 81 and the second Schottky barrier diode 82 are different from each other.

[0203] Although the semiconductor device according to one aspect of the present disclosure has been described above based on the first and second embodiments, the present disclosure is not limited to these embodiments. As long as it does not deviate from the spirit of the present disclosure, various modifications conceivable by a person skilled in the art to these embodiments and configurations constructed by combining components in different modifications may also be included within the scope of one or more aspects of the present disclosure.

[0204] The present disclosure is widely applicable to semiconductor devices including vertical MOS transistors.

[0205] REFERENCE SIGNS LIST 1, 1A Semiconductor device 10 First vertical MOS transistor 11 First electrode 13 First body contact region 14 First source region 15 First gate conductor 16 First gate insulating film 17 First gate trench 18 First body region 19 First gate electrode 20 Second vertical MOS transistor 21, 21A Second electrode 23 Second body contact region 24 Second source region 25 Second gate conductor 26 Second gate insulating film 27 Second gate trench 28 Second body region 29 Second gate electrode 30 Metal layer 32 Semiconductor substrate 33 Lightly doped impurity layer 34 Oxide film 35 Protective film 40 Semiconductor layer 41 First mesa portion 42 Second mesa portion 50, 50A Opposing region 51 Central region 61 First side 62 Second side 65 Center 71 First ohmic junction region 72 Second ohmic junction region 73 First Schottky junction region 74 Second Schottky junction region 81 First Schottky barrier diode 82 Second Schottky barrier diode 90 Straight line 91, 92 Guard ring region 111, 111a, 111b, 111c, 111d, 111e, 111f First source pad 112A First conductive layer 112AA Schottky junction layer 112AB Ohmic junction layer 112B Second conductive layer 112C Third conductive layer 119 First gate pad 121, 121a, 121b, 121c, 121d, 121e, 121f Second source pad 129 Second gate pad 611, 621 Midpoint

Claims

1. A semiconductor layer comprising: a semiconductor substrate of a first conductivity type containing impurities of a first concentration; and a low-concentration impurity layer of the first conductivity type, formed in contact with the upper surface of the semiconductor substrate and containing impurities of a second concentration lower than the first concentration; A first vertical MOS (Metal Oxide Semiconductor) transistor and a second vertical MOS transistor, with the semiconductor substrate having a common drain region, A first Schottky barrier diode wherein the low-concentration impurity layer serves as the cathode when the first conductivity type is N-type, and the low-concentration impurity layer serves as the anode when the first conductivity type is P-type, comprising the body diode of the first vertical MOS transistor and the first Schottky barrier diode connected in parallel in the same forward direction, The second vertical MOS transistor does not have a body diode and a Schottky barrier diode connected in parallel in the same forward direction. Semiconductor equipment.

2. The total gate width of the first vertical MOS transistor and the total gate width of the second vertical MOS transistor are equal. The semiconductor device according to claim 1.

3. moreover, A first electrode that functions as the source electrode of the first vertical MOS transistor, and when the first conductivity type is N-type, functions as the anode electrode of the first Schottky barrier diode, and when the first conductivity type is P-type, functions as the cathode electrode of the first Schottky barrier diode, The second electrode, which functions as the source electrode of the second vertical MOS transistor, comprises In a plan view of the semiconductor device, the area of ​​the first electrode is larger than the area of ​​the second electrode. The semiconductor device according to claim 2.

4. Furthermore, on the upper surface of the semiconductor device, One or more first source pads that function as source pads for the first vertical MOS transistor, The device comprises one or more second source pads, the same number as the one or more first source pads, which function as source pads for the second vertical MOS transistor, The semiconductor device is a rectangle having a first side and a second side that are parallel to each other in the plan view. In the plan view, the one or more first source pads and the one or more second source pads are positioned point-symmetrically with respect to the center of the semiconductor device, or line-symmetrically with respect to the line connecting the midpoint of the first side and the midpoint of the second side as the axis of symmetry. The semiconductor device according to claim 3.

5. Furthermore, the low-concentration impurity layer comprises a first body region having a second conductivity type different from the first conductivity type, which functions as the body region of the first vertical MOS transistor. The first electrode is, In the aforementioned plan view, within the region that does not include even a part of the first body region, there is a Schottky junction region that forms a Schottky bond with the upper surface of the semiconductor layer, In the plan view, the region that does not include even a part of the portion that does not contain the first body region has an ohmic junction region that forms an ohmic junction with the upper surface of the semiconductor layer, The first electrode comprises a plurality of conductive layers, including a Schottky junction layer that forms a Schottky junction with the upper surface of the semiconductor layer in the Schottky junction region, and an ohmic junction layer that forms an ohmic junction with the upper surface of the semiconductor layer in the ohmic junction region. The metal contained in the Schottky junction layer and the metal contained in the ohmic junction layer are the same. The semiconductor device according to claim 3.

6. Furthermore, the low-concentration impurity layer comprises a first body region having a second conductivity type different from the first conductivity type, which functions as the body region of the first vertical MOS transistor. The first electrode is, In the aforementioned plan view, within the region that does not include even a part of the first body region, there is a Schottky junction region that forms a Schottky bond with the upper surface of the semiconductor layer, In the plan view, the region that does not include even a part of the portion that does not contain the first body region has an ohmic junction region that forms an ohmic junction with the upper surface of the semiconductor layer, The first electrode comprises a plurality of conductive layers, including a Schottky junction layer that forms a Schottky junction with the upper surface of the semiconductor layer in the Schottky junction region, and an ohmic junction layer that forms an ohmic junction with the upper surface of the semiconductor layer in the ohmic junction region. The metal contained in the Schottky junction layer and the metal contained in the ohmic junction layer are different from each other. The semiconductor device according to claim 3.

7. The semiconductor device is a rectangle having a first side and a second side that are parallel to each other in the plan view. moreover, A first body region formed in the low-concentration impurity layer, having a second conductivity type different from the first conductivity type, and the first body region functioning as the body region of the first vertical MOS transistor, A second body region of the second conductivity type formed in the low-concentration impurity layer, the second body region which functions as the body region of the second vertical MOS transistor, In the plan view, the semiconductor device comprises the center of the semiconductor device, the midpoint of the first side, and the midpoint of the second side, and a continuous opposing region extending from the first side to the second side with a constant width, located between the first body region and the second body region, and not encompassing any part of the first body region or the second body region. In the plan view, the entire Schottky junction region of the first Schottky barrier diode is contained within the opposing region. The semiconductor device according to claim 3.

8. The semiconductor device is a rectangle having a first side and a second side that are parallel to each other in the plan view. moreover, A first body region formed in the low-concentration impurity layer, having a second conductivity type different from the first conductivity type, and the first body region functioning as the body region of the first vertical MOS transistor, A second body region of the second conductivity type formed in the low-concentration impurity layer, the second body region which functions as the body region of the second vertical MOS transistor, In the plan view, the semiconductor device comprises the center of the semiconductor device, the midpoint of the first side, and the midpoint of the second side, and a continuous opposing region with a finite width from the first side to the second side, located between the first body region and the second body region, and not encompassing any part of the first body region or the second body region. The opposing region includes a central region in which, in the plan view, the width in the direction parallel to the first side and the second side is the maximum width of the opposing region in that direction, In the plan view, the entire region of the Schottky junction in the first Schottky barrier diode is contained within the central region. The semiconductor device according to claim 3.

9. moreover, A first body region formed in the low-concentration impurity layer, having a second conductivity type different from the first conductivity type, and the first body region functioning as the body region of the first vertical MOS transistor, A second body region of the second conductivity type formed in the low-concentration impurity layer, the second body region which functions as the body region of the second vertical MOS transistor, The low-concentration impurity layer comprises a second conductivity type guard ring region formed therein, which functions as a guard ring for the first Schottky barrier diode, The first body region, the second body region, and the guard ring region are separated from each other. The semiconductor device according to claim 3.

10. A semiconductor layer comprising: a semiconductor substrate of a first conductivity type containing an impurity of a first concentration; and a low-concentration impurity layer of the first conductivity type, formed in contact with the upper surface of the semiconductor substrate and containing an impurity of a second concentration lower than the first concentration; A first vertical MOS (Metal Oxide Semiconductor) transistor and a second vertical MOS transistor, with the semiconductor substrate having a common drain region, A first Schottky barrier diode wherein the low-concentration impurity layer serves as the cathode when the first conductivity type is N-type, and the low-concentration impurity layer serves as the anode when the first conductivity type is P-type, comprising the body diode of the first vertical MOS transistor and the first Schottky barrier diode connected in parallel in the same forward direction, Furthermore, a second Schottky barrier diode wherein the low-concentration impurity layer serves as the cathode when the first conductivity type is N-type, and the low-concentration impurity layer serves as the anode when the first conductivity type is P-type, the semiconductor device comprising the second Schottky barrier diode connected in parallel in the same forward direction to the body diode of the second vertical MOS transistor, In a plan view of the semiconductor device, the area of ​​the Schottky junction region in the first Schottky barrier diode and the area of ​​the Schottky junction region in the second Schottky barrier diode are different from each other. Semiconductor equipment.