Semiconductor device

Abstract

This semiconductor device comprises: a semiconductor substrate having an upper surface and provided with a drift region; a plurality of trenches provided from the upper surface of the semiconductor substrate toward the inside thereof; a plurality of mesas which are regions sandwiched between two trenches; an emitter electrode; and an interlayer insulating film in which a contact hole is formed. The plurality of mesas include: a channel mesa section that is connected to the emitter electrode by the contact hole and that includes an emitter region of a first conductivity type and a base region of a second conductivity type which are disposed on the upper surface of the semiconductor substrate; and a hole-extraction mesa section in which channels are not formed and which is connected to the emitter electrode by means of the contact hole. The lower end of at least one of the trenches sandwiching the hole-extraction mesa section is provided with a first conductivity-type first trench bottom region having a higher concentration than the drift region.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Conventionally, semiconductor devices provided with transistors such as insulated gate bipolar transistors (IGBTs) have been known (see, for example, Patent Documents 1 and 2). [Prior art documents] [Patent Documents] [Patent Document 1] International Publication No. 2015 / 022989 [Patent Document 2] Japanese Patent Laid-Open No. 2019-91892 General disclosure

[0003] (Problem to be Solved) In a semiconductor device, it is preferable to reduce turn-on loss. (Means for Solving the Problem)

[0004] To solve the above problem, one aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and including a first conductivity type drift region; a plurality of trenches extending from the upper surface toward the interior of the semiconductor substrate in an extension direction; a plurality of mesa regions sandwiched between two of the trenches; an emitter electrode provided above the upper surface of the semiconductor substrate; and an interlayer insulating film provided between the upper surface of the semiconductor substrate and the emitter electrode, the interlayer insulating film having a contact hole formed therein. In any of the above semiconductor devices, the plurality of mesa regions may include a channel mesa region having a first conductivity type emitter region provided on the upper surface of the semiconductor substrate and a second conductivity type base region provided between the emitter region and the drift region, the channel mesa region connected to the emitter electrode by the contact hole. In any of the above semiconductor devices, the plurality of mesa regions may include a hole extraction mesa region in which a channel is not formed and which is connected to the emitter electrode by the contact hole. In any of the above semiconductor devices, a first trench bottom region of the first conductivity type having a higher concentration than the drift region may be provided at the bottom end of at least one of the trench portions sandwiching the hole extraction mesa portion.

[0005] In any of the above semiconductor devices, the multiple mesa portions may include floating mesa portions that do not have the contact hole provided above them, or in which the length of the contact hole above them in the extension direction is shorter than the length of the contact hole above the channel mesa portion.

[0006] In order to solve the above problem, another aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and including a first conductivity type drift region, a plurality of trenches extending from the upper surface toward the interior of the semiconductor substrate in an extension direction, a plurality of mesa regions sandwiched between two of the trenches, an emitter electrode provided above the upper surface of the semiconductor substrate, and an interlayer insulating film provided between the upper surface of the semiconductor substrate and the emitter electrode, with a contact hole formed therein. In any of the above semiconductor devices, the plurality of mesa regions may include a channel mesa portion having an emitter region of the first conductivity type provided on the upper surface of the semiconductor substrate and a base region of a second conductivity type provided between the emitter region and the drift region, and connected to the emitter electrode by the contact hole. In any of the semiconductor devices described above, the plurality of mesa portions may include floating mesa portions that do not have the contact hole provided thereover or that have a length of the contact hole provided thereover in the extension direction that is shorter than a length of the contact hole provided thereover in the channel mesa portion. In any of the semiconductor devices described above, a first trench bottom region of the first conductivity type that has a higher concentration than the drift region may be provided at a lower end of at least one of the trench portions that sandwich the floating mesa portion.

[0007] In any of the above semiconductor devices, a second trench bottom region of the second conductivity type having a higher concentration than the base region may be provided at the bottom end of at least one of the trench portions sandwiching the channel mesa portion.

[0008] In any of the above semiconductor devices, the trench portion may have a plurality of gate trench portions. In any of the above semiconductor devices, the plurality of mesa portions may include a first mesa portion sandwiched between two of the gate trench portions. In any of the above semiconductor devices, at least a portion of the first mesa portion may be the channel mesa portion.

[0009] In any of the above semiconductor devices, the trench portion may have a gate trench portion and a dummy trench portion. In any of the above semiconductor devices, the plurality of mesa portions may include a second mesa portion sandwiched between the gate trench portion and the dummy trench portion. In any of the above semiconductor devices, at least a portion of the second mesa portion may be the floating mesa portion.

[0010] In any of the above semiconductor devices, the trench portion may have a plurality of dummy trench portions. In any of the above semiconductor devices, the plurality of mesa portions may include a third mesa portion sandwiched between two of the dummy trench portions. In any of the above semiconductor devices, at least a portion of the third mesa portion may be the floating mesa portion.

[0011] In any of the above semiconductor devices, the trench portion may have a gate trench portion. In any of the above semiconductor devices, the plurality of mesa portions may include a second mesa portion sandwiched between the gate trench portion and the dummy trench portion. In any of the above semiconductor devices, the third mesa portion provided adjacent to the second mesa portion may be the floating mesa portion.

[0012] In any of the above semiconductor devices, the trench portion may have a gate trench portion. In any of the above semiconductor devices, the multiple mesa portions may include a second mesa portion sandwiched between the gate trench portion and the dummy trench portion. In any of the above semiconductor devices, the contact hole may be longer than the second mesa portion in at least a portion of the third mesa portion that is not adjacent to the second mesa portion.

[0013] In any of the above semiconductor devices, the floating mesa may have the contact hole provided outside the emitter region provided at the outermost position of the channel mesa in the extension direction.

[0014] In any of the above semiconductor devices, the floating mesa may have the contact hole provided on the inside of the emitter region provided on the outermost side of the channel mesa in the extension direction.

[0015] In any of the above semiconductor devices, the first trench bottom region may be provided at a lower end of the trench portion of at least one of the channel mesa portions.

[0016] In any of the above semiconductor devices, the first trench bottom region may be provided across the entire width of all the mesas.

[0017] In any of the above semiconductor devices, the trench portion may have a gate trench portion including two extension portions extending in the extension direction and a connection portion connecting ends of the two extension portions in a top view. In any of the above semiconductor devices, the trench portion may have a plurality of dummy trench portions provided in a region surrounded by the two extension portions and the connection portion.

[0018] In any of the above semiconductor devices, the trench portion may further include a gate trench portion that is provided between the extension portion that connects to one of the connection portions and the extension portion that connects to the other connection portion and is not connected to the connection portion.

[0019] The above summary of the invention does not list all of the necessary features of the present invention. In addition, subcombinations of these features may also constitute inventions.

[0020] 1 is a cross-sectional view showing an example of a semiconductor device 100 according to an embodiment of the present invention; FIG. 2 is a cross-sectional view showing a semiconductor device 200 according to a comparative example; FIG. 3 is a cross-sectional view showing another example of the semiconductor device 100 according to an embodiment of the present invention; FIG. 4 is a cross-sectional view showing a semiconductor device 300 according to a comparative example; FIG. 5 is a diagram showing turn-on waveforms of the semiconductor device 100 according to the embodiment and the semiconductor device 200 according to the comparative example; FIG. 6 is a diagram explaining self-charging of a gate trench portion 40; FIG. 7 is a top view showing an example of an active portion 120 of the semiconductor device 100 according to the embodiment; FIG. 8 is a top view showing another example of the active portion 120 of the semiconductor device 100 according to the embodiment; FIG. 9 is a top view showing an example of a termination portion 122 of the semiconductor device 100 according to the embodiment;

[0021] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0022] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0023] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0024] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0025] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0026] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0027] In this specification, the conductivity type of a doped region doped with impurities is described as p-type or n-type. Sometimes, n-type conductivity is referred to as the first conductivity type and p-type conductivity is referred to as the second conductivity type, but the corresponding conductivity types may be reversed. In this specification, impurities may particularly refer to either n-type donors or p-type acceptors, and may be referred to as dopants. In this specification, doping refers to introducing donors or acceptors into a semiconductor substrate to form a semiconductor exhibiting n-type conductivity or a semiconductor exhibiting p-type conductivity.

[0028] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N Ｄ , acceptor concentration is N Ａ Then, the net doping concentration at any position is N Ｄ -N Ａ In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0029] In this specification, when p+ type or n+ type is described, it means that the doping concentration is higher than that of p type or n type, and when p- type or n- type is described, it means that the doping concentration is lower than that of p type or n type. Furthermore, when p++ type or n++ type is described in this specification, it means that the doping concentration is higher than that of p+ type or n+ type. The unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0030] FIG. 1 is a cross-sectional view showing an example of a semiconductor device 100 according to an embodiment of the present invention. In this specification, an example will be described in which the semiconductor device 100 is provided with an IGBT (Insulated Gate Bipolar Transistor) as a transistor element. However, the semiconductor device 100 may also be provided with a MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor). In FIG. 1, only some components of the semiconductor device 100 are shown, and other components are omitted.

[0031] The semiconductor device 100 includes a semiconductor substrate 10, an interlayer insulating film 38, and an emitter electrode 52. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has an upper surface 21. FIG. 1 shows the configuration of the upper surface 21 side of the semiconductor substrate 10, and does not illustrate the lower surface side.

[0032] The interlayer insulating film 38 is provided between the upper surface 21 of the semiconductor substrate 10 and the emitter electrode 52. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. A contact hole 54 is formed in the interlayer insulating film 38. The contact hole 54 is a through-hole that penetrates the interlayer insulating film 38.

[0033] The emitter electrode 52 is provided above the upper surface 21 of the semiconductor substrate 10. In this example, the emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is connected to the upper surface 21 of the semiconductor substrate 10 via a contact hole 54. The emitter electrode 52 is, for example, an aluminum-silicon alloy.

[0034] An n-type drift region 18 is provided in the semiconductor substrate 10. The drift region 18 may be a region that remains without doping the semiconductor substrate 10. Although not shown, a collector region of a second conductivity type is provided on the lower surface side of the semiconductor substrate 10 in contact with the lower surface. A collector electrode is also provided in contact with the collector region. A field stop layer (FS layer) of a first conductivity type having a higher impurity concentration than the drift region 18 may be provided between the drift region 18 and the collector region.

[0035] The semiconductor substrate 10 has a plurality of trenches extending inward from the upper surface 21 of the semiconductor substrate 10. The trenches may include gate trenches 40 and dummy trenches 30. The gate trenches 40 are trenches to which a gate voltage is applied. The dummy trenches 30 are connected to an emitter electrode 52 in other cross sections. In FIG. 1 and the following figures, the gate trenches are indicated as G and the dummy trenches are indicated as E. In FIG. 1, the trenches are hatched.

[0036] The trench portion in this example has a plurality of gate trench portions 40 and a plurality of dummy trench portions 30. The trench portions are arranged in an arrangement direction (X-axis direction) and extend in an extension direction (Y-axis direction). In FIG. 1, three gate trench portions 40 and four dummy trench portions are arranged periodically.

[0037] A mesa portion 60 is provided between each trench portion in the arrangement direction. The mesa portion 60 refers to a region inside the semiconductor substrate 10 that is sandwiched between two trench portions. As an example, the upper end of the mesa portion 60 is the upper surface 21 of the semiconductor substrate 10. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion 60 is provided on the upper surface 21 of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench portion.

[0038] The semiconductor substrate 10 of this example is provided with a plurality of mesas 60. The plurality of mesas 60 include a channel mesa 60-1, a floating mesa 60-2, and a hole-punching mesa 60-3.

[0039] The channel mesa portion 60-1 has an n+ type emitter region 12 and a p-type base region 14. The emitter region 12 and the base region 14 are provided in this order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. The channel mesa portion 60 may also be provided with an n+ type accumulation region 16. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0040] The emitter region 12 is a first conductivity type region provided on the upper surface 21 of the semiconductor substrate 10. The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the channel mesa portion 60-1. The emitter region 12 has a higher doping concentration than the drift region 18.

[0041] The base region 14 is a region of the second conductivity type provided between the emitter region 12 and the drift region 18. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the channel mesa portion 60-1.

[0042] The accumulation region 16 is a first conductivity type region provided between the base region 14 and the drift region 18. The accumulation region 16 is an n+ type region with a higher doping concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the collector-emitter saturation voltage Vce(sat) can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in the channel mesa portion 60.

[0043] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and further inside than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0044] The gate trench portion 40 may be provided to be longer in the depth direction than the base region 14. The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40. As a result, a main current flows between the emitter electrode 52 and the collector electrode (not shown).

[0045] The dummy trench portion 30 may have a structure similar to that of the gate trench portion 40 in the cross section. That is, the dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52 in another cross section. The dummy insulating film 32 covers the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44.

[0046] In this example, the gate trench 40 and the dummy trench 30 are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench 30 and the gate trench 40 may have a downwardly convex curved shape (a curved shape in cross section). In this specification, the depth position of the lower end 46 of the gate trench 40 is designated Zt. The depth position of the lower end 46 of the gate trench 40 may be the same as the depth position of the lower end 36 of the dummy trench 30.

[0047] The channel mesa portion 60-1 is connected to the emitter electrode 52 via a contact hole 54. The channel mesa portion 60-1 may be a mesa portion 60 that is connected to the emitter electrode 52, has an emitter region 12 provided therein, and at least one of the trench portions sandwiching the mesa portion 60 is a gate trench portion 40. The channel mesa portion 60-1 may be sandwiched between two gate trench portions 40.

[0048] The floating mesa portion 60-2 has a base region 14 and an accumulation region 16. The floating mesa portion 60-2 may or may not have an emitter region 12. In this example, two floating mesa portions 60-2 are provided consecutively adjacent to the channel mesa portion 60-1.

[0049] The floating mesa portion 60-2 does not have a contact hole 54 above it, or the length of the contact hole 54 above it in the extension direction (Y-axis direction) is shorter than the length of the contact hole 54 above the channel mesa portion 60-1. In the cross section shown in Figure 1, no contact hole 54 is provided above the floating mesa portion 60-2. By providing the floating mesa portion 60-2, holes tend to accumulate more easily when the semiconductor device 100 is turned on.

[0050] The hole extraction mesa portion 60-3 has a base region 14 and an accumulation region 16. The hole extraction mesa portion 60-3 may or may not have an emitter region 12. The hole extraction mesa portion 60-3 of this example is provided next to the floating mesa portion 60-2.

[0051] The hole extraction mesa portion 60-3 is a mesa portion 60 in which no channel is formed and which is connected to the emitter electrode 52 via a contact hole 54. The hole extraction mesa portion 60-3 extracts holes injected from the lower surface side when the semiconductor device 100 is turned on. The hole extraction mesa portion 60-3 may be a mesa portion 60 which is connected to the emitter electrode 52 and which is not provided with an emitter region 12. The hole extraction mesa portion 60-3 may be a mesa portion which is connected to the emitter electrode 52 and which is sandwiched between dummy trench portions 30. The multiple mesas 60 may include at least one of a channel mesa portion 60-1, a floating mesa portion 60-2, and a hole extraction mesa portion 60-3, or may include any two of them.

[0052] The semiconductor device 100 of this example includes a first trench bottom region 202 of a first conductivity type provided at the lower end of the trench portion. The first trench bottom region 202 is an n-type region with a higher concentration than the drift region 18. The first trench bottom region 202 may be provided at the lower end of at least one of the trench portions that sandwich the hole extraction mesa portion 60-3. In FIG. 1 , the first trench bottom region 202 is provided at each of the lower ends 36 of the two dummy trench portions 30 that sandwich the hole extraction mesa portion 60-3.

[0053] The lower end 36 of the dummy trench portion 30 refers to the portion of the dummy trench portion 30 that is farthest from the upper surface 21 of the semiconductor substrate 10. In the example of FIG. 1, the lower end 36 of the dummy trench portion 30 is disposed at the center of the dummy trench portion 30 in the X-axis direction. Furthermore, the lower end 46 of the gate trench portion 40 refers to the portion of the gate trench portion 40 that is farthest from the upper surface 21 of the semiconductor substrate 10. In the example of FIG. 1, the lower end 46 of the gate trench portion 40 is disposed at the center of the gate trench portion 40 in the X-axis direction.

[0054] When the semiconductor device 100 is turned on, holes flow from the lower surface toward the upper surface 21. Because the channel mesa portion 60-1 is subjected to the gate voltage of the gate trench portion 40, holes are less likely to flow toward the channel mesa portion 60-1 and more likely to flow toward the hole extraction mesa portion 60-3. By providing the first trench bottom region 202 in the hole extraction mesa portion 60-3, holes are less likely to escape from the hole extraction mesa portion 60-3 and are more likely to accumulate. The accumulated holes generate a displacement current, which will be described later, and the gate voltage rises (self-charging), thereby making the dI / dt at turn-on faster. As a result, the loss generated at turn-on can be significantly reduced.

[0055] The first trench bottom region 202 may be provided at the lower end of at least one of the trench portions sandwiching the floating mesa portion 60-2. In FIG. 1, the first trench bottom region 202 is provided at the lower end 36 of one of the dummy trench portions 30 sandwiching the floating mesa portion 60-2. Specifically, the first trench bottom region 202 is provided at the lower end 36 of the dummy trench portion 30 located at the boundary between the floating mesa portion 60-2 and the hole-removing mesa portion 60-3. By providing the first trench bottom region 202 in the floating mesa portion 60-2, it is possible to prevent holes from moving toward the hole-removing mesa portion 60-3, making it easier for holes to accumulate.

[0056] At least a portion of the first trench bottom region 202 may be located at a position overlapping the lower end of the trench portion in a top view and may be located lower than the lower end in the Z-axis direction. The first trench bottom region 202 may include a portion that does not overlap with the lower end in a top view. The first trench bottom region 202 may include a portion that is located higher than the lower end. The first trench bottom region 202 is in contact with the lower end. In the example of FIG. 1 , the first trench bottom region 202 is in contact with the entire curved portion, including the lower end 36, of the dummy trench portion 30. The first trench bottom region 202 may be formed by implanting an n-type dopant near the lower end of the trench structure after forming the trench structure of the trench portion and before forming the conductive portion.

[0057] The first trench bottom region 202 is electrically floating with respect to electrodes such as the emitter electrode 52, the gate conductive portion 44, and the collector electrode. At least one of a p-type region and an insulating film is disposed between the first trench bottom region 202 and the electrode. In other words, the first trench bottom region 202 and the electrode are not connected only by an n-type region and a conductive material. The doping concentration of the first trench bottom region 202 may be lower than the doping concentration of the accumulation region 16. For example, the doping concentration of the first trench bottom region 202 is 1×10 １５ cm －３ That's it, 1 x 10 １７ cm －３ The following is the result.

[0058] The first trench bottom region 202 is disposed apart from the base region 14 and the accumulation region 16. In this example, the drift region 18 is provided between the first trench bottom region 202 and the accumulation region 16.

[0059] The semiconductor device 100 has one or more first trench bottom regions 202. The semiconductor device 100 may have a plurality of first trench bottom regions 202. The first trench bottom region 202 may be provided in at least one trench portion, the first trench bottom region 202 may be provided in 10% or more of the trench portion, the first trench bottom region 202 may be provided in 20% or more of the trench portion, or the first trench bottom region 202 may be provided in 50% or less of the trench portion.

[0060] If a trench portion having a first trench bottom region 202 at its lower end is defined as a corresponding trench portion, each first trench bottom region 202 may or may not extend to below the lower end of the trench portion (dummy trench portion 30 in this example) arranged adjacent to the corresponding trench portion. Each first trench bottom region 202 may or may not contact the adjacent trench portion.

[0061] The mesa 60 adjacent to the channel mesa 60-1 across the gate trench 40 may be a floating mesa 60-2. The floating mesa 60-2 may be sandwiched between the gate trench 40 and the dummy trench 30 (GE floating in the figure). This reduces the gate-emitter capacitance Cge and increases the gate-collector capacitance Cgc. As a result, the time change (dVce / dt) of the collector-emitter voltage Vce at turn-on is gradual, thereby reducing the gate resistance Rg when the magnitude of dVce / dt is uniform, thereby reducing turn-on loss. Furthermore, since dI / dt at turn-on increases, the drop in Vce due to L (circuit inductance) × dI / dt increases. This also reduces turn-on loss.

[0062] The mesa 60 adjacent to the floating mesa 60-2 and provided on the opposite side to the channel mesa 60-1 may be the floating mesa 60-2. The floating mesa 60-2 may be sandwiched between two dummy trenches (EE floating in the figure). This enhances the IE effect and reduces Vce(sat).

[0063] The semiconductor device 100 may include a second trench bottom region 204 of the second conductivity type provided at the lower end of the trench portion. The second trench bottom region 204 is a p-type region with a higher concentration than the base region 14. The second trench bottom region 204 may be provided at the lower end of at least one of the trench portions sandwiching the channel mesa portion 60-1. In FIG. 1 , the second trench bottom region 204 is provided at the lower end 46 of one of the gate trench portions 40 sandwiching the channel mesa portion 60-1. Specifically, the second trench bottom region 204 is provided at the lower end 46 of the gate trench portion 40 located at the boundary between the channel mesa portion 60-1 and the floating mesa portion 60-2.

[0064] By providing the second trench bottom region 204, the electric field at the lower end 46 of the gate trench portion 40 can be alleviated. Therefore, a breakdown voltage can be ensured even when the first trench bottom region 202 is formed. Furthermore, when the second trench bottom region 204 is provided, the gate potential near the lower end 46 of the gate trench portion 40 is less likely to increase. However, in the semiconductor device 100 of this example, self-charging of the gate occurs due to the accumulation of holes as described above, so the gate potential near the lower end 46 can be increased and Vce(sat) can be reduced.

[0065] The second trench bottom region 204 may be provided at the lower end 46 of the gate trench portion 40. The first trench bottom region 202 may be provided at the lower end 36 of the dummy trench portion 30. However, the second trench bottom region 204 does not have to be provided. The second trench bottom region 204 does not have to be provided at the lower end 46 of the gate trench portion 40 that sandwiches the channel mesa portion 60-1.

[0066] Similar to the first trench bottom region 202, the second trench bottom region 204 may be formed by implanting a p-type dopant near the bottom end of the trench structure after forming the trench structure and before forming the conductive portion. However, of the three gate trench portions 40 arranged in succession, the p-type dopant does not need to be implanted into the bottom end 46 of the central gate trench portion 40.

[0067] The second trench bottom region 204 may not be in contact with the base region 14 and the accumulation region 16. The second trench bottom region 204 may or may not extend below the lower ends of the trench portions (in this example, the gate trench portion 40 and the dummy trench portion 30) adjacent to the corresponding trench portion. The second trench bottom region 204 and the first trench bottom region 202 may or may not be in contact with each other in the X-axis direction. The second trench bottom region 204 may be provided in each of two adjacent mesa portions 60, and the respective second trench bottom regions 204 may not be connected to each other. The doping concentration of the second trench bottom region 204 may be the same as the doping concentration of the first trench bottom region 202.

[0068] 2 is a cross-sectional view showing a semiconductor device 200 according to a comparative example. In FIG. 2, the underside of the semiconductor substrate 10 is also omitted. Furthermore, descriptions of portions similar to those in FIG. 1 will be omitted. In the semiconductor device 200 of this example, one gate trench portion 40 and two dummy trench portions 30 are periodically arranged. Furthermore, all of the mesa portions 60 are connected to the emitter electrode 52, and no floating mesa portion 60-2 is provided.

[0069] The semiconductor device 200 of this embodiment has a second trench bottom region 204 at the lower end 46 of the gate trench portion 40. In this case, the gate potential near the lower end 46 of the gate trench portion 40 is less likely to rise. The semiconductor device 200 of this embodiment does not have a first trench bottom region 202 or a floating mesa portion 60-2. Therefore, self-charging of the gate due to hole accumulation does not occur. As a result, the dI / dt at turn-on is slower than in the semiconductor device 100 of the embodiment, resulting in increased turn-on loss. Furthermore, the gate potential near the lower end 46 does not rise sufficiently, resulting in an increase in Vce(sat).

[0070] 3 is a cross-sectional view showing another example of a semiconductor device 100 according to an embodiment of the present invention. In FIG. 3, the underside of the semiconductor substrate 10 is also omitted. Furthermore, descriptions of portions similar to those in FIG. 1 will be omitted. In the semiconductor device 100 of this example, two gate trenches 40 and four dummy trenches 30 are periodically arranged. In this example, an emitter region 12 is provided in the channel mesa 60-1, floating mesa 60-2, and hole extraction mesa 60-3.

[0071] In the semiconductor device 100, a first trench bottom region 202 may be provided at the bottom end of at least one trench portion of the channel mesa portion 60-1. In the semiconductor device 200 of this example, the first trench bottom region 202 is provided across the entire width of all mesa portions 60. Even with this arrangement of the first trench bottom regions 202, the same effect as in the case of FIG. 1 can be obtained. Furthermore, since the first trench bottom region 202 is provided at the bottom end of all trench portions, the uniformity of the breakdown voltage is improved. A drift region 18 may be provided between the first trench bottom region 202 and the accumulation region 16.

[0072] 4 is a cross-sectional view showing a semiconductor device 300 according to a comparative example. The semiconductor device 300 of this example does not have the first trench bottom region 202 or the floating mesa portion 60-2. Therefore, the dI / dt at turn-on is smaller than that of the semiconductor device 100 shown in FIG. 3, resulting in larger turn-on loss.

[0073] 5 is a diagram showing turn-on waveforms of the semiconductor device 100 according to the embodiment and the semiconductor device 200 according to the comparative example. The diagram shows Vce and collector current Ic, with the solid line indicating the waveform of the embodiment and the dotted line indicating the waveform of the comparative example.

[0074] As described above, in the embodiment, self-charging of the gate due to hole accumulation occurs, resulting in a large dI / dt. Furthermore, the above-mentioned GE floating increases Cgc, resulting in a large dI / dt. This increases the drop in Vce due to L·dI / dt. As a result, the turn-on loss can be significantly reduced.

[0075] 6 is a diagram illustrating self-charging of the gate trench portion 40. FIG. 6 is an enlarged view of one channel mesa portion 60-1, two floating mesa portions 60-2, and one hole extraction mesa portion 60-3 of the semiconductor device 100 in FIG.

[0076] The arrows indicated by dashed dotted lines in the figure indicate the flow of holes during turn-on. Holes flowing from the lower surface toward the upper surface 21 avoid the gate trench portion 40, which is at a high potential, and pass under the floating mesa portion 60-2 to the hole extraction mesa portion 60-3. At this time, the flow of holes is restricted by the floating mesa portion 60-2, the first trench bottom region 202, and the accumulation region 16, making it easier for holes to accumulate. Holes accumulate in the floating mesa portion 60-2 adjacent to the channel mesa portion 60-1, generating a displacement current toward the gate trench portion 40. This causes the gate trench portion 40 to self-charge, increasing dI / dt. Furthermore, the gate potential near the bottom end 46 is more likely to rise. In the depth direction, at least a portion of the first trench bottom region 202 may overlap with the gate conductive portion 44.

[0077] 1 and 3, the mesa portion 60 sandwiched between two gate trench portions 40 is referred to as a first mesa portion. Similarly, the mesa portion 60 sandwiched between the gate trench portion 40 and the dummy trench portion 30 is referred to as a second mesa portion, and the mesa portion 60 sandwiched between two dummy trench portions 30 is referred to as a third mesa portion. In other words, the multiple mesa portions 60 include a first mesa portion, a second mesa portion, and a third mesa portion.

[0078] At least a portion of the first mesa portion may be the channel mesa portion 60-1. All of the first mesa portions may be the channel mesa portion 60-1. The first trench bottom region 202 may be provided across the entire width direction (X-axis direction) of at least a portion of the first mesa portion. The first trench bottom region 202 may also be provided at the lower end 46 of the gate trench portion 40. However, the first mesa portion does not have to be provided. In this case, at least a portion of the second mesa portion becomes the channel mesa portion 60-1.

[0079] At least a portion of the second mesa portion may be a floating mesa portion 60-2. All of the second mesa portions may be floating mesa portions 60-2. The first trench bottom region 202 may be provided across the entire width direction (X-axis direction) of at least a portion of the second mesa portion. At least a portion of the first mesa portion may be a floating mesa portion 60-2. The second mesa portion provided adjacent to the first mesa portion may be a floating mesa portion 60-2 (GE floating). This makes it possible to reduce turn-on loss, as described above.

[0080] At least a portion of the third mesa portion may be a floating mesa portion 60-2. All of the third mesa portions may be floating mesa portions 60-2. The first trench bottom region 202 may be provided across the entire width direction (X-axis direction) of at least a portion of the third mesa portion. The third mesa portion provided adjacent to the second mesa portion may be a floating mesa portion 60-2 (EE floating). This enhances the IE effect and reduces Vce(sat). The third mesa portion may be in contact with the emitter electrode 52 via a contact hole 54. No contact hole may be provided above the third mesa portion. A portion of the third mesa portion may be a hole-punched mesa portion 60-3.

[0081] 7 is a top view showing an example of an active portion 120 of the semiconductor device 100 according to the embodiment. The semiconductor device 100 shown in FIG. 7 is a top view of the semiconductor device 100 shown in FIG. 1. The active portion 120 may be a region in the semiconductor device 100 through which a main current flows, and may be a portion located inside an emitter region 12 provided at the outermost position of a channel mesa portion 60-1 in the extension direction (Y-axis direction) of a trench portion (described later). FIG. 7 shows a portion of the active portion 120. The emitter electrode 52 and the interlayer insulating film 38 are also omitted.

[0082] The gate trench portion 40 and the dummy trench portion 30 extend in the extension direction. In addition to the emitter region 12, the channel mesa portion 60-1 is provided with a contact region 15. The contact region 15 is a p+ type region with a higher doping concentration than the base region 14. In this example, the emitter region 12 and the contact region 15 are provided alternately in the extension direction of the gate trench portion 40.

[0083] A contact hole 54 is provided above the channel mesa portion 60-1. In Fig. 7, the position where the contact hole 54 is provided is hatched. The contact hole 54 above the channel mesa portion 60-1 may be provided so as to cross the active portion 120. In this specification, the contact hole 54 above the channel mesa portion 60-1 may be referred to as a contact hole 54-1.

[0084] The base region 14 is exposed on the upper surface of the floating mesa portion 60-2. In the active portion 120, no contact hole 54 is provided above the floating mesa portion 60-2 in this example. The base region 14 is exposed on the upper surface of the hole-removing mesa portion 60-3. A contact hole 54 is provided above the hole-removing mesa portion 60-3. The contact hole 54 above the hole-removing mesa portion 60-3 may also be provided so as to cross the active portion 120. In this specification, the contact hole 54 above the hole-removing mesa portion 60-3 may be referred to as a contact hole 54-3. Neither a contact region 15 nor an emitter region 12 is provided in the hole-removing mesa portion 60-3. However, the contact region 15 and the emitter region 12 may be provided in the hole-removing mesa portion 60-3.

[0085] 8 is a top view showing another example of the active portion 120 of the semiconductor device 100 according to the embodiment. The semiconductor device 100 of this example differs from the semiconductor device 100 shown in FIG. 7 in the configurations of the floating mesa portion 60-2 and the hole-removing mesa portion 60-3. The hole-removing mesa portion 60-3 of this example is provided with a contact region 15.

[0086] In this example, a contact hole 54 is provided above the floating mesa portion 60-2. In this specification, the contact hole 54 above the floating mesa portion 60-2 may be referred to as a contact hole 54-2. The contact hole 54-2 is provided inside the emitter region 12 provided at the outermost position of the channel mesa portion 60-1 in the extension direction described below. In other words, the contact hole 54-2 is provided in the active portion. If the contact hole 54-2 is not provided above the floating mesa portion 60-2, the dI / dt may become too large. By providing the contact hole 54-2 above the floating mesa portion 60-2, the magnitude of dI / dt can be adjusted.

[0087] The length d1 of the contact hole 54-2 may be shorter than the length d2 of the contact hole 54-3. The floating mesa 60-2 in which the contact hole 54-2 is provided may be the second mesa or the third mesa.

[0088] At least a portion of the third mesa portion not adjacent to the second mesa portion may be provided with a contact hole 54 longer than the second mesa portion. In this example, the third mesa portion is the hole-opening mesa portion 60-3. The third mesa portion does not have to be the floating mesa portion 60-2. The length d2 of the contact hole 54-3 in the hole-opening mesa portion 60-3, which is the third mesa portion, may be longer than the length d1 of the contact hole 54-2 in the floating mesa portion 60-2, which is the second mesa portion. The phrase "length d2 being longer than length d1" may include the case where length d1 is zero (i.e., no contact hole 54-2 is provided). The same applies to the following length relationships. Length d1 may be half or less of length d2, or may be 10% or less, or may be 5% or less.

[0089] The length d1 may be shorter than the length d3 of the contact hole 54-1. The length d1 may be half or less of the length d3, 10% or less, or 5% or less. The lengths d2 and d3 may be equal. The contact holes 54-1 and 54-3 may extend further in the Y-axis direction than the active section 120 shown in FIGS. 7 and 8. In this case, the ends of the lengths d2 and d3 are also located outside the active section 120 shown in FIGS. 7 and 8.

[0090] At least one of the floating mesa portions 60-2 may be provided with a contact hole 54-2, while the other floating mesas 60-2 may not be provided with a contact hole 54-2. Furthermore, a plurality of contact holes 54-2 may be provided in the extension direction of the same floating mesa portion 60-2. In this case, the length d1 may be the sum of the lengths of the plurality of contact holes 54-2.

[0091] 9 is a top view showing an example of a termination portion 122 of the semiconductor device 100 according to the embodiment. The semiconductor device 100 shown in FIG. 9 is a top view of the semiconductor device 100 shown in FIG. 7. The termination portion 122 is a portion located outside the emitter region 12 provided at the outermost position of the channel mesa portion 60-1 in the extension direction (Y-axis direction). The emitter region 12 is shown in the channel mesa portion 60-1 in FIG.

[0092] 9 shows the area where the emitter electrode 52 is provided and the area where the gate wiring 131 is provided. The gate wiring 131 is a wiring that transmits a gate voltage to the gate conductive portion 44. In the terminal portion 122, the dummy trench portion 30 and the emitter electrode 52 are connected via a contact hole 54. In the terminal portion 122, the gate trench portion 40 and the gate wiring 131 are connected via a contact hole 54. However, the dummy trench portion 30 may be connected to the emitter electrode 52 via the contact hole 54 in the active portion 120. In a plan view, the contact hole 54 connected to the dummy trench portion 30 is not adjacent to the contact hole 54 connected to the gate trench portion 40. In other words, the contact hole 54 connected to the dummy trench portion 30 and the contact hole 54 connected to the gate trench portion 40 are located at different positions in the extension direction.

[0093] The gate trench portion 40 includes two extension portions 41 extending in the extension direction and a connection portion 43 connecting the ends of the two extension portions 41 in a top view. Similarly, the dummy trench portion 30 includes two extension portions 31 extending in the extension direction and a connection portion 33 connecting the ends of the two extension portions 31 in a top view. By providing the connection portions 43 and 33, the mesa portion 60 can be made floating. In this example, the termination portion 122 is provided with a base region 14, and the base region 14 is connected to an emitter electrode in another region, for example, and is at emitter potential. However, by providing the connection portions 43 and 33, the mesa portion 60 can be made floating. In other words, the base region 14 surrounded by the connection portions and extension portions is separated from the base region 14 outside the termination portion 122 by the connection portions and extension portions.

[0094] The connection portion 43 and the connection portion 33 may be provided in the termination portion 122. The extension portion 41 and the extension portion 31 extend from the active portion 120 to the termination portion 122. The ends of the two trench portions (extension portions) that sandwich the floating mesa portion 60-2 may be connected by a connection portion, or may be connected to different connection portions.

[0095] The ends of the two trench portions (extension portions) sandwiching the hole extraction mesa portion 60-3 may be connected by a connection portion. That is, the base region 14 of the hole extraction mesa portion 60-3 may be separated from the base region 14 of the floating mesa portion 60-2. Since the base region 14 of the hole extraction mesa portion 60-3 is connected to the emitter electrode 52, separating it from the base region 14 of the floating mesa portion 60-2 allows the floating mesa portion 60-2 to be floating.

[0096] In this example, the dummy trench portion 30 is provided in a region surrounded by the two extension portions 41 and the connection portion 43. Both the extension portion 31 and the connection portion 33 of the dummy trench portion 30 may be provided in the region surrounded by the two extension portions 41 and the connection portion 43. A plurality of dummy trench portions 30 may be provided in the region surrounded by the two extension portions 41 and the connection portion 43. Furthermore, another dummy trench portion 30 may be provided in the region surrounded by the two extension portions 31 and the connection portion 33 of the dummy trench portion 30, or both the extension portion 31 and the connection portion 33 of another dummy trench portion 30 may be provided, or a plurality of dummy trench portions 30 may be provided.

[0097] The trench portion may have a gate trench portion 40 that is provided between an extension portion that connects to one connection portion and an extension portion that connects to another connection portion, and that is not connected to the connection portion 43. In this example, the gate trench portion 40 located in the center in the X-axis direction in Figure 9 is a gate trench portion 40 that is provided between an extension portion 41 that connects to one connection portion 43 and an extension portion 41 that connects to the other connection portion 43, and that is not connected to the connection portion 43. The gate trench portion 40 may be a gate trench portion 40 that sandwiches the channel mesa portion 60-1.

[0098] FIG. 10 is a top view showing another example of the termination portion 122 of the semiconductor device 100 according to the embodiment. The semiconductor device 100 shown in FIG. 10 is a top view of the semiconductor device 100 shown in FIG. 8. In the floating mesa portion 60-2 of the semiconductor device 100 of this example, a contact hole 54-2 is provided outside the outermost emitter region 12 of the channel mesa portion 60-1 in the extension direction. That is, in the termination portion 122, the contact hole 54-2 is provided above the floating mesa portion 60-2. This allows the magnitude of dI / dt to be adjusted. In the top view of FIG. 10, the contact hole 54-1 provided in the channel mesa portion 60-1 and the contact hole 54-2 provided in the floating mesa portion 60-2 are arranged so as not to be adjacent to the contact holes 54 connecting to the dummy trench portion 30 and the gate trench portion 40. In other words, the contact holes 54-1 and 54-2 are provided at positions different from the contact holes 54 provided in the dummy trench portion 30 and the gate trench portion 40 in the trench extension direction.

[0099] The length d1 of the contact hole 54-2 in the terminal portion 122 may be shorter than the length d2 of the contact hole 54-3 and the length d3 of the contact hole 54-1. The contact hole 54-2 in the terminal portion 122 does not have to extend to the active portion 120. Note that although only one terminal portion 122 in the extension direction is shown in FIGS. 9 and 10, the other terminal portion may have the same length.

[0100] The contact hole 54-2 may be provided in both the termination portion 122 and the active portion 120. When the contact hole 54-2 is provided in the same floating mesa portion 60-2, the length d1 of the contact hole 54-2 may be the sum of the lengths of the contact hole 54-2 in the termination portion 122 and the contact hole 54-2 in the active portion 120.

[0101] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. For example, if the gate potential trench does not contact the emitter region 12, it can be considered a dummy trench portion 30. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0102] 10...Semiconductor substrate, 12...Emitter region, 14...Base region, 15...Contact region, 16...Accumulation region, 18...Drift region, 21...Upper surface, 30...Dummy trench portion, 31...Extension portion, 32...Dummy insulating film, 33...Connection portion, 34...Dummy conductive portion, 36...Lower end, 38...Interlayer insulating film, 40...Gate trench portion, 41...Extension portion, 42...Gate insulating film, 43...Connection portion, 44... Gate conductive portion, 46... lower end, 52... emitter electrode, 54... contact hole, 60... mesa portion, 60-1... channel mesa portion, 60-2... floating mesa portion, 60-3... hole-punched mesa portion, 100... semiconductor device, 120... active portion, 122... termination portion, 131... gate wiring, 200... semiconductor device, 202... first trench bottom region, 204... second trench bottom region, 300... semiconductor device

Claims

1. A semiconductor substrate having an upper surface and provided with a first conductivity type drift region, The semiconductor substrate is provided with a plurality of trench portions extending inward from the upper surface and extending in the stretching direction, Multiple mesa portions, which are regions sandwiched between the two trench portions, An emitter electrode provided above the upper surface of the semiconductor substrate, An interlayer insulating film is provided between the upper surface of the semiconductor substrate and the emitter electrode, and a contact hole is formed between them. Equipped with, The multiple mesa portions are, The semiconductor substrate has an emitter region of a first conductivity type provided on its upper surface and a base region of a second conductivity type provided between the emitter region and the drift region, and a channel mesa portion connected to the emitter electrode by the contact hole, A hole-less mesa portion in which no channel is formed and which is connected to the emitter electrode by the contact hole and Includes, At least one of the lower ends of the trench portions sandwiching the hole-removing mesa portion is provided with a first trench bottom region of a first conductivity type having a higher concentration than the drift region. Semiconductor equipment.

2. The multiple mesa portions include floating mesa portions that do not have the contact holes above them, or in which the length of the upper contact holes in the extending direction is shorter than the length of the upper contact holes in the channel mesa portion. The semiconductor device according to claim 1.

3. A semiconductor substrate having an upper surface and provided with a first conductivity type drift region, The semiconductor substrate is provided with a plurality of trench portions extending inward from the upper surface and extending in the stretching direction, Multiple mesa portions, which are regions sandwiched between the two trench portions, An emitter electrode provided above the upper surface of the semiconductor substrate, An interlayer insulating film is provided between the upper surface of the semiconductor substrate and the emitter electrode, and a contact hole is formed between them. Equipped with, The multiple mesa portions are, The semiconductor substrate has an emitter region of a first conductivity type provided on its upper surface and a base region of a second conductivity type provided between the emitter region and the drift region, and a channel mesa portion connected to the emitter electrode by the contact hole, Either the upper contact hole is not provided, or the length of the upper contact hole in the extending direction is shorter than the length of the upper contact hole in the channel mesa portion, and Includes, At least one of the trench portions sandwiching the floating mesa portion is provided at the lower end of the first trench bottom region, which has a higher concentration of a first conductivity type than the drift region. Semiconductor equipment.

4. At least one of the trenches sandwiching the channel mesa is provided at the lower end of the trench, which is provided with a second trench bottom region of a second conductivity type having a higher concentration than the base region. The semiconductor device according to any one of claims 1 to 3.

5. The trench section has a plurality of gate trench sections, The multiple mesa portions include a first mesa portion sandwiched between the two gate trench portions. At least a portion of the first mesa portion is the channel mesa portion. The semiconductor device according to any one of claims 1 to 3.

6. The trench section has a gate trench section and a dummy trench section. The multiple mesa portions include a second mesa portion sandwiched between the gate trench portion and the dummy trench portion. At least a portion of the second mesa portion is the floating mesa portion. The semiconductor device according to claim 2 or 3.

7. The trench section has multiple dummy trench sections, The multiple mesa portions include a third mesa portion sandwiched between the two dummy trench portions. At least a portion of the third mesa portion is the floating mesa portion. The semiconductor device according to claim 2 or 3.

8. The trench section has a gate trench section, The multiple mesa portions include a second mesa portion sandwiched between the gate trench portion and the dummy trench portion. The third mesa section, located next to the second mesa section, is the floating mesa section. The semiconductor device according to claim 7.

9. The trench section has a gate trench section, The multiple mesa portions include a second mesa portion sandwiched between the gate trench portion and the dummy trench portion. At least a portion of the third mesa portion that is not adjacent to the second mesa portion is provided with a contact hole that is longer than the second mesa portion. The semiconductor device according to claim 7.

10. The floating mesa portion has contact holes located outside the emitter region, which is the outermost part of the channel mesa portion in the stretching direction. The semiconductor device according to claim 2 or 3.

11. The floating mesa portion has contact holes located inside the emitter region, which is located on the outermost side of the channel mesa portion in the stretching direction. The semiconductor device according to claim 2 or 3.

12. The first trench bottom region is provided at the lower end of at least one of the trench portions of the channel mesa portion. The semiconductor device according to claim 1 or 2.

13. The first trench bottom region is provided over the entire width of all the mesa portions. The semiconductor device according to claim 12.

14. The trench section is A gate trench portion including two extending portions extending in the aforementioned extension direction and a connecting portion that connects the ends of the two extending portions in a top view, Multiple dummy trench sections are provided in the region surrounded by the two extension sections and the connecting section. A semiconductor device according to claim 1 or 2, having the following features.

15. The trench section is The device further comprises an extension portion connected to one of the connection portions and a gate trench portion provided between the extension portion connected to another connection portion, which is not connected to the connection portion. The semiconductor device according to claim 14.

16. The lower end of the trench portion where the first trench bottom region is provided is the portion of the trench portion that is furthest from the upper surface of the semiconductor substrate. The semiconductor device according to any one of claims 1 to 3.

17. The hole-punched mesa portion has a second conductivity type base region provided between the upper surface of the semiconductor substrate and the drift region, The base region of the hole-punching mesa portion is in contact with the trench portion that sandwiches the hole-punching mesa portion. The base region of the channel mesa portion is in contact with the trench portion that sandwiches the channel mesa portion. The first trench bottom region is separated from the base region of the channel mesa portion and the base region of the hole-punched mesa portion. The semiconductor device according to claim 1 or 2.

18. The first trench bottom region is provided at least in the floating mesa portion. The semiconductor device according to claim 2 or 3.

19. The plurality of mesa portions include the plurality of floating mesa portions, Multiple floating mesa sections are provided between the channel mesa section and the hole-removing mesa section. The semiconductor device according to claim 2.