Semiconductor device and power conversion device

Abstract

A semiconductor device (100) comprises a substrate (1), a semiconductor element (2), and a wiring layer (3). The substrate (1) has a first main surface (10a). The semiconductor element (2) is disposed on the first main surface (10a). The semiconductor element (2) is provided with an electrode (21). The wiring layer (3) is connected to the electrode (21). The wiring layer (3) includes a high thermal conductivity layer (32) and a high conductivity layer (31). The high conductivity layer (31) is laminated on the high thermal conductivity layer (32). The lamination direction of the high thermal conductivity layer (32) and the high conductivity layer (31) is a direction perpendicular to the extension direction of the wiring layer (3) in a plan view of the first main surface (10a).

Description

Semiconductor device and power conversion device

[0001] The present disclosure relates to a semiconductor device and a power conversion device.

[0002] Cooling of the element is important for semiconductor devices using power semiconductor elements (hereinafter referred to as elements), which pass the main current in the thickness direction of the semiconductor element. It is well known that in semiconductor devices with single-sided cooling, using a lead frame to guide the heat flow to the cooling surface instead of using wires in the wiring layer on the surface of the element improves cooling efficiency. However, a simple copper lead frame does not achieve significant improvement because the flow path is longer than if the heat flow were guided directly from the back surface of the element to the cooling surface, resulting in higher thermal resistance. Therefore, it has been proposed to use a lead frame in which a high-thermal conductivity layer, such as graphite, which has a higher thermal conductivity than copper, is added to a high-conductivity layer, such as copper.

[0003] Japanese Patent Application Laid-Open No. 2019-071399

[0004] M. Otsuki, et. al., “Advanced thin wafer IGBTs with new thermal management solution”, in Proc. 15th ISPSD, p. 144-147, 2003

[0005] However, since the high thermal conductivity layer has anisotropy in thermal conductivity, the thermal resistance of the wiring layer may increase depending on the direction in which the high electrical conductivity layer and the high thermal conductivity layer are stacked.

[0006] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a semiconductor device including a wiring layer with reduced thermal resistance and a power conversion device including the semiconductor device.

[0007] A semiconductor device according to the present disclosure includes a substrate, a semiconductor element, and a wiring layer. The substrate has a first main surface. The semiconductor element is disposed on the first main surface. An electrode is provided on the semiconductor element. The wiring layer is connected to the electrode. The wiring layer includes a high thermal conductivity layer and a high electrical conductivity layer. The high electrical conductivity layer is stacked on the high thermal conductivity layer. The stacking direction of the high thermal conductivity layer and the high electrical conductivity layer is perpendicular to the extending direction of the wiring layer in a plan view of the first main surface.

[0008] A power conversion device according to the present disclosure includes a main conversion circuit and a control circuit. The main conversion circuit has the semiconductor device described above and converts input power to output the converted power. The control circuit outputs a control signal to the main conversion circuit to control the main conversion circuit.

[0009] According to the above, it is possible to obtain a semiconductor device including a wiring layer with reduced thermal resistance, and a power conversion device including the semiconductor device.

[0010] 10 is a schematic plan view of a semiconductor device according to a first embodiment. 11 is a schematic front view of a semiconductor device according to the first embodiment. 12 is a schematic plan view of a first modified example of the semiconductor device according to the first embodiment. 13 is a schematic front view of a first modified example of the semiconductor device according to the first embodiment. 14 is a schematic front view of a second modified example of the semiconductor device according to the first embodiment. 15 is a schematic front view of a third modified example of the semiconductor device according to the first embodiment. 16 is a schematic front view of a fourth modified example of the semiconductor device according to the first embodiment. 17 is a schematic front view of a fifth modified example of the semiconductor device according to the first embodiment. 18 is a schematic front view of a semiconductor device according to a second embodiment. 19 is a schematic front view of a partial enlarged schematic front view of a region XI in FIG. 10. 20 is a partial enlarged schematic front view of a first modified example of the semiconductor device according to the second embodiment. 21 is a schematic plan view of a semiconductor device according to a third embodiment. 22 is a schematic cross-sectional view taken along line XIV-XIV in FIG. 21. 23 is a schematic cross-sectional view of a wiring layer and a conductive bridge member in a semiconductor device according to a third embodiment. 24 is a schematic cross-sectional view of a modified example of the wiring layer and the conductive bridge member in a semiconductor device according to a third embodiment. 25 is a schematic cross-sectional view of a modified example of the wiring layer and the conductive bridge member in a semiconductor device according to a third embodiment. 26 is a schematic cross-sectional view of a modified example of the wiring layer and the conductive bridge member in a semiconductor device according to a third embodiment. 27 is a schematic cross-sectional view of a modified example of the wiring layer and the conductive bridge member in a semiconductor device according to a third embodiment. Fig. 10 is a schematic cross-sectional view of a modified example of a wiring layer and a conductive bridge member in a semiconductor device according to embodiment 3. Fig. 11 is a schematic cross-sectional view of a modified example of a wiring layer and a conductive bridge member in a semiconductor device according to embodiment 3. Fig. 12 is a schematic plan view of a semiconductor device according to embodiment 4. Fig. 13 is a schematic front view of a semiconductor device according to embodiment 4. Fig. 14 is a block diagram showing the configuration of a power conversion system to which a power conversion device according to embodiment 5 is applied.

[0011] Hereinafter, embodiments of the present disclosure will be described. Unless otherwise specified, the same or corresponding parts in the following drawings will be denoted by the same reference numerals, and the description thereof will not be repeated.

[0012] First Embodiment <Configuration of Semiconductor Device> Fig. 1 is a schematic plan view of a semiconductor device 100 according to a first embodiment. Fig. 2 is a schematic front view of the semiconductor device 100 according to the first embodiment.

[0013] The semiconductor device 100 shown in FIGS. 1 and 2 is, for example, a power semiconductor device 100 and mainly comprises a substrate 1, a semiconductor element 2, a wiring layer 3, and leads 4.

[0014] The substrate 1 has a first main surface 10a and a second main surface 10b. The first main surface 10a is a surface on which a semiconductor element 2 is mounted. The second main surface 10b is a surface opposite to the first main surface 10a.

[0015] 2, the substrate 1 includes an upper metal layer 11, an insulating plate 12, and a lower metal layer 13. The upper metal layer 11 is disposed on the insulating plate 12. The insulating plate 12 is disposed on the lower metal layer 13. In the z-direction, the upper metal layer 11 is located opposite the lower metal layer 13 when viewed from the insulating plate 12.

[0016] The surface (top surface) of the upper metal layer 11 forms a first major surface 10a, and the back surface (bottom surface) of the lower metal layer 13 forms a second major surface 10b.

[0017] The directions in which the first major surface 10a extends are the x-direction and the y-direction. The y-direction is perpendicular to the x-direction. The direction perpendicular to the first major surface 10a is the z-direction. The z-direction is perpendicular to the x-direction and the y-direction.

[0018] The material constituting the upper metal layer 11 may include, for example, copper (Cu), aluminum (Al), a copper alloy, or an aluminum alloy. The material constituting the upper metal layer 11 is a material having high electrical conductivity and high thermal conductivity.

[0019] A circuit pattern is formed on the upper metal layer 11. Specifically, as shown in Fig. 1, the upper metal layer 11 includes a first conductive portion 11a, a second conductive portion 11b, and a third conductive portion 11c. The first conductive portion 11a, the second conductive portion 11b, and the third conductive portion 11c are arranged on the insulating plate 12 at a distance from each other.

[0020] In a plan view of the first main surface 10a, the first conductive portion 11a has a rectangular shape. In a plan view of the first main surface 10a, the second conductive portion 11b has an L-shape. In a plan view of the first main surface 10a, the third conductive portion 11c has a rectangular shape. In a plan view of the first main surface 10a, the first conductive portion 11a, the second conductive portion 11b, and the third conductive portion 11c may each have any shape.

[0021] The insulating plate 12 is, for example, a ceramic insulating substrate. That is, the material constituting the insulating plate 12 is, for example, ceramic having insulating properties. The material constituting the insulating plate 12 is, for example, silicon nitride (Si ３ N ４ ), aluminum nitride (AlN), and aluminum oxide (Al ２ O ３ ) may be either.

[0022] The material constituting the lower metal layer 13 may be the same as or different from the material constituting the upper metal layer 11. The thickness of the lower metal layer 13 in the z direction may be the same as or different from the thickness of the upper metal layer 11 in the z direction.

[0023] A circuit pattern is formed on the upper metal layer 11. Therefore, the thickness of the lower metal layer 13 in the z direction may be smaller than the thickness of the upper metal layer 11 in the z direction. In this way, the volume of the lower metal layer 13 may be made the same as the volume of the upper metal layer 11.

[0024] Fig. 3 is a schematic plan view of a first modified example of the semiconductor device 100 according to the first embodiment. Fig. 3 corresponds to Fig. 1. Fig. 4 is a schematic front view of the first modified example of the semiconductor device 100 according to the first embodiment. Fig. 4 corresponds to Fig. 2. The semiconductor device 100 shown in Figs. 3 and 4 basically has the same configuration as the semiconductor device 100 shown in Figs. 1 and 2 and can obtain the same effects, but the configuration of the substrate 1 is different.

[0025] 4, the substrate 1 includes a metal block layer 14, an insulating sheet layer 15, and a base plate 16. The metal block layer 14 is disposed on the insulating sheet layer 15. The insulating sheet layer 15 is disposed on the base plate 16. In the z direction, the metal block layer 14 is located opposite the base plate 16 when viewed from the insulating sheet layer 15.

[0026] The surface of the metal block layer 14 forms the first main surface 10a. The back surface of the base plate 16 forms the second main surface 10b. The material constituting the metal block layer 14 has high electrical conductivity and high thermal conductivity, such as copper (Cu) or a copper alloy.

[0027] 3, the metal block layer 14 includes a first block 14a, a second block 14b, and a third block 14c, which are arranged on the insulating sheet layer 15 at intervals.

[0028] The insulating sheet layer 15 is a thin film having a smaller thickness in the z direction than the insulating plate 12. The base plate 16 is made of a material having high thermal conductivity, such as Cu or Al-Si-C. The base plate 16 may include a cooler. The cooler is provided on the second main surface 10b, for example. The cooler is, for example, a fin.

[0029] 1, the semiconductor element 2 is disposed on the first main surface 10a in the second conductive portion 11b. The semiconductor element 2 is provided with an electrode 21. The electrode 21 includes, for example, a main electrode 22 and a control electrode 23. The main electrode 22 includes a front main electrode 22a and a back main electrode 22b. As shown in FIG. 2, the back main electrode 22b is connected to the first main surface 10a via a joint 51.

[0030] A main current flows through the main electrode 22. The control electrode 23 controls the main current. The front main electrode 22a and the control electrode 23 are disposed on the front surface (upper surface) of the semiconductor element 2. The back main electrode 22b is disposed on the back surface (lower surface) of the semiconductor element 2. On the front surface of the semiconductor element 2, the front main electrode 22a and the control electrode 23 are disposed spaced apart from each other.

[0031] The electrode 21 is made of a material having high electrical and thermal conductivity. The electrode 21 may be formed by copper (Cu) plating or nickel (Ni) plating. The electrode 21 may be a plate made of copper or a copper alloy. The plate may be directly bonded to the semiconductor element 2, or may be bonded to the semiconductor element 2 via a bonding material that uses a sintered material containing fine particles of silver (Ag), copper (Cu), or the like.

[0032] When the material forming the surface main electrode 22a is copper or a copper alloy, the short-circuit resistance of the semiconductor element 2 is improved.

[0033] An electric field strength reduction portion 24 is provided on the surface of the semiconductor element 2. The electric field strength reduction portion 24 reduces the electric field strength generated by the electrode 21. As shown in FIGS. 1 and 2 , the electric field strength reduction portion 24 is arranged so as to surround the electrode 21. In other words, the electric field strength reduction portion 24 is formed on the outer periphery of the surface of the semiconductor element 2. As shown in FIG. 1 , the electric field strength reduction portion 24 may be annular in shape. Specifically, the electric field strength reduction portion 24 may be a termination structure called a guard ring.

[0034] The shape of the electric field intensity reduction portion 24 does not have to be annular. Specifically, the electric field intensity reduction portion 24 may be a termination structure called a JTE (Junction Termination Extension) structure. The electric field intensity reduction portion 24 is, for example, a p-type region formed by ion implantation. The electric field intensity reduction portion 24 may be formed on the surface of the semiconductor element 2 as shown in FIG. 2 , or may be formed inside the semiconductor element 2.

[0035] The semiconductor element 2 is a so-called power semiconductor element 2 that controls electric power. Any material may be used as a material for forming the semiconductor element 2. Examples of materials for forming the semiconductor element 2 include silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (GaO). ２ O ３ ), diamond, etc. In particular, gallium oxide has a low thermal conductivity. Therefore, when the material constituting the semiconductor element 2 is gallium oxide (Ga ２ O ３ ), the effect of dissipating heat from the main electrode 22 located near the heat source is enhanced. Specifically, the amount of heat flowing into the wiring layer 3 increases.

[0036] The semiconductor element 2 in the first embodiment is an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET), but may be a diode or have other functions. The type of the semiconductor element is not particularly limited, but may be, for example, a vertical semiconductor element. The semiconductor device 100 may be a semiconductor device 100 using flip-chip mounting in which the front surface main electrode 22 a is connected to the substrate 1.

[0037] 2, the wiring layer 3 is connected to the electrode 21 and the substrate 1. Specifically, one end of the wiring layer 3 is connected to the surface main electrode 22a via a joint 52. The other end of the wiring layer 3 is connected to the first main surface 10a of the third conductive portion 11c via a joint 53. Heat generated in the semiconductor element 2 flows along the extending direction of the wiring layer 3.

[0038] 1, the wiring layer 3 includes a plurality of high thermal conductivity layers 32 and a plurality of high electrical conductivity layers 31. The high electrical conductivity layers 31 are arranged adjacent to the high thermal conductivity layers 32. In other words, the wiring layer 3 is formed by alternately stacking the high thermal conductivity layers 32 and the high electrical conductivity layers 31.

[0039] The material constituting the high thermal conductivity layer 32 is, for example, graphite. As will be described later, graphite has anisotropy. The material constituting the high electrical conductivity layer 31 is, for example, copper (Cu) or a copper alloy. The high thermal conductivity layer 32 has high thermal conductivity in the in-plane direction. The high electrical conductivity layer 31 also has high electrical conductivity. In this way, it is possible to obtain a wiring layer 3 that maintains high electrical conductivity and has reduced thermal resistance.

[0040] The wiring layer 3 extends from the second conductive portion 11b toward the third conductive portion 11c. As shown in FIG. 1 , the extension direction of the wiring layer 3 in a plan view of the first main surface 10a is, for example, the x direction. The stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 in a plan view of the first main surface 10a is, for example, the y direction. In other words, the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is a direction perpendicular to the extension direction of the wiring layer 3 in a plan view of the first main surface 10a.

[0041] The wiring layer 3 is disposed at a distance from the electric field intensity mitigating portion 24 so that the electric field formed by the wiring layer 3 does not affect the electric field intensity mitigating portion 24. The wiring layer 3 may be disposed at a distance of at least 0.1 mm from the electric field intensity mitigating portion 24. The wiring layer 3 may be disposed at a distance of 0.2 mm or more from the electric field intensity mitigating portion 24, or may be disposed at a distance of 0.3 mm or more in consideration of manufacturing variations.

[0042] 2, the wiring layer 3 has a side surface 34. The side surface 34 is continuous with the front surface main electrode 22a via a joint 52. The side surface 34 is continuous with the first main surface 10a of the third conductive portion 11c via a joint 53. The side surface 34 faces the electric field intensity mitigation portion 24. A part of the wiring layer 3 extends so as to surround the electric field intensity mitigation portion 24. Specifically, as shown in FIG. 2, the shape of the side surface 34 is, for example, U-shaped when viewed in the y direction.

[0043] Specifically, the side surface 34 includes a first region s1, a second region s2, and a third region s3. The first region s1 is continuous with the second region s2 and the bonding portion 52. The first region s1 extends in the z direction. From a different perspective, the first region s1 extends perpendicular to the first main surface 10a. The second region s2 is continuous with the first region s1 and the third region s3. The second region s2 extends in the x direction. From a different perspective, the second region s2 extends parallel to the first main surface 10a. The third region s3 is continuous with the second region s2 and the bonding portion 53. The third region s3 extends in the z direction. From a different perspective, the third region s3 extends perpendicular to the first main surface 10a. When viewed from the y direction, the first region s1, the second region s2, and the third region s3 each have a linear shape. In this manner, the wiring layer 3 is disposed at a distance from the electric field intensity mitigating portion 24.

[0044] Electric current and heat pass through the joints 51, 52, and 53 in the z direction (thickness direction). Therefore, the material forming the joints 51, 52, and 53 may have high electrical conductivity and high thermal conductivity. The joints 51, 52, and 53 may be formed using a sintered material containing fine particles of silver (Ag), copper (Cu), or the like, or may be formed using solder.

[0045] The joints 51, 52, and 53 may be formed by liquid phase diffusion of Sn—Cu, Sn—Ag, or the like. In this way, the joint thickness in the z direction can be made 0.02 mm or less. As a result, the thermal resistance of the joints 51, 52, and 53 can be reduced.

[0046] The control electrode 23 is connected to the first main surface 10a of the first conductive portion 11a via a metal connection portion 6. The material forming the metal connection portion 6 may be, for example, copper (Cu), aluminum (Al), a copper alloy, or an aluminum alloy.

[0047] The metal connection portion 6 may be a wire formed by wire bonding or may be a clip. The metal connection portion 6 is arranged at a distance from the electric field strength reduction portion 24 so that the electric field formed by the metal connection portion 6 does not affect the electric field strength reduction portion 24. As shown in FIG. 2 , the metal connection portion 6 extends so as to surround the electric field strength reduction portion 24.

[0048] The leads 4 are provided on the first main surface 10a. As shown in Fig. 2, the leads 4 extend in the z direction. The leads 4 may be made of copper.

[0049] The lead 4 may be directly connected to the upper metal layer 11. Specifically, the lead 4 may be connected to the upper metal layer 11 using ultrasonic welding or laser welding. The lead 4 may be indirectly connected to the upper metal layer 11 using a bonding material such as solder. The bonding material for connecting the lead 4 to the upper metal layer 11 may be the same as the bonding material for forming the bonding portions 51, 52, and 53.

[0050] 1, the lead 4 includes a first lead 41, a second lead 42, and a third lead 43. The first lead 41 is connected to the first main surface 10a of the first conductive portion 11a. The first lead 41 is spaced apart from the metal connection portion 6 in the y direction. The second lead 42 is connected to the first main surface 10a of the second conductive portion 11b. The second lead 42 is spaced apart from the semiconductor element 2 in the x direction. The third lead 43 is connected to the first main surface 10a of the third conductive portion 11c. The third lead 43 is spaced apart from the wiring layer 3 in the x direction.

[0051] Fig. 5 is a schematic front view of a second modification of the semiconductor device 100 according to the first embodiment. Fig. 5 corresponds to Fig. 2. The semiconductor device 100 shown in Fig. 5 basically has the same configuration as the semiconductor device 100 shown in Figs. 1 and 2 and can achieve the same effects, but differs in that it includes a case 82. Note that Fig. 5 shows the internal structure of the case 82 for ease of explanation.

[0052] The semiconductor device 100 according to the first embodiment may be used as a case-type module. The semiconductor device 100 includes a sealing portion 81, a case 82, and a mounting portion 83. The lower metal layer 13 is connected to the mounting portion 83 via a joint 54. The bonding material forming the joint 54 may be the same as the bonding material forming the joints 51, 52, and 53. Electric current and heat pass through the joint 54 in the z direction (thickness direction). Therefore, the material forming the joint 54 has high thermal conductivity.

[0053] The substrate 1, semiconductor element 2, wiring layer 3, and case 82 are mounted on the front surface (top surface) of the mounting portion 83. A cooler may be provided on the back surface (bottom surface) of the mounting portion 83. The cooler may be, for example, a pin fin or a cooling fin having another shape. A part of the cooler may be connected to the back surface (bottom surface) of the mounting portion 83, or the entire cooler may be connected to the back surface (bottom surface) of the mounting portion 83. The cooler may be connected to the mounting portion 83 via a TIM (thermal interface material).

[0054] The substrate 1, the semiconductor element 2, and the wiring layer 3 are disposed inside the case 82. Inside the case 82, the substrate 1, the semiconductor element 2, and the wiring layer 3 are sealed by a sealing portion 81. The leads 4 extend from the substrate 1 toward the outside of the sealing portion 81.

[0055] The sealing portion 81 has insulating properties. The sealing portion 81 is formed by potting or supplying a sheet material. The material constituting the sealing portion 81 is not particularly limited, but may be, for example, silicone gel or epoxy resin.

[0056] The semiconductor device 100 may be a case-type module as shown in FIG. 5, a transfer mold-type module, or any other module.

[0057] 1 and 2 is a so-called 1-in-1 type circuit configuration in which one semiconductor element 2 is mounted on one module. The circuit configuration of the semiconductor device 100 may be a 2-in-1 type circuit configuration in which two semiconductor elements 2 are mounted on one module, or a so-called 6-in-1 type circuit configuration in which six semiconductor elements 2 are mounted on one module.

[0058] Fig. 6 is a schematic plan view of a third modification of the semiconductor device 100 according to the first embodiment. Fig. 6 corresponds to Fig. 1. Fig. 7 is a schematic front view of the third modification of the semiconductor device 100 according to the first embodiment. Fig. 7 corresponds to Fig. 2. The semiconductor device 100 shown in Figs. 6 and 7 basically has the same configuration as the semiconductor device 100 shown in Figs. 1 and 2 and can obtain the same effects, but differs in that the circuit configuration of the semiconductor device 100 is a 2-in-1 type that forms a half bridge.

[0059] 6, the upper metal layer 11 includes a first conductive portion 11a, a second conductive portion 11b, a third conductive portion 11c, a fourth conductive portion 11d, and a fifth conductive portion 11e. The first conductive portion 11a, the second conductive portion 11b, the third conductive portion 11c, the fourth conductive portion 11d, and the fifth conductive portion 11e are arranged on the insulating plate 12 at a distance from one another.

[0060] The semiconductor element 2 includes a first semiconductor element 2a and a second semiconductor element 2b. The first semiconductor element 2a is disposed on the first main surface 10a in the second conductive portion 11b. The second semiconductor element 2b is disposed on the first main surface 10a in the third conductive portion 11c.

[0061] The wiring layer 3 includes a first wiring layer 3 a on the upper arm side and a second wiring layer 3 b on the lower arm side. One end of the first wiring layer 3 a is connected to the front surface main electrode 22 a of the first semiconductor element 2 a via a bonding portion 52. The other end of the first wiring layer 3 a is connected to the first main surface 10 a of the third conductive portion 11 c via a bonding portion 53.

[0062] One end of the second wiring layer 3b is connected to the surface main electrode 22a of the second semiconductor element 2b via a joint 52. The other end of the second wiring layer 3b is connected to the first main surface 10a of the fourth conductive portion 11d via a joint 53 (not shown).

[0063] 6, the first wiring layer 3a extends from the second conductive portion 11b toward the third conductive portion 11c. As shown in FIG. 6, the extension direction of the first wiring layer 3a in the plan view of the first main surface 10a is the x-direction. The stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 in the plan view of the first main surface 10a is, for example, the y-direction.

[0064] The second wiring layer 3b extends from the third conductive portion 11c toward the fourth conductive portion 11d. As shown in FIG. 6 , the extension direction of the second wiring layer 3b in a plan view of the first main surface 10a is the y direction. The stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 in a plan view of the first main surface 10a is, for example, the x direction. The extension direction (x direction) of the first wiring layer 3a is perpendicular to the extension direction (y direction) of the second wiring layer 3b. That is, the stacking directions of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 in each of the first wiring layer 3a and the second wiring layer 3b are perpendicular to each other.

[0065] The first wiring layer 3a and the second wiring layer 3b may be arranged parallel to each other, or may be arranged in a line.

[0066] The control electrode 23 of the first semiconductor element 2a is connected to the first main surface 10a of the first conductive portion 11a via the metal connection portion 6. The control electrode 23 of the second semiconductor element 2b is connected to the first main surface 10a of the fifth conductive portion 11e via the metal connection portion 6.

[0067] The leads 4 include a first lead 41, a second lead 42, a third lead 43, a fourth lead 44, and a fifth lead 45. The first lead 41 is connected to the first main surface 10a of the first conductive portion 11a. The second lead 42 is connected to the first main surface 10a of the second conductive portion 11b. The third lead 43 is connected to the first main surface 10a of the third conductive portion 11c. The fourth lead 44 is connected to the first main surface 10a of the fourth conductive portion 11d. The fifth lead 45 is connected to the first main surface 10a of the fifth conductive portion 11e.

[0068] The first lead 41 and the fifth lead 45 extract signals to the outside. The second lead 42 is connected to a terminal having a P-type conductivity. The third lead 43 is connected to an AC terminal. The fourth lead 44 is connected to a terminal having an N-type conductivity.

[0069] The fourth lead 44 and the second wiring layer 3b may be connected above the substrate 1 in the z direction.

[0070] A lead frame may be connected to the second wiring layer 3b. The lead frame may be made of a material having high conductivity, such as copper. An insulating layer may be sandwiched between the lead frame and the first wiring layer 3a. In other words, the lead frame may be arranged so as to form a parallel plate with respect to the first wiring layer 3a. This arrangement can suppress parasitic inductance in the semiconductor device 100.

[0071] Fig. 8 is a schematic plan view of a fourth modification of the semiconductor device 100 according to the first embodiment. Fig. 8 corresponds to Fig. 1. The semiconductor device 100 shown in Fig. 8 basically has the same configuration as the semiconductor device 100 shown in Figs. 1 and 2 and can achieve the same effects, but differs in that a plurality of semiconductor elements 2 are arranged on the first main surface 10a of the second conductive portion 11b.

[0072] The semiconductor element 2 includes a first semiconductor element 2 a and a second semiconductor element 2 b. The first semiconductor element 2 a and the second semiconductor element 2 b are each disposed on the first main surface 10 a in the second conductive portion 11 b. The second semiconductor element 2 b is disposed spaced apart from the first semiconductor element 2 a in the y direction.

[0073] The wiring layer 3 includes a first wiring layer 3 a and a second wiring layer 3 b. One end of the first wiring layer 3 a is connected to the front surface main electrode 22 a of the first semiconductor element 2 a via a bonding portion 52 (not shown). The other end of the first wiring layer 3 a is connected to the first main surface 10 a of the third conductive portion 11 c via a bonding portion 53 (not shown).

[0074] One end of the second wiring layer 3b is connected to the surface main electrode 22a of the second semiconductor element 2b via a joint 52 (not shown), and the other end of the second wiring layer 3b is connected to the first main surface 10a of the third conductive portion 11c via a joint 53 (not shown).

[0075] The first wiring layer 3a and the second wiring layer 3b each extend from the second conductive portion 11b toward the third conductive portion 11c. As shown in FIG. 8 , the extension direction of the first wiring layer 3a and the second wiring layer 3b in a plan view of the first main surface 10a is the x-direction. The first wiring layer 3a and the second wiring layer 3b are arranged parallel to each other. The first wiring layer 3a and the second wiring layer 3b are arranged spaced apart from each other in the y-direction.

[0076] The control electrode 23 of each of the first semiconductor element 2 a and the second semiconductor element 2 b is connected to the first main surface 10 a of the first conductive portion 11 a via the metal connection portion 6 .

[0077] In this way, a plurality of semiconductor elements 2 may be disposed on the substrate 1. The number of semiconductor elements 2 may be two or more, or may be three or more.

[0078] 1 , the semiconductor device 100 according to the first embodiment is characterized in that the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is perpendicular to the extension direction of the wiring layer 3 in a plan view of the first main surface 10a. In the semiconductor device 100 according to the first embodiment, the extension direction of the wiring layer 3 is the x direction. Therefore, the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is the y direction. When the extension direction of the wiring layer 3 is the y direction, the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 may be the x direction. In this way, the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is horizontal to the first main surface 10a.

[0079] An example of a material constituting the high thermal conductivity layer 32 is graphite. Graphite has a layered structure. Graphite is anisotropic. Specifically, the thermal conductivity of graphite is high in the in-plane directions (x and z directions in the semiconductor device 100 according to the first embodiment) in which the hexagonal rings are arranged. On the other hand, the thermal conductivity of graphite is low in the direction perpendicular to the in-plane directions (y direction in the semiconductor device 100 according to the first embodiment). That is, the thermal conductivity of graphite in the in-plane directions is higher than the thermal conductivity in the direction perpendicular to the in-plane directions. Therefore, when heat generated in the semiconductor element 2 flows in the direction perpendicular to the in-plane direction of the high thermal conductivity layer 32, the thermal resistance of the wiring layer 3 increases.

[0080] On the other hand, in the semiconductor device 100 according to the first embodiment, the extension direction of the wiring layer 3 in a plan view of the first main surface 10a is the x-direction. Therefore, the direction of heat flow in the wiring layer 3 is the x-direction. The stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is the y-direction. That is, the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is perpendicular to the extension direction of the wiring layer 3 in a plan view of the first main surface 10a. Because the high thermal conductivity layer 32 is arranged in this manner, the direction of heat flow is along the in-plane direction of the graphite. In the high thermal conductivity layer 32, the thermal conductivity in the direction (x-direction) perpendicular to the stacking direction (y-direction) is greater than the thermal conductivity in the stacking direction (y-direction). Therefore, the thermal resistance of the wiring layer 3 can be reduced.

[0081] The number of layers in the wiring layer 3 formed by alternately stacking high thermal conductivity layers 32 and high electrical conductivity layers 31 may be two or more. Specifically, the wiring layer 3 may be formed from one high thermal conductivity layer 32 and one high electrical conductivity layer 31.

[0082] The number of stacked layers in the wiring layer 3 may be three or more. Specifically, the wiring layer 3 may be formed from two high thermal conductivity layers 32 and one high electrical conductivity layer 31. One high electrical conductivity layer 31 may be disposed so as to be sandwiched between two high thermal conductivity layers 32. Increasing the number of stacked layers in this way suppresses imbalances in the temperature distribution and current density distribution in the wiring layer 3.

[0083] The number of layers in the wiring layer 3 may be 5 or 7. In this way, the number of layers in the wiring layer 3 may be an odd number. In this way, the wiring layer 3 is configured to be mirror-symmetric in the y direction. As a result, it is possible to suppress bias in the flow of current and heat in the y direction. Thermal stress occurs in the wiring layer 3 due to the difference in the linear expansion coefficients of the high thermal conductivity layer 32 and the high electrical conductivity layer 31. However, since the number of layers in the wiring layer 3 is an odd number, the wiring layer 3 is configured to be mirror-symmetric in the y direction. Therefore, thermal stress occurring in the y direction is suppressed.

[0084] The conductivity of graphite is 10 ６ S / m. Therefore, the conductivity of graphite is low compared to the conductivity of other conductors. On the other hand, the conductivity of copper (Cu) is 5×10 ７ The conductivity of copper is about 50 times higher than that of graphite. Therefore, when high thermal conductivity layer 32 is made of graphite and high conductivity layer 31 is made of copper, most of the current flowing through wiring layer 3 flows through high conductivity layer 31.

[0085] A typical lead frame has a thickness of about 0.64 mm. If the width w of the wiring layer 3 in the z direction is about the same as the thickness of a typical lead frame, the electrical resistance of the wiring layer 3 increases. As a result, the wiring layer 3 becomes a heat source.

[0086] The substantial cross-sectional area of ​​the high conductivity layer 31 as viewed from the direction in which the wiring layer 3 extends may be equal to or greater than the cross-sectional area of ​​a typical lead frame. That is, as shown in Fig. 2, the width w of the wiring layer 3 in the direction (z direction) perpendicular to the extension direction (x direction) of the wiring layer 3 and the stacking direction (y direction) of the high thermal conductivity layer 32 and the high conductivity layer 31 may be 1.0 mm or more, 1.3 mm or more, or 2.0 mm or more. In this way, the cross-sectional area of ​​the high conductivity layer 31 is reduced, and electrical resistance is suppressed.

[0087] 1, the thickness t of each high conductivity layer 31 in the y direction may be 1.0 mm or less, or may be 0.64 mm or less, which can reduce eddy current loss caused by the skin effect.

[0088] When the high conductivity layer 31 is formed as a thin film, when it is formed by coating, or when it is formed by plating, the thickness t of each high conductivity layer 31 in the y direction is less than 0.1 mm. If the thickness t of each high conductivity layer 31 in the y direction is less than 0.1 mm, the wiring layer 3 will not be self-supporting. Therefore, the thickness t of each high conductivity layer 31 in the y direction may be 0.1 mm or more. In this way, the wiring layer 3 will be self-supporting.

[0089] When viewed from the stacking direction of high thermal conductivity layer 32 and high electrical conductivity layer 31 (the y direction in semiconductor device 100 according to the first embodiment), high thermal conductivity layer 32 may have the same shape as high electrical conductivity layer 31. In this way, the cross-sectional area of ​​wiring layer 3 at any position in the x direction as viewed from the x direction is maximized. As a result, the electrical resistance and thermal resistance of wiring layer 3 are suppressed.

[0090] Fig. 9 is a schematic front view of a fifth modification of the semiconductor device 100 according to the first embodiment. Fig. 9 corresponds to Fig. 2. The semiconductor device 100 shown in Fig. 9 basically has the same configuration as the semiconductor device 100 shown in Figs. 1 and 2 and can achieve the same effects, but differs in that a metal coating layer 33 is provided on at least a part of the surface of the wiring layer 3.

[0091] As described above, the wiring layer 3 is connected to the front surface main electrode 22a via the joint 52. The wiring layer 3 is also connected to the first main surface 10a of the third conductive portion 11c via the joint 53. As shown in FIG. 9 , by providing the metal coating layer 33 on the surface of the wiring layer 3 connected to the joints 52 and 53 (the end faces where the high thermal conductivity layer 32 and the high electrical conductivity layer 31 are exposed), the compatibility between the joints 52 and 53 and the surface of the wiring layer 3 is improved. As a result, the thermal and electrical contact resistance at the interfaces between the joints 52 and 53 and the wiring layer 3 is reduced.

[0092] The metal coating layer 33 may be formed by plating. The metal coating layer 33 may be, for example, a silver (Ag) plating layer, a copper (Cu) plating layer, a nickel (Ni) plating layer, or a tin (Sn) plating layer. The metal coating layer 33 may be, for example, a plating layer with a multilayer structure in which different materials are stacked. The material constituting the metal coating layer 33 is not particularly limited, and may be a material other than those mentioned above.

[0093] The metal coating layer 33 does not have to be formed by plating, but may be formed by, for example, physical vapor deposition or chemical vapor deposition.

[0094] Furthermore, the metal coating layer 33 only needs to be provided on at least the surface where the wiring layer 3 is connected to the bonding portions 52 and 53 , and may be formed on the entire surface of the wiring layer 3 .

[0095] Next, a method for manufacturing the wiring layer 3 will be described. The wiring layer 3 can be manufactured using any method. The high thermal conductivity layer 32 and the high electrical conductivity layer 31 may be joined via a brazing material. The high thermal conductivity layer 32 and the high electrical conductivity layer 31 are joined by heating and pressurizing the brazing material. The brazing material may be, for example, an active metal brazing material.

[0096] The high thermal conductivity layer 32 and the high electrical conductivity layer 31 may be bonded together using a bonding material. The bonding material may be a non-metallic material such as a resin. The high thermal conductivity layer 32 and the high electrical conductivity layer 31 may also be bonded together directly.

[0097] The high thermal conductivity layer 32 may be formed by a chemical vapor deposition (CVD) method. Specifically, the wiring layer 3 may be manufactured by using the high electrical conductivity layer 31 as a base material and depositing the high thermal conductivity layer 32 on the surface of the high electrical conductivity layer 31.

[0098] The high thermal conductivity layer 32 and the high electrical conductivity layer 31 may each be shaped using punching, laser processing, or electrical discharge processing. The shaped high thermal conductivity layers 32 and high electrical conductivity layers 31 are then alternately stacked to bond the high thermal conductivity layers 32 and high electrical conductivity layers 31 together.

[0099] Alternatively, high thermal conductivity layers 32 and high electrical conductivity layers 31 may be alternately stacked, and the high thermal conductivity layers 32 and high electrical conductivity layers 31 may be bonded together, and then the stacked high thermal conductivity layers 32 and high electrical conductivity layers 31 may be shaped by punching, laser machining, or electrical discharge machining. The wiring layer 3 thus manufactured by bonding the high thermal conductivity layers 32 and high electrical conductivity layers 31 and then shaping them has better dimensional accuracy than the wiring layer 3 manufactured by bonding the high thermal conductivity layers 32 and high electrical conductivity layers 31 together after shaping them.

[0100] <Effects> A semiconductor device 100 according to the present disclosure includes a substrate 1, a semiconductor element 2, and a wiring layer 3. The substrate 1 has a first main surface 10a. The semiconductor element 2 is disposed on the first main surface 10a. An electrode 21 is provided on the semiconductor element 2. The wiring layer 3 is connected to the electrode 21. The wiring layer 3 includes a high thermal conductivity layer 32 and a high electrical conductivity layer 31. The high electrical conductivity layer 31 is stacked on the high thermal conductivity layer 32. The stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is a direction (y direction) perpendicular to the extending direction (x direction) of the wiring layer 3 in a plan view of the first main surface 10a.

[0101] In this way, the direction of heat flow is along the in-plane direction of the high thermal conductivity layer 32. In the high thermal conductivity layer 32, the thermal conductivity in the direction (x direction) perpendicular to the stacking direction (y direction) is greater than the thermal conductivity in the stacking direction (y direction). Therefore, it is possible to obtain a wiring layer 3 that maintains high electrical conductivity and has reduced thermal resistance.

[0102] In the semiconductor device 100, the material constituting the high thermal conductivity layer 32 is graphite. In the high thermal conductivity layer 32, the thermal conductivity in a direction (x direction or z direction) perpendicular to the stacking direction (y direction) is greater than the thermal conductivity in the stacking direction (y direction).

[0103] Graphite has anisotropy, so by arranging the graphite so that the direction of heat flow is the in-plane direction (x direction or z direction) in which the thermal conductivity of the graphite is high, the thermal resistance of the wiring layer 3 can be reduced.

[0104] According to the semiconductor device 100, the material constituting the semiconductor element 2 contains gallium oxide.

[0105] Gallium oxide has a low thermal conductivity. Therefore, the material constituting the semiconductor element 2 is gallium oxide (Ga ２ O ３ ), the effect of dissipating heat from the main electrode 22 located near the heat source is increased.

[0106] According to the semiconductor device 100, the number of layers in the wiring layer 3 formed by alternately stacking the high thermal conductivity layers 32 and the high electrical conductivity layers 31 is three or more.

[0107] In this way, the deviation of the temperature distribution and the current density distribution in the wiring layer 3 can be suppressed.

[0108] According to the semiconductor device 100, the number of stacked layers is odd. In this way, the wiring layer 3 is configured to be mirror-symmetric in the y direction. Therefore, thermal stress occurring in the y direction is suppressed. As a result, warping occurring in the wiring layer 3 is suppressed.

[0109] According to the semiconductor device 100, the width w of the wiring layer 3 in the direction (z direction) perpendicular to the extending direction (x direction) and stacking direction (y direction) of the wiring layer 3 is 1.0 mm or more. The thickness t of the high conductivity layer 31 in the stacking direction (y direction) is 0.1 mm or more and 1.0 mm or less.

[0110] In this way, the electrical resistance in the wiring layer 3 and the eddy current loss caused by the skin effect can be reduced.

[0111] According to the semiconductor device 100 described above, the shape of the high thermal conductivity layer 32 is the same as the shape of the high electrical conductivity layer 31 when viewed in the stacking direction (y direction).

[0112] In this way, the cross-sectional area of ​​the wiring layer 3 as viewed from the x direction at any position in the x direction is maximized, thereby suppressing the electrical resistance and thermal resistance of the wiring layer 3.

[0113] According to the semiconductor device 100 , the metal coating layer 33 is provided on at least a part of the surface of the wiring layer 3 .

[0114] This improves the compatibility of the wiring layer 3 with the bonding portions 52 and 53. As a result, thermal and electrical contact resistance at the interfaces between the bonding portions 52 and 53 and the wiring layer 3 is reduced.

[0115] Second Embodiment <Configuration of Semiconductor Device> Figure 10 is a schematic front view of a semiconductor device 100 according to a second embodiment. Figure 10 corresponds to Figure 2. Figure 11 is a partially enlarged schematic front view of region XI in Figure 10. The semiconductor device 100 shown in Figures 10 and 11 basically has the same configuration as the semiconductor device 100 shown in Figures 1 and 2 and can achieve the same effects, but differs in that the first region s1 and the third region s3 are inclined with respect to the first main surface 10a.

[0116] The electrical resistance and thermal resistance of the wiring layer 3 are inversely proportional to the cross-sectional area of ​​the wiring layer 3. However, the electrical resistance and thermal resistance of the wiring layer 3 are proportional to the length of the wiring layer 3. The length of the wiring layer 3 is the distance from the front surface main electrode 22a to the first main surface 10a of the third conductive portion 11c along the direction in which the wiring layer 3 extends.

[0117] When viewed from the y direction, part of the side surface 34 extends so as to be inclined with respect to the first main surface 10a, thereby making it possible to reduce the length of the wiring layer 3. As a result, the electrical resistance and thermal resistance of the wiring layer 3 are reduced.

[0118] As described above, the side surface 34 of the wiring layer 3 is spaced at least 0.1 mm from the electric field intensity mitigating portion 24 so that the electric field formed by the wiring layer 3 does not affect the electric field intensity mitigating portion 24 .

[0119] 11 , the width Le in the x-direction of the second region s2 may be larger than the width We in the x-direction of the electric field intensity mitigation portion 24. In this way, the shortest distance De1 from the first region s1 to the electric field intensity mitigation portion 24, the shortest distance De2 from the second region s2 to the electric field intensity mitigation portion 24, and the shortest distance De3 from the third region s3 to the electric field intensity mitigation portion 24 are each 0.1 mm or more. In this way, the influence of the electric field formed by the wiring layer 3 on the electric field intensity mitigation portion 24 is suppressed.

[0120] Fig. 12 is a partially enlarged schematic front view of Modification 1 of the semiconductor device 100 according to Embodiment 2. Fig. 12 corresponds to Fig. 11. The semiconductor device 100 shown in Fig. 12 basically has the same configuration as the semiconductor device 100 shown in Figs. 10 and 11 and can obtain the same effects, but differs in that the side surface 34 includes curved portions R1 and R2.

[0121] Specifically, the first region s1 and the second region s2 are connected via a curved surface portion R1. The second region s2 and the third region s3 are connected via a curved surface portion R2. As shown in FIG. 12 , the shape of each of the curved surface portions R1 and R2 may be curved or arc-shaped when viewed from the y direction. In this way, the width Le of the second region s2 in the x direction can be made the same as the width We of the electric field intensity mitigation portion 24 in the x direction. As long as the shortest distance from each of the curved surface portions R1 and R2 to the electric field intensity mitigation portion 24 is 0.1 mm or more, the shape of each of the curved surface portions R1 and R2 may be any shape.

[0122] By using punching, laser processing, and electric discharge processing, it is possible to easily manufacture a wiring layer 3 having side surfaces 34 that are inclined or curved relative to the first main surface 10a shown in Figures 10 to 12.

[0123] <Operation and Effect> According to the semiconductor device 100, the electric field strength mitigating portion 24 is provided in the semiconductor element 2. The wiring layer 3 is spaced apart from the electric field strength mitigating portion 24 by 0.1 mm or more.

[0124] In this way, the influence of the wiring layer 3 on the electric field intensity mitigating portion 24 is suppressed. Third Embodiment <Configuration of Semiconductor Device> Fig. 13 is a schematic plan view of a semiconductor device 100 according to a third embodiment. Fig. 13 corresponds to Fig. 8. Fig. 14 is a schematic cross-sectional view taken along line XIV-XIV in Fig. 13. Fig. 15 is a schematic cross-sectional view of the wiring layer 3 and the conductive bridge member 7 in the semiconductor device 100 according to the third embodiment. The semiconductor device 100 shown in Figs. 13 to 15 basically has the same configuration as the semiconductor device 100 shown in Fig. 8 and can achieve the same effects, but differs in that the wiring layer 3 includes a conductive bridge member 7.

[0125] The conductive bridge member 7 is disposed so as to be sandwiched between the first wiring layer 3 a and the second wiring layer 3 b in the y direction. As shown in Fig. 13, the conductive bridge member 7 connects the first wiring layer 3 a and the second wiring layer 3 b. The conductive bridge member 7 is conductive.

[0126] In this manner, the first wiring layer 3a and the second wiring layer 3b are electrically and thermally connected. As a result, the electrical resistance and thermal resistance in the wiring layer 3 are reduced. Furthermore, since the first wiring layer 3a and the second wiring layer 3b are electrically connected, the semiconductor device 100 is improved in resistance to oscillation. As a result, by using a wide bandgap semiconductor as the semiconductor element 2, high-speed operation of the semiconductor device 100 is possible.

[0127] The conductive bridge member 7 is disposed at a distance of 0.1 mm or more from the electric field intensity mitigating portion 24 so that the electric field formed by the conductive bridge member 7 does not affect the electric field intensity mitigating portion 24 .

[0128] The shape of the conductive bridge member 7 as viewed in the y direction may be the same as the shape of the wiring layer 3. In this way, the thermal resistance in the wiring layer 3 can be suppressed.

[0129] 15 , at least one of the thickness Ty of the conductive bridge member 7 in the y direction (the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31) and the thickness Tz of the conductive bridge member 7 in the z direction may be 1.0 mm or less. This reduces eddy current loss, thereby suppressing the electrical resistance in the wiring layer 3.

[0130] 16 to 20 are schematic cross-sectional views of modified examples of the wiring layer 3 and the conductive bridge member 7 in the semiconductor device 100 according to the third embodiment. As shown in Fig. 16, the cross-sectional shape of the conductive bridge member 7 as viewed from the x direction may be U-shaped. Specifically, a groove GR may be provided in the center of the conductive bridge member 7 in the y direction. The groove GR extends in the x direction.

[0131] In this way, the thicknesses Ty and Tz of the conductive bridge member 7 can be reduced, which in turn reduces eddy current loss and suppresses electrical resistance in the wiring layer 3.

[0132] 17 , the cross-sectional shape of the conductive bridge member 7 when viewed from the x direction may be O-shaped. Specifically, a hollow HL may be provided in the center of the conductive bridge member 7 in the z direction and the y direction. The hollow HL extends in the x direction.

[0133] In this way, the thicknesses Ty and Tz of the conductive bridge member 7 can be reduced, which in turn reduces eddy current loss and suppresses electrical resistance in the wiring layer 3.

[0134] 18 , a plurality of grooves GR may be provided in the conductive bridge member 7. The plurality of grooves GR extend in the x direction. In this way, the electrical resistance in the wiring layer 3 can be reduced.

[0135] 19, the conductive bridge member 7 includes a high thermal conductivity bridge layer 71 and a high electrical conductivity bridge layer 72. The high electrical conductivity bridge layer 72 is laminated on the high thermal conductivity bridge layer 71. As shown in FIG. 19, the high thermal conductivity bridge layers 71 and the high electrical conductivity bridge layers 72 are laminated alternately.

[0136] The stacking direction of the high thermal conductivity bridge layer 71 and the high electrical conductivity bridge layer 72 is the z direction as shown in FIG. 19 . The material constituting the high thermal conductivity bridge layer 71 may be the same as that of the high thermal conductivity layer 32, such as graphite. The material constituting the high electrical conductivity bridge layer 72 may be the same as that of the high electrical conductivity layer 31, such as copper. In this way, the thermal resistance in the wiring layer 3 can be suppressed.

[0137] 20, the conductive bridge member 7 includes a high conductivity bridge layer 72 and an insulating bridge layer 73. The high conductivity bridge layer 72 is laminated on the insulating bridge layer 73. As shown in FIG. 20, the insulating bridge layers 73 and the high conductivity bridge layers 72 are laminated alternately.

[0138] The potential of the conductive bridge member 7 is uniform across the conductive bridge member 7 when viewed from the x direction. The insulating bridge layer 73 does not need to have a high withstand voltage. Therefore, the material forming the insulating bridge layer 73 may be, for example, polyimide.

[0139] That is, a thin film may be used as the insulating bridge layer 73. By using a thin insulating bridge layer 73, the area occupied by the high conductivity bridge layer 72 increases. In this way, the electrical resistance in the wiring layer 3 can be reduced.

[0140] <Effects> According to the semiconductor device 100, the wiring layer 3 includes a first wiring layer 3 a, a second wiring layer 3 b, and a conductive bridge member 7. The second wiring layer 3 b is disposed apart from the first wiring layer 3 a. The conductive bridge member 7 connects the first wiring layer 3 a and the second wiring layer 3 b.

[0141] In this way, the first wiring layer 3 a and the second wiring layer 3 b are electrically and thermally connected, which results in a reduction in the electrical resistance and thermal resistance in the wiring layer 3. Furthermore, since the first wiring layer 3 a and the second wiring layer 3 b are electrically connected, the semiconductor device 100 has improved resistance to oscillation.

[0142] According to the semiconductor device 100, the thickness Ty of the conductive bridge member 7 in the stacking direction (y direction) is 1.0 mm or less.

[0143] In this way, eddy current loss can be reduced, that is, the electrical resistance in the wiring layer 3 can be suppressed.

[0144] According to the semiconductor device 100, the conductive bridge member 7 includes a high thermal conductivity bridge layer 71 and a high electrical conductivity bridge layer 72. The high electrical conductivity bridge layer 72 is stacked on the high thermal conductivity bridge layer 71. The high thermal conductivity bridge layers 71 and the high electrical conductivity bridge layers 72 are stacked alternately.

[0145] This configuration makes it possible to suppress the thermal resistance in the wiring layer 3. According to the semiconductor device 100, the conductive bridge member 7 includes a high conductivity bridge layer 72 and an insulating bridge layer 73. The insulating bridge layer 73 is stacked on the high conductivity bridge layer 72.

[0146] In this way, a thin film such as polyimide can be used as the insulating bridge layer 73. As a result, the area occupied by the high conductivity bridge layer 72 in the cross section of the conductive bridge member 7 increases. In this way, the electrical resistance in the wiring layer 3 can be reduced.

[0147] Fourth Embodiment <Configuration of Semiconductor Device> Fig. 21 is a schematic plan view of a semiconductor device 100 according to a fourth embodiment. Fig. 21 corresponds to Fig. 1. Fig. 22 is a schematic front view of the semiconductor device 100 according to the fourth embodiment. Fig. 22 corresponds to Fig. 2. The semiconductor device 100 shown in Figs. 21 and 2 basically has the same configuration as the semiconductor device 100 shown in Figs. 1 and 2 and can obtain the same effects, but differs in that it includes a metal block portion 35.

[0148] 22, the wiring layer 3 is connected to the front surface main electrode 22a via a metal block portion 35. The wiring layer 3 is connected to the first main surface 10a of the third conductive portion 11c via the metal block portion 35.

[0149] 22 , the wiring layer 3 may be connected to the metal block portion 35 via a joint 57. The metal block portion 35 may be connected to the front surface main electrode 22a via a joint 56. The metal block portion 35 may be connected to the first main surface 10a of the third conductive portion 11c via a joint 58.

[0150] The material forming the metal block portion 35 may be a material having high electrical conductivity and high thermal conductivity, such as copper (Cu) or a copper alloy.

[0151] Current and heat pass through the joints 56, 57, and 58 in the z direction (thickness direction). Therefore, the materials forming the joints 56, 57, and 58 may have high thermal conductivity in order to reduce the thermal resistance at the joints 56, 57, and 58. The joining material forming the joints 56, 57, and 58 may be the same as the joining material forming the joints 51, 52, and 53. The joints 56, 57, and 58 may be formed using solder.

[0152] 22 , by disposing a metal block portion 35 between the wiring layer 3 and the surface main electrode 22 a, the shape of the wiring layer 3 can be made rectangular when viewed in the y direction. When the wiring layer 3 has a rectangular shape, the yield in manufacturing the wiring layer 3 is improved. As a result, the manufacturing cost of the wiring layer 3 can be reduced.

[0153] <Operation and Effect> The semiconductor device 100 includes the metal block portion 35. The wiring layer 3 is connected to the electrode 21 via the metal block portion 35.

[0154] In this way, the shape of the wiring layer 3 can be made rectangular. When the shape of the wiring layer 3 is rectangular, the yield in manufacturing the wiring layer 3 is improved. As a result, the manufacturing cost of the wiring layer 3 can be reduced.

[0155] Fifth Embodiment Here, a power conversion device to which the semiconductor devices described in the above-mentioned first to fourth embodiments are applied will be described. Although the present disclosure is not limited to a specific power conversion device, the following will describe a case in which the present disclosure is applied to a three-phase inverter as the fifth embodiment.

[0156] Fig. 23 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied. The power conversion system shown in Fig. 23 is composed of a power supply 400, a power conversion device 200, and a load 300. The power supply 400 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 400 can be composed of various elements, such as a DC system, a solar cell, or a storage battery. It may also be composed of a rectifier circuit or an AC / DC converter connected to an AC system. The power supply 400 may also be composed of a DC / DC converter that converts DC power output from the DC system into a predetermined power.

[0157] The power conversion device 200 is a three-phase inverter connected between a power source 400 and a load 300, and converts DC power supplied from the power source 400 into AC power and supplies the AC power to the load 300. As shown in Fig. 23 , the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.

[0158] The load 300 is a three-phase electric motor that is driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0159] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheel diodes (neither of which is shown). When the switching elements are switched, DC power supplied from the power source 400 is converted into AC power and supplied to the load 300. There are various specific circuit configurations for the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full-bridge circuit that can be configured from six switching elements and six freewheel diodes connected in anti-parallel to each switching element.

[0160] The semiconductor device 100 according to at least one of the first to fourth embodiments is configured as a semiconductor module 202 for at least one of the switching elements and freewheel diodes of the main conversion circuit 201. Two of the six switching elements are connected in series to form upper and lower arms, and each upper and lower arm constitutes one phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to a load 300.

[0161] The main conversion circuit 201 also includes a drive circuit (not shown) that drives each switching element. The drive circuit may be built into the semiconductor module 202, or may be provided separately from the semiconductor module 202. The drive circuit generates drive signals that drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. To maintain a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or greater than the threshold voltage of the switching element, and to maintain a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or less than the threshold voltage of the switching element.

[0162] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 203 then outputs a control command (control signal) to a drive circuit included in the main conversion circuit 201 so that an on signal is output to a switching element that should be in the on state at each time point, and an off signal is output to a switching element that should be in the off state at each time point. In accordance with this control signal, the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0163] In the power conversion device according to the present embodiment, the semiconductor device 100 according to the first to fourth embodiments described above is applied as the semiconductor module 202 to at least one of the switching elements and free wheel diodes of the main conversion circuit 201, thereby improving electrical insulation and improving the reliability of the power conversion device. Note that the free wheel diodes may be integral with the switching elements, or may be substituted by the body diodes of the switching elements.

[0164] In the present embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used. In addition, when supplying power to a single-phase load, the present disclosure may also be applied to a single-phase inverter. Furthermore, when supplying power to a DC load, etc., the present disclosure may also be applied to a DC / DC converter or an AC / DC converter.

[0165] Furthermore, the power conversion device to which the present disclosure is applied is not limited to cases in which the above-mentioned load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0166] The semiconductor devices described in the respective embodiments can be combined in various ways as needed. In addition, the dependent claims described in the claims also contemplate dependent aspects corresponding to the combinations.

[0167] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. Unless there is a contradiction, at least two of the embodiments disclosed herein may be combined. The basic scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0168] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) A semiconductor device comprising: a substrate having a first main surface; a semiconductor element disposed on the first main surface and provided with an electrode; and a wiring layer connected to the electrode, wherein the wiring layer includes a high thermal conductivity layer and a high electrical conductivity layer stacked on the high thermal conductivity layer, and the stacking direction of the high thermal conductivity layer and the high electrical conductivity layer is perpendicular to the extending direction of the wiring layer in a plan view of the first main surface. (Appendix 2) The semiconductor device according to Appendix 1, wherein the high thermal conductivity layer is made of graphite, and the thermal conductivity of the high thermal conductivity layer in a direction perpendicular to the stacking direction is higher than the thermal conductivity in the stacking direction. (Appendix 3) The semiconductor device according to Appendix 1 or Appendix 2, wherein the material of the semiconductor element includes gallium oxide. (Appendix 4) The semiconductor device according to any one of Appendix 1 to Appendix 3, wherein the number of layers in the wiring layer formed by alternately stacking the high thermal conductivity layers and the high electrical conductivity layers is three or more. (Appendix 5) The semiconductor device according to Appendix 4, wherein the number of layers is an odd number. (Appendix 6) The semiconductor device according to any one of Appendixes 1 to 5, wherein a width of the wiring layer in the extending direction and a direction perpendicular to the stacking direction is 1.0 mm or more, and a thickness of the high conductivity layer in the stacking direction is 0.1 mm or more and 1.0 mm or less. (Appendix 7) The semiconductor device according to any one of Appendixes 1 to 6, wherein a shape of the high thermal conductivity layer when viewed from the stacking direction is the same as a shape of the high conductivity layer. (Appendix 8) The semiconductor device according to any one of Appendixes 1 to 3, wherein a metal coating layer is provided on a surface of at least a part of the wiring layer. (Appendix 9) The semiconductor device according to any one of Appendixes 1 to 8, wherein an electric field strength mitigating portion is provided in the semiconductor element, and the wiring layer is spaced apart from the electric field strength mitigating portion by 0.1 mm or more. (Appendix 10) A semiconductor device described in any one of Appendix 1 to Appendix 9, wherein the wiring layer includes a first wiring layer, a second wiring layer arranged at a distance from the first wiring layer, and a conductive bridge member connecting the first wiring layer and the second wiring layer.(Supplementary Note 11) The semiconductor device according to Supplementary Note 10, wherein the thickness of the conductive bridge member in the stacking direction is 1.0 mm or less. (Supplementary Note 12) The semiconductor device according to Supplementary Note 10 or Supplementary Note 11, wherein the conductive bridge member includes a high thermal conductivity bridge layer and a high electrical conductivity bridge layer stacked on the high thermal conductivity bridge layer, and the high thermal conductivity bridge layers and the high electrical conductivity bridge layers are stacked alternately. (Supplementary Note 13) The semiconductor device according to Supplementary Note 10 or Supplementary Note 11, wherein the conductive bridge member includes a high electrical conductivity bridge layer and an insulating bridge layer stacked on the high electrical conductivity bridge layer. (Supplementary Note 14) The semiconductor device according to any one of Supplementary Notes 1 to 13, further comprising a metal block portion, and the wiring layer is connected to the electrode via the metal block portion. (Supplementary Note 15) A power conversion device including the semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 14, comprising: a main conversion circuit that converts input power and outputs the converted power; and a control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit.

[0169] 1 Substrate, 2 Semiconductor element, 2a First semiconductor element, 2b Second semiconductor element, 3 Wiring layer, 3a First wiring layer, 3b Second wiring layer, 4 Lead, 6 Metal connection portion, 7 Conductive bridge member, 10a First main surface, 10b Second main surface, 11 Upper metal layer, 11a First conductive portion, 11b Second conductive portion, 11c Third conductive portion, 11d Fourth conductive portion, 11e Fifth conductive portion, 12 Insulating plate, 13 Lower metal layer, 14 Metal block layer, 14a First block, 14b Second block, 14c Third block, 15 Insulating sheet layer, 16 Base plate, 21 Electrode, 22 Main electrode, 22a Surface main electrode, 22b Back main electrode, 23 Control electrode, 24 Electric field intensity mitigation portion, 31 High conductivity layer, 32 High thermal conductivity layer, 33 Metal coating layer, 34 Side surface, 35 metal block portion, 41 first lead, 42 second lead, 43 third lead, 44 fourth lead, 45 fifth lead, 51, 52, 53, 54, 55, 56, 57, 58 joint portion, 71 high thermal conductivity bridge layer, 72 high electrical conductivity bridge layer, 73 insulating bridge layer, 81 sealing portion, 82 case, 83 mounting portion, 100 semiconductor device, 200 power conversion device, 201 main conversion circuit, 202 semiconductor module, 203 control circuit, 300 load, 400 power supply, De1, De2, De3 shortest distance, GR groove, HL hollow, Le width, R1, R2 curved surface portion, s1 first region, s2 second region, s3 third region, w width, We width.

Claims

1. A substrate having a first main surface, A semiconductor element disposed on the first main surface and having electrodes provided, The electrode comprises a wiring layer connected to the electrode, The wiring layer includes a high thermal conductivity layer and a high conductivity layer laminated on the high thermal conductivity layer. The lamination direction of the high thermal conductivity layer and the high conductivity layer is perpendicular to the extension direction of the wiring layer in a plan view of the first main surface. The aforementioned semiconductor element is provided with an electric field strength relaxation section. The aforementioned wiring layer includes a portion that is separated from the electric field strength relaxation portion, wherein the semiconductor device.

2. The material constituting the aforementioned high thermal conductivity layer is graphite. The semiconductor device according to claim 1, wherein in the high thermal conductivity layer, the thermal conductivity in a direction perpendicular to the stacking direction is greater than the thermal conductivity in the stacking direction.

3. The semiconductor device according to claim 1, wherein the material constituting the semiconductor element includes gallium oxide.

4. The semiconductor device according to claim 1, wherein the number of layers in the wiring layer, which is formed by alternately stacking the high thermal conductivity layer and the high conductivity layer, is three or more.

5. The semiconductor device according to claim 4, wherein the number of layers is odd.

6. The width of the wiring layer in the direction perpendicular to the extending direction and the stacking direction is 1.0 mm or more. The semiconductor device according to claim 1, wherein the thickness of the high conductivity layer in the stacking direction is 0.1 mm or more and 1.0 mm or less.

7. The semiconductor device according to claim 1, wherein the shape of the high thermal conductivity layer as viewed from the stacking direction is the same as the shape of the high conductivity layer.

8. The semiconductor device according to claim 1, wherein a metal coating layer is provided on at least a portion of the surface of the wiring layer.

9. The semiconductor device according to claim 1, wherein the wiring layer is spaced at least 0.1 mm away from the electric field strength relaxation portion.

10. The semiconductor device according to claim 1, wherein the wiring layer includes a first wiring layer, a second wiring layer spaced apart from the first wiring layer, and a conductive bridge member connecting the first wiring layer and the second wiring layer.

11. The semiconductor device according to claim 10, wherein the thickness of the conductive bridge member in the stacking direction is 1.0 mm or less.

12. The conductive bridge member includes a high thermal conductivity bridge layer and a high conductivity bridge layer laminated on the high thermal conductivity bridge layer. The semiconductor device according to claim 10, wherein the high thermal conductivity bridge layer and the high conductivity bridge layer are alternately stacked.

13. The semiconductor device according to claim 10, wherein the conductive bridge member includes a high conductivity bridge layer and an insulating bridge layer laminated on the high conductivity bridge layer.

14. Equipped with a metal block section, The semiconductor device according to claim 1, wherein the wiring layer is connected to the electrode via the metal block portion.

15. The wiring layer has a side surface facing the electric field strength relaxation portion, The semiconductor device according to claim 1, wherein the shape of the side surface when viewed from the stacking direction is U-shaped.

16. The wiring layer is A first portion extending in the aforementioned extending direction and spaced apart from the electric field strength relaxation portion, The semiconductor device according to claim 1, further comprising: a second portion disposed between the first portion and the electrode.

17. A semiconductor device according to any one of claims 1 to 16, comprising a main conversion circuit that converts and outputs input power, A power conversion device comprising a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit.