Lead frame, semiconductor device, and power conversion device

Abstract

A lead frame (3) is provided with at least one high thermal conductivity layer (32) and at least one high electric conductivity layer (31). The high thermal conductivity layer (32) and the high electric conductivity layer (31) are alternately stacked. At least one of the high thermal conductivity layer (32) and the high electric conductivity layer (31) includes at least two layers.

Description

Lead frame, semiconductor device and power conversion device

[0001] The present disclosure relates to a lead frame, a semiconductor device, and a power conversion device.

[0002] Cooling of the element is important for semiconductor devices using power semiconductor elements (hereinafter referred to as elements), which pass the main current in the thickness direction of the semiconductor element. It is well known that in semiconductor devices with single-sided cooling, using a lead frame to guide the heat flow to the cooling surface instead of using wires in the wiring layer on the surface of the element improves cooling efficiency. However, a simple copper lead frame does not achieve significant improvement because the flow path is longer than if the heat flow were guided directly from the back surface of the element to the cooling surface, resulting in higher thermal resistance. Therefore, it has been proposed to use a lead frame in which a high-thermal conductivity layer, such as graphite, which has a higher thermal conductivity than copper, is added to a high-conductivity layer, such as copper.

[0003] Japanese Patent Application Laid-Open No. 2019-071399

[0004] M. Otsuki, et. al., “Advanced thin wafer IGBTs with new thermal management solution”, in Proc. 15th ISPSD, p. 144-147, 2003

[0005] However, since the high electrical conductivity layer and the high thermal conductivity layer have different linear expansion coefficients, there is a risk that warping will occur if thermal stress occurs in the lead frame.

[0006] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a lead frame in which the occurrence of warping is suppressed, and a semiconductor device and a power conversion device that include such a lead frame.

[0007] A lead frame according to the present disclosure includes at least one high thermal conductivity layer and at least one high electrical conductivity layer. The high thermal conductivity layers and the high electrical conductivity layers are alternately stacked. At least one of the high thermal conductivity layer and the high electrical conductivity layer has two or more layers.

[0008] A semiconductor device according to the present disclosure includes a semiconductor element and the lead frame. A power conversion device according to the present disclosure includes a main conversion circuit and a control circuit. The main conversion circuit has the semiconductor device and converts and outputs input power. The control circuit outputs a control signal to the main conversion circuit to control the main conversion circuit.

[0009] According to the above, it is possible to obtain a lead frame in which the occurrence of warping is suppressed, and a semiconductor device and a power conversion device each including the lead frame.

[0010] 1 is a schematic plan view of a lead frame according to a first embodiment. FIG. 2 is a schematic front view of a lead frame according to a first embodiment. FIG. 3 is a schematic front view of a first modified example of the lead frame according to the first embodiment. FIG. 4 is a schematic plan view of a fourth modified example of the lead frame according to the first embodiment. FIG. 5 is a schematic front view of a semiconductor device according to the first embodiment. FIG. 6 is a schematic front view of a first modified example of the semiconductor device according to the first embodiment. FIG. 7 is a schematic front view of a second modified example of the semiconductor device according to the first embodiment. FIG. 8 is a schematic front view of a third modified example of the semiconductor device according to the first embodiment. FIG. 9 is a schematic front view of a fourth modified example of the semiconductor device according to the first embodiment. FIG. 10 is a schematic front view of a fifth modified example of the semiconductor device according to the first embodiment. FIG. 11 is a schematic front view of a fifth modified example of the semiconductor device according to the first embodiment. FIG. 12 is a schematic front view of a sixth modified example of the semiconductor device according to the first embodiment. FIG. 13 is a schematic plan view of a seventh modified example of the semiconductor device according to the first embodiment. Fig. 1 is a schematic plan view of a semiconductor device according to a second embodiment. Fig. 2 is a schematic front view of a semiconductor device according to the second embodiment. Fig. 3 is a schematic front view of a first modified example of the semiconductor device according to the second embodiment. Fig. 4 is a schematic plan view of a second modified example of the semiconductor device according to the second embodiment. Fig. 5 is a schematic front view of a second modified example of the semiconductor device according to the second embodiment. Fig. 6 is a block diagram showing the configuration of a power conversion system to which a power conversion device according to a third embodiment is applied.

[0011] Hereinafter, embodiments of the present disclosure will be described. Unless otherwise specified, the same or corresponding parts in the following drawings will be denoted by the same reference numerals, and the description thereof will not be repeated.

[0012] First Embodiment <Lead Frame Configuration> Fig. 1 is a schematic plan view of a lead frame 3 according to the first embodiment. Fig. 2 is a schematic front view of the lead frame 3 according to the first embodiment. The lead frame 3 shown in Figs. 1 and 2 is a wiring layer used in a power semiconductor device 100, and includes at least one high thermal conductivity layer 32 and at least one high electrical conductivity layer 31. That is, the lead frame 3 is formed by stacking the high thermal conductivity layer 32 and the high electrical conductivity layer 31 on top of each other. The high electrical conductivity layer 31 is adjacent to the high thermal conductivity layer 32.

[0013] 2, the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is defined as the z direction. The directions perpendicular to the z direction are defined as the x direction and the y direction. The y direction is perpendicular to the x direction.

[0014] The material constituting the high thermal conductivity layer 32 is, for example, graphite. As will be described later, graphite has anisotropy. The material constituting the high electrical conductivity layer 31 is, for example, copper (Cu) or a copper alloy. The material constituting the high electrical conductivity layer 31 may also be, for example, aluminum (Al) or an aluminum alloy. The high thermal conductivity layer 32 has high thermal conductivity in the in-plane direction. Furthermore, the high electrical conductivity layer 31 has high electrical conductivity. In this way, a lead frame 3 can be obtained that maintains high electrical conductivity and has reduced thermal resistance.

[0015] The conductivity of graphite is 10 ６ S / m. Therefore, the conductivity of graphite is low compared to the conductivity of other conductors. On the other hand, the conductivity of copper (Cu) is 5×10 ７ The conductivity of copper is about 50 times higher than that of graphite. Therefore, when high thermal conductivity layer 32 is made of graphite and high conductivity layer 31 is made of copper, most of the current flowing through lead frame 3 flows through high conductivity layer 31.

[0016] Here, lead frame 3 according to the first embodiment is characterized in that at least one of high thermal conductivity layer 32 and high electrical conductivity layer 31 has two or more layers, as shown in Fig. 2. From a different perspective, the number of layers in lead frame 3 may be three or more. In lead frame 3 according to the first embodiment, the number of layers is seven, as shown in Fig. 2.

[0017] The high electrical conductivity layer 31 and the high thermal conductivity layer 32 have different linear expansion coefficients. When a current flows through the lead frame 3, the lead frame 3 generates heat. Therefore, if the lead frame 3 is a bimetal formed of one high thermal conductivity layer 32 and one high electrical conductivity layer 31 (if the lead frame 3 has two layers), thermal stress occurs in the lead frame 3 due to the difference in the linear expansion coefficients of the high electrical conductivity layer 31 and the high thermal conductivity layer 32. As a result, the lead frame 3 warps.

[0018] The number of layers is three or more, and high thermal conductivity layers 32 and high electrical conductivity layers 31 are alternately stacked, thereby suppressing deviations in temperature distribution and current density distribution within lead frame 3. As a result, the occurrence of warpage in lead frame 3 is suppressed.

[0019] The number of layers in the lead frame 3 may be 3 or more, 5 or more, or 7 or more. A larger number of layers further suppresses deviations in the temperature distribution and current density distribution within the lead frame 3. As a result, the influence of warpage per layer of the lead frame 3 is reduced.

[0020] The number of layers in the lead frame 3 may be an even number as long as it is three or more, but may also be an odd number. If the number of layers in the lead frame 3 is an odd number, the lead frame 3 is configured to be mirror symmetrical in the layering direction (z direction). As a result, thermal stresses generated in the layering direction (z direction) cancel each other out, further suppressing the occurrence of warpage.

[0021] The thickness variation in the z-direction of each of the high thermal conductivity layers 32 and the high electrical conductivity layers 31 may be 10% or less, which balances the thermal stress generated in the stacking direction (z-direction) and further suppresses warpage.

[0022] 2, the thickness t of each high conductivity layer 31 in the stacking direction (z direction) may be 1.0 mm or less, or 0.64 mm or less, which can reduce eddy current loss caused by the skin effect.

[0023] When the high conductivity layer 31 is formed as a thin film, when it is formed by coating, or when it is formed by plating, the thickness t of each high conductivity layer 31 in the stacking direction (z direction) is less than 0.1 mm. If the thickness t of each high conductivity layer 31 in the stacking direction (z direction) is less than 0.1 mm, the lead frame 3 will not be self-supporting. Therefore, the thickness t of each high conductivity layer 31 in the stacking direction (z direction) may be 0.1 mm or more. In this way, the lead frame 3 will be self-supporting.

[0024] Fig. 3 is a schematic front view of a first modified example of the lead frame 3 according to the first embodiment. Fig. 3 corresponds to Fig. 2. The lead frame 3 shown in Fig. 3 basically has the same configuration as the lead frame 3 shown in Figs. 1 and 2 and can achieve the same effects, but differs in that the number of layers is three.

[0025] 3, the number of layers in the lead frame 3 may be three. The lead frame 3 may be formed from one high thermal conductivity layer 32 and two high electrical conductivity layers 31, or may be formed from two high thermal conductivity layers 32 and one high electrical conductivity layer 31.

[0026] If there are two or more high conductivity layers 31, the high conductivity layers 31 may be disposed on both ends in the stacking direction (z direction) of the lead frame 3. The linear expansion coefficient of graphite as the high thermal conductivity layer 32 is smaller than the linear expansion coefficient of copper as the high conductivity layer 31. Therefore, by disposing the high conductivity layers 31 on both ends in the stacking direction (z direction) of the lead frame 3, the occurrence of warping is suppressed.

[0027] 1, the shape of the lead frame 3 as viewed from the stacking direction (z direction) is rectangular. The shape of the lead frame 3 as viewed from the stacking direction (z direction) may be changed to suit the semiconductor device 100 to be used.

[0028] 4 to 6 are schematic plan views of modified examples 2 to 4 of the lead frame 3 according to the first embodiment. Figures 4 to 6 correspond to Figure 1. Each of the lead frames 3 shown in Figures 4 to 6 basically has the same configuration as the lead frame 3 shown in Figures 1 and 2 and can achieve the same effects, but the shape of the lead frame 3 in plan view from the stacking direction (z direction) is different.

[0029] As shown in FIG. 4 , the lead frame 3 may have a cross shape in a plan view from the stacking direction (z direction). In a plan view from the stacking direction (z direction), the lead frame 3 is mirror-symmetric in the x direction. Specifically, the width of the lead frame 3 in the y direction does not have to be constant in the x direction. In a plan view from the stacking direction (z direction), the lead frame 3 includes a central region Q1 and a peripheral region Q2 in the x direction. The width w1 of the lead frame 3 in the y direction in the central region Q1 may be larger than the width w2 in the peripheral region Q2.

[0030] 5, the lead frame 3 may have a U-shape in plan view in the stacking direction (z direction). In plan view in the stacking direction (z direction), the lead frame 3 does not have to be mirror-symmetric in the x direction. The width w1 of the lead frame 3 in the y direction in the central region Q1 may be smaller than the width w2 in the peripheral region Q2.

[0031] 6, in a plan view seen from the stacking direction (z direction), the side surface 34 of the lead frame 3 may include a curved portion RN and a straight portion LN. The curved portion RN and the straight portion LN are arranged in a central region Q1.

[0032] In a plan view seen from the stacking direction (z direction), the shape of high thermal conductivity layer 32 may be the same as or different from the shape of high electrical conductivity layer 31. The number of layers, shape, etc. of lead frame 3 may be determined based on a balance of materials, processing, performance, etc. when manufacturing lead frame 3.

[0033] Next, a method for manufacturing the lead frame 3 will be described. The lead frame 3 may be manufactured using any method. The high thermal conductivity layer 32 and the high electrical conductivity layer 31 may be joined via a brazing material. The high thermal conductivity layer 32 and the high electrical conductivity layer 31 are joined by heating and pressurizing the brazing material. The brazing material may be, for example, an active metal brazing material.

[0034] The high thermal conductivity layer 32 and the high electrical conductivity layer 31 may be bonded together using a bonding material. The bonding material may be a non-metallic material such as a resin. The high thermal conductivity layer 32 and the high electrical conductivity layer 31 may also be bonded together directly.

[0035] The high thermal conductivity layer 32 may be formed by a chemical vapor deposition (CVD) method. Specifically, the lead frame 3 may be manufactured by using the high electrical conductivity layer 31 as a base material and depositing the high thermal conductivity layer 32 on the surface of the high electrical conductivity layer 31.

[0036] Each of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 may be shaped using punching, laser processing, or electrical discharge processing. Then, the shaped high thermal conductivity layers 32 and high electrical conductivity layers 31 may be alternately stacked to bond the high thermal conductivity layers 32 and high electrical conductivity layers 31.

[0037] Alternatively, high thermal conductivity layers 32 and high electrical conductivity layers 31 may be alternately stacked, and the high thermal conductivity layers 32 and high electrical conductivity layers 31 may be joined together, and then the stacked high thermal conductivity layers 32 and high electrical conductivity layers 31 may be shaped using punching, laser processing, or electrical discharge processing.

[0038] <Configuration of Semiconductor Device> Fig. 7 is a schematic plan view of the semiconductor device 100 according to the first embodiment. Fig. 8 is a schematic front view of the semiconductor device 100 according to the first embodiment.

[0039] The semiconductor device 100 shown in Figures 7 and 8 is, for example, a power semiconductor device 100, and mainly comprises a substrate 1, a semiconductor element 2, a lead frame 3 as a wiring layer, leads 4, and a metal block portion 35.

[0040] The substrate 1 has a first main surface 10a and a second main surface 10b. The first main surface 10a is a surface on which a semiconductor element 2 is mounted. The second main surface 10b is a surface opposite to the first main surface 10a.

[0041] The lead frame 3 is disposed so that the direction perpendicular to the first main surface 10a is the stacking direction (z direction) of the lead frame 3. In other words, the direction in which the first main surface 10a extends is the x direction and the y direction.

[0042] 8, the substrate 1 includes an upper metal layer 11, an insulating plate 12, and a lower metal layer 13. The upper metal layer 11 is disposed on the insulating plate 12. The insulating plate 12 is disposed on the lower metal layer 13. In the z-direction, the upper metal layer 11 is located opposite the lower metal layer 13 when viewed from the insulating plate 12.

[0043] The surface of the upper metal layer 11 forms a first major surface 10a, and the back surface of the lower metal layer 13 forms a second major surface 10b.

[0044] A circuit pattern is formed on the upper metal layer 11. Specifically, the material constituting the upper metal layer 11 may include, for example, copper (Cu), aluminum (Al), a copper alloy, or an aluminum alloy. The material constituting the upper metal layer 11 is a material having high electrical conductivity and high thermal conductivity.

[0045] 7, the upper metal layer 11 includes a first conductive portion 11a, a second conductive portion 11b, and a third conductive portion 11c, which are arranged on the insulating plate 12 and spaced apart from one another.

[0046] In a plan view of the first main surface 10a, the first conductive portion 11a has a rectangular shape. In a plan view of the first main surface 10a, the second conductive portion 11b has an L-shape. In a plan view of the first main surface 10a, the third conductive portion 11c has a rectangular shape. In a plan view of the first main surface 10a, the first conductive portion 11a, the second conductive portion 11b, and the third conductive portion 11c may each have any shape.

[0047] The insulating plate 12 is, for example, a ceramic insulating substrate. That is, the material constituting the insulating plate 12 is, for example, ceramic having insulating properties. The material constituting the insulating plate 12 is, for example, silicon nitride (Si ３ N ４ ), aluminum nitride (AlN), and aluminum oxide (Al ２ O ３ The insulating plate 12 may be an insulating sheet.

[0048] The material constituting the lower metal layer 13 may be the same as or different from the material constituting the upper metal layer 11. The thickness of the lower metal layer 13 in the z direction may be the same as or different from the thickness of the upper metal layer 11 in the z direction.

[0049] A circuit pattern is formed on the upper metal layer 11. Therefore, the thickness of the lower metal layer 13 in the z direction may be smaller than the thickness of the upper metal layer 11 in the z direction. In this way, the volume of the lower metal layer 13 may be made the same as the volume of the upper metal layer 11.

[0050] 7, the semiconductor element 2 is disposed on the first main surface 10a in the second conductive portion 11b. The semiconductor element 2 is provided with an electrode 21. The electrode 21 includes, for example, a main electrode 22 and a control electrode 23. The main electrode 22 includes a front main electrode 22a and a back main electrode 22b. As shown in FIG. 8, the back main electrode 22b is connected to the first main surface 10a via a joint 51.

[0051] A main current flows through the main electrode 22. The control electrode 23 controls the main current. The front main electrode 22a and the control electrode 23 are disposed on the front surface (upper surface) of the semiconductor element 2. The back main electrode 22b is disposed on the back surface (lower surface) of the semiconductor element 2. On the front surface of the semiconductor element 2, the front main electrode 22a and the control electrode 23 are disposed spaced apart from each other.

[0052] The electrode 21 is made of a material having high electrical and thermal conductivity. The electrode 21 may be formed by copper (Cu) plating or nickel (Ni) plating. The electrode 21 may be a plate made of copper or a copper alloy. The plate may be directly bonded to the semiconductor element 2, or may be bonded to the semiconductor element 2 via a bonding material that uses a sintered material containing fine particles of silver (Ag), copper (Cu), or the like.

[0053] When the material forming the surface main electrode 22a is copper or a copper alloy, the short-circuit resistance of the semiconductor element 2 is improved.

[0054] An electric field strength reduction portion 24 is provided on the surface of the semiconductor element 2. The electric field strength reduction portion 24 reduces the electric field strength generated by the electrode 21. As shown in FIGS. 7 and 8 , the electric field strength reduction portion 24 is arranged so as to surround the electrode 21. In other words, the electric field strength reduction portion 24 is formed on the outer periphery of the surface of the semiconductor element 2. As shown in FIG. 7 , the shape of the electric field strength reduction portion 24 may be, for example, annular. Specifically, the electric field strength reduction portion 24 may be a termination structure called a guard ring.

[0055] The shape of the electric field intensity reduction portion 24 does not have to be annular. Specifically, the electric field intensity reduction portion 24 may be a termination structure called a JTE (Junction Termination Extension) structure. The electric field intensity reduction portion 24 is, for example, a p-type region formed by ion implantation. The electric field intensity reduction portion 24 may be formed on the surface of the semiconductor element 2 as shown in FIG. 8 , or may be formed inside the semiconductor element 2.

[0056] The semiconductor element 2 is a so-called power semiconductor element 2 that controls electric power. Any material may be used as a material for forming the semiconductor element 2. Examples of materials for forming the semiconductor element 2 include silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (GaO). ２ O ３ ), diamond, etc. In particular, gallium oxide has a low thermal conductivity. Therefore, when the material constituting the semiconductor element 2 is gallium oxide (Ga ２ O ３ ), the effect of dissipating heat from the main electrode 22 located near the heat source is increased.

[0057] The semiconductor element 2 in the first embodiment is an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET), but may be a diode or have other functions. The type of the semiconductor element is not particularly limited, but may be, for example, a vertical semiconductor element. The semiconductor device 100 may be a semiconductor device 100 using flip-chip mounting in which the front surface main electrode 22 a is connected to the substrate 1.

[0058] 8, the lead frame 3 is connected to the electrode 21 and the substrate 1. Specifically, the lead frame 3 is connected to the front surface main electrode 22a via a metal block portion 35. The lead frame 3 is connected to the first main surface 10a of the third conductive portion 11c via the metal block portion 35.

[0059] As shown in Fig. 8 , the lead frame 3 is connected to the metal block portion 35 via a joint 57. The metal block portion 35 is connected to the surface main electrode 22a via a joint 56. The metal block portion 35 may be connected to the first main surface 10a of the third conductive portion 11c via a joint 58. As shown in Figs. 7 and 8 , the lead frame 3 is arranged so as to be sandwiched between two metal block portions 35 in the x direction. Note that the lead frame 3 may be connected directly to the metal block portions 35 without via the joint 57.

[0060] The joint 57 is provided on an end surface of the lead frame 3. The end surface is a surface where the high thermal conductivity layer 32 and the high electrical conductivity layer 31 are exposed. In other words, the end surface is formed from the high thermal conductivity layer 32 and the high electrical conductivity layer 31. In this way, heat and current do not flow along the stacking direction (z direction) of the lead frame 3, but flow from the end surface along the extension direction (x direction) of the lead frame 3.

[0061] The metal block 35 may be made of a material having high electrical conductivity and high thermal conductivity, such as copper (Cu) or a copper alloy. Heat generated in the semiconductor element 2 flows along the extension direction (x direction) of the lead frame 3.

[0062] The lead frame 3 extends from the second conductive portion 11b toward the third conductive portion 11c. As shown in FIG. 7 , the extension direction of the lead frame 3 in a plan view of the first main surface 10a is, for example, the x direction. The stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 in a plan view of the first main surface 10a is the z direction. In other words, the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is a direction perpendicular to the extension direction of the lead frame 3 in a plan view of the first main surface 10a.

[0063] The lead frame 3 is arranged at a distance from the electric field intensity mitigating portion 24 so that the electric field formed by the lead frame 3 does not affect the electric field intensity mitigating portion 24. The lead frame 3 may be arranged at a distance of 0.3 mm or more from the electric field intensity mitigating portion 24.

[0064] Electric current and heat pass through the joints 51, 56, 57, and 58. Therefore, the material forming the joints 51, 56, 57, and 58 may have high electrical conductivity and high thermal conductivity. The joints 51, 56, 57, and 58 may be formed using a sintered material containing fine particles of silver (Ag), copper (Cu), or the like, or may be formed using solder.

[0065] The joints 51, 56, 57, and 58 may be formed by liquid phase diffusion of Sn—Cu, Sn—Ag, or the like. This allows the joint thickness in the z direction to be 0.02 mm or less. As a result, the thermal resistance at the joints 51, 56, 57, and 58 can be reduced.

[0066] The control electrode 23 is connected to the first main surface 10a of the first conductive portion 11a via a metal connection portion 6. The material forming the metal connection portion 6 may be, for example, copper (Cu), aluminum (Al), a copper alloy, or an aluminum alloy.

[0067] The metal connection portion 6 may be a wire formed by wire bonding or may be a clip. The metal connection portion 6 is arranged at a distance from the electric field strength reduction portion 24 so that the electric field formed by the metal connection portion 6 does not affect the electric field strength reduction portion 24. As shown in FIG. 8 , the metal connection portion 6 extends so as to surround the electric field strength reduction portion 24.

[0068] The leads 4 are provided on the first main surface 10a. As shown in Fig. 8, the leads 4 extend in the z direction. The leads 4 may be made of copper.

[0069] The lead 4 may be directly connected to the upper metal layer 11. Specifically, the lead 4 may be connected to the upper metal layer 11 using ultrasonic welding or laser welding. The lead 4 may be indirectly connected to the upper metal layer 11 using a bonding material such as solder. The bonding material for connecting the lead 4 to the upper metal layer 11 may be the same as the bonding material for forming the bonding portions 51, 56, 57, and 58.

[0070] 7, the lead 4 includes a first lead 41, a second lead 42, and a third lead 43. The first lead 41 is connected to the first main surface 10a of the first conductive portion 11a. The first lead 41 is spaced apart from the metal connection portion 6 in the y direction. The second lead 42 is connected to the first main surface 10a of the second conductive portion 11b. The second lead 42 is spaced apart from the semiconductor element 2 in the x direction. The third lead 43 is connected to the first main surface 10a of the third conductive portion 11c. The third lead 43 is spaced apart from the lead frame 3 in the x direction.

[0071] As described above, graphite is an example of a material that constitutes the high thermal conductivity layer 32. Graphite has a layered structure. Graphite is anisotropic. Specifically, the thermal conductivity of graphite is high in the in-plane directions in which the hexagonal rings are arranged (x direction and y direction in the semiconductor device 100 according to the first embodiment). On the other hand, the thermal conductivity of graphite is low in the direction perpendicular to the in-plane directions (z direction in the semiconductor device 100 according to the first embodiment).

[0072] As shown in Figure 8, the end face of the lead frame 3 perpendicular to the stacking direction (z direction) is connected to the metal block portion 35. In this way, heat and current flow from the metal block portion 35 along the extension direction (x direction) of the lead frame 3. In other words, the direction of heat flow is the in-plane direction of the graphite. In the high thermal conductivity layer 32, the thermal conductivity in the direction perpendicular to the stacking direction (z direction) (x direction) is greater than the thermal conductivity in the stacking direction (z direction). Therefore, the thermal resistance of the lead frame 3 can be reduced.

[0073] Fig. 9 is a schematic plan view of a first modified example of the semiconductor device 100 according to the first embodiment. Fig. 9 corresponds to Fig. 7. Fig. 10 is a schematic front view of the first modified example of the semiconductor device 100 according to the first embodiment. Fig. 10 corresponds to Fig. 8. The semiconductor device 100 shown in Figs. 9 and 10 basically has the same configuration as the semiconductor device 100 shown in Figs. 7 and 8 and can achieve the same effects, but the shape of the metal block portion 35 is different.

[0074] In a front view seen from the y direction, the metal block portion 35 may be L-shaped. Specifically, the metal block portion 35 has a notch n. The lead frame 3 has a lower surface 36 facing the first main surface 10a. The lower surface 36 is continuous with an end surface of the lead frame 3 in the extension direction (x direction). As shown in FIG. 10 , the end surface and the lower surface 36 of the lead frame 3 are arranged to face the notch n. The joint portion 57 is provided not only on the end surface of the lead frame 3 but also on the lower surface 36. This facilitates positioning of the lead frame 3.

[0075] Fig. 11 is a schematic plan view of a second modification of the semiconductor device 100 according to the first embodiment. Fig. 11 corresponds to Fig. 7. Fig. 12 is a schematic front view of the second modification of the semiconductor device 100 according to the first embodiment. Fig. 12 corresponds to Fig. 8. The semiconductor device 100 shown in Figs. 11 and 12 basically has the same configuration as the semiconductor device 100 shown in Figs. 7 and 8 and can achieve the same effects, but differs in that the lower surface 36 of the lead frame 3 is connected to the metal block portion 35.

[0076] 12 , the lead frame 3 may be connected to the metal block portion 35 at the bottom surface 36 instead of at the end surface. From a different perspective, the entire metal block portion 35 may overlap the lead frame 3 in a plan view of the first main surface 10 a.

[0077] In this way, the metal block portion 35 may have any shape, may be inclined relative to the first main surface 10a, or may be curved.

[0078] Fig. 13 is a schematic plan view of modified example 3 of semiconductor device 100 according to embodiment 1. Fig. 13 corresponds to Fig. 7. Fig. 14 is a schematic front view of modified example 3 of semiconductor device 100 according to embodiment 1. Fig. 14 corresponds to Fig. 8. Semiconductor device 100 shown in Figs. 13 and 14 basically has the same configuration as semiconductor device 100 shown in Figs. 7 and 8 and can obtain the same effects, but differs in that it does not have metal block portion 35.

[0079] The lead frame 3 may be disposed at a distance from the electric field intensity mitigating portion 24 so that the electric field formed by the lead frame 3 does not affect the electric field intensity mitigating portion 24. Therefore, as shown in Figures 13 and 14, one end of the lead frame 3 may be connected to the front surface main electrode 22a via a joint 52 without via the metal block portion 35. The other end of the lead frame 3 may be connected to the first main surface 10a of the third conductive portion 11c via a joint 53 without via the metal block portion 35.

[0080] In order to suppress the thermal resistance at the joints 52 and 53, the material forming the joints 52 and 53 may be a material having high thermal conductivity. The bonding material forming the joints 52 and 53 may be the same as the bonding material forming the joints 51, 56, 57, and 58, or may be formed using solder. The joints 52 and 53 may be formed by thickly applying the bonding material so that the lead frame 3 is spaced 0.3 mm or more from the electric field intensity mitigation portion 24. Since the metal block portion 35 is not required, the manufacturing cost of the semiconductor device 100 can be reduced.

[0081] Fig. 15 is a schematic front view of a fourth modification of the semiconductor device 100 according to the first embodiment. Fig. 15 corresponds to Fig. 8. The semiconductor device 100 shown in Fig. 15 basically has the same configuration as the semiconductor device 100 shown in Figs. 7 and 8 and can achieve the same effects, but differs in that it includes a case 82. Note that Fig. 15 shows the internal structure of the case 82 for ease of explanation.

[0082] The semiconductor device 100 according to the first embodiment may be used as a case-type module. The semiconductor device 100 includes a sealing portion 81, a case 82, and a mounting portion 83. The lower metal layer 13 is connected to the mounting portion 83 via a joint 54. The bonding material forming the joint 54 may be the same as the bonding material forming the joints 51, 56, 57, and 58. Electric current and heat pass through the joint 54 in the z direction (thickness direction). Therefore, the material forming the joint 54 has high thermal conductivity.

[0083] The substrate 1, semiconductor element 2, lead frame 3, and case 82 are mounted on the front surface (top surface) of the mounting portion 83. A cooler may be provided on the back surface (bottom surface) of the mounting portion 83. The cooler may be, for example, a pin fin or a cooling fin having another shape. A part of the cooler may be connected to the back surface (bottom surface) of the mounting portion 83, or the entire cooler may be connected to the back surface (bottom surface) of the mounting portion 83. The cooler may be connected to the mounting portion 83 via a TIM (thermal interface material).

[0084] The substrate 1, the semiconductor element 2, and the lead frame 3 are disposed inside the case 82. Inside the case 82, the substrate 1, the semiconductor element 2, and the lead frame 3 are sealed by a sealing portion 81. The leads 4 extend from the substrate 1 toward the outside of the sealing portion 81.

[0085] The sealing portion 81 has insulating properties. The sealing portion 81 is formed by potting or supplying a sheet material. The material constituting the sealing portion 81 is not particularly limited, but may be, for example, silicone gel or epoxy resin.

[0086] The semiconductor device 100 may be a case-type module as shown in FIG. 15, a transfer mold-type module, or any other module.

[0087] 7 and 8 is a so-called 1-in-1 type in which one semiconductor element 2 is mounted on one module. The circuit configuration of the semiconductor device 100 may be a 2-in-1 type in which two semiconductor elements 2 are mounted on one module, or a so-called 6-in-1 type in which six semiconductor elements 2 are mounted on one module.

[0088] Fig. 16 is a schematic plan view of Modification 5 of semiconductor device 100 according to embodiment 1. Fig. 16 corresponds to Fig. 7. Fig. 17 is a schematic front view of Modification 5 of semiconductor device 100 according to embodiment 1. Fig. 17 corresponds to Fig. 8. Semiconductor device 100 shown in Figs. 16 and 17 basically has the same configuration as semiconductor device 100 shown in Figs. 7 and 8 and can obtain the same effects, but differs in that the circuit configuration of semiconductor device 100 is a 2-in-1 type that forms a half bridge.

[0089] 16, the upper metal layer 11 includes a first conductive portion 11a, a second conductive portion 11b, a third conductive portion 11c, a fourth conductive portion 11d, and a fifth conductive portion 11e. The first conductive portion 11a, the second conductive portion 11b, the third conductive portion 11c, the fourth conductive portion 11d, and the fifth conductive portion 11e are arranged on the insulating plate 12 at a distance from one another.

[0090] The semiconductor element 2 includes a first semiconductor element 2a and a second semiconductor element 2b. The first semiconductor element 2a is disposed on the first main surface 10a in the second conductive portion 11b. The second semiconductor element 2b is disposed on the first main surface 10a in the third conductive portion 11c.

[0091] The lead frame 3 includes a first wiring layer 3 a on the upper arm side and a second wiring layer 3 b on the lower arm side. One end of the first wiring layer 3 a is connected to the front surface main electrode 22 a of the first semiconductor element 2 a via a metal block portion 35. The other end of the first wiring layer 3 a is connected to the first main surface 10 a of the third conductive portion 11 c via the metal block portion 35.

[0092] One end of the second wiring layer 3b is connected to the surface main electrode 22a of the second semiconductor element 2b via the metal block portion 35. The other end of the second wiring layer 3b is connected to the first main surface 10a of the fourth conductive portion 11d via the metal block portion 35.

[0093] 16 , the first wiring layer 3a extends from the second conductive portion 11b toward the third conductive portion 11c. As shown in FIG. 16 , the extension direction of the first wiring layer 3a in a plan view of the first main surface 10a is the x-direction. Furthermore, the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 in a plan view of the first main surface 10a is, for example, the z-direction.

[0094] The second wiring layer 3b extends from the third conductive portion 11c toward the fourth conductive portion 11d. As shown in FIG. 16 , the extension direction of the second wiring layer 3b in a plan view of the first main surface 10a is the y direction. The stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 in a plan view of the first main surface 10a is, for example, the z direction. The extension direction (x direction) of the first wiring layer 3a is perpendicular to the extension direction (y direction) of the second wiring layer 3b.

[0095] The first wiring layer 3a and the second wiring layer 3b may be arranged parallel to each other, or may be arranged in a line.

[0096] The control electrode 23 of the first semiconductor element 2a is connected to the first main surface 10a of the first conductive portion 11a via the metal connection portion 6. The control electrode 23 of the second semiconductor element 2b is connected to the first main surface 10a of the fifth conductive portion 11e via the metal connection portion 6.

[0097] The leads 4 include a first lead 41, a second lead 42, a third lead 43, a fourth lead 44, and a fifth lead 45. The first lead 41 is connected to the first main surface 10a of the first conductive portion 11a. The second lead 42 is connected to the first main surface 10a of the second conductive portion 11b. The third lead 43 is connected to the first main surface 10a of the third conductive portion 11c. The fourth lead 44 is connected to the first main surface 10a of the fourth conductive portion 11d. The fifth lead 45 is connected to the first main surface 10a of the fifth conductive portion 11e.

[0098] The first lead 41 and the fifth lead 45 extract signals to the outside. The second lead 42 is connected to a terminal having a P-type conductivity. The third lead 43 is connected to an AC terminal. The fourth lead 44 is connected to a terminal having an N-type conductivity.

[0099] The fourth lead 44 and the second wiring layer 3b may be connected above the substrate 1 in the z direction.

[0100] A lead frame different from the lead frame 3 may be connected to the second wiring layer 3b. The material constituting the lead frame may be, for example, copper, which has high conductivity. An insulating layer may be sandwiched between the lead frame and the first wiring layer 3a. In other words, the lead frame may be arranged so as to form a parallel plate with respect to the first wiring layer 3a. This can suppress parasitic inductance in the semiconductor device 100.

[0101] Fig. 18 is a schematic plan view of a sixth modification of the semiconductor device 100 according to the first embodiment. Fig. 18 corresponds to Fig. 7. The semiconductor device 100 shown in Fig. 18 basically has the same configuration as the semiconductor device 100 shown in Fig. 7 and Fig. 8 and can obtain the same effects, but differs in that a plurality of semiconductor elements 2 are arranged on the first main surface 10a of the second conductive portion 11b.

[0102] The semiconductor element 2 includes a first semiconductor element 2 a and a second semiconductor element 2 b. The first semiconductor element 2 a and the second semiconductor element 2 b are each disposed on the first main surface 10 a in the second conductive portion 11 b. The second semiconductor element 2 b is disposed spaced apart from the first semiconductor element 2 a in the y direction.

[0103] The lead frame 3 includes a first wiring layer 3 a and a second wiring layer 3 b. One end of the first wiring layer 3 a is connected to the surface main electrode 22 a of the first semiconductor element 2 a via a metal block portion 35. The other end of the first wiring layer 3 a is connected to the first main surface 10 a of the third conductive portion 11 c via the metal block portion 35.

[0104] One end of the second wiring layer 3b is connected to the surface main electrode 22a of the second semiconductor element 2b via the metal block portion 35. The other end of the second wiring layer 3b is connected to the first main surface 10a of the third conductive portion 11c via the metal block portion 35.

[0105] The first wiring layer 3a and the second wiring layer 3b each extend from the second conductive portion 11b toward the third conductive portion 11c. As shown in Figure 18, the extension direction of the first wiring layer 3a and the second wiring layer 3b in a plan view of the first main surface 10a is the x-direction. The first wiring layer 3a and the second wiring layer 3b are arranged parallel to each other. The first wiring layer 3a and the second wiring layer 3b are arranged spaced apart from each other in the y-direction.

[0106] The control electrode 23 of each of the first semiconductor element 2 a and the second semiconductor element 2 b is connected to the first main surface 10 a of the first conductive portion 11 a via the metal connection portion 6 .

[0107] In this way, a plurality of semiconductor elements 2 may be disposed on the substrate 1. The number of semiconductor elements 2 may be two or more, or may be three or more.

[0108] Fig. 19 is a schematic plan view of a seventh modification of the semiconductor device 100 according to the first embodiment. Fig. 19 corresponds to Fig. 18. The semiconductor device 100 shown in Fig. 19 basically has the same configuration as the semiconductor device 100 shown in Fig. 18 and can obtain the same effects, but differs in that the first semiconductor element 2a and the second semiconductor element 2b are connected to at least a part of the lead frame 3.

[0109] 19 , the first semiconductor element 2a and the second semiconductor element 2b are each connected to one lead frame 3 via a metal block portion 35. The first main surface 10a of the third conductive portion 11c is connected to the lead frame 3 via two metal block portions 35. In this manner, a plurality of semiconductor elements 2 may be connected to one lead frame 3. Two or more, or three or more, semiconductor elements 2 may be connected to one lead frame 3.

[0110] As shown in FIG. 19 , in a plan view seen from the stacking direction (z direction), the longitudinal direction of the lead frame 3 is the y direction. In a plan view seen from the stacking direction (z direction), the lateral direction of the lead frame 3 is the x direction. By doing so, the cross-sectional area of ​​the lead frame 3 increases in the x direction. As a result, the thermal resistance and electrical resistance of the lead frame 3 are suppressed. In addition, the multiple electrodes 21 are connected to each other with extremely small impedance. Therefore, the multiple electrodes 21 are at the same potential. As a result, oscillation in the semiconductor device 100 is suppressed.

[0111] <Effects> The lead frame 3 according to the present disclosure includes at least one high thermal conductivity layer 32 and at least one high electrical conductivity layer 31. The high thermal conductivity layers 32 and the high electrical conductivity layers 31 are alternately stacked. At least one of the high thermal conductivity layers 32 and the high electrical conductivity layers 31 has two or more layers.

[0112] This suppresses deviations in temperature distribution and current density distribution within the lead frame 3. As a result, the occurrence of warpage in the lead frame 3 is suppressed.

[0113] According to the lead frame 3, the high conductivity layer 31 has two or more layers. The high conductivity layers 31 are disposed on both ends of the lead frame 3.

[0114] This further suppresses the occurrence of warpage in the lead frame 3. According to the above-described lead frame 3, the number of layers in the lead frame 3 formed by alternately stacking high thermal conductivity layers 32 and high electrical conductivity layers 31 is an odd number.

[0115] In this way, the lead frame 3 is configured to be mirror symmetrical in the stacking direction (z direction), and as a result, thermal stresses occurring in the stacking direction (z direction) cancel each other out, further suppressing the occurrence of warping.

[0116] In the lead frame 3, the material constituting the high thermal conductivity layer 32 is graphite. The thermal conductivity of the high thermal conductivity layer 32 in the direction (x direction) perpendicular to the stacking direction (z direction) of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is greater than the thermal conductivity of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 in the stacking direction (z direction).

[0117] In this way, the direction of heat flow is along the in-plane direction of the high thermal conductivity layer 32. In the high thermal conductivity layer 32, the thermal conductivity in the direction (x direction) perpendicular to the stacking direction (z direction) is greater than the thermal conductivity in the stacking direction (z direction). Therefore, it is possible to obtain a lead frame 3 that maintains high electrical conductivity and has reduced thermal resistance.

[0118] According to the lead frame 3, the thickness t of the high electrical conductivity layer 31 in the stacking direction (z direction) of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is 0.1 mm or more and 1.0 mm or less.

[0119] In this way, the electrical resistance in the lead frame 3 and the eddy current loss caused by the skin effect can be reduced.

[0120] The semiconductor device 100 according to the present disclosure includes a semiconductor element 2 and the lead frame 3 described above.

[0121] In this way, the reliability of the semiconductor device 100 is improved because the lead frame 3 is suppressed from warping.

[0122] According to the semiconductor device 100, the material constituting the semiconductor element 2 contains gallium oxide.

[0123] Gallium oxide has a low thermal conductivity. Therefore, the material constituting the semiconductor element 2 is gallium oxide (Ga ２ O ３ ), the effect of dissipating heat from the main electrode 22 located near the heat source is increased.

[0124] According to the semiconductor device 100, a joint is provided on the end surface of the lead frame 3. In this way, heat and current do not flow along the stacking direction (z direction) of the lead frame 3, but flow from the end surface along the extending direction (x direction) of the lead frame 3.

[0125] According to the semiconductor device 100, the semiconductor element 2 includes a first semiconductor element 2 a and a second semiconductor element 2 b. The second semiconductor element 2 b is disposed spaced apart from the first semiconductor element 2 a. The first semiconductor element 2 a and the second semiconductor element 2 b are connected to at least a portion of the lead frame 3.

[0126] In this way, oscillation between the plurality of semiconductor elements 2 is suppressed. Second Embodiment. <Configuration of Semiconductor Device> FIG. 20 is a schematic front view of a semiconductor device 100 according to a second embodiment. FIG. 20 corresponds to FIG. 7. FIG. 21 is a schematic front view of a semiconductor device 100 according to a second embodiment. FIG. 21 corresponds to FIG. 8. The semiconductor device 100 shown in FIGS. 20 and 21 basically has the same configuration as the semiconductor device 100 shown in FIGS. 7 and 8 and can achieve the same effects, except that the stacking direction of the lead frame 3 is horizontal to the first main surface 10a. Even in this case, the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is perpendicular to the extension direction (x direction) of the lead frame.

[0127] In the second embodiment, the lead frame 3 is disposed so that the direction parallel to the first main surface 10a is the stacking direction (y direction) of the lead frame 3.

[0128] By arranging the lead frame 3 in this manner, heat and current do not flow along the stacking direction (y direction) of the lead frame 3, but rather flow from the end face along the extension direction (x direction and z direction) of the lead frame 3.

[0129] The lead frame 3 may be, for example, a U-shaped lead frame 3 as shown in Fig. 5. In this way, the lead frame 3 is disposed at a distance from the electric field intensity mitigating portion 24 so that the electric field formed by the lead frame 3 does not affect the electric field intensity mitigating portion 24.

[0130] 21 , the lead frame 3 has a side surface 34. The side surface 34 is connected to the front surface main electrode 22a via a joint 52. The side surface 34 is connected to the first main surface 10a of the third conductive portion 11c via a joint 53. The side surface 34 faces the electric field intensity mitigating portion 24. A portion of the lead frame 3 extends to surround the electric field intensity mitigating portion 24.

[0131] Specifically, the side surface 34 includes a first region s1, a second region s2, and a third region s3. The first region s1 is continuous with the second region s2 and the bonding portion 52. The first region s1 extends in the z direction. From a different perspective, the first region s1 extends perpendicular to the first main surface 10a. The second region s2 is continuous with the first region s1 and the third region s3. The second region s2 extends in the x direction. From a different perspective, the second region s2 extends parallel to the first main surface 10a. The third region s3 is continuous with the second region s2 and the bonding portion 53. The third region s3 extends in the z direction. From a different perspective, the third region s3 extends perpendicular to the first main surface 10a. When viewed in the y direction, the first region s1, the second region s2, and the third region s3 each have a linear shape. In this way, the lead frame 3 is disposed at a distance from the electric field intensity mitigating portion 24 .

[0132] Fig. 22 is a schematic front view of a first modification of the semiconductor device 100 according to the second embodiment. Fig. 22 corresponds to Fig. 21. The semiconductor device 100 shown in Fig. 22 basically has the same configuration as the semiconductor device 100 shown in Fig. 20 and Fig. 22 and can obtain the same effects, but differs in that a metal coating layer 33 is provided on at least a part of the surface of the lead frame 3.

[0133] As described above, the lead frame 3 is connected to the surface main electrode 22a via the joint 52. The lead frame 3 is also connected to the first main surface 10a of the third conductive portion 11c via the joint 53. As shown in Fig. 22, by providing the metal coating layer 33 on the surface of the lead frame 3 connected to the joints 52 and 53 (the end faces where the high thermal conductivity layer 32 and the high electrical conductivity layer 31 are exposed), the compatibility between the joints 52 and 53 and the surface of the lead frame 3 is improved. As a result, the thermal and electrical contact resistance at the interfaces between the joints 52 and 53 and the lead frame 3 is reduced.

[0134] The metal coating layer 33 may be formed by plating. The metal coating layer 33 may be, for example, a silver (Ag) plating layer, a copper (Cu) plating layer, a nickel (Ni) plating layer, or a tin (Sn) plating layer. The metal coating layer 33 may be, for example, a plating layer with a multilayer structure in which different materials are stacked. The material constituting the metal coating layer 33 is not particularly limited, and may be a material other than those mentioned above.

[0135] The metal coating layer 33 does not have to be formed by plating, but may be formed by, for example, physical vapor deposition or chemical vapor deposition.

[0136] Furthermore, the metal coating layer 33 only needs to be provided on at least the surface (end face) of the lead frame 3 where the lead frame 3 is connected to the bonding portions 52 and 53 , and may be formed on the entire surface of the lead frame 3 .

[0137] Fig. 23 is a schematic plan view of modified example 2 of semiconductor device 100 according to embodiment 2. Fig. 23 corresponds to Fig. 20. Fig. 24 is a schematic front view of modified example 2 of semiconductor device 100 according to embodiment 2. Fig. 24 corresponds to Fig. 21. Semiconductor device 100 shown in Figs. 23 and 24 basically has the same configuration as semiconductor device 100 shown in Figs. 20 and 21 and can obtain the same effects, but differs in that it includes metal block portion 35.

[0138] The lead frame 3 may be, for example, the rectangular lead frame 3 shown in Fig. 1. As shown in Fig. 24, by disposing a metal block portion 35 between the lead frame 3 and the surface main electrode 22a, the shape of the lead frame 3 can be made rectangular when viewed from the y direction. When the lead frame 3 has a rectangular shape, the yield in manufacturing the lead frame 3 is improved. As a result, the manufacturing cost of the lead frame 3 can be reduced.

[0139] <Operation and Effect> According to the lead frame 3, the metal coating layer 33 is provided on at least a part of the surface.

[0140] This improves the compatibility of the lead frame 3 with the joints 52 and 53. As a result, thermal and electrical contact resistance at the interfaces between the joints 52 and 53 and the lead frame 3 is reduced.

[0141] According to the lead frame 3, the lamination direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is perpendicular to the extending direction of the lead frame.

[0142] In this way, heat and current do not flow along the stacking direction (z direction) of the lead frame 3, but flow from the end face along the extending direction of the lead frame 3 (x direction and z direction).

[0143] Third Embodiment Here, a power conversion device will be described that applies the semiconductor device described in the first and second embodiments. Although the present disclosure is not limited to a specific power conversion device, the following third embodiment will describe a case where the present disclosure is applied to a three-phase inverter.

[0144] FIG. 25 is a block diagram showing the configuration of a power conversion system to which the power conversion apparatus according to the third embodiment is applied. The power conversion system shown in FIG. 25 includes a power supply 400, a power conversion apparatus 200, and a load 300. The power supply 400 is a DC power supply and supplies DC power to the power conversion apparatus 200. The power supply 400 can be configured from various sources, such as a DC system, a solar cell, or a storage battery. Alternatively, the power supply 400 may be configured from a rectifier circuit connected to an AC system or an AC / DC converter. Alternatively, the power supply 400 may be configured from a DC / DC converter that converts DC power output from the DC system into a predetermined power.

[0145] The power conversion device 200 is a three-phase inverter connected between a power source 400 and a load 300, and converts DC power supplied from the power source 400 into AC power and supplies the AC power to the load 300. As shown in Fig. 25 , the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.

[0146] The load 300 is a three-phase electric motor that is driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0147] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheel diodes (neither of which is shown). When the switching elements are switched, DC power supplied from the power supply 400 is converted into AC power and supplied to the load 300. There are various specific circuit configurations for the main conversion circuit 201, but the main conversion circuit 201 according to the third embodiment is a two-level three-phase full-bridge circuit that can be configured with six switching elements and six freewheel diodes connected in anti-parallel to each switching element. The freewheel diodes may be integral with the switching elements or may be substituted by body diodes of the switching elements.

[0148] The semiconductor device 100 according to at least one of the first and second embodiments is configured as a semiconductor module 202 for at least one of the switching elements and freewheel diodes of the main conversion circuit 201. Six switching elements are connected in series in pairs to form upper and lower arms, each of which constitutes a phase (U phase, V phase, W phase) of a full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to a load 300.

[0149] The main conversion circuit 201 also includes a drive circuit (not shown) that drives each switching element. The drive circuit may be built into the semiconductor module 202, or may be provided separately from the semiconductor module 202. The drive circuit generates drive signals that drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. To maintain a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or greater than the threshold voltage of the switching element, and to maintain a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or less than the threshold voltage of the switching element.

[0150] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 203 then outputs a control command (control signal) to a drive circuit included in the main conversion circuit 201 so that an on signal is output to a switching element that should be in the on state at each time point, and an off signal is output to a switching element that should be in the off state at each time point. In accordance with this control signal, the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0151] In the power conversion device of this embodiment 3, the semiconductor device 100 of the above-mentioned embodiments 1 and 2 is applied as a semiconductor module 202 to at least one of each switching element and each freewheel diode of the main conversion circuit 201, thereby improving electrical insulation and improving the reliability of the power conversion device.

[0152] In the third embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. In the third embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used. When supplying power to a single-phase load, the present disclosure may also be applied to a single-phase inverter. Furthermore, when supplying power to a DC load or the like, the present disclosure may also be applied to a DC / DC converter or an AC / DC converter.

[0153] Furthermore, the power conversion device to which the present disclosure is applied is not limited to cases in which the above-mentioned load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0154] The semiconductor devices described in the respective embodiments can be combined in various ways as needed. In addition, the dependent claims described in the claims also contemplate dependent aspects corresponding to the combinations.

[0155] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. Unless there is a contradiction, at least two of the embodiments disclosed herein may be combined. The basic scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0156] Various aspects of the present disclosure are described below as appendices. (Appendix 1) A lead frame comprising at least one high thermal conductivity layer and at least one high electrical conductivity layer, the high thermal conductivity layers and the high electrical conductivity layers being alternately stacked, and at least one of the high thermal conductivity layer and the high electrical conductivity layer having two or more layers. (Appendix 2) The lead frame according to Appendix 1, wherein the high electrical conductivity layer has two or more layers, and the high electrical conductivity layers are disposed on both ends of the lead frame. (Appendix 3) The lead frame according to Appendix 1 or Appendix 2, wherein the number of layers in the lead frame formed by alternately stacking the high thermal conductivity layers and the high electrical conductivity layers is odd. (Supplementary Note 4) The lead frame according to any one of Supplementary Notes 1 to 3, wherein a material constituting the high thermal conductivity layer is graphite, and wherein the thermal conductivity of the high thermal conductivity layer in a direction perpendicular to a stacking direction of the high thermal conductivity layer and the high electrical conductivity layer is greater than the thermal conductivity in the stacking direction of the high thermal conductivity layer and the high electrical conductivity layer. (Supplementary Note 5) The lead frame according to any one of Supplementary Notes 1 to 4, wherein a thickness of the high electrical conductivity layer in the stacking direction of the high thermal conductivity layer and the high electrical conductivity layer is 0.1 mm or more and 1.0 mm or less. (Supplementary Note 6) The lead frame according to any one of Supplementary Notes 1 to 5, wherein a metal coating layer is provided on at least a part of the surface of the lead frame. (Supplementary Note 7) A semiconductor device comprising: a semiconductor element; and the lead frame according to any one of Supplementary Notes 1 to 6, connected to the semiconductor element. (Supplementary Note 8) The semiconductor device according to Supplementary Note 7, wherein a material constituting the semiconductor element includes gallium oxide. (Supplementary Note 9) The semiconductor device according to Supplementary Note 7 or Supplementary Note 8, wherein a bonding portion is provided on an end surface of the lead frame. (Supplementary Note 10) The semiconductor device according to any one of Supplementary Note 7 to Supplementary Note 9, wherein the semiconductor element includes a first semiconductor element and a second semiconductor element arranged spaced apart from the first semiconductor element, and the first semiconductor element and the second semiconductor element are connected to at least a portion of the lead frame.(Supplementary Note 11) The semiconductor device according to any one of Supplementary Note 7 to Supplementary Note 10, wherein a stacking direction of the high thermal conductivity layer and the high electrical conductivity layer is a direction perpendicular to an extending direction of the lead frame. (Supplementary Note 12) A power conversion device having the semiconductor device according to any one of Supplementary Note 7 to Supplementary Note 11, comprising: a main conversion circuit that converts input power and outputs the power; and a control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit.

[0157] REFERENCE SIGNS LIST 1 Substrate, 2 Semiconductor element, 2a First semiconductor element, 2b Second semiconductor element, 3 Lead frame, 3a First wiring layer, 3b Second wiring layer, 4 Lead, 6 Metal connection portion, 10a First main surface, 10b Second main surface, 11 Upper metal layer, 11a First conductive portion, 11b Second conductive portion, 11c Third conductive portion, 11d Fourth conductive portion, 11e Fifth conductive portion, 12 Insulating plate, 13 Lower metal layer, 21 Electrode, 22 Main electrode, 22a Front surface main electrode, 22b Back surface main electrode, 23 Control electrode, 24 Electric field intensity mitigation portion, 31 High conductivity layer, 32 High thermal conductivity layer, 33 Metal coating layer, 34 Side surface, 35 Metal block portion, 36 Lower surface, 41 First lead, 42 Second lead, 43 Third lead, 44 Fourth lead, 45 Fifth lead, 51, 52, 53, 54, 56, 57, 58 Joint portion, 81 Sealing portion, 82 Case, 83 Mounting portion, 100 Semiconductor device, 200 Power conversion device, 201 Main conversion circuit, 202 Semiconductor module, 203 Control circuit, 300 Load, 400 Power supply, LN Straight portion, n Notched portion, Q1 Central region, Q2 Outer circumferential region, RN Curved portion, s1 First region, s2 Second region, s3 Third region, w1 Width, w2 Width.

Claims

1. A lead frame comprising at least one high thermal conductivity layer and at least one high electrical conductivity layer, The high thermal conductivity layer and the high conductivity layer are stacked alternately. At least one of the high thermal conductivity layer and the high electrical conductivity layer consists of two or more layers. The aforementioned high conductivity layer consists of two or more layers. A lead frame in which the high conductivity layer is disposed at both ends of the lead frame.

2. The lead frame according to claim 1, wherein the number of layers in the lead frame, which is formed by alternately stacking the high thermal conductivity layer and the high conductivity layer, is odd.

3. The material constituting the aforementioned high thermal conductivity layer is graphite. The lead frame according to claim 1, wherein in the high thermal conductivity layer, the thermal conductivity in a direction perpendicular to the stacking direction of the high thermal conductivity layer and the high conductivity layer is greater than the thermal conductivity in the stacking direction of the high thermal conductivity layer and the high conductivity layer.

4. The lead frame according to claim 1, wherein the thickness of the high conductivity layer in the lamination direction of the high thermal conductivity layer and the high conductivity layer is 0.1 mm or more and 1.0 mm or less.

5. The lead frame according to claim 1, wherein a metal coating layer is provided on at least a portion of the surface of the lead frame.

6. Semiconductor elements and A semiconductor device comprising a lead frame according to any one of claims 1 to 5 connected to the semiconductor element.

7. The semiconductor device according to claim 6, wherein the material constituting the semiconductor element includes gallium oxide.

8. The semiconductor device according to claim 6, wherein a joint is provided on the end face of the lead frame.

9. The semiconductor element includes a first semiconductor element and a second semiconductor element that is spaced apart from the first semiconductor element. The semiconductor device according to claim 6, wherein the first semiconductor element and the second semiconductor element are connected to at least a portion of the lead frame.

10. The semiconductor device according to claim 6, wherein the stacking direction of the high thermal conductivity layer and the high conductivity layer is perpendicular to the extending direction of the lead frame.

11. A semiconductor device according to claim 6, comprising a main conversion circuit that converts and outputs input power, A power conversion device comprising a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit.