Reception device, control circuit, storage medium, and decoding method

Abstract

The present invention provides a reception device (20) capable of suppressing deterioration in decoding performance while suppressing calculation load in decoding a polar code. This reception device (20) for decoding a polar-encoded signal includes a likelihood generation unit (4) for acquiring, via a communication path (3), a transmitted transmission signal in which an information bit is polar-encoded by a transmission device (10), and generating a logarithmic likelihood ratio for the number corresponding to the number of code bits generated by polar encoding performed by the transmission device (10), and a polar decoding unit (5) for performing a decoding process for polar encoding by performing a calculation specified for an absolute value of the logarithmic likelihood ratio, and also generating an estimation bit for which the information bit is estimated by performing correction for improving decoding performance in accordance with the absolute value of the logarithmic likelihood ratio.

Description

Receiving device, control circuit, storage medium, and decoding method

[0001] The present disclosure relates to a receiving device, a control circuit, a storage medium, and a decoding method that perform polar decoding.

[0002] The decoding calculation for polar codes uses two types of formulas f(α, β) and g(α, β) to estimate information bits from the reception likelihood as shown in formula (1), where α and β are real numbers, and b is either 0 or 1.

[0003]

[0004] Of the two formulas, f(α, β) would result in a very complicated circuit if implemented as is, so it is often implemented as an approximate formula such as formula (2). In formula (2), sgn(x) is a sign function that returns -1 if x<0 and +1 if x≧0.

[0005]

[0006] However, when the approximation formula of Equation (2) is used, the decoding performance deteriorates. Therefore, implementation methods that achieve higher decoding performance are being studied. For example, Non-Patent Document 1 proposes a method of correcting the calculation result of the approximation formula of f(α, β) by a predetermined constant term (hereinafter referred to as "scaled min-sum") as a method of improving decoding performance, and reports that the decoding performance has been improved. Furthermore, Non-Patent Document 1 proposes that the value of the constant term to be multiplied is set to 0.9375 (= 1 - 2 －４ ) realizes processing in which multiplication is replaced by shift operations and subtraction.

[0007] Yuan Bo and Keshab K.Parhi. "Architecture optimizations for Bp Polar decoders." 2013 IEEE international conference on acoustics, speech and signal processing. IEEE, 2013.

[0008] In order to improve decoding performance, it is necessary to make corrections according to the code configuration, the state of the communication channel, the modulation method, etc. However, according to the above-mentioned conventional technology, a constant is multiplied. Therefore, there is a problem that improvement in decoding performance may not be expected depending on the code configuration, the state of the communication channel, the modulation method, etc. Furthermore, in the above-mentioned conventional technology, an accumulation is performed for correction, which increases the calculation load depending on the value of the constant used for multiplication, and a complex circuit is required for hardware implementation.

[0009] The present disclosure has been made in view of the above, and aims to provide a receiving device that can suppress degradation of decoding performance while suppressing the calculation load in decoding polar codes.

[0010] In order to solve the above-mentioned problems and achieve the object, the present disclosure provides a receiving device that decodes a polar-coded signal. The receiving device is characterized by including: a likelihood generating unit that acquires, via a communication channel, a transmission signal in which information bits have been polar-coded by a transmitting device and transmitted, and generates a number of log-likelihood ratios corresponding to the number of code bits generated when the signal was polar-coded by the transmitting device; and a polar decoding unit that performs a decoding process for the polar-coded signal by performing a specified operation on the absolute value of the log-likelihood ratio, and performs correction to improve decoding performance according to the absolute value of the log-likelihood ratio, thereby generating estimated bits that estimate the information bits.

[0011] The receiving device of the present disclosure has an advantage that it is possible to suppress the deterioration of decoding performance while suppressing the calculation load in decoding polar codes.

[0012] 1 is a diagram showing an example of the configuration of a communication system according to the first embodiment; FIG. 2 is a flowchart showing the operation of a polar decoding unit included in a receiving device according to the first embodiment; FIG. 3 is a diagram showing an example of the configuration of a decoding circuit used for the iterative decoding calculation shown in FIG. 2 in a polar decoding unit included in a receiving device according to the first embodiment; FIG. 4 is a diagram showing the flow of decoding calculation in a decoding circuit shown in FIG. 3 used in a polar decoding unit included in a receiving device according to the first embodiment; FIG. 5 is a diagram showing an example of the configuration of a decoding circuit used when calculating an approximation formula of formula (2);

[0013] Hereinafter, a receiving device, a control circuit, a storage medium, and a decoding method according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0014] Embodiment 1. Fig. 1 is a diagram showing an example of the configuration of a communication system 30 according to embodiment 1. The communication system 30 includes a transmitting device 10 and a receiving device 20. The communication system 30 is a system in which the transmitting device 10 transmits a polar-encoded signal to the receiving device 20 via a communication path 3, and the receiving device 20 polar-decodes the signal that has been polar-encoded by the transmitting device 10 and received via the communication path 3. The transmitting device 10 includes a polar encoding unit 1 and a modulation unit 2. The receiving device 20 includes a likelihood generation unit 4 and a polar decoding unit 5.

[0015] In the transmitting device 10, the polar encoding unit 1 encodes k information bits s ０ , s １ , ..., s ｋ－１ (s ｉ∈{0, 1}), where k is an integer equal to or greater than 2. The polar encoding unit 1 obtains k information bits s ０ , s １ , ..., s ｋ－１ may be acquired from inside the transmitting device 10 or from outside the transmitting device 10. The polar encoding unit 1 ０ , s １ , ..., s ｋ－１ is polar-encoded, and an n-bit code bit c ０ , c １ , ..., c ｎ－１ (c ｉ ∈{0, 1}), where n is an integer equal to or greater than 2 and equal to or greater than k.

[0016] The modulation unit 2 generates an n-bit code bit c ０ , c １ , ..., c ｎ－１ The modulation unit 2 obtains the obtained n-bit code bit c ０ , c １ , ..., c ｎ－１ The modulation unit 2 modulates the signal to generate a transmission signal. The modulation unit 2 transmits the generated transmission signal to the receiving device 20 via a communication path 3.

[0017] In the receiving device 20, the likelihood generating unit 4 acquires, via the communication path 3, a transmission signal in which information bits have been polar-encoded and transmitted by the transmitting device 10. The likelihood generating unit 4 receives as input the signal transmitted from the transmitting device 10 and passed through the communication path 3, and generates n log-likelihood ratios l ０ , l １ , ..., l ｎ－１ (l ｉ ∈R) generated by the transmitting device 10. ０ , c １ , ..., c ｎ－１ The log-likelihood ratio l ０ , l １ , ..., l ｎ－１ Generate.

[0018] The polar decoder 5 receives n log-likelihood ratios l from the likelihood generator 4. ０ , l １, ..., l ｎ－１ The polar decoding unit 5 obtains n log-likelihood ratios l ０ , l １ , ..., l ｎ－１ The polar decoding unit 5 receives the k-bit estimated bits s(^) as the decoding result obtained from the decoding process. ０ , s(^) １ , ..., s(^) ｋ－１ (s(^) ｉ ∈{0, 1}). In this embodiment, the polar decoding unit 5 outputs the log-likelihood ratio l ０ , l １ , ..., l ｎ－１ By performing a specified operation on the absolute value of ０ , l １ , ..., l ｎ－１ Correction is performed to improve the decoding performance according to the absolute value of ０ , s １ , ..., s ｋ－１ The estimated bit s(^) ０ , s(^) １ , ..., s(^) ｋ－１ The polar decoder 5 generates the k-bit estimated bits s(^). ０ , s(^) １ , ..., s(^) ｋ－１ may be output to the inside of the receiving device 20 or may be output to the outside of the receiving device 20.

[0019] In the specification, since it is not possible to express a state in which ^ is added above s, the state in which ^ is added above s is expressed as s(^).

[0020] 2 is a flowchart showing the operation of the polar decoding unit 5 included in the receiving device 20 according to the first embodiment. The polar decoding unit 5 receives n log-likelihood ratios l from the likelihood generating unit 4. ０ , l １ , ..., l ｎ－１is input and initialization is performed (step S11). The polar decoding unit 5 repeatedly performs decoding calculations (step S12). In the example of FIG. 2, the polar decoding unit 5 repeatedly performs the decoding calculations m times, where m is an integer equal to or greater than 2. The polar decoding unit 5 outputs the result obtained by repeating the decoding calculations m times in step S12 as the decoding result (step S13). This type of decoding process is called "Belief Propagation (BP) decoding," "belief propagation," or "belief propagation." In this embodiment, the polar decoding unit 5 performs decoding processing and correction by repeatedly performing a specified calculation one or more times.

[0021] 3 is a diagram showing an example of the configuration of a decoding circuit used for the iterative decoding calculation shown in FIG. 2 in the polar decoding unit 5 included in the receiving device 20 according to the first embodiment. In the example of FIG. 3, the number n of log-likelihood ratios input to the polar decoding unit 5 is set to 8, and the number k of estimated bits to be estimated is set to 4. In the initialization, the polar decoding unit 5 converts the input from the right side of the decoding circuit shown in FIG. 3 into log-likelihood ratios l ｉ , and the input from the left side of the decoding circuit shown in FIG. 3 is set to 0 or ∞, and the decoding calculation proceeds from right to left along the decoding circuit. One round of decoding calculation in which the polar decoding unit 5 performs decoding calculation from right to left and from left to right is considered to be one decoding calculation. After repeating the decoding calculation a specified number of times, the polar decoding unit 5 calculates the decoding result from the log-likelihood ratio output from the leftmost side of the decoding circuit shown in FIG. 3. In the decoding circuit shown in FIG. 3, the polar decoding unit 5 performs specific decoding calculations at two locations, "xor" and "=". Note that in the example of FIG. 3, ∞ may be replaced with the maximum value within the implementable range or a sufficiently large number when performing computer simulation or hardware implementation.

[0022] Regarding the symbol with a + inside a circle shown in FIG. 3, the specification does not allow the symbol with a + inside a circle to be expressed, so the symbol with a + inside a circle is expressed by xor.

[0023] 4 is a diagram showing the flow of decoding calculations in the decoding circuit shown in FIG. 3 used in the polar decoding unit 5 provided in the receiving device 20 according to the first embodiment. As shown in FIG. 4, the basic configuration of the polar decoding unit 5, which is composed of one "xor" and one "=", is called a "unit." The unit of the polar decoding unit 5 is ａ , R ｂ , L ｃ , L ｄ is input, and L ａ , L ｂ , R ｃ , R ｄ The output is calculated as shown in equation (3).

[0024]

[0025] Here, f(α,β) and g(α,β) are expressed by equation (1), and in the calculation of equation (3), b = 0 is set and g(α,β) = α + β is used. f(α,β) is tanh, tanh －１ Therefore, an approximation of equation (2) is sometimes implemented as f(α, β).

[0026] FIG. 5 shows an example of the configuration of a decoding circuit used to calculate the approximation of Equation (2). The decoding circuit includes absolute value extraction units 51 and 52, a minimum value comparison unit 53, sign extraction units 54 and 55, and an exclusive OR calculation unit 56. The absolute value extraction unit 51 extracts the absolute value |α| of the input α. The absolute value extraction unit 52 extracts the absolute value |β| of the input β. The minimum value comparison unit 53 selects and outputs the smaller of the absolute value |α| of α and the absolute value |β| of β. The sign extraction unit 54 extracts the sign of the input α. The sign extraction unit 55 extracts the sign of the input β. The exclusive OR calculation unit 56 performs an exclusive OR calculation using the outputs from the minimum value comparison unit 53, the sign extraction unit 54, and the sign extraction unit 55 to obtain an output.

[0027] The circuit shown in Figure 5 calculates the absolute value and sign of two inputs, α and β in the example of Figure 5, and calculates the output by multiplying the smaller absolute value by the sign. In equation (2), the sign is multiplied by multiplication, but in hardware implementation, a single sign bit representing positive or negative is prepared, and the value of the single sign bit is inverted to invert the positive or negative sign, so this is realized using an XOR operation in Figure 5. In this case, sgn(x) outputs 1 if x<0 and 0 if x≥0. While the approximation formula for bit f(α,β) can be implemented in hardware as described above, this can cause degradation of decoding performance. In "scaled min-sum," implementation is performed by applying correction as f(α,β) = s * sgn(α)sgn(β)min(|α|, |β|), but depending on the value of the constant s, complex circuitry may be required for hardware implementation. Therefore, a method for performing correction calculations that is independent of the code configuration and does not require complex circuitry is needed.

[0028] The characteristic decoding algorithm of the polar decoding unit 5 in this embodiment will be described below. The characteristic decoding algorithm in this embodiment does not depend on the code structure of polar coding, and is based on tanh and tanh shown in equation (1) or (2). －１ This realizes a simple circuit implementation compared to the hardware implementation of the above. In this embodiment, the decoding calculation is performed by replacing equation (3) with equation (4).

[0029]

[0030] R ｉ , L ｉ represents a real number. The polar decoding unit 5 performs the calculation shown in equation (5) for the operator αxorβ.

[0031]

[0032] Incidentally, D included in the formula (5) is expressed by the formula (6).

[0033]

[0034] In equation (5), the polar decoding unit 5 subtracts the correction term D from min(|α|, |β|), so it calculates the correction term D using equation (6) and then calculates αxorβ using equation (5). In equation (6), C represents a constant that is determined in advance before the decoding calculation. By using equation (5), the polar decoding unit 5 can dynamically calculate the correction term D based on the values ​​of α and β, and therefore can adjust the correction term D independently of the code configuration.

[0035] 6 is a diagram showing an example of the configuration of a decoding circuit used by the polar decoding unit 5 included in the receiving device 20 according to the first embodiment when calculating equation (5). The decoding circuit includes absolute value extraction units 51 and 52, sign extraction units 54 and 55, an exclusive-OR operation unit 56, a subtraction unit 57, and maximum value comparison units 58 and 59. The subtraction unit 57 calculates δ using a constant C, the absolute value |α| of α, and the absolute value |β| of β. The maximum value comparison unit 58 selects the larger of δ and 0, and outputs this as the correction term D. The maximum value comparison unit 59 selects and outputs the larger of either 0 or the value obtained by subtracting the correction term D from the smaller of the absolute value |α| of α and the absolute value |β| of β. The exclusive-OR operation unit 56 performs an exclusive-OR operation using the outputs from the sign extraction unit 54, the sign extraction unit 55, and the maximum value comparison unit 59 to obtain an output.

[0036] 6, equation (5) can be implemented by extracting the absolute value of the log-likelihood ratio, extracting the sign of the log-likelihood ratio, subtraction, maximum value comparison, minimum value comparison, XOR operation, and shift operation. In subtraction unit 57, the calculation of C-||α|-|β|| / 2 includes division, but because division by 2 is the same as shifting one bit to the right in binary, it becomes a shift operation. Polar decoding unit 5 performs the aforementioned specified operations: extracting the absolute value of the log-likelihood ratio, extracting the sign of the log-likelihood ratio, subtraction, maximum value comparison, minimum value comparison, exclusive OR operation, and shift operation.

[0037] In this way, in this embodiment, tanh, tanh －１ A simple circuit can be implemented without implementing the above in hardware, and the dynamic calculation of the correction term D can be implemented in hardware with a realistic circuit scale.

[0038] Next, the hardware configuration of the receiving device 20 will be described. In the receiving device 20, the likelihood generation unit 4 and the polar decoding unit 5 are realized by a processing circuit. The processing circuit may be a processor and memory that executes a program stored in a memory, or may be dedicated hardware. The processing circuit is also called a control circuit.

[0039] FIG. 7 is a diagram illustrating an example of the configuration of a processing circuit 90 that implements the receiving device 20 according to the first embodiment, when the processing circuit is configured with a processor 91 and a memory 92. The processing circuit 90 illustrated in FIG. 7 is a control circuit and includes a processor 91 and a memory 92. When the processing circuit 90 is configured with the processor 91 and the memory 92, each function of the processing circuit 90 is implemented by software, firmware, or a combination of software and firmware. The software or firmware is written as a program and stored in the memory 92. The processing circuit 90 implements each function by having the processor 91 read and execute the program stored in the memory 92. That is, the processing circuit 90 includes the memory 92 for storing a program that results in the processing of the receiving device 20 being executed. This program can also be said to be a program that causes the receiving device 20 to execute each function implemented by the processing circuit 90. This program may be provided by a storage medium on which the program is stored, or by other means such as a communication medium.

[0040] The above program can also be said to be a program that causes the receiving device 20 to execute: a first step in which the likelihood generating unit 4 acquires, via the communication path 3, a transmission signal in which information bits have been polar-encoded by the transmitting device 10 and transmitted, and generates a number of log-likelihood ratios corresponding to the number of code bits generated when the information bits were polar-encoded by the transmitting device 10; and a second step in which the polar decoding unit 5 performs a specified calculation on the absolute value of the log-likelihood ratio to perform decoding processing for the polar encoding, and makes corrections to improve decoding performance according to the absolute value of the log-likelihood ratio to generate estimated bits that estimate the information bits.

[0041] Here, the processor 91 is, for example, a CPU (Central Processing Unit), a processing device, an arithmetic unit, a microprocessor, a microcomputer, or a DSP (Digital Signal Processor), etc. The memory 92 is, for example, a non-volatile or volatile semiconductor memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable ROM), or an EEPROM (Electrically EPROM), a magnetic disk, a flexible disk, an optical disk, a compact disk, a minidisk, or a DVD (Digital Versatile Disc).

[0042] FIG. 8 is a diagram illustrating an example of a processing circuit 93 that implements the receiving device 20 according to the first embodiment when the processing circuit is configured with dedicated hardware. The processing circuit 93 illustrated in FIG. 8 corresponds to, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a combination thereof. The processing circuit may be partially implemented with dedicated hardware and partially implemented with software or firmware. In this way, the processing circuit can implement each of the above-described functions by dedicated hardware, software, firmware, or a combination thereof.

[0043] As described above, according to this embodiment, in the receiving device 20, the polar decoding unit 5 performs the polar code decoding calculation using tanh, tanh －１The calculation load can be reduced by realizing the above-mentioned calculations without using calculations such as the above, by extracting the absolute value of the log-likelihood ratio, extracting the sign of the log-likelihood ratio, subtracting, comparing the maximum value, comparing the minimum value, performing an XOR operation, and shifting. Furthermore, compared to "scaled min-sum," the polar decoding unit 5 can perform dynamic correction according to the input value, thereby enabling correction that is independent of the code configuration. In this way, the receiving device 20 can suppress the calculation load in decoding polar codes while suppressing degradation of decoding performance.

[0044] Embodiment 2 In embodiment 2, a case will be described in which a decoding method different from the decoding method of embodiment 1 is used. Note that in embodiment 2, the configuration of the communication system 30 is the same as the configuration of the communication system 30 in embodiment 1 shown in FIG.

[0045] 9 is a flowchart showing the operation of the polar decoding unit 5 included in the receiving device 20 according to the second embodiment. In the flowchart shown in FIG. 9, the operations of steps S11 and S13 are the same as those of steps S11 and S13 in the flowchart of the first embodiment shown in FIG. 2. In the second embodiment, after step S11, the polar decoding unit 5 performs a decoding calculation to estimate output bits one bit at a time (step S22), and finally outputs the result as a decoding result (step S13). At this time, in the decoding calculation of step S22, the polar decoding unit 5 performs a decoding calculation of the next bit using a previously estimated bit. This type of decoding process is called "successive cancellation (SC) decoding."

[0046] 10 is a diagram showing an example of the configuration of a decoding circuit used for the decoding calculation shown in FIG. 9 to estimate one bit at a time in the polar decoding unit 5 included in the receiving device 20 according to the second embodiment. In the example of FIG. 10, the number n of log-likelihood ratios input to the polar decoding unit 5 is set to 8, and the number k of estimated bits to be estimated is set to 4. In this embodiment, the polar decoding unit 5 converts the input from the right side of the decoding circuit shown in FIG. 10 into log-likelihood ratios l ｉ and the intermediate value of the estimated bits u ｉ The polar decoding unit 5 estimates the intermediate value uｉ For the estimation of ０ to the intermediate value u ７ In the example of FIG. 10, the log-likelihood ratio l ｉ are arranged in ascending order of index from top to bottom, but the intermediate value u ｉ are arranged in the order in which the indexes are bit-reversed, and the intermediate value u ０ , u １ , ..., u ７ are estimated in the order of

[0047] 11 is a diagram showing the flow of decoding calculations in the decoding circuit shown in FIG. 10 used in the polar decoding unit 5 included in the receiving device 20 according to the second embodiment. The polar decoding unit 5 receives two log-likelihood ratios α and β as inputs and calculates f(α, β) and g(α, β) in equation (1). Here, the calculation of g(α, β) cannot be performed unless the value of b∈{0, 1} is determined, but this is because the intermediate value u ｉ Since the value is determined from the estimation result of , it is not estimated from the top down as shown in FIG. 10, but is estimated in bit reverse order.

[0048] The polar decoding unit 5 calculates f(α, β) in the decoding calculation shown in Figure 11 as in embodiment 1, so by replacing f(α, β) with αxorβ expressed by equation (5), it is possible to perform dynamic calculation of the correction term D even in SC decoding.

[0049] As described above, according to this embodiment, in the receiving device 20, the polar decoding unit 5 calculates the intermediate value u ｉ and performs decoding and correction. At this time, the polar decoding unit 5 estimates the estimated bit one bit at a time, and estimates the next estimated bit using the obtained estimated bit estimation result. In this way, the receiving device 20 can suppress the degradation of decoding performance while suppressing the calculation load in decoding polar codes, as in the first embodiment.

[0050] The configurations shown in the above embodiments are merely examples, and may be combined with other known technologies, or different embodiments may be combined with each other. It is also possible to omit or modify parts of the configurations as long as they do not deviate from the gist of the invention.

[0051] REFERENCE SIGNS LIST 1 Polar encoding unit, 2 Modulation unit, 3 Communication channel, 4 Likelihood generation unit, 5 Polar decoding unit, 10 Transmitting device, 20 Receiving device, 30 Communication system, 51, 52 Absolute value extraction unit, 53 Minimum value comparison unit, 54, 55 Code extraction unit, 56 Exclusive OR operation unit, 57 Subtraction unit, 58, 59 Maximum value comparison unit, 90, 93 Processing circuit, 91 Processor, 92 Memory.

Claims

1. A receiving device for decoding a polar-encoded signal, A likelihood generation unit that acquires the transmission signal transmitted by the transmitting device after the information bits have been polar encoded, via the communication channel, and generates a log-likelihood ratio corresponding to the number of code bits generated when the transmitting device performed the polar encoding, A Polar decoding unit performs a decoding process for the Polar encoding by performing operations defined on the absolute value of the log-likelihood ratio, such as extracting the absolute value of the log-likelihood ratio, extracting the sign of the log-likelihood ratio, calculating a correction term according to the log-likelihood ratio, subtraction, maximum value comparison, minimum value comparison, exclusive OR operation, and shift operation, and also performs a correction to improve decoding performance according to the absolute value of the log-likelihood ratio to generate estimated bits that estimate the information bits. A receiving device characterized by being equipped with the following features.

2. The Polar decoding unit performs the decoding process and correction by repeating the defined calculation one or more times. The receiving device according to feature 1.

3. The Polar decoding unit estimates the intermediate value of the estimated bit by the defined calculation and performs the decoding process and the correction. The receiving device according to feature 1.

4. The Polar decoding unit estimates one estimated bit at a time, and uses the estimation result of the obtained estimated bit to estimate the next estimated bit. The receiving device according to claim 1 or 3.

5. A control circuit for controlling a receiving device that decodes a polar-encoded signal, The transmitting device acquires the transmitted signal, in which the information bits have been polar-encoded and transmitted, via the communication channel, and generates a log-likelihood ratio corresponding to the number of code bits generated when the transmitting device performed the polar encoding. As operations defined for the absolute value of the log-likelihood ratio, the decoding process for the Polar encoding is performed by extracting the absolute value of the log-likelihood ratio, extracting the sign of the log-likelihood ratio, calculating a correction term according to the log-likelihood ratio, subtraction, maximum value comparison, minimum value comparison, exclusive OR operation, and shift operation, and a correction is applied according to the absolute value of the log-likelihood ratio to improve the decoding performance and generate estimated bits that estimate the information bits. A control circuit characterized by causing the receiving device to perform the above.

6. A storage medium storing a program for controlling a receiving device that decodes a Polar-encoded signal, The aforementioned program, The transmitting device acquires the transmitted signal, in which the information bits have been polar-encoded and transmitted, via the communication channel, and generates a log-likelihood ratio corresponding to the number of code bits generated when the transmitting device performed the polar encoding. As operations defined for the absolute value of the log-likelihood ratio, the decoding process for the Polar encoding is performed by extracting the absolute value of the log-likelihood ratio, extracting the sign of the log-likelihood ratio, calculating a correction term according to the log-likelihood ratio, subtraction, maximum value comparison, minimum value comparison, exclusive OR operation, and shift operation, and a correction is applied according to the absolute value of the log-likelihood ratio to improve the decoding performance and generate estimated bits that estimate the information bits. A storage medium characterized by causing the receiving device to perform the above action.

7. A decoding method for a receiving device that decodes a polar-encoded signal, The likelihood generation unit performs a first step of acquiring a transmission signal transmitted by a transmitting device after the information bits have been polar encoded, via a communication channel, and generating a log-likelihood ratio corresponding to the number of code bits generated when the transmitting device performed the polar encoding. The Polar decoding unit performs a decoding process for the Polar encoding by performing operations defined on the absolute value of the log-likelihood ratio, including extracting the absolute value of the log-likelihood ratio, extracting the sign of the log-likelihood ratio, calculating a correction term according to the log-likelihood ratio, subtraction, maximum value comparison, minimum value comparison, exclusive OR operation, and shift operation, and also performs a correction to improve the decoding performance according to the absolute value of the log-likelihood ratio to generate estimated bits that estimate the information bits. A decryption method characterized by including the following.