Semiconductor device and electric power conversion device comprising same
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Filing Date
- 2026-03-06
- Publication Date
- 2026-06-16
Abstract
Description
Semiconductor device and power conversion device including the same
[0001] The present disclosure relates to a semiconductor device and a power conversion device including the same.
[0002] Power semiconductor devices (power modules) are required to have high breakdown voltage and high reliability. In a semiconductor device, for example, a power semiconductor element is mounted on an insulating substrate disposed on a base plate to which a case is attached, and the semiconductor element is sealed with a sealant filled in the case. The components, such as the case, base plate, insulating substrate, and sealant, have different linear expansion coefficients. Thus, a semiconductor device is formed by combining multiple components with different linear expansion coefficients.
[0003] The sealing material used to seal semiconductor elements and the like also comes into contact with insulating substrates and cases, which have different linear expansion coefficients. Therefore, the sealing material may peel off from the case due to differences in expansion and contraction of the various components caused by heat generation from the semiconductor element. Furthermore, cracks may occur in the case. To address these issues, Patent Document 1 proposes a semiconductor device in which the case is reinforced by providing beams. Patent Document 2 proposes a semiconductor device in which a coating film is interposed between the sealing material and the case to prevent the sealing material from coming into contact with the case.
[0004] JP 2012-209470 A JP 2017-28159 A
[0005] As described above, semiconductor devices are required to suppress peeling or cracking caused by differences in the linear expansion coefficients of the members that come into contact with the sealing material.
[0006] The present disclosure has been made based on such development, and one object is to provide a semiconductor device that can suppress peeling or cracking caused by differences in the linear expansion coefficients of each component, and another object is to provide a power conversion device equipped with such a semiconductor device.
[0007] The semiconductor device according to the present disclosure includes a base plate, an insulating substrate, a semiconductor element, a case, and an encapsulant. The insulating substrate is disposed on the base plate. The semiconductor element is mounted on the insulating substrate. The case is attached to the base plate so as to surround the insulating substrate and the semiconductor element. The encapsulant is filled into the area surrounded by the case and encapsulates the semiconductor element. The encapsulant includes a single resin material and an inorganic material added to the resin material. The encapsulant has a first part and a second part. The first part is located from the base plate toward the encapsulant surface of the encapsulant so as to cover the semiconductor element. The second part is located from the encapsulant surface toward the base plate so as to cover the first part. The amount of inorganic material in the first part of the encapsulant is greater than the amount of inorganic material in the second part of the encapsulant.
[0008] The power conversion device according to the present disclosure has the above-described semiconductor device and includes a main conversion circuit that converts and outputs input power, and a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit.
[0009] According to the semiconductor device disclosed herein, the encapsulant that is filled in the case and encapsulates the semiconductor element and the like is made of a single organic material to which an inorganic material is added. The encapsulant has a first portion that covers the semiconductor element and the like and a second portion that covers the first portion. The amount of inorganic material in the first portion is greater than the amount of inorganic material in the second portion. This allows the difference in linear expansion coefficient between the encapsulant and the insulating substrate on which the semiconductor element is mounted to be reduced in the first portion. The difference in linear expansion coefficient between the encapsulant and the case to be reduced in the second portion. As a result, peeling or cracking due to the difference in linear expansion coefficients can be suppressed.
[0010] In the power conversion device according to the present disclosure, by including the above-described semiconductor device, peeling or cracking caused by differences in the linear expansion coefficients is suppressed, thereby contributing to improving the reliability of the power conversion device.
[0011] FIG. 1 is a cross-sectional view showing a cross-sectional structure of a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view showing a schematic distribution of an inorganic material in a sealing material injected into a case in the same embodiment. FIG. 3 is a diagram for explaining the amount of inorganic material in a sealing material in the same embodiment. FIG. 4 is a cross-sectional view showing a cross-sectional structure of a semiconductor device according to a modified example in the same embodiment. FIG. 5 is a cross-sectional view showing a cross-sectional structure of a semiconductor device according to a second embodiment. FIG. 6 is a cross-sectional view showing a schematic distribution of an inorganic material in a sealing material injected into a case in the same embodiment. FIG. 7 is a block diagram of a power conversion device according to a third embodiment.
[0012] First Embodiment An example of a semiconductor device according to a first embodiment will be described. As shown in Fig. 1, the semiconductor device 1 mainly includes a base plate 3, an insulating substrate 15, a semiconductor element 21, a case 5, and a sealing material 25. The insulating substrate 15 includes a first insulating substrate 15a and a second insulating substrate 15b. The semiconductor element 21 includes a first semiconductor element 21a and a second semiconductor element 21b.
[0013] Examples of materials that can be used for the case 5 include polyphenylene sulfide (PPS), polybutylene terephthalate (PBT), polyethylene terephthalate (PET), a mixture of polybutylene terephthalate and polyethylene terephthalate, nylon, phenolic resin, and epoxy resin. The case 5 has a protrusion 7 that protrudes from the inner wall toward the side where the semiconductor element 21 is located. The case 5 is attached to the base plate 3 with an adhesive 9.
[0014] For example, a ceramic substrate or an aluminum nitride substrate is used as the insulating substrate 15. The insulating substrate 15 is disposed on the base plate 3. The semiconductor element 21 is mounted on the insulating substrate 15. A sealing material 25 is filled inside the case 5. The sealing material 25 seals the semiconductor element 21 and the like.
[0015] The structure of the semiconductor device 1 will be described in more detail. An element circuit board 17 is disposed on one main surface of the insulating substrate 15. The element circuit board 17 includes a first element circuit board 17a and a second element circuit board 17b. A conductor plate 13 is disposed on the other main surface of the insulating substrate 15. The conductor plate 13 includes a first conductor plate 13a and a second conductor plate 13b. The conductor plate 13 (first conductor plate 13a, second conductor plate 13b) is joined to the base plate 3 with solder 11.
[0016] The semiconductor element 21 is joined to the element circuit board 17 by solder 19. The first semiconductor element 21a is joined to the first element circuit board 17a. The second semiconductor element 21b is joined to the second element circuit board 17b. The semiconductor element 21 is electrically connected to wiring members 23. The wiring members 23 include a first wiring member 23a, a second wiring member 23b, and a third wiring member 23c.
[0017] The first semiconductor element 21a is electrically connected to an electrode terminal (not shown) attached to the case 5 by a first wiring member 23a. The second semiconductor element 21b is electrically connected to an electrode terminal (not shown) attached to the case 5 by a second wiring member 23b. The first semiconductor element 21a and the second semiconductor element 21b are electrically connected by a third wiring member 23c. The insulating substrate 15, the semiconductor element 21, the wiring member 23, etc. are sealed with a sealing member 25.
[0018] Next, the sealing material 25 will be described in more detail. The sealing material 25 is composed of a single resin material 27 and an inorganic material 29 as a filler. The sealing material 25 is filled into the case 5 in such a manner that the amount (wt %) of the inorganic material 29 gradually increases from the sealing material surface 25 a toward the base plate 3.
[0019] As the single resin material 27, for example, an epoxy resin is used. In addition to the epoxy resin, for example, any of polyimide, polyamide, acrylic resin, and silicone resin may be used. As the inorganic material 29, for example, silica is used. The shape of the silica as the inorganic material 29 is approximately spherical. The size of the inorganic material 29 is 0.1 μm to 100 μm. In addition to silica, for example, alumina, aluminum nitride, silicon nitride, boron nitride, boron oxide, or the like may be used.
[0020] 2 shows the cross-sectional structure of the semiconductor device 1, in which the distribution of the inorganic material 29 in the encapsulant 25 is schematically shown by the density of dots. As shown in FIG. 2, the encapsulant 25 includes a lower layer 31 as a first portion and an upper layer 33 as a second portion. The lower layer 31 is located from the base plate 3 toward the encapsulant surface 25a of the encapsulant 25 so as to cover the semiconductor element 21. The lower layer 31 includes a first region 31a having a thickness L1 of 3 mm from the base plate 3.
[0021] The upper layer 33 is located from the sealant surface 25a toward the base plate 3 so as to cover the lower layer 31. The upper layer 33 includes a second region 33a having a thickness L2 of 3 mm from the sealant surface 25a. The amount of inorganic material 29 in the lower layer 31 is greater than the amount of inorganic material 29 in the upper layer 33. The thickness L of the sealant 25 is approximately 6 mm to 20 mm.
[0022] 2, for convenience of explanation, the lower layer 31, the first region 3a, the upper layer 33, and the second region 33a are shown by dividing the sealing material 25 with dotted lines, but there are no boundaries corresponding to the dotted lines in the sealing material 25. The sealing material 25 is formed as a single layer of sealing material 25 from the surface of the base plate 3 to the sealing material surface 25a.
[0023] As described above, the sealant 25 is formed in such a manner that the amount (wt %) of the inorganic material 29 gradually increases from the sealant surface 25a toward the base plate 3. The amount of the inorganic material 29 in the sealant 25 varies within a range of, for example, about 70 wt % to 90 wt %. Here, the depth from the sealant surface 25a is defined as position X. The amount of the inorganic material 29 at the sealant surface 25a is defined as B. The amount of the inorganic material 29 at position X from the sealant surface 25a is defined as Y.
[0024] 3, the amount Y of inorganic material 29 is approximately expressed as a linear function by Y = AX + B. The amount of inorganic material 29 at position X is the amount of inorganic material 29 contained within a thickness of 1 mm below position X. Note that, for example, in portions located near the surface of sealing material 25 and portions located near the surface of base plate 3, the amount of inorganic material may deviate from the amount estimated by this linear function.
[0025] In the actual sealing material 25, the amount of inorganic material varies (fluctuations) to some extent with respect to the amount estimated from the linear function. In particular, the amount (distribution) of inorganic material 29 may vary greatly between the top and bottom layers of the sealing material 25. In the top layer, the inorganic material 29 is not supplied from the upper layer, so the amount of inorganic material 29 tends to be small. On the other hand, in the bottom layer, the inorganic material 29 does not settle to the lower layer, so the amount of inorganic material 29 tends to be large.
[0026] In the semiconductor device 1 described above, the sealing material 25 is injected (filled) into the case 5 after the insulating substrate 15 and the semiconductor element 21 are mounted on the base plate 3 and the wiring material 23 is connected. At this time, in order to reduce the interface resistance between the inorganic material 29 as the filler and the epoxy resin (organic material) as the single resin material 27, a coupling treatment is performed in advance to coat the surface of the inorganic material 29.
[0027] The coupling treatment reduces the interfacial resistance between the inorganic material 29 and the resin material 27 (epoxy resin), which makes it easier for the inorganic material 29 to settle in the resin material 27 toward the base plate 3 before the injected sealant 25 hardens. This allows the amount of inorganic material 29 to gradually increase from the sealant surface 25 a toward the base plate 3.
[0028] Here, we will explain the difference between this method and semiconductor devices encapsulated by transfer molding, which is a method for encapsulating semiconductor elements and the like. In transfer molding, semiconductor elements and the like are encapsulated by injecting an encapsulant into a mold. In this case, the encapsulant hardens in an extremely short time (for example, from a dozen seconds). Therefore, it is believed that the inorganic material added to the encapsulant will be distributed almost uniformly throughout the encapsulant.
[0029] In contrast to the transfer molding method, in the method of sealing the semiconductor element 21 and the like by injecting the sealing material 25 into the case 3, it takes, for example, about 30 minutes to 1 hour for the sealing material 25 to harden. During this time, the inorganic material 29 in the sealing material 25 settles toward the base plate 3, and a gradient in the amount of the inorganic material 29 can be created.
[0030] In the semiconductor device 1 described above, the sealing material 25 is formed in such a manner that the amount (wt %) of the inorganic material 29 gradually increases from the sealing material surface 25a toward the base plate 3. This makes it possible to suppress peeling or cracking caused by differences in the linear expansion coefficients of the respective members. This will be explained below.
[0031] First, the linear expansion coefficient of insulating substrate 15 is approximately 3 to 7 ppm / K. The linear expansion coefficient of case 5 is approximately 10 to 30 ppm / K. The linear expansion coefficient of sealing material 25 varies depending on the amount of inorganic material 29 contained in resin material 27. When the amount of inorganic material 29 is small, the linear expansion coefficient is approximately 20 ppm / K. On the other hand, when the amount of inorganic material 29 is large, the linear expansion coefficient is approximately 8 ppm / K.
[0032] The sealing material 25 is formed such that the amount (wt %) of the inorganic material 29 gradually increases from the sealing material surface 25a toward the base plate 3. As a result, in the lower layer 31 of the sealing material 25, the difference between the linear expansion coefficient of the lower layer 31 (first linear expansion coefficient) and the linear expansion coefficient of the insulating substrate 15 that the lower layer 31 seals is small. On the other hand, in the upper layer 33 of the sealing material 25, the difference between the linear expansion coefficient of the upper layer 33 (second linear expansion coefficient) and the linear expansion coefficient of the case 5 with which the upper layer 33 comes into contact is small. As a result, peeling of the sealing material 25 from the case 5 can be suppressed. Furthermore, the occurrence of cracks in the case 5 can be suppressed. Suppressing peeling and cracks can contribute to improving the reliability of the semiconductor device.
[0033] From the viewpoint of suppressing peeling or cracking, it is desirable to adjust the amount of inorganic material 29 added to resin material 27 so that the difference between the amount of inorganic material 29 in first region 31 a of lower layer 31 and the amount of inorganic material 29 in second region 33 a of upper layer 33 is greater than 0 wt % and less than 15 wt %, as a material characteristic of sealing material 25. If the difference in the amount of inorganic material 29 exceeds 15 wt %, the linear expansion coefficient of sealing material 25 becomes much larger than that of other components, which may cause warping of semiconductor device 1 and cracks in sealing material 25 itself.
[0034] The reason why the thickness L1 of the first region 31a is set to 3 mm is as follows. First, the distance from the surface (top surface) of the base plate 3 to the surface (top surface) of the semiconductor element 21 is approximately 2 mm. Therefore, it is believed that the portion of the encapsulant 25, which has a thickness of approximately 3 mm (2 mm + 1 mm) from the base plate 3, affects the reliability of the semiconductor element 21 and its surroundings. Therefore, the thickness L1 of the first region 31a, which affects the reliability of the semiconductor element 21, etc., is set to 3 mm.
[0035] Furthermore, if the thickness L1 of the first region 31a and the thickness L2 of the second region 33a are set to be greater than 3 mm, the difference between the amount of inorganic material in the first region 31a and the amount of inorganic material in the second region 33a becomes small, making it difficult to clearly identify the effect of the sealing material 25 due to the distribution of the inorganic material 29.
[0036] On the other hand, if the thickness L2 of the second region 33a is set to be thinner than 3 mm, the amount of inorganic material 29 near the sealing material surface 25a will be extremely small, resulting in a layer consisting almost entirely of resin material 27, making it difficult to identify the effect of the sealing material 25 containing inorganic material 29.
[0037] In the semiconductor device 1 described above, the amount of inorganic material 29 is adjusted so that the difference between the amount of inorganic material 29 in the first region 31 a and the amount of inorganic material 29 in the second region 33 a is greater than 0 wt % and less than 15 wt %, which makes it possible to prevent the sealing material 25 from peeling off from the case 5 and also to prevent cracks from occurring in the case 5. By preventing peeling and cracks, the reliability of the semiconductor device 1 is improved.
[0038] One method for measuring the amount of inorganic material contained in the encapsulant of a semiconductor device is to heat the encapsulant, and the amount of inorganic material can be determined from the residual fraction when a resin material (encapsulant) to which the inorganic material has been added is heated, for example, at a temperature of 600° C. for about four hours. Another method for measuring the linear expansion coefficient of the encapsulant is to use a thermomechanical analyzer (TMA), and by measuring the expansion rate of the encapsulant while changing the temperature, the expansion coefficient per unit temperature (linear expansion coefficient) can be calculated.
[0039] (Modification) An example of a semiconductor device according to a modification will be described. As shown in Fig. 4, in the semiconductor device 1 according to the modification, a sloped portion 7a is formed on the protrusion 7 provided on the inner wall of the case 5. The sloped portion 7a slopes from the base plate 3 toward the sealing material surface 25a in a manner that gradually approaches the insulating substrate 15. Note that the rest of the configuration is the same as that of the semiconductor device 1 shown in Fig. 1, so the same components are designated by the same reference numerals, and their description will not be repeated unless necessary.
[0040] In the semiconductor device 1 according to the modified example, the inclined portion 7a is inclined from the base plate 3 toward the sealing material surface 25a so as to gradually approach the insulating substrate 15. In other words, the inclined portion 7a is inclined from the upper end of the protrusion 7 toward the base plate 3 so as to move away from the insulating substrate 15, etc. This further expands the space DC between the insulating substrate 15 and the case 5, into which the sealing material 25 is filled. This space DC is filled with the sealing material 25, which contains a larger amount of inorganic material 29 and has a relatively small linear expansion coefficient.
[0041] The space between the insulating substrate 15, which has a relatively small linear expansion coefficient, and the case 5, which has a relatively large linear expansion coefficient, is filled with the sealing material 25, which has a relatively small linear expansion coefficient. As a result, in the semiconductor device 1 according to the comparative example, it is possible to effectively prevent thermal distortion caused by temperature changes in the semiconductor device 1 from affecting the insulating substrate 15, which has a relatively small linear expansion coefficient, and the like.
[0042] Embodiment 2 An example of a semiconductor device according to embodiment 2 will be described. As shown in Figures 5 and 6, the sealing material 25 includes a lower layer 31 as a first portion, an upper layer 33 as a second portion, and an intermediate layer 35 as an intermediate portion.
[0043] 6, the distribution of the inorganic material 29 in the sealant 25 is shown schematically by the density of dots. For ease of explanation, the sealant 25 is divided by dotted lines to show the lower layer 31, the intermediate layer 35, the upper layer 33, etc., but the sealant 25 does not have boundaries corresponding to the dotted lines. The sealant 25 is formed as a single layer of sealant 25 from the surface of the base plate 3 to the sealant surface 25a.
[0044] The sealing material 25 is composed of a single resin material 27 and an inorganic material 29 as a filler. The amount of inorganic material 29 in the lower layer 31 is greater than the amount of inorganic material 29 in the upper layer 33. The amount of inorganic material 29 in the intermediate layer 35 is less than the amount of inorganic material 29 in the lower layer 31 and greater than the amount of inorganic material 29 in the upper layer 33.
[0045] The amount of inorganic material 29 in sealing material 25 varies within a range of, for example, 70% to 90% by weight. The difference between the amount of inorganic material 29 in first region 31a of lower layer 31 and the amount of inorganic material 29 in second region 33a of upper layer 33 is greater than 0% by weight and less than 15% by weight.
[0046] The linear expansion coefficient (third linear expansion coefficient) of the intermediate layer 35 is larger than the linear expansion coefficient (first linear expansion coefficient) of the lower layer 31 and smaller than the linear expansion coefficient (second linear expansion coefficient) of the upper layer 33. Note that the rest of the configuration is similar to that of the semiconductor device 1 shown in Fig. 1 etc., and therefore the same members are denoted by the same reference numerals, and description thereof will not be repeated unless necessary.
[0047] In the semiconductor device 1 described above, the sealing material 25 is injected (filled) into the case 5 after the insulating substrate 15 and the semiconductor element 21 are mounted on the base plate 3 and the wiring material 23 is connected. At this time, the sealing material 25 that will become the lower layer 31 is filled into the case 5 first. Next, before the sealing material 25 that will become the lower layer 31 hardens, the sealing material 25 that will become the upper layer 33 is filled into the case 3 so as to cover the sealing material 25 that will become the lower layer 31. A larger amount of inorganic material 29 is added to the sealing material 25 that will become the lower layer 31 than to the sealing material 25 that will become the upper layer 33.
[0048] By the time the entire sealing material 25 has hardened, a portion of the sealing material 25 that will become the lower layer 31 and a portion of the sealing material 25 that will become the upper layer 33 are mixed together to form an intermediate layer 35. In the intermediate layer 35, the amount of inorganic material 29 is greater than the amount of inorganic material 29 contained in the sealing material 25 that will become the upper layer 33, but less than the amount of inorganic material 29 contained in the sealing material 25 that will become the lower layer.
[0049] As described above, by subjecting the surface of the inorganic material 29 to a coupling treatment, the interfacial resistance between the resin material 27 (epoxy resin) and the inorganic material 29 is reduced. As a result, by the time the entire sealing material 25 is cured, the inorganic material 29 settles toward the base plate 3, and the amount of inorganic material 29 is distributed so that it is greater on the side closer to the base plate 3 in each of the sealing material 25 that becomes the lower layer 31 and the sealing material 25 that becomes the upper layer 33. Furthermore, in the intermediate layer 35, the amount of inorganic material 29 increases from the upper layer 33 toward the lower layer 31.
[0050] In the semiconductor device 1 described above, in the same manner as described above, in the lower layer 31 of the sealing material 25, the difference between the linear expansion coefficient of the lower layer 31 and the linear expansion coefficient of the insulating substrate 15 that the lower layer 31 seals is small. On the other hand, in the upper layer 33 of the sealing material 25, the difference between the linear expansion coefficient of the upper layer 33 and the linear expansion coefficient of the case 5 with which the upper layer 33 comes into contact is small. As a result, it is possible to prevent the sealing material 25 from peeling off from the case 5. It is also possible to prevent cracks from occurring in the case 5. By preventing peeling and cracks, the reliability of the semiconductor device 1 is improved.
[0051] Furthermore, the above-described semiconductor device 1 has the following effect: In the encapsulant 25, the intermediate layer 35 is located between the upper layer 33, which has a relatively large linear expansion coefficient, and the lower layer 31, which has a relatively small linear expansion coefficient, thereby reducing stress caused by the difference in linear expansion coefficient between the upper layer 33 and the lower layer 31.
[0052] Third Embodiment In a third embodiment, an example of a power conversion device including the semiconductor device described in each embodiment will be described.
[0053] Here, a power conversion device will be described that applies the semiconductor device 1 described in the above-described first or second embodiment. Although the present disclosure is not limited to a specific power conversion device, a case in which the present disclosure is applied to a three-phase inverter will be described below as a fourth embodiment.
[0054] Fig. 7 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied. The power conversion system shown in Fig. 7 is composed of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be composed of various elements, such as a DC system, a solar cell, or a storage battery. It may also be composed of a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 100 may also be composed of a DC / DC converter that converts DC power output from the DC system into a predetermined power.
[0055] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, and converts DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. As shown in Fig. 7 , the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.
[0056] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.
[0057] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheel diodes (not shown). When the switching elements are switched, DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300. There are various specific circuit configurations for the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full-bridge circuit that can be configured with six switching elements and six freewheel diodes connected in anti-parallel to each switching element.
[0058] At least one of the switching elements and freewheel diodes of the main conversion circuit 201 is a switching element or a freewheel diode included in a semiconductor device 202 corresponding to the semiconductor device 1 according to at least one of the first and second embodiments described above. The six switching elements form upper and lower arms in which two switching elements are connected in series, and each upper and lower arm forms one phase (U phase, V phase, W phase) of a full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to a load 300.
[0059] The main conversion circuit 201 also includes a drive circuit (not shown) that drives each switching element. The drive circuit may be built into the semiconductor device 202, or may be provided separately from the semiconductor device 202. The drive circuit generates drive signals that drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. To maintain a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or greater than the threshold voltage of the switching element, and to maintain a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or less than the threshold voltage of the switching element.
[0060] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 203 then outputs a control command (control signal) to a drive circuit included in the main conversion circuit 201 so that an on signal is output to a switching element that should be in the on state at each time point, and an off signal is output to a switching element that should be in the off state at each time point. In accordance with this control signal, the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.
[0061] In the power conversion device of this embodiment, the semiconductor device 1 of embodiment 1 or embodiment 2 is applied as the semiconductor device 202 that constitutes the main conversion circuit 201, thereby improving reliability and achieving a longer lifespan.
[0062] In the present embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used. In addition, when supplying power to a single-phase load, the present disclosure may also be applied to a single-phase inverter. Furthermore, when supplying power to a DC load, etc., the present disclosure may also be applied to a DC / DC converter or an AC / DC converter.
[0063] Furthermore, the power conversion device to which the present disclosure is applied is not limited to cases in which the above-mentioned load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.
[0064] The semiconductor devices described in the respective embodiments can be combined in various ways as required.
[0065] The embodiments disclosed herein are examples and are not intended to be limiting. The scope of the present disclosure is defined by the scope of the claims, not the scope described above, and is intended to include all modifications within the meaning and scope equivalent to the scope of the claims.
[0066] The present disclosure includes the following aspects: [Supplementary Note 1] A semiconductor device comprising: a base plate; an insulating substrate disposed on the base plate; a semiconductor element mounted on the insulating substrate; a case attached to the base plate so as to surround the insulating substrate and the semiconductor element; and a sealing material filled in an area surrounded by the case and sealing the semiconductor element, the sealing material including a single resin material and an inorganic material added to the resin material, the sealing material having: a first portion located from the base plate toward a surface of the sealing material so as to cover the semiconductor element; and a second portion located from the surface of the sealing material toward the base plate so as to cover the first portion,
[0067] [Supplementary Note 2] The semiconductor device according to Supplementary Note 1, wherein the sealing material is formed in such a manner that the amount of the inorganic material gradually increases from the sealing material surface toward the base plate.
[0068] [Supplementary Note 3] The semiconductor device according to Supplementary Note 2, wherein the first portion includes a first region having a thickness of 3 mm from the base plate toward the surface of the sealing material, the second portion includes a second region having a thickness of 3 mm from the surface of the sealing material toward the base plate, and a difference between the amount of the inorganic material contained in the first region and the amount of the inorganic material contained in the second region is greater than 0 wt % and less than 15 wt %.
[0069] [Appendix 4] The semiconductor device according to Appendix 1, wherein the sealing material includes an intermediate portion located between the first portion and the second portion, and the amount of the inorganic material in the intermediate portion is less than the amount of the inorganic material in the first portion and greater than the amount of the inorganic material in the second portion.
[0070] [Appendix 5] The semiconductor device according to Appendix 4, wherein in the first portion, the amount of the inorganic material increases from the side where the second portion is located toward the base plate; in the second portion, the amount of the inorganic material increases from the surface of the sealing material toward the side where the first portion is located; and in the intermediate portion, the amount of the inorganic material increases from the side where the second portion is located toward the side where the first portion is located.
[0071] [Appendix 6] The semiconductor device according to Appendix 4, wherein the first portion includes a first region having a thickness of 3 mm from the base plate toward the surface of the sealing material, the second portion includes a second region having a thickness of 3 mm from the surface of the sealing material toward the base plate, and a difference between the amount of the inorganic material contained in the first region and the amount of the inorganic material contained in the second region is greater than 0 wt % and less than 15 wt %.
[0072] [Supplementary Note 7] The semiconductor device according to Supplementary Note 1, wherein the first portion includes a first region having a thickness of 3 mm from the base plate toward the surface of the sealing material, the second portion includes a second region having a thickness of 3 mm from the surface of the sealing material toward the base plate, the first region having a first linear expansion coefficient, the second region having a second linear expansion coefficient, the insulating substrate having a third linear expansion coefficient, the first linear expansion coefficient being greater than the third linear expansion coefficient, and the second linear expansion coefficient being greater than the first linear expansion coefficient.
[0073] [Appendix 8] The semiconductor device according to any one of Appendices 1 to 7, wherein the case has a protruding portion formed thereon that protrudes from the base plate side toward the surface of the sealing material while being inclined in a manner that gradually approaches the insulating substrate.
[0074] [Supplementary Note 9] The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein the single resin material is any one selected from the group consisting of epoxy resin, polyimide, polyamide, acrylic resin, and silicone resin.
[0075] [Supplementary Note 10] The semiconductor device according to any one of Supplementary Notes 1 to 9, wherein the inorganic material includes at least one selected from the group consisting of silica, alumina, aluminum nitride, silicon nitride, boron nitride, and boron oxide.
[0076] [Supplementary Note 11] A power conversion device including: a main conversion circuit having the semiconductor device according to any one of Supplementary Notes 1 to 10, which converts input power and outputs the converted power; and a control circuit which outputs a control signal for controlling the main conversion circuit to the main conversion circuit.
[0077] The present disclosure is effectively used in a semiconductor device in which a semiconductor element or the like mounted in a case is sealed with a sealing material.
[0078] 1 semiconductor device, 3 base plate, 5 case, 7 protrusion, 7a inclined portion, 9 adhesive, 11 solder, 13 conductor plate, 13a first conductor plate, 13b second conductor plate, 15 insulating substrate, 15a first insulating substrate, 15b second insulating substrate, 17 element circuit board, 17a first element circuit board, 17b second element circuit board, 19 solder, 21 semiconductor element, 21a first semiconductor element, 21b second semiconductor element, 23 wiring material, 23a first wiring material, 23b second wiring material, 23c third wiring material, 25 sealing material, 25a sealing material surface, 27 resin material, 29 inorganic material, 31 lower layer, 31a first region, 33 upper layer, 33a second region, 35 intermediate layer, L1, L2, L thickness, 100 power supply, 200 Power conversion device, 300 load, 201 main conversion circuit, 202 semiconductor device, 203 control circuit.
Claims
1. Base plate and An insulating substrate placed on the base plate, A semiconductor element mounted on the aforementioned insulating substrate, A case mounted on the base plate so as to surround the insulating substrate and the semiconductor element, A sealing material is provided to fill the region enclosed by the aforementioned case and to encapsulate the semiconductor element. Equipped with, The aforementioned sealing material is A single resin material, An inorganic material added to the aforementioned resin material and subjected to coupling treatment and Includes, The aforementioned sealing material is A first portion is positioned from the base plate toward the surface of the sealing material of the sealing material so as to cover the semiconductor element, A second part is positioned from the surface of the sealing material toward the base plate so as to cover the first part, It has, A semiconductor device wherein the amount of the inorganic material in the first part of the sealing material is greater than the amount of the inorganic material in the second part of the sealing material.
2. The semiconductor device according to claim 1, wherein the sealing material is formed in such a manner that the amount of the inorganic material gradually increases from the surface of the sealing material toward the base plate.
3. The first part includes a first region having a thickness of 3 mm from the base plate toward the surface of the sealing material, The second part includes a second region having a thickness of 3 mm from the surface of the sealing material toward the base plate, The semiconductor device according to claim 2, wherein the difference between the amount of inorganic material contained in the first region and the amount of inorganic material contained in the second region is greater than 0% by weight and less than 15% by weight.
4. The sealing material includes an intermediate portion located between the first and second parts. The semiconductor device according to claim 1, wherein the amount of the inorganic material in the intermediate portion is less than the amount of the inorganic material in the first portion and greater than the amount of the inorganic material in the second portion.
5. In the first part, the amount of the inorganic material increases from the side where the second part is located toward the base plate. In the second part, the amount of the inorganic material increases from the surface of the sealing material toward the side where the first part is located. The semiconductor device according to claim 4, wherein in the intermediate portion, the amount of the inorganic material increases from the side where the second portion is located to the side where the first portion is located.
6. The first part includes a first region having a thickness of 3 mm from the base plate toward the surface of the sealing material, The second part includes a second region having a thickness of 3 mm from the surface of the sealing material toward the base plate, The semiconductor device according to claim 4, wherein the difference between the amount of inorganic material contained in the first region and the amount of inorganic material contained in the second region is greater than 0% by weight and less than 15% by weight.
7. The first part includes a first region having a thickness of 3 mm from the base plate toward the surface of the sealing material, The second part includes a second region having a thickness of 3 mm from the surface of the sealing material toward the base plate, The first region has a first coefficient of thermal expansion, The second region has a second coefficient of thermal expansion, The insulating substrate has a third coefficient of thermal expansion, The first coefficient of thermal expansion is greater than the third coefficient of thermal expansion. The semiconductor device according to claim 1, wherein the second coefficient of thermal expansion is greater than the first coefficient of thermal expansion.
8. The semiconductor device according to claim 1, wherein the case has a protruding portion formed thereon that is inclined and protrudes from the base plate side toward the surface of the sealing material, gradually approaching the insulating substrate.
9. The semiconductor device according to claim 1, wherein the single resin material is selected from the group consisting of epoxy resin, polyimide, polyamide, acrylic resin, and silicone resin.
10. The semiconductor device according to claim 1, wherein the inorganic material comprises at least one selected from the group consisting of silica, alumina, aluminum nitride, silicon nitride, boron nitride, and boron oxide.
11. A semiconductor device according to any one of claims 1 to 10, comprising a main conversion circuit that converts and outputs input power, A control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit. A power conversion device equipped with this device.