Semiconductor equipment
JPWO2026018577A5Active Publication Date: 2026-06-23SHINDENGEN ELECTRIC MANUFACTURING CO LTD
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- SHINDENGEN ELECTRIC MANUFACTURING CO LTD
- Filing Date
- 2025-05-30
- Publication Date
- 2026-06-23
Smart Images

Figure 00000008_0000 
Figure 00000008_0001 
Figure 00000008_0002
Abstract
A semiconductor device 1 comprises multiple semiconductor chips, multiple inner leads, multiple connectors, and a sealing resin 70. The multiple inner leads include a first common inner lead 20 having a portion extending along a first direction D1 or being arranged along the first direction D1, multiple individual inner leads 31, 32, 33, and a second common inner lead 40. The multiple connectors include first connectors 51, 52, 53 connecting semiconductor chips (diodes 11, 12, 13) mounted on the first common inner lead 20 to the individual inner leads 31, 32, 33, and second connectors 61, 62, 63 connecting semiconductor chips (diodes 14, 15, 16) mounted on the individual inner leads 31, 32, 33 to the second common inner lead 40. Therefore, the semiconductor device 1 of the present invention is a semiconductor device that can suppress the tilting of the inner leads in the sealing resin compared to conventional semiconductor devices.
Need to check novelty before this filing date? Find Prior Art