Method of manufacturing semiconductor device and system for manufacturing semiconductor device

Abstract

This method for manufacturing a semiconductor device includes: performing bevel filling with respect to an unbonded region of a polymeric substrate obtained by bonding a first bonding layer of a first substrate having a laser absorption layer and the first bonding layer to a second bonding layer of a second substrate having the second bonding layer, a filler being filled to a second outer peripheral position determined in advance and corresponding to a first outer peripheral position of the first bonding layer; irradiating the laser absorption layer with a laser; and separating the first substrate from the second substrate in the polymeric substrate.

Description

Semiconductor device manufacturing method and semiconductor device manufacturing system

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a system for manufacturing a semiconductor device.

[0002] Patent Document 1 discloses a method for manufacturing a NAND flash memory including a three-dimensional memory cell array in which a plurality of memory cells are arranged three-dimensionally and a CMOS circuit that controls the memory cell array. The manufacturing method includes bonding a first substrate and a second substrate, each substrate having a semiconductor element including a CMOS and a memory cell array, via a separable layer, and separating the first substrate at the separable layer.

[0003] Patent Document 2 discloses a manufacturing method for forming a semiconductor device by bonding a semiconductor substrate having memory cells to a semiconductor substrate having a CMOS, in which an insulating film is filled in an unbonded area on the periphery of the bonded substrates, and then back-grinding is performed.

[0004] Japanese Patent Publication No. 2021-44408 Japanese Patent Publication No. 2021-48303

[0005] The technology according to the present disclosure appropriately separates the first substrate and the second substrate in a laminated substrate in which the first substrate and the second substrate are bonded together.

[0006] One aspect of the present disclosure is a method for manufacturing a semiconductor device, the method including: performing bevel filling of an unbonded region of an overlapping substrate, in which the first bonding layer and the second bonding layer are bonded together, with a filler up to a second outer periphery position that is predetermined to correspond to a first outer periphery position of the first bonding layer, in which a first substrate having a laser absorption layer and a first bonding layer and a second substrate having a second bonding layer are bonded together; irradiating the laser absorption layer with a laser; and separating the first substrate from the second substrate in the overlapping substrate.

[0007] According to the present disclosure, in a laminated substrate in which a first substrate and a second substrate are bonded together, the first substrate and the second substrate can be appropriately separated.

[0008] 1 is a flow diagram showing main steps of wafer processing; FIG. 2 is an explanatory diagram showing main steps of wafer processing; FIG. 3 is an explanatory diagram showing bonding of a first wafer and a second wafer; FIG. 4 is an explanatory diagram showing an example of bevel filling of an unbonded region; FIG. 5 is an explanatory diagram showing another example of bevel filling of an unbonded region; FIG. 6 is an explanatory diagram showing irradiating a laser absorption layer with laser light; FIG. 7 is an explanatory diagram showing separating the first wafer and the second wafer; FIG. 8 is an explanatory diagram showing main steps of preparing a first wafer according to an embodiment; FIG. 9 is a flow diagram showing main steps of preparing a first wafer according to an embodiment; FIG. 10 is an explanatory diagram showing some steps of preparing a first wafer according to an embodiment; FIG. 11 is an explanatory diagram showing some steps of preparing a first wafer according to an embodiment; FIG. 12 is a plan view showing an overview of the configuration of a wafer processing apparatus according to an embodiment; FIG. 13 is a plan view showing an overview of the configuration of an interface modification apparatus according to an embodiment; FIG. 14 is a side view showing an overview of the configuration of an interface modification apparatus according to an embodiment; FIG. 15 is an explanatory diagram showing an overview of bevel filling according to the first embodiment; FIG. 16 is an explanatory diagram showing an example of the operation of bevel filling according to the first embodiment; FIG. 10 is an explanatory diagram showing an example of the operation of bevel filling according to the first embodiment; FIG. 11 is an explanatory diagram showing an outline of bevel filling according to the second embodiment; FIG. 12 is an explanatory diagram showing an outline of formation of separation base points according to the second embodiment; FIG. 13 is an explanatory diagram showing an outline of formation of separation base points according to the second embodiment; FIG. 14 is an explanatory diagram showing an example of the operation of bevel filling and separation according to the second embodiment; FIG. 15 is an explanatory diagram showing an outline of formation of separation base points according to the third embodiment; and FIG. 16 is an explanatory diagram showing wafer processing according to a comparative example.

[0009] In the manufacturing process of semiconductor devices, a device layer formed on the surface of a first semiconductor substrate (hereinafter referred to as "wafer") is transferred to a second wafer in a bonded wafer. This transfer of the device layer from the first wafer to the second wafer is performed, for example, by irradiating a separation layer inside the first wafer with laser light to reduce the bonding strength between the first and second wafers, and then separating the first wafer from the second wafer. Furthermore, after separation, the first wafer is reused and bonded to the next second wafer.

[0010] An unbonded region B, where the beveled portions of the first wafer W and the second wafer S are not bonded to each other, may occur at the peripheral edge of the overlapped wafer T (see FIG. 2 ). The inventors have conducted extensive research and found that, during separation of the first wafer W, even if the bonding strength of the separation layer of the first wafer W is reduced, separation in other regions near the unbonded region B may take precedence over separation in the separation layer. For example, as shown in FIG. 25( a), when an upward force Fup is applied to the outer periphery We of the first wafer W, as shown in FIG. 25( b), a portion of the bevel of the first wafer W corresponding to the unbonded region B may be separated from the overlapped wafer T while remaining bonded to the first wafer W. As another example, as shown in FIG. 25( c), separation may progress from the outer periphery of the bonding surfaces of the first wafer W and the second wafer S to the surface of the second wafer S, such that the device region of the second wafer S (or the first wafer W) is torn.

[0011] The reason why such inappropriate separation occurs is not clear, but it is thought that the stress that should be concentrated in the separation layer is concentrated not only in the separation layer but also in the region near the outer circumferential edge of the bonding surfaces of the first wafer W and the second wafer S, and separation begins from that region.

[0012] 25(b), when a portion of the bevel is lost, the area in which devices can be formed on the first wafer W separated from the overlapped wafer T is limited, which may result in reduced productivity. Furthermore, in a process in which bonding and separation are repeated two or more times, such loss of the bevel may occur repeatedly, resulting in significant consumption of the area in which devices can be formed.

[0013] When separation progresses so that the device region of the second wafer S (or the first wafer W) is torn apart as in the example shown in FIG. 25(c), this may more directly result in a decrease in productivity.

[0014] The technology disclosed herein appropriately separates a first substrate and a second substrate in a laminated substrate in which the first substrate and the second substrate are bonded. Hereinafter, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to the drawings. Note that in this specification and the drawings, elements having substantially the same functional configuration are designated by the same reference numerals, and redundant description will be omitted.

[0015] In the method for manufacturing a semiconductor device according to this embodiment, first, a first wafer W is prepared as a first substrate (St1 in FIG. 1 ), and a second wafer S is prepared as a second substrate (St2 in FIG. 1 ). The preparation of the first wafer W and the preparation of the second wafer S may be performed in parallel. Hereinafter, as shown in FIGS. 2 and 3 , the surface of the first wafer W that is to be bonded to the second wafer S is referred to as the front surface Wa, and the surface opposite the front surface Wa is referred to as the back surface Wb. Similarly, the surface of the second wafer S that is to be bonded to the first wafer W is referred to as the front surface Sa, and the surface opposite the front surface Sa is referred to as the back surface Sb.

[0016] The first wafer W prepared in St1 is a semiconductor wafer such as a silicon substrate. In one embodiment, the first wafer W has a substantially circular disk shape. As shown in FIG. 3A , a laminated film is formed on the front surface Wa of the first wafer W. The laminated film includes, in order from the front surface Wa, a laser absorption layer P, an etching stop layer Q, a device layer Dw, and a surface film Fw. The laser absorption layer P, the etching stop layer Q, the device layer Dw, and the surface film Fw are each formed on the first wafer W by a process including, for example, chemical vapor deposition (CVD) in a film formation apparatus (not shown) or reactive ion etching (RIE) in an etching apparatus (not shown). Other desired films may be formed between the laser absorption layer P, the etching stop layer Q, the device layer Dw, and the surface film Fw as components of the laminated film. Details of the formation of the laminated film will be described later.

[0017] The device layer Dw according to this embodiment includes at least a portion of a memory cell array of a NAND flash memory. However, the technology according to the present disclosure is not limited thereto and can also be applied to the manufacture of other semiconductor devices by bonding substrates having other desired devices. In one embodiment, the device layer Dw includes at least a portion of a memory cell array of a DRAM. In another embodiment, the device layer Dw includes at least a portion of a peripheral circuit for controlling the memory cell array of a NAND flash memory or the memory cell array of a DRAM. Note that, in some cases, devices are not formed in the device layer Dw when it is prepared in St1, and devices are formed in a subsequent process. In other words, the device layer Dw may be a region where devices are to be formed, such as a region where devices are to be formed in a process after St1.

[0018] The surface film Fw may be, for example, an oxide film (THOX film, SiO ２ The surface film Fw of the first wafer W constitutes the first bonding layer of the present disclosure.

[0019] As will be described later, the laser absorption layer P absorbs laser light (e.g., CO ２ The laser absorption layer P is made of, for example, an oxide film (SiO ２ However, there is no particular limitation as long as it absorbs laser light.

[0020] The etching stop layer Q is configured to enable selective wet etching on the separation surface of the overlapped wafer T after separation of the first wafer W, which will be described later. Specifically, since the laser absorption layer P is the main separation surface during separation of the first wafer W, a portion of the laser absorption layer P and the etching stop layer Q remain on the side of the first device layer Dw after separation. In this state, selective etching of the laser absorption layer P and the etching stop layer Q first removes only the laser absorption layer P. Subsequently, selective etching of the etching stop layer Q and the first device layer Dw removes only the etching stop layer Q. This improves the total thickness variation (TTV) of the first device layer Dw after wet etching. The material of the etching stop layer Q is, for example, polycrystalline silicon (Poly-Si), but is not particularly limited as long as it ensures an etching selectivity between the etching stop layer Q and the first device layer Dw. Details of the method for forming the etching stop layer Q will be described later.

[0021] The second wafer S prepared in St2 is a semiconductor wafer such as a silicon substrate. In one embodiment, the second wafer S has a substantially circular disk shape. As shown in FIG. 3B, a laminated film Ms is formed on the surface Sa of the second wafer S. The laminated film Ms includes a device layer Ds and a surface film Fs, in this order from the surface Sa side. The device layer Ds and the surface film Fs are each formed on the second wafer S by a process including CVD in a film formation apparatus (not shown), for example.

[0022] The device layer Ds and the surface film Fs are the same as the device layer Dw and the surface film Fw of the first wafer W, respectively. The surface film Fs of the second wafer W constitutes the second bonding layer of the present disclosure. The device layer Ds according to this embodiment includes at least a portion of a peripheral circuit for controlling a memory cell array of a NAND flash memory. In one embodiment, when the device layer Dw of the first wafer W includes at least a portion of a memory cell array of a DRAM, the device layer Ds includes at least a portion of a peripheral circuit for controlling the memory cell array. In another embodiment, when the device layer Dw of the first wafer W includes at least a portion of a peripheral circuit for controlling the memory cell array, the device layer Ds includes at least a portion of the memory cell array of a NAND flash memory. In yet another embodiment, when the device layer Dw of the first wafer W includes at least a portion of a peripheral circuit for controlling the memory cell array, the device layer Ds includes at least a portion of the memory cell array of a DRAM.

[0023] After preparing the first wafer W and the second wafer S as described above, the first wafer W and the second wafer S are bonded together as shown in FIG. 3( c) to form a first overlapping wafer T1 as an overlapping substrate (St3 in FIGS. 1 and 2). In St3, the surface film Fw of the first wafer W and the surface film Fs of the second wafer S are bonded together. Any method for bonding the first wafer W and the second wafer S may be used. For example, the surface films Fw and Fs may be modified by plasma treatment in a surface modification device (not shown), and then the surface films Fw and Fs may be hydrophilized by supplying pure water to them in a surface hydrophilization device (not shown). After that, the surface films Fw and Fs may be bonded together in a bonding device (not shown) by van der Waals forces and hydrogen bonds (intermolecular forces).

[0024] Next, as shown in FIG. 4 or FIG. 5 , bevel filling is performed on the unbonded region B1 of the periphery of the first overlapped wafer T1 (Step 4 in FIGS. 1 and 2 ). The bevel filling includes injecting a liquid filler G into the bevel portion of the first overlapped wafer T1, including the unbonded region B1. In one embodiment, the process includes injecting the liquid filler G into the unbonded region B and then baking (firing) the filler G to solidify it. As an example, in a bevel filling device 70 (described later), the first overlapped wafer T1 is rotated while injecting the liquid filler G from an injector 9. This causes the filler G to be filled in the unbonded region B1 around the entire periphery of the first overlapped wafer T1. The filler G may be filled only in the unbonded region B1, as shown in FIG. 4 . Alternatively, the filler G may be filled in the entire bevel portion, including the unbonded region B1, as shown in FIG. 5 . The first overlapped wafer T1 filled with the filler material G is sent to, for example, a baking apparatus 80 (described later) to bake the filler material G. In one embodiment, the first overlapped wafer T1 is then sent to a cleaning apparatus 90 (described later) to clean and remove excess filler material G adhering to unnecessary locations.

[0025] Next, as shown in Fig. 6, the laser absorbing layer P is irradiated with laser light L (St5 in Figs. 1 and 2). In St5, for example, in a laser processing device 50 described later, pulsed laser light is irradiated onto the laser absorbing layer P or the interface between the laser absorbing layer P and the etching stop layer Q. The type of laser light can be determined depending on the material of the laser absorbing layer P or other target material for laser irradiation. In one embodiment, the laser light is CO ２ Laser light, CO ２The wavelength of the laser light is, for example, 8.9 μm to 11 μm. In one embodiment, the laser light is IR laser light, and the wavelength of the IR laser light is, for example, 1.5 μm to 2.5 μm. The laser light L may be irradiated spirally over the entire surface of the laser absorbing layer P in a planar view, or may be irradiated concentrically over the entire surface of the laser absorbing layer P in an annular pattern. The laser light L may also be irradiated in pulses onto the laser absorbing layer P while a lens (not shown) included in the laser irradiation device is moved linearly. In this case, for example, a linear movement mechanism (transporter) may be provided for the lens to move the lens horizontally, or the laser light from the lens may be scanned by, for example, a galvanometer scanner (not shown). The laser light L passes through the first wafer W from the back surface Wb side of the first wafer W and is absorbed in the laser absorbing layer P. This laser light L reduces the bonding strength at the laser absorbing layer P, the interface between the laser absorbing layer P and the wafer W, or the interface between the laser absorbing layer P and the etching stop layer Q.

[0026] In the following description, the interface inside the first overlapping wafer T1 where the bonding strength has decreased (in this embodiment, the inner surface of the laser absorbing layer P) may be referred to as the "separation surface" in the technology of the present disclosure. Furthermore, in this embodiment, "decreased bonding strength" refers to a state where the bonding strength has decreased at least compared to before the irradiation of the laser light L, and includes separation between the laser absorbing layer P and the etching stop layer Q.

[0027] Next, as shown in FIG. 7 , the first wafer W is separated from the second wafer S in the first overlapping wafer T1 (St6 in FIGS. 1 and 2 ). In St6, for example, in a separation device 60 described later, the first wafer W is separated using the laser absorption layer P, the bonding strength of which has been reduced in St5, as a base point. Note that in this specification, the second wafer S after at least some of the layers formed on the first wafer W have been transferred and the first wafer W has been separated is referred to as the "second wafer S to which the layers have been transferred" or simply as the "second wafer S." In the example of FIG. 7 , the first device layer Dw, the surface films Fw and Fs, the second device layer Ds, and the second wafer S are referred to as the "second wafer S to which the first device layer Dw has been transferred" or simply as the "second wafer S." The same applies to the second overlapping wafer T2 described later.

[0028] The first wafer W can be separated by any method. For example, as shown in FIG. 7( a), a suction chuck 210 suction-holds the back surface Sb of the second wafer S, and a suction pad 211 suction-holds the front surface Wa of the first wafer W. Then, as shown in FIG. 7( b), while the suction pad 211 suction-holds the first wafer W, the suction pad 211 is raised to separate the first wafer W. At this time, as described above, the bonding strength is reduced inside the laser absorption layer P or at the interface between the laser absorption layer P and the etching stop layer Q due to the irradiation of the laser light L. Therefore, the first wafer W can be separated without applying a large load. Furthermore, since the unbonded region B1 is bevel-filled, a bonding force is generated in the unbonded region B1, ensuring separation at the interface. This prevents partial bevel damage, as shown in the comparative example of FIG. 25. As a result, the first device layer Dw transferred to the second wafer S can be widened, improving productivity.

[0029] Next, the separated surface of the first overlapping wafer T1 obtained by separating the first wafer W is subjected to surface treatment (St7 in FIGS. 1 and 2). In St7, the separated surface may be cleaned in, for example, a cleaning apparatus 90. Alternatively, the separated surface may be polished and planarized or removed in, for example, a polishing apparatus (not shown) or an etching apparatus (not shown). Details of the surface treatment according to this embodiment will be described later.

[0030] In one embodiment, the surface treatment includes a chemical mechanical polishing (CMP) process. In the CMP process, a polishing pad is brought into contact with the separated surface of the first overlapped wafer T1, and the surface is polished while applying pressure. In this process, the filler G according to this embodiment serves to prevent damage to the unbonded region of the bevel portion of the first overlapped wafer T1 due to the pressure.

[0031] In one embodiment, the material of the filler G is selected from the viewpoint of resistance to the laser light irradiation in St5. In this case, if the surface treatment in St7 includes CMP, it is preferable that the filler G also be resistant to each process step included in CMP. In one embodiment, if the filler G filled in St4 does not have resistance to one of the CMP processes, the filler G is removed after the separation of the first wafer W (St6) and before the CMP is performed in the surface treatment (St7). In this case, when the CMP is performed in the surface treatment (St7), another filler G that is resistant to each process step included in CMP is again filled in the unbonded region B1 of the first overlapped wafer T1. This prevents the unbonded region B1 from being damaged during the subsequent CMP. The refilling of the other filler G can be performed in the same manner as in St4 described above.

[0032] Next, a wiring layer Wr is formed on the surface-treated first overlapping wafer T1 (St8 in FIGS. 1 and 2 ). The wiring layer Wr can be formed by a known wiring process (BEOL: Back End of Line). Since a third wafer U (described later) is further bonded to the wiring layer Wr of the first overlapping wafer T1 according to this embodiment, a bonding surface film Ft is provided on the wiring layer Wr in St8. In one embodiment, the manufacturing method ends without bonding another wafer to the wiring layer Wr of the first overlapping wafer T1. In this case, the wiring layer Wr does not necessarily have to have a bonding surface film Ft.

[0033] Next, a third wafer U is prepared (St9 in FIGS. 1 and 2 ). The preparation of the third wafer U in St9 is similar to the preparation of the first wafer W in St1. That is, a stacked film including a laser absorption layer P, an etching stop layer Q, a third device layer Du, and a surface film Fu is formed on the surface of the third wafer U. The absorption layer P, the etching stop layer Q, the third device layer Du, and the surface film Fu of the third wafer U according to this embodiment are similar to the absorption layer P, the etching stop layer Q, the first device layer Dw, and the surface film Fw of the first wafer W, respectively. In one embodiment, the third device layer Du of the third wafer U includes devices different from the first device layer Dw of the first wafer W.

[0034] 1 and 2 , the second wafer S onto which the first device layer Dw has been transferred is bonded to a third wafer U to obtain a second overlapping wafer T2 as an overlapping substrate (St10). The bonding between the third wafer U and the second wafer S in St10 is similar to the bonding between the first wafer W and the second wafer S in St3. Thereafter, the filler G is filled in the unbonded region B2 of the second overlapping wafer T2 by bevel filling (St11) of the second overlapping wafer T2. In one embodiment, if the filler G filled in the unbonded region B1 of the first overlapping wafer T1 has been removed in a process prior to St11, the filler G is filled in both the unbonded regions B1 and B2 in St11. Thereafter, irradiation with laser light L (St12), separation of the third wafer U (St13), surface treatment of the second wafer S onto which the third device layer Du has been transferred (St14), and formation of a wiring layer Wr (St15) are sequentially performed. St11 to St15 are the same as St4 to St8. In this embodiment, the manufacturing method ends after the wiring layer Wr is formed in St15. In one embodiment, after the wiring layer Wr is formed in St15, another wafer (not shown) may be further bonded onto the wiring layer Wr of the second overlapping wafer T2, and steps similar to St3 to St8 may be performed. Note that in this specification, the first overlapping wafer T1 and the second overlapping wafer T2 may be collectively referred to simply as "overlapping wafers T1 and T2."

[0035] In the separation of St13, since the unbonded regions B1 and B2 are bevel filled, a bonding force is generated in the unbonded regions B1 and B2, and therefore it is possible to ensure separation at the bonding interface between the second wafer S and the third wafer U. This makes it possible to prevent repeated damage to the bevel and to prevent consumption of the region where a device can be formed, even in a process in which bonding and separation are repeated two or more times.

[0036] The first wafer W separated in St7 is reused (St20 in FIG. 1 ). As an example of the recycling process for the first wafer W, the laser absorbing layer P remaining on the first wafer W is etched and removed in an etching apparatus (not shown). The etching of the laser absorbing layer P may be dry etching or wet etching. From this perspective, the laser absorbing layer P is configured to be selectively etched with respect to the front surface Wa of the first wafer W. In one embodiment, when a sacrificial layer is present between the laser absorbing layer P and the first wafer W, selective etching is first performed between the laser absorbing layer P and the sacrificial layer, and then selective etching is performed between the sacrificial layer and the front surface Wa of the first wafer W.

[0037] The first wafer W from which the laser absorbing layer P has been removed is then subjected to the same process as in St1, and a separation layer Mw, a first device layer Dw, and a surface film Fw are formed on the front surface Wa. In this way, the first wafer W is reused for the next second wafer S. Note that the first wafer W from which the laser absorbing layer P has been removed is a bare wafer with no film formed on the front surface Wa, and therefore may be reused as the next second wafer S.

[0038] The third wafer U separated in St13 is reused (St21 in FIG. 1) in the same manner as the first wafer W in St20.

[0039] 8, a manufacturing method according to one embodiment will be described below in which, in preparation of a first wafer W (St1 in FIG. 1), at least a part of a 3D NAND memory cell array is formed in a device layer Dw of the first wafer W. The device layer Dw includes memory holes H formed by the following method, for example.

[0040] Specifically, the preparation of the first wafer W (St1 in FIG. 1) according to this embodiment includes the steps shown in FIGS. 9 and 10. FIGS. 10A to 10C are diagrams showing an example of the state of the device layer Dw in major steps among the steps. The same applies to the preparation of the third wafer U in St9 in FIG. 1.

[0041] First, a laser absorbing layer P is formed above the surface Wa of the first wafer W (Step 101 in FIGS. 9 and 10). The laser absorbing layer P is a desired oxide film (SiO ２ film, TEOS film).

[0042] Next, an etching stop layer Q is formed above the laser absorption layer P (Step 102 in FIGS. 9 and 10). The etching stop layer Q is made of polycrystalline silicon.

[0043] Next, an etching stop structure ES is formed in a part of the etching stop layer Q corresponding to a position where a memory hole H, which will be described later, is to be formed (St103 in FIG. 9).

[0044] In St103, first, a recess ES' is formed in the part of the etching stop layer Q (St103a in FIG. 10). Then, a pad Pd and an oxide film Ox are formed in the recess ES' (St103b in FIG. 10). The pad Pd has the function of stopping etching so that the laser absorption layer P, the first wafer W, and the like below the pad Pd are not etched in a high aspect ratio (HAR) etching process when forming the memory hole H, which will be described later. Examples of materials for the pad Pd include titanium nitride (TiN), tungsten (W), and tungsten silicide (WSi ２ However, the present invention is not limited to these, and other known materials that have the above-mentioned effects may be used.

[0045] In one embodiment, the etching stop structure ES is configured not to have a pad Pd. In this case, the etching stop layer Q may be configured not to have an etching stop structure ES. Furthermore, in this case, the etching stop layer Q may be formed to have a thickness sufficient to prevent etching below the pad Pd in ​​the etching step for forming the memory hole H, which will be described later.

[0046] Next, an alternating layer AL in which a plurality of oxide films and nitride films are alternately stacked as a laminated film is formed above the etching stop layer Q (Step 104 in FIGS. 9 and 10).

[0047] Next, deep holes DH are formed by HAR etching so as to penetrate the alternating layers AL at positions where memory holes H are to be formed (Step 105 in FIGS. 9 and 10 ). Step 105 can be performed using a known patterning device and etching device. The deep holes DH formed by etching stop at the etching stop structures ES and do not reach the laser absorption layer P or the first wafer W. This allows for subsequent separation of the laser absorption layer P to be performed favorably. Furthermore, the possibility of reusing the separated first wafer W is improved.

[0048] Next, the etching stop structure ES is removed (Step 106 in FIGS. 9 and 10). The etching stop structure ES is removed by, for example, dry etching.

[0049] Next, a memory hole H is formed in the deep hole DH from which the etching stop structure ES has been removed (Step 107 in FIGS. 9 and 10). The memory hole H can be formed by, for example, forming various films on the sidewall of the deep hole DH.

[0050] After the memory holes H are formed, a wiring layer Wr and a surface film Fw are formed as shown in FIG. 10C (Step 108 in FIG. 9). The wiring layer Wr according to this embodiment includes a conductive material that forms a signal network or a power supply network. The surface film Fw includes a copper pad Cu that is electrically connected to the wiring layer Wr.

[0051] In one embodiment, a memory hole H with an even higher aspect ratio is obtained by further forming another deep hole DH above the deep hole DH formed in St105 and St106. Specifically, as shown in FIGS. 11 and 12, after the execution of St101 to St106, St110 to St113 are further executed, and then St107 and St108 are executed.

[0052] After St106 is performed, first, a sacrificial layer SL is formed in the deep hole DH (St110 in FIGS. 11 and 12).

[0053] Next, above the deep hole DH filled with the sacrificial layer SL, another alternating layer AL of multiple oxide and nitride films is formed (St111 in FIGS. 11 and 12 ). The other alternating layer AL is configured to include an etching stop portion EP. The etching stop portion EP has the function of stopping etching so that the area below the etching stop portion EP is not etched during HAR etching of the other alternating layer AL. The material of the etching stop portion EP is not particularly limited as long as it can ensure an etching selectivity relative to the oxide or nitride film that constitutes the other alternating layer AL.

[0054] Next, at the position where the memory hole H is to be formed, another deep hole DH is formed by performing HAR etching so as to penetrate the other alternating layers AL (Step 112 in FIGS. 11 and 12 ). Step 112 is the same as Step 105 described above. The etching of the other deep hole DH formed by the etching stops at the etching stop portion EP.

[0055] Next, the etching stopper EP is removed, and then the sacrificial layer SL is removed (Step 113 in FIGS. 11 and 12). The etching stopper EP and the sacrificial layer SL are removed by, for example, dry etching. By Step 113, the lower deep hole DH formed by Steps 105 and 106 is connected to another upper deep hole DH, forming a single deep hole.

[0056] Thereafter, various films are formed on the sidewalls of the communicating deep holes DH in Step St107 to form memory holes H. In addition, a wiring layer Wr and a surface film Fw are formed in Step St108.

[0057] Referring again to FIG. 8 , in preparation of the second wafer S (St2 in FIG. 1 ), a second wafer S is prepared on which a peripheral circuit for controlling a memory cell array is formed in the device layer Ds. The peripheral circuit according to this embodiment includes a CMOS (Complementary Metal-Oxide-Semiconductor) and a wiring layer Wr electrically connected to the CMOS. The surface film Fs of the second wafer S also includes a copper pad Cu electrically connected to the wiring layer Wr. Note that in St2, the second wafer S may be prepared on which a peripheral circuit has already been formed, or the second wafer S may be prepared by forming the peripheral circuit in St2.

[0058] After the first wafer W and the second wafer S are prepared as described above, the first wafer W and the second wafer S are bonded together to obtain a first overlapping wafer T1 (St3 in FIGS. 1 and 8).

[0059] Next, bevel filling of the unbonded region B of the first overlapping wafer T1 (St4 in FIGS. 1 and 8), irradiation of the laser light L onto the laser absorption layer P (St5 in FIGS. 1 and 8), and separation of the first wafer W (St6 in FIGS. 1 and 8) are sequentially performed.

[0060] Next, a surface treatment is performed on the separated surface of the first overlapping wafer T1 from which the first wafer W has been separated (St7 in FIGS. 1 and 8 ). In the surface treatment according to this embodiment, the laser absorbing layer P remaining on the separated surface of the first overlapping wafer T1 after separation of the first wafer W is removed. Subsequently, the etching stop layer Q is removed. Removal of the laser absorbing layer P may include, for example, selective etching of the laser absorbing layer P relative to the etching stop layer Q. Removal of the etching stop layer Q may also include selective etching of the etching stop layer Q relative to the device layer Dw of the first wafer W. Surface treatment including selective etching of the etching stop layer Q can improve the total thickness variation (TTV) of the first overlapping wafer T1 after the surface treatment.

[0061] In this embodiment, at least a portion of the memory hole H included in the device layer Dw is exposed on the separation surface of the first overlapping wafer T1 after the surface treatment. Then, a wiring layer Wr is formed to be electrically connected to the exposed memory hole H (St8 in FIGS. 1 and 8 ). In one embodiment, after the surface treatment, a portion of the memory hole H including a polycrystalline silicon film doped with impurities and rendered conductive is exposed. In this case, the wiring layer Wr can be formed in St8 so as to be electrically connected to the polycrystalline silicon film.

[0062] Thereafter, a surface film Ft for bonding may be formed when bonding the first overlapped wafer T1 and the third wafer U. Thereafter, the second overlapped wafer T2 may be formed by further performing bonding with the third wafer U (St9 to St15). In this case, the third wafer U may be configured to include at least a part of the memory cell array of the 3D NAND, similar to the first wafer W.

[0063] The bevel filling according to the first embodiment will be described below. The bevel filling according to the first embodiment is performed on the overlapped wafer T, and can be performed on the first overlapped wafer T1 in St4 or the second overlapped wafer T2 in St11 according to the above-described embodiments. For ease of explanation, the etching stop layer Q of the first wafer W, the device layer Dw, and the device layer Ds of the second wafer S, which are described in the above-described embodiments, are not shown in the following FIGS. 16 to 19.

[0064] 16 , in the bevel fill according to the first embodiment, the filler G is filled up to a second outer periphery position E2, which is predetermined as a position radially inward from a first outer periphery position E1 of the surface film Fw of the first wafer W serving as the first bonding layer of the overlapped wafer T. Note that the first outer periphery position E1 of the surface film Fw is the outermost position in the radial direction in a cross-sectional view of the overlapped wafer T. The second outer periphery position E2 of the filler G is the outermost position in the radial direction in a cross-sectional view of the overlapped wafer T. This also applies to the second and third embodiments described below.

[0065] In one embodiment, filling the filler G up to the second outer circumferential position E2 can be achieved, for example, by adjusting the supply speed of the filler G from the injector 9 or the rotation speed of the overlapped wafer T while rotating the overlapped wafer T while injecting liquid filler G from the injector 9. In one embodiment, filling the filler G up to the second outer circumferential position E2 can be achieved by injecting the filler G into the overlapped wafer T up to the radial outside of the second outer circumferential position E2, and then removing the filler G up to the second outer circumferential position E2.

[0066] In one embodiment, a third outer periphery position E3, which is the outermost position in the radial direction of the contact interface between the surface film Fw and the filler G, can be determined as follows using a first distance D1 and a second distance D2 in a cross-sectional view of the overlapped wafer T. The first distance D1 is the distance between a separation surface Sf, which is an interface where the bonding strength is reduced by laser irradiation of the laser absorbing layer P, and a bonding interface Bf between the first wafer W and the second wafer S. The second distance D2 is the distance between the separation surface Sf and the third outer periphery position E3. At this time, the third outer periphery position E3 is determined so that D1-D2>Th holds for a predetermined threshold value Th. Note that in the example shown in FIG. 17 according to this embodiment, the separation layer Sf is the interface between the laser absorbing layer P and the first wafer W. However, the separation surface Sf may be other than this, for example, an internal surface of the laser absorbing layer P or the interface between the laser absorbing layer P and the etching stop layer Q according to the above embodiment.

[0067] In one embodiment, the third outer periphery position E3 may be determined such that the first distance D1 and the second distance D2 satisfy the relationship D1 / D2>Th2, where Th2 is a predetermined threshold value.

[0068] In the bevel fill of the first embodiment, the filler G is filled up to a second outer peripheral position E2, which is predetermined as a position radially inward from the first outer peripheral position E1, thereby suppressing inappropriate separation as described above using Figure 25.

[0069] The reason why the bevel fill according to the first embodiment suppresses inappropriate separation is not clear, but the following example of operation can be assumed. As shown in Fig. 18 , when an upward force Fup is applied to the outer periphery We of the first wafer W, it is considered that stress σ1 concentrated near the outermost periphery of the bonding interface Bf between the first wafer W and the second wafer S and stress σ2 concentrated near the third outer periphery position E3 act. At this time, the contribution of stress σ2 to separation is greater than the contribution of stress σ1 to separation, and therefore it is considered that a crack Cr occurs with its base point near the third outer periphery position E3.

[0070] 19 , in the case where the laser absorption layer P is formed so as to extend to the unbonded region B, there may be a case where a crack Cr is not formed with the third outer peripheral position E3 as the base point when an upward force Fup is applied to the outer peripheral portion We of the first wafer W. This is thought to be because the separation layer Sf is formed up to the unbonded region B, and therefore separation in the separation layer Sf takes precedence.

[0071] Furthermore, by determining the third outer peripheral position E3 so that D1-D2>Th holds, the above-described inappropriate separation can be further suppressed. The reason for this is not clear, but the following example of operation can be assumed. For the crack Cr shown in FIG. 18, it is believed that more appropriate separation will occur if the crack Cr propagates toward the separation surface Sf. Therefore, by determining the third outer peripheral position E3 as described above, it is possible to shorten the distance between the third outer peripheral position E3 and the separation surface Sf, and it is believed that the crack Cr will be more likely to propagate toward the separation surface Sf.

[0072] The inventors have conducted extensive research and found that the above-described inappropriate separation is particularly likely to occur in a first wafer W having a stacked film with a large first distance D1. Here, a stacked film with a large first distance D1 is considered to be a case in which the entire stacked film is thickened by forming a device layer Dw through repeated processes, as in the first wafer W according to the above-described embodiment. In particular, when the device layer Dw includes a memory cell array of a NAND flash memory, the stacked film including the device layer Dw is significantly thickened.

[0073] The bevel fill according to the first embodiment can prevent the above-described inappropriate separation even when separating the overlapped wafer T having the first wafer W with a laminated film having a large first distance D1.

[0074] Bevel filling and separation according to the second embodiment will be described below. The bevel filling and separation according to the second embodiment is performed on the overlapped wafer T, and can be performed on the first overlapped wafer T1 in Sts 4 and 6 or on the second overlapped wafer T2 in Sts 11 and 13 according to the above embodiments. For ease of explanation, the etching stop layer Q of the first wafer W, the device layer Dw, and the device layer Ds of the second wafer S, which are described in the above embodiments, are not shown in FIGS. 20 to 23 below.

[0075] In the bevel fill according to the second embodiment, as shown in FIG. 20 , the filler G is filled up to a second outer peripheral position E2, which is predetermined as a position radially outward from the first outer peripheral position E1 of the surface film Fw of the first wafer W as the first bonding layer of the overlapped wafer T.

[0076] Next, separation base points A are formed in the filler G of the overlapped wafer T after the bevel filling. The separation base points A can be formed, for example, using a blade 220 provided in a separation device 60 described later. To form the separation base points A, first, as shown in FIG. 21 , the blade 220 is inserted around the periphery of the filler G. Then, by further advancing the blade 220 in the direction of the straight arrow in FIG. 21 , separation base points A are formed where the filler G loses strength near the insertion position. Furthermore, with the blade 220 inserted, the overlapped wafer T is rotated. As a result, separation base points A are formed around the entire periphery of the overlapped wafer T in a plan view, as shown in FIG. 22 . Note that the blade 220 may be rotated around the periphery of the overlapped wafer T to form separation base points A around the entire periphery of the overlapped wafer T.

[0077] After the separation base point A is formed, the first wafer W or the third wafer U is separated from the second wafer S in the same manner as described for St6 and St13 according to the above embodiment.

[0078] The blade 220 is configured to be movable so as to be inserted into at least one location on the circumference of the filler G. The blade 220 constitutes a base point forming portion in the present disclosure.

[0079] In one embodiment, the base point forming unit in the present disclosure includes a moving mechanism 221 that holds the blade 220 movably at least in the horizontal direction. The base point forming unit also includes a sensor 222 that detects the horizontal position or horizontal pressure of the blade 220 relative to the filler G with which the blade 220 is in contact. The horizontal position or pressure of the blade 220 detected by the sensor 222 is output to the control device 61. Furthermore, the control device 61 controls the moving mechanism 221 based on the horizontal position or pressure of the blade 220 to adjust the horizontal position of the blade 220 so that separation base points A are formed at a desired radial depth in the filler G. In one embodiment, when separation base points A are formed around the entire circumference of the filler G, the control device 61 controls the moving mechanism 221 to adjust the horizontal position of the blade 220 so that the radial depth of the separation base points A is uniform around the entire circumference.

[0080] In one embodiment, after forming separation base points A around the entire periphery of the interface between the first wafer W and the second wafer S, a further separation base point A may be formed at one location on the interface. In this case, after forming separation base points A around the entire periphery, the blade 150 is further inserted toward the center at one location on the interface to form a peel base point A.

[0081] In one embodiment, the base point forming portion in the present disclosure may include an ultrasonic oscillator (not shown) that applies ultrasonic vibrations to the blade 220 .

[0082] The base point forming unit is not limited to the above embodiment including the blade 220, and any desired configuration capable of forming the separation base points A on the circumference of the filler G can be employed. For example, the separating device 60 may include an air cutter (not shown) as the base point forming unit. The air cutter supplies air to the interface between the first wafer W and the second wafer S to form the separation base points A. To facilitate the formation of the separation base points A, the air may be pressurized high-pressure air or heated high-temperature air. Alternatively, instead of the air cutter, a water cutter may be used that supplies water to the interface between the first wafer W and the second wafer S. The water supplied from the water cutter may be pressurized high-pressure water or heated high-temperature water.

[0083] Furthermore, for example, the separating device 60 may include a rotating cutter (not shown) as the base point forming unit. The rotating cutter has a configuration in which the cutter is rotated by, for example, a motor (not shown). In such a case, the rotating cutter is inserted into the interface between the first wafer W and the second wafer S while being rotated, thereby forming the separation base point A.

[0084] Furthermore, for example, the separating apparatus 60 may include a heating unit (not shown) as a base point forming unit. The heating unit heats the interface between the first wafer W and the second wafer S to expand the first wafer W and the second wafer S, and applies thermal stress to the interface to form the separation base point A.

[0085] Furthermore, for example, the separation device 60 may be provided with a suction mechanism 230 below the base point forming portion such as the blade 220, as shown in FIG. 21 . The suction mechanism 230 is connected to a suction source (not shown) and sucks the atmosphere near the separation base point A. When the blade 220 is inserted into the filler G to form the separation base point A, particles and the like may be generated by cutting. The suction mechanism 230 can suck and remove the particles and the like, thereby maintaining the interior of the separation device 60 clean. Furthermore, a downflow may be formed inside the separation device 60 during separation. In such a case, by disposing the suction mechanism 230 below the blade 220, the particles and the like can be more efficiently sucked by the suction mechanism 230.

[0086] In the bevel filling and separation according to the second embodiment, the filler G is filled up to a second outer peripheral position E2, which is predetermined as a position radially outward from the first outer peripheral position E1, and a separation base point A is formed around the entire circumference of the filler G, thereby suppressing inappropriate separation as described above using FIG. 25 .

[0087] The reason why the bevel fill according to the second embodiment suppresses improper separation is unclear, but the following example of operation can be assumed. First, the inventors conducted extensive research and found that, particularly when the filler G is filled up to a second outer peripheral position E2 radially outward of the first outer peripheral position E1, cracks Cr may occur at random positions on the contact interface between the filler G and the surface film Fw at each position on the circumference of the overlapped wafer T during separation. Such cracks Cr at random positions can cause the above-mentioned improper separation. In contrast, in the separation according to the second embodiment, as shown in FIG. 23 , when an upward force Fup is applied to the outer peripheral portion We of the first wafer W, stress tends to concentrate in the region of the contact interface between the filler G and the surface film Fw near the portion where the separation base point A is formed, and it is believed that cracks Cr originate from this region. Furthermore, since the separation base point A is formed around the entire circumference of the filler G, cracks Cr propagate uniformly around the entire circumference, resulting in favorable separation.

[0088] Hereinafter, bevel filling and irradiation of laser light L according to the third embodiment will be described. The bevel filling and irradiation of laser light L according to the third embodiment are performed on the overlapped wafer T, and can be performed as the bevel filling and irradiation of laser light L on the first overlapped wafer T1 in St4 and St5 or the bevel filling and irradiation of laser light L on the second overlapped wafer T2 in St11 and St12 according to the above embodiments. Note that, for convenience of explanation, the etching stop layer Q of the first wafer W, the device layer Dw, and the device layer Ds of the second wafer S, which are described in the above embodiments, are not shown in FIG. 19 below.

[0089] The bevel fill according to the third embodiment is similar to the bevel fill according to the second embodiment, and as shown in FIG. 20 , the filler G is filled up to a second outer peripheral position E2, which is predetermined as a position radially outward from the first outer peripheral position E1, corresponding to the first outer peripheral position E1 of the surface film Fw of the first wafer W as the first bonding layer of the overlapped wafer T.

[0090] Next, separation base points A are formed on the filler G of the laminated wafer T after bevel filling. The separation base points A are formed by irradiating the filler G with laser light, as shown in FIG. 24 . The irradiation of laser light is similar to the irradiation of laser light L on the laser absorption layer P described in St5 according to the above embodiment. By irradiating the filler G with laser light L, separation base points A are formed where the filler G has lost its strength. The separation base points A may be formed around the entire periphery of the filler G, similar to the separation according to the second embodiment shown in FIG.

[0091] The bevel filling and laser irradiation according to the third embodiment achieve the same effects and advantages as those described for the bevel filling and separation according to the second embodiment. That is, as shown in FIG. 23 , when an upward force Fup is applied to the outer peripheral portion We of the first wafer W, stress tends to concentrate in the region of the contact interface between the filler G and the surface film Fw near the portion where the separation base point A is formed, and cracks Cr are thought to have occurred starting from that region. Furthermore, since separation base points A are formed around the entire circumference of the filler G, cracks Cr are thought to have propagated uniformly around the entire circumference, resulting in favorable separation. Therefore, inappropriate separation as described above with reference to FIG. 25 can be suppressed.

[0092] A wafer processing system 1 will be described below as an example of a substrate processing system capable of performing the bonding and separation of the first substrate and the second substrate in the wafer processing method described above.

[0093] 13 , wafer processing system 1 has a configuration in which a load / unload station 2 and a processing station 3 are integrally connected. In load / unload station 2, for example, a cassette C capable of accommodating a plurality of overlapping wafers T1, T2 is loaded and unloaded between the load / unload station 2 and the outside. Processing station 3 is equipped with various processing devices that perform desired processing on overlapping wafers T1, T2.

[0094] The carry-in / out station 2 is provided with a cassette mounting table 10 on which a cassette C capable of accommodating a plurality of overlapping wafers T1, T2 is mounted. A wafer transfer device 20 is provided adjacent to the cassette mounting table 10 on the positive side of the X-axis of the cassette mounting table 10. The wafer transfer device 20 moves on a transfer path 21 extending in the Y-axis direction, and is configured to be able to transfer the overlapping wafers T1, T2 between the cassette C on the cassette mounting table 10 and a transition stage 30, which will be described later.

[0095] In the loading / unloading station 2, a transition stage 30 is provided adjacent to the wafer transport device 20 on the positive X-axis side of the wafer transport device 20 for transferring the overlapping wafers T1 and T2 between the processing station 3.

[0096] In the processing station 3, a wafer transfer device 40, a laser processing device 50, a separation device 60, a bevel filling device 70, a baking device 80, and a cleaning device 90 are arranged.

[0097] The wafer transfer device 40 is provided on the positive X-axis side of the transition stage 30. The wafer transfer device 40 is configured to be movable on a transfer path 41 extending in the X-axis direction, and is configured to be able to transfer the overlapped wafers T1 and T2 to the transition stage 30 of the carry-in / out station 2, the laser processing device 50, the separation device 60, the bevel fill device 70, the bake device 80, and the cleaning device 90.

[0098] The laser processing device 50 irradiates the laser absorption layer P at the interface between the first wafer W and the second wafer S with laser light L1, thereby forming a region of reduced bonding strength where the first wafer W and the second wafer S are separated. The laser processing device 50 has a control device 51, which will be described later.

[0099] As shown in FIGS. 14 and 15 , the laser processing apparatus 50 includes a chuck 100 that holds the overlapping wafers T1 and T2 on their upper surfaces. The chuck 100 suction-holds the back surface Sb of the second wafer S, with the first wafer W positioned on top and the second wafer S positioned on the bottom. The chuck 100 is supported by a slider table 102 via an air bearing 101. A rotation mechanism 103 is provided on the underside of the slider table 102. The rotation mechanism 103 incorporates, for example, a motor as a drive source. The chuck 100 is configured to be rotatable about a vertical axis by the rotation mechanism 103 via the air bearing 101. The slider table 102 is configured to be movable on rails 106 extending in the Y-axis direction on a base 105 via a movement mechanism 104 provided on the underside of the slider table 102. The drive source of the movement mechanism 104 is not particularly limited, but may be, for example, a linear motor.

[0100] A laser head 110 is provided above the chuck 100. The laser head 110 has a lens 111. The lens 111 irradiates the laser absorption layer P of the overlapping wafers T1 and T2 held by the chuck 100 with laser light L1. This causes the first wafer W and the laminated film to separate at the portion irradiated with the laser light L1, forming a reduced bonding strength region where the first wafer W and the second wafer S are separated. The location of the reduced bonding strength region is not particularly limited as long as separation occurs at the interface between the first wafer W and the second wafer S and the bonding strength can be reduced. That is, separation between the first wafer W and the second wafer S may occur at the interface between the first wafer W and the laminated film as shown in the figure, or may occur at the interface between the laminated films or the interface between the second wafer S and the laminated film.

[0101] The laser head 110 is supported by a support member 112. The laser head 110 is configured to be able to move up and down by an elevating mechanism 114 along rails 113 extending in the vertical direction. The laser head 110 is also configured to be able to move in the Y-axis direction by a moving mechanism 115. The elevating mechanism 114 and the moving mechanism 115 are each supported by a support column 116.

[0102] In the illustrated example, the chuck 100 is configured to be rotatable relative to the laser head 110 and movable horizontally by the rotation mechanism 103 and the movement mechanism 104, but the laser head 110 may be configured to be rotatable relative to the chuck 100 and movable horizontally. Alternatively, both the chuck 100 and the laser head 110 may be configured to be rotatable relative to each other and movable horizontally.

[0103] 7A, the separation device 60 includes the suction chuck 210 and the suction pad 211. Then, by the method described above, the first wafer W is separated from the second wafer S, using the bonding strength reduced region as a base point. In one embodiment, the separation device 60 includes the blade 220, the moving mechanism 221, and the sensor 222 described above.

[0104] The bevel fill device 70 includes an injector 9 as shown in FIG. 4 or 5 and is configured to be able to inject filler G into the bevel portions of the overlapping wafers T1, T2. As an example, the bevel fill device 70 includes a chuck (not shown) similar to the chuck 100. The overlapping wafers T1, T2 are held on the chuck, and filler G is injected from the injector 9 into the bevel portions while the overlapping wafers T1, T2 are rotated. This makes it possible to inject filler G into the bevel portions around the entire periphery of the overlapping wafers T1, T2. In one embodiment, the bevel fill device 70 is controlled to inject filler G only into the unbonded regions of the bevel portions of the overlapping wafers T1, T2.

[0105] The baking device 80 is configured to bake (fire) the filler G in the overlapping wafers T1 and T2 in which the filler G has been injected into the bevel portion.

[0106] The cleaning device 90 performs a cleaning process on the first wafer W and the second wafer S after the filler G has been injected by the bevel fill device 70 or after the filler G has been baked by the bake device 80, thereby removing particles on these wafers and the filler G adhering to unnecessary locations. The cleaning method can be selected arbitrarily.

[0107] In one embodiment, the wafer processing system 1 is divided into a plurality of systems, including one wafer processing system including a laser processing device 50 and a separation device 60, and another wafer processing system including a bevel fill device 70 and a bake device 80. Wafers W, S, U, overlapping wafers T1, T2, etc. are transported between these multiple systems, and desired processing is performed on each wafer.

[0108] The above-described wafer processing system 1 is provided with a control device 51, a control device 61, and at least one control device 95. The control device 51 individually controls the operation of the laser processing device 50. The control device 61 individually controls the operation of the separation device 60. The control device 95 comprehensively controls a series of wafer processing operations in the wafer processing system 1.

[0109] Controller 51, controller 61, and controller 95 each process computer-executable instructions that cause laser processing device 50, separation device 60, and wafer processing system 1 to perform the various steps described in this disclosure. Controller 51, controller 61, and controller 95 can each be configured to control elements of laser processing device 50, separation device 60, and wafer processing system 1 to perform the various steps described herein. In one embodiment, some or all of controller 51 may be included in laser processing device 50, some or all of controller 61 may be included in separation device 60, and some or all of controller 95 may be included in wafer processing system 1.

[0110] The control devices 51, 61, and 95 may each include a processing unit, a storage unit, and a communication interface. The control devices 51, 61, and 95 may each be realized by, for example, a computer. The processing unit may be configured to read a program providing logic or routines that enable various control operations from the storage unit and execute the read program to perform various control operations. This program may be stored in the storage unit in advance or may be acquired via a medium when needed. The acquired program is stored in the storage unit and read from the storage unit and executed by the processing unit. The medium may be various computer-readable storage media or a communication line connected to the communication interface. The storage medium may be temporary or non-temporary. The processing unit may be a CPU (Central Processing Unit) or one or more circuits. The storage unit may include a RAM (Random Access Memory), a ROM (Read Only Memory), a HDD (Hard Disk Drive), a SSD (Solid State Drive), or a combination thereof. The communication interface may communicate between the laser processing device 50 and the wafer processing system 1 via a communication line such as a LAN (Local Area Network).

[0111] In this embodiment, the control device 51 is installed separately from the laser processing device 50, but the control device 51 may be configured integrally with the control device 95. Furthermore, the control device 61 is installed separately from the separating device 60, but the control device 61 may be configured integrally with the control device 95. In other words, the operations of the laser processing device 50 and the separating device 60 may be controlled by the control device 95.

[0112] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The above-described embodiments may be omitted, substituted, or modified in various ways without departing from the scope and spirit of the appended claims. For example, the components of the above-described embodiments may be arbitrarily combined. Such an arbitrary combination naturally provides the functions and effects of each of the components involved in the combination, and also provides other functions and effects that are apparent to those skilled in the art from the description of this specification.

[0113] Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology according to the present disclosure may achieve other effects that would be apparent to a person skilled in the art from the description of this specification, in addition to or in place of the above-described effects.

[0114] B: Unbonded region P: Laser absorbing layer S: Second wafer T: Overlapped wafer W: First wafer

Claims

1. A method for manufacturing a semiconductor device, In a first substrate having a laser absorption layer and a first bonding layer, and a second substrate having a second bonding layer, a bevel fill is performed in which a filler is filled into the unbonded region of the polymerized substrate where the first bonding layer and the second bonding layer are bonded, up to a second outer peripheral position predetermined to correspond to the first outer peripheral position of the first bonding layer. Irradiating the laser absorption layer with a laser, A method for manufacturing a semiconductor device, comprising separating the first substrate from the second substrate in the polymerization substrate.

2. The second outer peripheral position is radially inward from the first outer peripheral position. A method for manufacturing a semiconductor device according to claim 1, wherein the laser is irradiated onto the laser absorption layer in the polymerization substrate, where the second outer peripheral position is radially inward from the first outer peripheral position, and then the first substrate is separated from the second substrate in the polymerization substrate.

3. The distance between the separation surface between the first substrate and the second substrate formed by irradiation with the laser and the bonding interface between the first bonding layer and the second bonding layer is defined as the first distance. When the distance between the separation surface and the third outer peripheral position, which is the outermost position in the radial direction of the contact interface between the first bonding layer and the filler, is defined as the second distance, The method for manufacturing a semiconductor device according to claim 2, wherein the third outer peripheral position is predetermined such that the difference between the first distance and the second distance is greater than a predetermined threshold.

4. The second outer peripheral position is radially outward from the first outer peripheral position. Before separating the first substrate from the second substrate, A method for manufacturing a semiconductor device according to claim 1, comprising forming separation base points on the entire circumference of the filler material in a plan view.

5. In separating the first substrate from the second substrate, A method for manufacturing a semiconductor device according to claim 4, comprising forming the separation base point using a base point forming unit.

6. The base point forming portion includes a blade, A method for manufacturing a semiconductor device according to claim 5, comprising forming the separation base point by rotating the blade and the polymerization substrate relative to each other while the blade is inserted into the filler.

7. Along with irradiating the laser absorption layer with a laser A method for manufacturing a semiconductor device according to claim 4, comprising irradiating the filler with laser light to form the separation base point.

8. Forming an etching stop layer on the laser absorption layer, A method for manufacturing a semiconductor device according to claim 1, comprising forming a device layer on the etching stop layer.

9. On the first substrate, Forming a wiring layer, A method for manufacturing a semiconductor device according to claim 8, further comprising forming a surface film for bonding.

10. After separating the first substrate from the second substrate, The method further includes surface treatment of the separation surface of the second substrate onto which the device layer has been transferred, The etching stop layer is made of a material that allows selective etching with respect to the separation surface. The aforementioned surface treatment is performed by A method for manufacturing a semiconductor device according to claim 8, comprising removing the etching stop layer by performing the selective etching of the etching stop layer and the separation surface.

11. The aforementioned surface treatment is performed by A method for manufacturing a semiconductor device according to claim 10, comprising exposing at least a portion of the device layer from the separation surface.

12. Forming the aforementioned device layer is Forming a laminated film on the etching stop layer, This includes forming deep holes by etching the laminated film, Forming the etching stop layer means This includes forming an etching stop structure in a portion of the etching stop layer corresponding to the location where the deep hole is to be formed in the device layer, The method for manufacturing a semiconductor device according to claim 8, wherein the etching stopping structure is configured to stop the etching that forms the deep hole at the etching stopping structure.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the etching stop structure includes a pad made of a material selected from one or more of titanium nitride, tungsten, and tungsten silicide.

14. After separating the first substrate from the polymerization substrate, The method for manufacturing a semiconductor device according to claim 1, further comprising removing the filler material that has filled the unbonded region with the bevel filler.

15. After separating the first substrate from the polymerization substrate, The method further includes surface treatment of the separation surface of the polymerized substrate from which the first substrate has been separated, The method for manufacturing a semiconductor device according to claim 14, further comprising performing the bevel fill again on the unbonded region of the polymerized substrate after removing the filler and before surface treating the separation surface.

16. The method for manufacturing a semiconductor device according to claim 8, wherein the device layer includes at least a portion of a memory cell array.

17. The aforementioned second substrate includes other device layers, The method for manufacturing a semiconductor device according to claim 16, wherein the other device layer includes at least a portion of peripheral circuits for controlling the memory cell array.

18. A second polymerized substrate is formed by joining a third substrate having a laser absorption layer with the polymerized substrate, Performing bevel filling on the unbonded region of the second polymerized substrate, Irradiating the laser absorption layer of the third substrate with a laser, A method for manufacturing a semiconductor device according to claim 1, further comprising separating the third substrate from the second substrate in the second polymerization substrate.

19. A semiconductor device manufacturing system, A laser irradiation device that irradiates the laser absorption layer of a polymer substrate, which comprises a first substrate having a laser absorption layer and a first bonding layer, and a second substrate having a second bonding layer, with a laser, and which has been bevel-filled in the unbonded region of the polymer substrate where the first bonding layer and the second bonding layer are bonded, up to a second outer peripheral position predetermined to correspond to a first outer peripheral position of the first bonding layer, in which case a bevel-fill is applied. A semiconductor device manufacturing system comprising: a separation device for separating the first substrate from the second substrate in the polymerization substrate.

20. A semiconductor device manufacturing system according to claim 19, comprising a bevel fill apparatus for performing the bevel fill on the unbonded region of the polymerized substrate.