Semiconductor device production method and plasma processing method

Abstract

Provided is a plasma processing method in which, for a GAA FET having a layered structure of wire-shaped or sheet-shaped channels, in a step of differently fabricating work function metals according to the types of transistors, it is possible to differently fabricate work function metals without using a sacrificial layer for filling a gap, even after a gate insulating film and the work function metals are formed on the channels and even when there is a gap between layered channels 3. To this end, after an organic film mask for covering the layered channels is applied, and patterning for exposing a necessary transistor region is performed to vertically etching the organic film mask, a protective insulating film 13 is entirely deposited. Next, the protective insulating film 13 is isotopically etched such that the protective insulating film 13 remains only on the side walls in the organic film mask. In this state, by removing a work function metal in an opening of the pattern and the organic film mask that fills the gap between the channels 3 in the opening of the pattern, it is possible to remove only the work function metal in the opening of the pattern. By continuously performing the processes from the vertical etching of the organic film mask to the removal of the work function metal using the same apparatus, the steps are simplified.

Description

Semiconductor device manufacturing method and plasma processing method

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a plasma processing method.

[0002] To continuously improve the functionality and performance of integrated circuit chips, which are semiconductor devices, there is a continuing demand for higher integration of transistors, which are semiconductor elements mounted on integrated circuits. Higher integration of transistors has been achieved primarily through miniaturization of transistor element size. To achieve element miniaturization while maintaining or improving transistor performance, numerous improvements have been made to transistor structure and the materials that make up the transistor. These improvements include, for example, the introduction of strain into the source and drain regions of metal oxide semiconductor field effect transistors (MOSFETs), the introduction of high-dielectric gate insulating films and metal gates, and the change in transistor channel structure from planar to three-dimensional fin structures. With further advances in miniaturization, channels are becoming wire-like or sheet-like laminates, and the transistor structure is evolving toward gate-all-around FETs (GAA), in which the channel is surrounded by a gate.

[0003] These improvements are intended to suppress the short-channel effect that occurs as transistor sizes shrink, i.e., the phenomenon in which leakage current flows between the source and drain due to the shortened distance, even when the transistor is off. Among these, metal gates are designed to suppress this leakage current by using the metal's work function, and are characterized by the ability to select the appropriate material depending on the transistor's application (low leakage current or high operating current) and conductivity type (n-type or p-type). For this reason, metal gates are also called work function metals, and the ability to tailor these metals to suit the transistor's characteristics is an essential technology for miniaturizing transistor sizes.

[0004] A method for fabricating different work function metals in transistors with fin-shaped channels is disclosed, for example, in Patent Document 1. A high-k gate insulating film and a work function metal are sequentially deposited on a fin-shaped channel. A mask material is then applied or deposited, followed by patterning parallel to the channel orientation and vertical etching of the mask material. During this process, the fin channel is divided into two portions, one covered by the mask and the other not. The work function metal deposited on the fin channel of a specific transistor can then be removed by isotropically etching a thickness equivalent to the work function metal film thickness. Repeating the above process using multiple mask patterns allows the desired work function metal to be deposited on the desired transistor.

[0005] On the other hand, a method for separately fabricating the work function metal in a GAA transistor is disclosed, for example, in Non-Patent Document 1. In a GAA transistor, wire- or sheet-shaped channels are stacked. Therefore, when the mask material is applied or deposited, the gaps between the stacked channels are filled with the mask material. Therefore, even after patterning and vertical etching of the mask material, the mask material remains in the gaps between the stacked channels in the areas where the mask material should have been etched. Therefore, the work function metal deposited in the areas between the stacked channels is protected by the mask material. Even after etching the work function metal by a thickness equivalent to the film thickness, the work function metal remains in the areas between the stacked channels. This creates a problem: the work function metal cannot be removed from transistor areas where it should be removed.

[0006] Non-Patent Document 1 also discloses a method for avoiding the above-mentioned problems. The high-k gate insulating film and work function metal are sequentially deposited on wire- or sheet-shaped channels, and then the gaps between the stacked channels are filled with a sacrificial layer made of an insulating film. The mask material is then applied or deposited, preventing the mask material from entering the gaps between the channels. However, in this case, the sacrificial layer that has entered the gaps between the stacked channels must be removed by isotropic etching. Because the isotropic etching is performed from the sidewalls of the sacrificial layer that has filled the gaps, an etching depth of at least half the width of the channel is required to remove the sacrificial layer. For example, if the channel width is 60 nm, isotropic etching of at least 30 nm from at least one side of the sidewall is required to remove the sacrificial layer that has filled the gaps between the channels. Assuming the sacrificial layer is approximately 3 nm thick, an etching depth of at least 10 times the thickness of the sacrificial layer is required. In normal etching, the sacrificial layer is etched in the area covered with the mask material by the isotropic etching, and depending on the layout design, the sacrificial layer deposited on the channel of the transistor covered with the mask material may also be removed. In this case, the work function metal of the transistor that should be protected may be removed by the subsequent etching of the work function metal.

[0007] The above-mentioned problems encountered during isotropic etching of the sacrificial film can be avoided by utilizing a phenomenon disclosed in, for example, Patent Document 2. Specifically, when an organic film such as a spin-on carbon film is used as the mask material, a heat treatment during the process increases the adhesion coefficient between the organic film mask and the sacrificial layer, significantly reducing the etching rate of the sacrificial layer in the area covered by the organic film mask. This phenomenon is utilized. This allows for suppressing etching of the sacrificial layer in the area covered by the organic film mask, while etching away the sacrificial layer filling the gaps in the stacked channel in the area not covered by the organic film mask. After etching the sacrificial layer, a structure in which a high-k gate insulating film and a channel formed with a work function metal are stacked with gaps between them is exposed in the area not covered by the organic film mask. Therefore, by isotropically etching a thickness equivalent to the thickness of the work function metal, it is possible to remove the work function metal deposited on the wire- or sheet-shaped channel of a specific transistor.

[0008] US Patent Application Publication No. 2016 / 9236446 US Patent Application Publication No. 2020 / 0411387

[0009] R. Bao, et al., “Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications”, Proceedings of IEDM (IEEE International Electron Device Meeting) 2019, 2019, pp. 234-237

[0010] When the processes disclosed in Non-Patent Document 1 and Patent Document 2 are applied to a GAA transistor, the gap between the stacked channels must be filled with the sacrificial layer to allow for the separate fabrication of the work function metal. However, the process constraint of always having to fill the gap between the stacked channels with the sacrificial layer places limitations on transistor design. In the separate work function metal fabrication process, the organic film mask must always extend into the transistor gate region to cover the stacked channel of the transistor to be protected. The gate region corresponds to the high-k gate insulating film and work function metal deposited on the stacked channel, as well as the trench in which the sacrificial layer is formed, and its width corresponds to a dimension called the gate length or channel length. Because the gate length shrinks with transistor miniaturization, the width of the gate region, i.e., the width of the high-k gate insulating film, work function metal, and trench in which the sacrificial layer is formed, also shrinks with the miniaturization. Therefore, if the sacrificial layer must always be deposited to fill the gap between the stacked channels, there is a possibility that the gate region will be filled when the sacrificial layer is deposited. In this case, the process for creating separate work function metals cannot be performed. In other words, as long as the process using the sacrificial layer is applied, the gate length cannot be reduced beyond a certain point, which places a limit on transistor miniaturization.

[0011] The present disclosure provides a technology for fabricating separate work function metal layers in transistors with stacked channels, including filling gaps between stacked channels with a high-k gate insulating film, work function metal, and an organic film mask, vertically etching the organic film mask along a lithographic pattern to form a protective insulating film covering the partially exposed areas of the work function metal and the sidewalls of the organic film mask, isotropically etching the protective insulating film to form a structure in which only the sidewalls of the organic film are covered with the protective insulating film, and then repeating the isotropic etching of the work function metal and the removal of the organic film that fills the gaps between the stacked channels to remove the work function metal layer on the stacked channel layer that is present in the openings of the pattern while protecting the work function metal layer covered by the pattern. The present disclosure also provides a technology for continuously performing these steps using the same equipment.

[0012] A brief summary of representative aspects of this disclosure is as follows.

[0013] According to one embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor device having a gate region on a semiconductor substrate where a gate is formed, and a semiconductor laminate structure in which sheet-like semiconductor layers or wire-like semiconductor layers having a gate insulating film and a work function control metal deposited on a surface thereof are laminated within the gate region, the method comprising: a first step of etching an organic film mask formed so as to cover the semiconductor laminate structure and filling gaps between the laminated semiconductor layers in a direction perpendicular to the semiconductor substrate; a second step of depositing, after the first step, the work function control metal in exposed regions and a first insulating film on sidewalls of the organic film mask; a third step of removing, after the second step, the first insulating film in regions other than the sidewalls of the organic film mask by isotropic etching; a fourth step of removing, after the third step, the work function control metal exposed in locations other than the gaps; a fifth step of removing the exposed organic film mask after the fourth step; and a sixth step of removing, after the fifth step, the work function control metal in the gaps by isotropic etching.

[0014] Another embodiment of the present disclosure is a plasma processing method for plasma etching a work function control metal in a semiconductor laminate structure having a gate region on a semiconductor substrate where a gate is formed, the semiconductor laminate structure having a sheet-like semiconductor layer or a wire-like semiconductor layer on a surface of which a gate insulating film and a work function control metal are formed, laminated in the gate region, the method comprising: a first step of etching an organic film mask formed so as to cover the semiconductor laminate structure and filling gaps between the laminated semiconductor layers in a direction perpendicular to the semiconductor substrate; a second step of depositing, after the first step, a first insulating film on the exposed region of the work function control metal and on sidewalls of the organic film mask; a third step of removing, after the second step, the first insulating film in regions other than the sidewalls of the organic film mask by isotropic etching; a fourth step of removing the work function control metal exposed in places other than the gaps after the third step; and a fifth step of removing the exposed organic film mask after the fourth step. and a sixth step of removing the work function control metal in the gap by isotropic etching after the fifth step.

[0015] According to one embodiment of the present disclosure, in a process for forming different work function control metals for gate-all-around (GAA) transistors depending on the transistor, even if gaps exist between stacked channels after the work function control metal is formed, the formation of a sacrificial layer to fill the gaps is not required, thereby preventing the phenomenon of the sacrificial layer filling the grooves in the gate formation region. In other words, it is possible to reduce the gate length compared to a process using the sacrificial layer. Furthermore, due to the device characteristics that allow multiple steps for forming the different work function control metals to be performed continuously in the same device, it is possible to suppress an increase in the number of process steps.

[0016] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0017] FIG. 1 is a bird's-eye view showing a manufacturing process of the process for forming separate work function metals in the GaAs FET of Example 1. FIG. 2 is a cross-sectional view of a gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of the process for forming separate work function metals in the GaAs FET of Example 1. FIG. 3 is a cross-sectional view of a gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of the process for forming separate work function metals in the GaAs FET of Example 1. FIG. 4 is a cross-sectional view of a gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of the process for forming separate work function metals in the GaAs FET of Example 1. FIG. 5 is a cross-sectional view of a gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of the process for forming separate work function metals in the GaAs FET of Example 1. FIG. 6 is a cross-sectional view of a gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of the process for forming separate work function metals in the GaAs FET of Example 1. 1A and 1B are enlarged cross-sectional views of a transistor gate region in a direction parallel to the gate in regions inside and outside a pattern mask, respectively, showing a process of removing work function metal in a process of separately creating work function metal in a GaAs FET of Example 1. 1C are enlarged cross-sectional views of a transistor gate region in a direction parallel to the gate in regions inside and outside a pattern mask, respectively, showing a process of removing work function metal in a process of separately creating work function metal in a GaAs FET of Example 1. 1D are enlarged cross-sectional views of a transistor gate region in a direction parallel to the gate in regions inside and outside a pattern mask, respectively, showing a process of removing work function metal in a process of separately creating work function metal in a GaAs FET of Example 1.FIG. 1 is an enlarged cross-sectional view of a transistor gate region in a direction parallel to the gate in regions inside and outside a pattern mask, showing a step of removing work function metal in the process of differentiating work function metal in the GaAs FET of Example 1. FIG. 2 is a cross-sectional view of a transistor gate region in a direction parallel to the gate, showing a structure after forming different work function metals and gate buried metals after manufacturing steps of the process of differentiating work function metal in the GaAs FET of Example 1. FIG. 3 is a flow chart of manufacturing steps of the process of differentiating work function metal in the GaAs FET of Example 1. FIG. 4 is a diagram showing an example of the configuration of a plasma processing apparatus. FIG. 5 is a cross-sectional view of a transistor gate region in a direction parallel to the gate, showing a manufacturing step of the process of differentiating work function metal in the GaAs FET of Example 2. FIG. 6 is a cross-sectional view of a transistor gate region in a direction parallel to the gate, showing a manufacturing step of the process of differentiating work function metal in the GaAs FET of Example 2. FIG. 7 is a cross-sectional view of a transistor gate region in a direction parallel to the gate, showing a manufacturing step of the process of differentiating work function metal in the GaAs FET of Example 3. FIG. 8 is a cross-sectional view of a transistor gate region in a direction parallel to the gate, showing a manufacturing step of the process of differentiating work function metal in the GaAs FET of Example 3. 10A to 10C are cross-sectional views of a gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of a process for forming separate work function metals in a GaAs FET of Example 3. FIG. 10B are cross-sectional views of a gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of a process for forming separate work function metals in a GaAs FET of Example 3. FIG. 10C are cross-sectional views of a gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of a process for forming separate work function metals in a GaAs FET of Example 3. FIG. 10D are cross-sectional views of a gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of a process for forming separate work function metals in a GaAs FET of Example 3.FIG. 10 is a flow diagram of the manufacturing process for separately fabricating work function metals in the GAA FET of Example 3.

[0018] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The present disclosure is not limited to the examples described below, and various modifications are possible within the scope of its technical concept. In all drawings used to explain the examples, components having the same function are designated by the same reference numerals, and repeated description of such components may be omitted. It goes without saying that many modifications are possible to the contents disclosed as the present examples, such as changing the combination of materials and manufacturing processes. The drawings are not necessarily drawn to scale, and important parts are depicted schematically to emphasize the logic. The drawings may be more schematic than the actual embodiment for clarity of explanation, but they are merely examples and do not limit the interpretation of the present disclosure.

[0019] In Example 1, a semiconductor device manufacturing method or plasma processing method for a GAA-type FET (Gate All Around Type Field Effect Transistor) serving as a semiconductor element included in a semiconductor device is described. In this process, even if an organic film mask used for patterning enters into gaps between stacked sheet-like channel layers, the organic film mask filling the gaps in the pattern opening region and the work function metal deposited on the channel can be removed without horizontally shifting the pattern boundary. Figures 1, 2A to 2F, 3A to 3D, 4, and 5 are used as figures for the above description. The semiconductor device manufacturing method or plasma processing method for plasma etching the work function control metal described in this example are process techniques for a transistor serving as a semiconductor element, which has thin wire-like or sheet-like channels stacked perpendicular to the substrate in the gate formation region, and which forms work function metals out of the gate insulating film and work function metal deposited on the channel, depending on the type of transistor, when the organic film mask used for patterning enters into the gaps between the stacked channels.

[0020] FIG. 1 is a bird's-eye view of a structure immediately before the process for forming the separate work function metals in the manufacturing process of a GAA FET. FIGS. 2A to 2F are cross-sectional views of the transistor's gate region (line AA' in FIG. 1) in a direction parallel to the gate, illustrating the process for forming the separate work function metals. FIGS. 3A to 3D are enlarged cross-sectional views of the transistor's gate region (line AA' in FIG. 1) in a direction parallel to the gate, illustrating details of the process for removing the work function metal deposited on the stacked channel in the pattern opening region during the separate work function metal forming process. FIG. 4 is an enlarged cross-sectional view of the transistor's gate region (line AA' in FIG. 1) in a direction parallel to the gate, illustrating the structure after forming a work function metal different from the work function metal and a gate buried metal after the separate work function metal forming process. FIG. 5 is a flow chart of the series of manufacturing steps shown in FIGS. 2A to 2F and 3A to 3D.

[0021] In FIG. 1 , a single-crystal semiconductor substrate 1 is partially processed into lines, and an element isolation (STI) insulating film (referred to as an STI insulating film) 2 constituting an element isolation region is formed between the lines. On the semiconductor substrate 1, multiple semiconductor channel layers 3, each oriented parallel to the line pattern and having a wire-like or sheet-like shape, are stacked. A gate insulating film 4 and a work function metal 5 are sequentially deposited on each channel layer 3. A transistor gate pattern is formed perpendicular to the line pattern. In the cross section of the gate, a gate sidewall inner spacer 6 is formed in a region sandwiched between the stacked channel layers 3 so as to contact the sidewall of the gate insulating film 4. A gate sidewall spacer 7 is formed in an upper region of the structure consisting of the stacked channel layers 3 so as to contact the sidewall of the gate insulating film 4. Similarly, in the gate cross section, a source / drain epitaxial layer 8 is formed so as to contact the sidewalls of the gate sidewall inner spacer 6 and the channel layer 3, and an interlayer insulating film 9 is formed on the source / drain epitaxial layer 8 so as to contact the sidewalls of the gate sidewall spacer 7. An organic film mask 10 is formed in the groove formed by the gate pattern and on the interlayer insulating film 9, and a hard mask 11 is deposited on the organic film mask 10. A photoresist 12 patterned in a direction perpendicular to the gate pattern is formed on the hard mask 11. Here, the organic film mask 10 can be formed so as to fill the gap between the gate insulating film 4 and the stacked channel layer 3 on which the work function metal 5 is deposited.

[0022] The semiconductor substrate 1 may be made of silicon (Si), for example. Alternatively, it may be a substrate in which silicon germanium (SiGe) is deposited on Si, or an SOI (Silicon-on-Insulator) substrate, which uses a laminate of an insulating film such as silicon dioxide (SiO2) and a Si layer on a Si substrate. The wire- or sheet-shaped laminated channel 3 is formed by forming a laminated film of alternating layers of Si and SiGe on the semiconductor substrate 1, patterning the laminated film using lithography, and then vertically etching a portion of the laminated film and the semiconductor substrate 1. For example, when using a laser using argon fluoride gas (ArF) as a light source for patterning, single patterning is used if the pattern period is, for example, 80 nm or more, and self-aligned double patterning (SADP) is used if the pattern period is 40 nm to 80 nm. Furthermore, if the pattern period is, for example, 20 nm or more and 40 nm or less, self-aligned quadruple patterning (SAQP) can be used. Furthermore, when extreme ultraviolet (EUV) exposure with a wavelength of 13.5 nm is performed, single exposure can be used if the pattern period is, for example, 40 nm or more. If the pattern period is, for example, 20 nm or more and 40 nm or less, SADP can be used. Using the above pattern, the SiGe / Si stacked film is etched vertically to the semiconductor substrate 1. As described below, after forming a gate pattern, the SiGe layer is selectively etched away relative to Si, thereby forming a channel layer 3 made of patterned Si in a multi-layered configuration. The number of layers of the Si channel layer 3 is determined in consideration of the transistor characteristics, and is preferably approximately two to six layers.The SiGe / Si stacked film is formed by chemical vapor deposition (CVD) or the like, using, for example, hydrogen-diluted monosilane (SiH4) or disilane (Si2H6) as the source gas for the Si film, and a mixed gas of hydrogen-diluted SiH4 or disilane Si2H6 or the like and germane (GeH4) or the like as the source gas for the SiGe film.

[0023] The STI insulating film 2 is formed by depositing an insulating film such as an SiO2 film, a silicon oxynitride film (SiON), or a silicon carbon oxide film (SiCO) by a CVD method or the like, and then etching back the STI insulating film 2 until the SiGe / Si stacked film is exposed.

[0024] The gate sidewall spacers 7 are formed on the sidewalls of a dummy gate (not shown). The dummy gate is formed by depositing a dummy gate insulating film made of SiO2 or a similar insulating film and amorphous Si or polycrystalline (poly) Si on the pattern made of the SiGe / Si stacked film and the STI insulating film 2, and then patterning the dummy gate insulating film into a periodic or similar line pattern oriented perpendicular to the SiGe / Si stacked film pattern. The patterning is performed using a single exposure method using the ArF light source or the SADP method, depending on the pattern period. The gate pattern size is preferably set, for example, to a gate pitch of 40 nm to 70 nm and a dummy gate width, i.e., gate length, in the range of 10 nm to 30 nm. A low-k film, such as a SiON film, silicon carbon oxynitride film (SiOCN), or SiCO film, is deposited on the patterned dummy gate using a CVD method or the like, and then anisotropically etched back using a dry etching device to obtain the gate sidewall spacers 7. The thickness of the gate sidewall spacer 7 is preferably adjusted to fall within the range of, for example, 5 nm to 15 nm.

[0025] The SiGe / Si stacked film is etched along the gate sidewall spacer 7 in a direction perpendicular to the semiconductor substrate 1, and the exposed sidewall of the SiGe layer is selectively etched by isotropic etching to form a groove in the groove, within which a gate sidewall inner spacer 6 is formed. A low-k film such as an SiON film, an SiOCN film, or an SiCO film is used as the material for the gate sidewall inner spacer 6, and after forming these films by a CVD method or the like, the gate sidewall inner spacer 6 can be formed only within the groove by isotropically etching a portion corresponding to the film thickness.

[0026] The source / drain epitaxial layer 8 is formed by selective epitaxial growth starting from the sidewall of the Si channel layer 3 exposed after the formation of the gate sidewall inner spacer 6. Different epitaxial layers are formed in the n-type transistor region and the p-type transistor region using masks and patterning. A Si layer doped with phosphorus (P) or arsenic (As) is preferably formed in the n-type transistor region, and a SiGe layer doped with boron (B) or the like is preferably formed in the p-type transistor region. The film formation is performed using a CVD method or the like, and a hydrogen-diluted gas containing phosphine (PH3) as the source gas for P, arsine (AsH3) as the source gas for As, and diborane (B2H6) as the source gas for B is preferably used.

[0027] The interlayer insulating film 9 is formed so as to fill the source / drain regions surrounded by the gate sidewall spacers 7 outside the gate region, and is preferably formed using a material such as an SiO2 film, an SiON film, or an SiOCN film, and using a CVD method or the like.

[0028] The laminated Si channel layer 3 is formed by removing the dummy gate and the dummy gate insulating film, and then removing the SiGe layer constituting the SiGe / Si laminated film. The dummy gate and dummy gate insulating film are removed by forming the interlayer insulating film 9, exposing the dummy gate using chemical mechanical polishing (CMP), and sequentially etching away the dummy gate and the dummy gate insulating film. Thereafter, selective etching of the SiGe layer is performed from the sidewall of the exposed SiGe layer, and only the SiGe layer is etched away, resulting in a structure in which the Si channel layer 3 is laminated.

[0029] The gate insulating film 4 and work function metal 5 deposited on the Si channel layer 3 are formed by, for example, CVD or atomic layer deposition (ALD). The gate insulating film 4 can be made of a high-dielectric material such as hafnium oxide (HfO2) or aluminum oxide (Al2O3), or a laminated film of these high-dielectric materials. The thickness of the gate insulating film 4 can be adjusted to, for example, a range of 1 nm to 2 nm. The work function metal 5 is determined taking into account the target transistor performance or transistor conductivity type. For example, the work function metal 5, which determines the threshold voltage of a p-type FET, can be made of titanium nitride (TiN), tantalum nitride (TaN), or a metal compound with a work function equivalent to these. The work function metal 5, which determines the threshold voltage of an n-type FET, can be made of, for example, titanium aluminum (TiAl), or a metal compound consisting of TiAl containing carbon (C), oxygen (O), nitrogen (N), or a metal compound with a work function equivalent to these. The work function metal 5 may be composed of a single film or multiple laminated films, and the total film thickness is adjusted in the range of 2 nm to 10 nm, for example. Here, after the work function metal 5 is formed, it is not necessary to fill the gaps between the laminated Si channel layers 3 with the work function metal 5.

[0030] After the gate insulating film 4 and work function metal 5 are deposited, an organic film mask 10 is formed to fill the gate region. The organic film mask 10 may be formed by coating a carbon-containing film such as a spin-on carbon film, or by depositing an amorphous carbon film using a CVD method or other method. If the organic film mask 10 is deposited using a CVD method, the surface may be planarized using a CMP method or other method. If gaps exist between the stacked Si channel layers 3, the organic film mask 10 fills the gaps. The hard mask 11 formed on the organic film mask 10 may be a spin-on-glass film formed by coating. The spin-on-glass film is preferably an organic film containing Si and oxygen. The hard mask 11 may also be an inorganic film, such as a metal oxide film such as titanium oxide (TiO2), deposited using a CVD method or other method. A photoresist 12 is deposited on the hard mask 11, and the resist is patterned using lithography to obtain the structure shown in Figure 1. The patterned photoresist is oriented in a direction perpendicular to the gate, and the boundary position of the pattern is preferably adjusted between the stacked Si channel layers 3 adjacent to each other in the horizontal direction.

[0031] FIG. 2A shows the bird's-eye view of FIG. 1 , viewed from a cross section of the transistor's gate region (line AA' in FIG. 1 ) in a direction parallel to the gate. While the figure shows a case where three Si channel layers 3 are stacked, the number of layers is not limited to three and can be any number. Furthermore, the gap between the Si stacked channel layers 3 in the direction perpendicular to the semiconductor substrate 1, which is filled with the organic film mask 10, is preferably designed to be approximately 1 to 6 nm. As shown in FIG. 2A , the semiconductor device has a gate region on the semiconductor substrate 1 where a gate is formed, and a semiconductor stack structure in which a sheet-like semiconductor layer or a wire-like semiconductor layer having a gate insulating film 4 and a work function control metal 5 on the surface is stacked within the gate region.

[0032] From the structure shown in FIG. 2A , vertical etching of the hard mask 11 is performed using the photoresist 12 as a mask, and then vertical etching of the organic film mask 10 is performed using the hard mask 11 as a mask, resulting in the structure shown in FIG. 2B . That is, the organic film mask 10 is anisotropically etched in a direction perpendicular to the semiconductor substrate 1 along the lithography pattern of the hard mask 11. In other words, the organic film mask 10, which is formed to cover the semiconductor stacked structure and fill the gaps between the stacked semiconductor layers, is anisotropically etched in a direction perpendicular to the semiconductor substrate 1. The hard mask 11 is etched by dry etching. When the hard mask 11 is made of a spin-on-glass film, the etching gas used may be, for example, a halogen-based gas containing carbon, such as tetrafluoromethane (CF 4 ) or octafluorocyclobutane (CF 4 F 8 ), or a mixed gas containing oxygen (O 2 ), nitrogen (N 2 ), argon (Ar), helium (He), or the like. If the hard mask 11 is made of a metal oxide film such as TiO2, a carbon-containing halogen-based gas such as CF4 or a mixed gas containing such a gas, such as Ar, may be used. The etching is performed under conditions that allow selective etching of the organic film mask 10. The organic film mask 10 is etched under conditions that allow selective etching of the hard mask 11, gate insulating film 4, work function metal 5, gate sidewall spacer 7, and interlayer insulating film 9. For example, if the organic film mask 10 is made of a carbon film deposited by a spin-on carbon film or CVD method, a mixed gas of O2 and N2, a mixed gas of O2 and hydrogen bromide (HBr), a mixed gas of N2 and hydrogen (H2), ammonia (NH3), or a mixed gas of any of these with Ar may be used. In the structure shown in Figure 2B, the gate insulating film 4 and work function metal 5 remain on the Si channel layer 3, and the organic film mask 10 remains in the gaps between the stacked Si channel layers 3. This step (first step) shown in FIG. 2B corresponds to hard mask / carbon mask vertical etching 101 in the process flow diagram shown in FIG.

[0033] Next, a protective insulating film 13 is deposited on the structure shown in FIG. 2B to obtain the structure shown in FIG. 2C. That is, the protective insulating film 13, which serves as a first insulating film, is deposited on the structure after etching, i.e., the structure including the work function control metal 5 in the region exposed by etching and the sidewall of the organic film mask 10 formed by etching. In other words, after the first step, the first insulating film 13 is deposited on the work function control metal 5 in the exposed region and on the sidewall of the organic film mask 10. The film formation is preferably performed using a CVD method or an ALD (Atomic Layer Deposition) method. The film formation is preferably performed under conditions that result in a uniform film thickness across the entire surface of the structure shown in FIG. 2B. Taking into consideration adhesion to the sidewall of the organic film mask 10, the material for the protective insulating film 13 is preferably an insulating film containing carbon or nitrogen, such as a silicon nitride film such as silicon nitride (Si3N4) film or a silicon carbonitride film such as silicon carbonitride (SiCN) film. The thickness of the protective insulating film 13 is controlled to, for example, approximately 2 nm to 3 nm. The condition for this thickness is that the trench in the gate formation region is not filled after film formation. For example, when the protective insulating film 10 is a Si3N4 film formed by the ALD method, the source gases used to form the protective insulating film 13 are, for example, bis(tert-butylamino)silane (BTBAS), bis(diethylamino)silane (BDEAS), or dichlorosilane (SiH2Cl2) as the Si source, and N2 gas, a mixed gas of N2 gas and hydrogen (H2), or a gas containing nitrogen, such as NH3 gas, as the nitrogen source. The Si3N4 film may also be formed by the CVD method, in which case source gases such as SiH4, NH3, or N2 are preferably used. When SiCN is used for the protective insulating film 13, the film may be formed by an ALD method using, for example, hexachlorodisilane (Si2Cl6) as the Si source and methylamine (CH3NH2) or the like as the carbon and nitrogen source, or by a CVD method using, as the source, a gas obtained by adding methane (CH4) and an inert gas such as Ar or He to SiH4 or tetrachlorosilane (SiCl4), and NH3 or N2.The ALD or CVD method may be a thermal ALD or thermal CVD method in which a source gas is decomposed on the surface of the semiconductor substrate by heat, or a plasma ALD or plasma CVD method in which thermal decomposition is performed by irradiating the semiconductor substrate with plasma. This step (second step) shown in Figure 2C corresponds to the protective insulating film deposition 102 in the process flow diagram shown in Figure 5, and may be performed continuously in the chamber of the same device following the hard mask / carbon mask vertical etching 101 shown in Figure 2B.

[0034] Next, the protective insulating film 13 is isotropically etched from the structure shown in FIG. 2C to obtain the structure shown in FIG. 2D. That is, the protective insulating film 13 is isotropically etched to remove the protective insulating film 13 deposited in the region other than the sidewall of the organic film mask 10. In other words, after the second step, the first insulating film 13 in the region other than the sidewall of the organic film mask 10 is isotropically etched away. This etching is performed under selective etching conditions for the hard mask 11 and the work function metal 5. For example, if the protective insulating film 13 is a SiN film, the etching gas may be CHF, difluoromethane (CHF), or fluoromethane (CHF), or a mixture of fluorocarbon gases such as CF or CF with H, or a gas equivalent thereto. For example, if the protective insulating film 13 is a SiCN film, the etching gas may be a mixture of a fluoride compound such as nitrogen trifluoride (NF) and an inert gas such as Ar, or a gas equivalent thereto. This etching is performed for a time 1 to 2 times the etching time required to etch the protective insulating film 13 by the thickness of the film, under conditions that remove the protective insulating film 13 deposited on the work function metal 5. However, because of its high adhesion to the organic film mask 10 material, the etching rate of the protective insulating film 13 on the sidewalls of the organic film mask 10 is slower than the etching rate of the protective insulating film 13 on the work function metal 5. Therefore, the etching time is adjusted so that the protective insulating film 13 deposited on the sidewalls of the organic film 10 remains after the etching. This etching results in a structure in which the sidewalls of the organic film mask 10 are protected by the protective insulating film 13 and the protective insulating film 13 deposited on the work function metal 5 has been removed. This step (third step) shown in FIG. 2D corresponds to the isotropic etching of the protective insulating film 103 in the process flow diagram shown in FIG. 5 and is preferably performed continuously in the same chamber as the protective insulating film deposition 102 shown in FIG. 2C.

[0035] The work function metal 5 is etched from the structure shown in FIG. 2D to obtain the structure shown in FIG. 2E. That is, after the third step, the work function control metal 5 exposed in areas other than the gaps between the stacked semiconductor layers is removed by plasma etching. As described below, the work function control metal 5 is removed by repeating a cycle process of isotropic etching and anisotropic etching one or more times to remove the work function control metal exposed in areas other than the gaps. This etching is performed under selective etching conditions for the hard mask 11, gate insulating film 4, and protective insulating film 13. For example, if the work function metal 5 is TiN or TaN, a mixture of Cl2, O2, and He, a mixture of Cl2 and Ar, or a mixture of CF4 and O2 may be used. When the work function metal 5 is composed of TiAl or TiAl containing C, O, N, etc., the etching gas used may be a mixture of CF4 and Cl2, a mixture of CF4 and hydrogen chloride (HCl), or a mixture of these gases with Ar, He, N2, etc. This etching is performed for a time 1 to 2 times longer than the etching time required to etch the work function metal 5 by its thickness, under conditions that remove the work function metal 5 deposited on the sidewalls of the gate insulating film 4. However, because the etching rate of the work function metal 5 decreases near the organic film mask 10 material that fills the gaps between the Si stacked channel layers 3, the work function metal 5 remains on the surface in contact with the organic film mask 10, resulting in a tapered shape after etching, as shown in Figure 2E. Because the thickness of the work function metal 5 is essentially zero in the region where the work function metal 5 contacts the organic film mask 10 and the protective insulating film 13, it is desirable to slightly expose the surface of the organic film mask 10 in this region. The above etching is mainly performed by isotropic etching, but in order to expose the organic film mask 10, a small amount of anisotropic etching may be added after the isotropic etching, or a cycle process in which isotropic etching and anisotropic etching are repeated may be used.During this etching, the work function metal 5 exposed below the region covered with the hard mask 11 is in contact with the organic film mask 10, so etching does not proceed in the horizontal direction, and the work function metal 5 can maintain almost its pre-etching state. This step (fourth step) shown in Figure 2E corresponds to work function control metal film etching 104 in the process flow diagram shown in Figure 5, and is preferably performed continuously in the chamber of the same device following the protective insulating film isotropic etching 103 shown in Figure 2D.

[0036] From the structure shown in FIG. 2E, the organic film mask 10 embedded between the Si stacked channel 3 is etched and removed, resulting in the structure shown in FIG. 2F. That is, after the fourth process, the organic film mask 10 exposed in the fourth process is removed by etching. This etching is performed under selective etching conditions for the hard mask 11 and the gate insulating film 4. When the organic film mask 10 is a spin-on carbon film or an amorphous carbon film formed by CVD, the etching gas may be, for example, a mixture of O2 and N2, a mixture of N2 and H2, or NH3 gas. In the structure shown in FIG. 2E, this etching proceeds from the slightly exposed surface of the organic film mask 10 in the area where the work function metal 5, the organic film mask 10, and the protective insulating film 13 contact each other. Plasma conditions are adjusted to facilitate horizontal etching so that the organic film mask 10 embedded in a narrow area is etched away. During this etching, the organic film mask 10 directly below the hard mask 11 is protected by the protective insulating film 13 covering the sidewalls of the organic film mask 10 and is therefore not affected by this etching. Meanwhile, the protective insulating film 13 in contact with the organic film mask 10 in the region not covered by the hard mask 11 is simultaneously removed by lift-off when the organic film mask 10 is etched away. After this etching, a structure is obtained in which the work function metal 5 is present only on the top and bottom surfaces of the Si stacked channel 3 in the region not covered by the hard mask 11. This step (the fifth step) shown in FIG. 2F corresponds to the carbon mask etching 105 in the process flow diagram shown in FIG. 5 and is preferably performed consecutively in the chamber of the same apparatus following the work function control metal film etching 104 shown in FIG. 2E.

[0037] Next, the work function metal 5 is etched from the structure shown in FIG. 2F to obtain the structure shown in FIG. 2G. That is, the work function control metal 5 present in the gaps between the stacked semiconductor layers 3, exposed in the fifth step, is removed by isotropic etching. In other words, after the fifth step, the work function control metal 5 in the gaps between the semiconductor layers is removed by isotropic etching. This etching is performed under selective etching conditions for the hard mask 11, gate insulating film 4, and protective insulating film 13. The etching conditions are isotropic, and the process conditions, such as the gas used, are preferably approximately the same as those used in FIG. 2E. This etching is performed for a time 1 to 2 times the etching time required to etch the work function metal 5 by the film thickness, under conditions that completely remove the work function metal 5 deposited on the gate insulating film 4. During this etching, the work function metal 5 exposed below the area covered by the hard mask 11 is in contact with the organic film mask 10, so etching does not proceed horizontally, allowing the work function metal 5 to maintain its pre-etching state. This step (sixth step) shown in Fig. 2G corresponds to the work function controlled metal film isotropic etching 106 in the process flow diagram shown in Fig. 5, and is preferably performed consecutively in the chamber of the same apparatus following the carbon mask etching 105 shown in Fig. 2F. In other words, it is preferable to perform the first step to the sixth step consecutively in the same plasma processing apparatus that forms a semiconductor device by plasma processing.

[0038] 3A to 3D are diagrams illustrating in detail the process of removing the organic film mask 10 embedded between the work function metal 5 and the Si stacked channel 3 shown in FIGS. 2E to 2G, including the flow of etching gas.

[0039] FIG. 3A is an enlarged view of a region 15-1 not covered by the hard mask 11 and a region 15-2 covered by the hard mask 11 in FIG. 2E after etching the work function metal 5 shown in FIG. 2E. In the region 15-1, the work function metal 5 has already been removed from the sidewalls of the Si stacked channel layer 3. Therefore, the work function metal 5 remaining on the upper and lower surfaces of the Si stacked channel layer 3 is exposed to ionized or radicalized etching gas 14 from the vertical and horizontal directions of the semiconductor substrate 1. As a result, the work function metal 5 has a tapered shape, and in the region where the work function metal 5 contacts the organic film mask 10 and the protective insulating film 13, there are locations where the effective film thickness of the work function metal 5 is almost zero. On the other hand, in the region 15-2 covered by the hard mask 11, the etching gas 14 reaches the work function metal 5 only from the horizontal direction of the semiconductor substrate 1. In addition, due to the strong adhesion between the work function metal 5 and the organic film mask 10, horizontal etching of the work function metal 5 hardly progresses in the region 15-2.

[0040] After the process shown in FIG. 3A , further etching of the work function metal 5 results in the structure shown in FIG. 3B . In region 15-1, the work function metal 5 is exposed to the etching gas 14 from multiple directions, so that etching of the work function metal 5 progresses from the region farthest from the organic film mask 10, resulting in a gentler taper angle of the work function metal 5 as shown in region 15-1 of FIG. 3B . This makes it easier to expose the surface of the organic film mask 10. On the other hand, in region 15-2, the etching gas 14 reaching the work function metal 5 is still limited to only the horizontal direction of the semiconductor substrate 1, so that etching of the work function metal 5 in the horizontal direction hardly progresses.

[0041] Next, the organic film mask 10 is etched away to obtain the structure shown in FIG. 3C. In region 15-1, as the organic film mask 10 is etched away, the protective insulating film 13 remaining on the sidewalls of the organic film mask 10 is removed together with the organic film mask 10 by lift-off. To further ensure the removability of the protective insulating film 13 when etching the organic film mask 10, an additional etching step for the protective insulating film 13 may be performed. In this case, the same etching conditions as those used in the step shown in FIG. 2D may be used.

[0042] Following the structure of FIG. 3C, the work function metal 5 is isotropically etched again to obtain the structure shown in FIG. 3D and FIG. 2G.

[0043] 2E to 2G, 3A to 3D, and 5 show an example in which the work function control metal film etching 104 and the carbon mask etching 105 in FIG. 5 are each performed once to remove the organic film mask 10 buried between the Si stacked channels 3. However, a cycle process in which the work function control metal film etching 104 and the carbon mask etching 105 are repeated multiple times may also be applied. In other words, it is preferable to apply a cycle process in which the fourth step (work function control metal film etching 104) and the fifth step (carbon mask etching 105) are repeated two or more times. Applying the cycle process improves the removability of the organic film mask 10 buried between the Si stacked channels 3.

[0044] In the embodiment shown in FIGS. 2A to 2G, the gate insulating film 4 is exposed after the work function metal 5 is removed. However, the work function metal 5 may be made up of a plurality of work function metals, and the process may involve removing the upper work function metal and leaving the lower work function metal.

[0045] By carrying out the process consisting of the successive steps shown in Figures 2A to 2G, in the process of forming the work function metal 5 formed on the stacked wire-shaped or sheet-shaped Si channel layers 3 of a GAA type FET depending on the type of transistor, even in a state where the organic film mask 10 remains between the stacked Si channel layers 3, the organic film mask 10 and the work function metal 5 can be removed at the pattern opening without changing the position of the organic film mask 10 at the pattern boundary, and it becomes possible to alleviate restrictions on reducing the gate length compared to a process in which the gap between the stacked Si channel layers 3 is filled with a sacrificial layer.

[0046] After the process shown in FIG. 2G , the hard mask 11 is removed by wet etching or dry etching, and then the organic film mask 10 is removed by ashing, for example, in an oxygen plasma atmosphere. The protective insulating film 13 on the sidewall of the organic film mask 10 is also removed simultaneously with the removal of the organic film mask 10. However, a separate etching process for the protective insulating film 13 may be performed. After this, a second work function metal 15 made of a material different from the work function metal 5 is deposited on the entire surface, followed by a buried metal layer 16 for burying the gate, resulting in the structure shown in FIG. 4 . In the structure shown in FIG. 4 , one transistor has a stacked structure in which the gate insulating film 4, work function metal 5, and second work function metal 15 are deposited on the Si channel layer 3, while the other transistor has a stacked structure in which the gate insulating film 4 and second work function metal 15 are deposited on the Si channel layer 3. By forming the work function metal 5 and the second work function metal 15 from materials with different work functions, it is possible to achieve optimized threshold voltages for each transistor. For example, when TiN or TaN, which lowers the threshold of a p-type transistor, or a metal compound having an equivalent work function, or a laminate film of these, is used as work function metal 5, TiAl, which lowers the threshold of an n-type transistor, or a metal compound made of a metal in which TiAl contains C, O, N, etc., or a metal compound having an equivalent work function, may be used as second work function metal 15.

[0047] By using a plasma processing apparatus equipped with an ALD film formation function or a CVD film formation function and anisotropic and isotropic etching control functions, it is possible to continuously perform the integrated process from hard mask / carbon mask vertical etching 101 (FIG. 2B) to work function controlled metal film isotropic etching 106 (FIG. 2G) in Fig. 5 within the same plasma processing apparatus. The plasma processing apparatus may be any of an etching apparatus using inductively coupled plasma (ICP), an etching apparatus using capacitively coupled plasma (CCP), and an etching apparatus using microwave electron cyclotron resonance (ECR) plasma.

[0048] As an example, Figure 6 shows the configuration of a plasma processing apparatus 200 using microwave ECR plasma. The plasma processing apparatus 200 has a processing chamber 201, which is connected to a vacuum exhaust system (not shown) via a vacuum exhaust port 202. During plasma processing, the processing chamber 201 is maintained at a vacuum of approximately 0.1 Pa to 10 Pa. The processing chamber 201 also has a window 203 that allows microwaves to pass through and hermetically seals the processing chamber 201, and a perforated plate 204 for blocking ions. The perforated plate 204 divides the processing chamber 201 into an upper section 201A and a lower section 201B. The window 203 is made of a material that transmits microwaves, such as a dielectric material such as quartz. The porous plate 204 has a plurality of holes, and is preferably made of a dielectric material such as quartz or alumina.

[0049] The gas supply mechanism includes a gas source 205, a gas supply device 206, and a gas inlet 207, and supplies raw gases for plasma processing. The gas source 205 contains multiple gases required for processing. The gas supply device 206 includes a control valve for controlling gas supply and cutoff, and a mass flow controller for controlling the gas flow rate. The gas inlet 207 is provided between the window portion 203 and the porous plate 204.

[0050] A waveguide 209 for propagating electromagnetic waves is connected to the top of the processing chamber 201, and a plasma-generating high-frequency power supply 208, which is a high-frequency power supply, is connected to one end of the waveguide 209. The plasma-generating high-frequency power supply 208 is a power supply for generating electromagnetic waves for plasma generation. For example, microwaves with a frequency of 2.45 GHz are used as the electromagnetic waves. The microwaves generated from the plasma-generating high-frequency power supply 208 propagate through the waveguide 209 and enter the processing chamber 201. The waveguide 209 includes a vertical waveguide extending vertically and a waveguide converter that also functions as a corner that bends the microwave direction by 90 degrees, so that the microwaves enter the processing chamber 201 perpendicularly. The microwaves propagate vertically within the processing chamber 201 via the window 203. A magnetic field generating coil 210 arranged on the outer periphery of the processing chamber 201 forms a magnetic field in the processing chamber 201. The microwaves generated from the plasma generating high frequency power supply 208 interact with the magnetic field generated by the magnetic field generating coil 210 to generate high density plasma within the processing chamber 201 .

[0051] A sample stage 212 is disposed below the processing chamber 201, facing the window 203. The sample stage 212 is made of, for example, aluminum or titanium. A semiconductor substrate 211 (corresponding to the semiconductor substrate 1) serving as a sample is placed on and held by the sample stage 212. The central axes of the waveguide 209, processing chamber 201, sample stage 212, and semiconductor substrate 211 are aligned. An electrode for electrostatically adsorbing the semiconductor substrate 211 is provided inside the sample stage 212, and the semiconductor substrate 211 is electrostatically adsorbed to the sample stage 212 by applying a DC voltage. A high-frequency voltage is applied to the sample stage 212 from a high-frequency bias power supply 213 to control the isotropy and anisotropy of etching. The frequency of the applied high-frequency bias may be, for example, 400 kHz.

[0052] Each mechanism of the plasma processing apparatus 200 is controlled by a control signal 221 from a control unit 220. The control unit 220 controls each mechanism by instructing each mechanism to perform a predetermined operation using the control signal 221 according to the processing conditions (anisotropic etching, isotropic etching, ALD film formation, etc.) to be executed by the plasma processing apparatus 200. The control unit 220 controls, for example, the plasma generation high-frequency power supply 208 to control the ON / OFF of electromagnetic waves for plasma generation. The control unit 220 also controls a gas supply mechanism to adjust the type and flow rate of gas introduced into the processing chamber 201. The control unit 220 also controls a high-frequency bias power supply 213 to control the intensity of the high-frequency voltage applied to a semiconductor substrate 211 on a sample stage 212.

[0053] When anisotropic etching is performed using this plasma processing apparatus 200, the control unit 220 controls the magnetic field generating coil 210 so that plasma is generated in the lower part 201B of the processing chamber 201 below the porous plate 204. Because the porous plate 204 is made of a dielectric material, microwaves pass through the porous plate 204 and interact with the magnetic field in the lower part 201B of the processing chamber 201 to generate plasma. Furthermore, a high-frequency bias is applied to the sample stage 212 on which the Si substrate 1 serving as the semiconductor substrate 211 is placed. This allows ions in the plasma to be attracted to the semiconductor substrate 211 without being blocked by the porous plate 204 or the like, enabling anisotropic etching that maintains perpendicularity.

[0054] When isotropic etching is performed using this plasma processing apparatus 200, the control unit 220 controls the magnetic field generating coil 210 so that the plasma generation position is in the upper part 201A of the processing chamber 201 above the porous plate 204. Since ions in the plasma generated in the upper part 201A of the processing chamber 201 are blocked by the porous plate 204, only radicals in the plasma are supplied to the lower part 201B of the processing chamber 201. This enables isotropic etching using radicals.

[0055] When forming a film by the ALD method using the plasma processing apparatus 200, the following cycle process controlled by the control unit 220 can be applied. For example, when forming a SiN film by the ALD method, the Si source BTBAS or BDEAS, or the gaseous SiHCl, is used. When using the liquid source BTBAS or BDEAS, the liquid source is vaporized and sent to the gas line as a gas. The gaseous source is sent into the processing chamber 201 along with the carrier gas Ar and adsorbed onto the substrate surface as a Si precursor. Unnecessary precursors are then evacuated from the processing chamber 201 using a purge gas such as Ar. Next, nitrogen-containing gases such as N2 gas, a mixture of N2 gas and H2 gas, or NH3 gas are introduced into the processing chamber 201 to generate plasma and react with the substrate surface. After this, an inert gas such as Ar is again introduced into the processing chamber 201 to purge the processing chamber 201, and unnecessary gases are evacuated from the processing chamber 201. This series of processes, in principle, deposits a Si3N4 film with an atomic layer thickness on the substrate surface. By repeating this series of processes (performing a cycle process), a thin insulating film can be formed by the ALD method. For example, when forming an Al2O3 film by the ALD method, Al(CH3)3 is used as the Al precursor, and vaporized H2O is used as the oxygen source, and the same cycle process as for Si3N4 is performed to form the Al2O3 film.

[0056] In the second embodiment, a method is provided in the process of replacing the work function metal 5 in the first embodiment, in which the protective insulating film 13 is a laminated film made up of two or more different films.

[0057] 7A and 7B show the steps and structure when the protective insulating film 13 is formed from a plurality of laminated films (312, 313) in the film formation step (FIG. 2C) and the isotropic etching step (FIG. 2D) of the protective insulating film 13 shown in FIGS. 2C and 2D of Example 1. The plurality of films (312, 313) constituting the protective insulating film (first insulating film) 13 are made of a plurality of types of films made of different materials.

[0058] 2B in Example 1, the hard mask 311 and the organic film mask 310 are vertically etched, and a first protective insulating film 312 and a second protective insulating film 313 are sequentially formed on the resulting structure, resulting in the structure shown in FIG. 7A. That is, the protective insulating film 13, which is the first insulating film, is composed of the first protective insulating film 312 as a lower insulating film in contact with the gate insulating film 304, and the second protective insulating film 313 as an upper insulating film formed above the lower insulating film 312. For example, the first protective insulating film 312 may be made of a SiN or SiCN film, which has good adhesion to the organic film mask 310 made of carbon, and the second protective insulating film 313 may be made of a film such as SiO (SiO film), which can maintain high etching selectivity when etching the work function metal 305. For example, if the first protective insulating film 312 is a SiCN film formed using plasma CVD, a gas mixture of SiH4 or SiCl4 and NH3 or N2 with CH4, Ar, He, or the like is preferably used as the source gas. In this case, due to the effect of plasma irradiation, the thickness of the first protective insulating film 312 is thick in the direction perpendicular to the semiconductor substrate 301 and thins on the sidewalls of structures such as the patterned organic film mask 310. If the second protective insulating film is a SiO2 film formed using plasma CVD, a gas mixture of SiH4 or SiCl4 and O2 or CO2 with H2, Ar, He, or the like is preferably used as the source gas. Compared to a SiCN film, a SiO2 film can be formed isotropically (conformally). The combined thickness of the first protective insulating film 312 and the second protective insulating film 313 is preferably adjusted to 2 to 4 nm along the sidewalls of the organic film mask 310. The condition is that, after the deposition of the second protective insulating film 313, the groove in the gate formation region is not filled with the first protective insulating film 312 and the second protective insulating film 313. When the first protective insulating film 312 and the second protective insulating film 313 are deposited by plasma CVD or plasma ALD, the adhesion between the organic film mask 310 and the first protective insulating film 312 and the second protective insulating film 313 increases due to the influence of plasma energy during film deposition, and the etching rate of the second protective insulating film 313 on the organic film mask 310 also decreases significantly.

[0059] The structure shown in FIG. 7A is subjected to isotropic etching of the second protective insulating film 313 and the first protective insulating film 312 to obtain the structure shown in FIG. 7B. For example, if the second protective insulating film 313 is made of a SiO2 film, the etching gas for the second protective insulating film 313 may be a gas such as CF4 or C4F8, or a mixed gas of these gases with CH3F, H2, Ar, or similar gases. For example, if the first protective insulating film 312 is made of a SiCN film, the etching gas for the first protective insulating film 312 may be a mixed gas of a fluoride compound such as NF3 and an inert gas such as Ar, or similar gases. Here, because the adhesion of the second protective insulating film 313 to the organic film mask 310 is enhanced via the first protective insulating film 312, the second protective insulating film 313 remains on the sidewalls of the organic film mask 310 even after etching the second protective insulating film 313 and the first protective insulating film 312. During the subsequent etching of the work function metal 305, the second protective insulating film 313, which can maintain a selectivity against the etching, remains on the sidewall of the organic film mask 310, thereby reducing etching damage to the organic film mask 310 during the etching of the work function metal 305, and further reducing the possibility of etching the organic film mask 310. Furthermore, by using a material for the first protective insulating film 312 that has a higher film formation rate on the organic film mask 310 than that for the second protective insulating film 313, the top of the organic film mask 310 can be more reliably protected by the first protective insulating film 312 and the second protective insulating film 313.

[0060] From the structure shown in FIG. 7B, the steps from work function control metal film etching 104 to work function control metal film isotropic etching 106 shown in FIG. 5 of Example 1 are performed to obtain the structure shown in FIG. 2G of Example 1.

[0061] In the third embodiment, a method is provided in which, in the work function metal 5 replacement process in the first embodiment, a protective insulating film 13 is deposited and etched, the work function metal 5 is etched, and then a process of depositing and etching a second protective insulating film as a second insulating film is added.

[0062] 8A to 8F show a method of adding a film formation process and an isotropic etching process of a second protective insulating film 413 as a second insulating film to the structure in which the work function metal 5 is etched, as shown in FIG. 2E of Example 1, and FIG. 9 shows a flow chart of the manufacturing process.

[0063] 8A shows the structure after the first protective insulating film 412 is deposited and etched and the work function metal 405 is etched, similar to FIG. 2E in Example 1. This process corresponds to work function control metal film etching-1 504 in FIG. 9. Note that the process flow shown in FIG. 9 from hard mask / carbon mask vertical etching 501 to work function control metal film etching-1 504 is the same as the hard mask / carbon mask vertical etching 101 to work function control metal film etching 104 in FIG. 5 in Example 1, and it is preferable that the hard mask / carbon mask vertical etching 501 to work function control metal film etching-1 504 in FIG. 9 be performed continuously in the chamber of the same apparatus.

[0064] Next, a second protective insulating film 413 is formed using CVD or ALD to obtain the structure shown in FIG. 8B . That is, after the fourth process, the second protective insulating film 413 is formed as the second insulating film. Here, the first protective insulating film 412 is preferably a SiN, SiCN, or equivalent film that has good adhesion to the organic film mask 410, and the second protective insulating film 413 is preferably a film such as SiO (SiO) that can maintain high etching selectivity during etching of the work function metal 405. For example, if the second protective insulating film 413 is a SiO film and is formed by plasma CVD, a mixed gas containing SiH or SiCl, and gases such as O or CO, plus H, Ar, or He is preferably used as the source gas. The thickness of the second protective insulating film 413 is preferably set to be equal to or less than the thickness of the work function metal 405. That is, when the film thickness of the work function metal 405 is set to 2 to 4 nm, the film thickness of the second protective insulating film 413 is preferably set to approximately 1 to 3 nm. Furthermore, it is desirable to adjust the total film thickness of the first protective insulating film 412 and the second protective insulating film 413 to 2 to 4 nm in the sidewall direction of the organic film mask 410. After the second protective insulating film 413 is formed, the groove in the gate formation region must not be filled with the first protective insulating film 412 and the second protective insulating film 413. By this film formation, in the region covered with the hard mask 411, the overhang region formed by the first protective insulating film 412 and the work function metal 405 is filled with the second protective insulating film 413. This process (the seventh process) shown in FIG. 8B corresponds to the second protective insulating film deposition 505 in the process flow diagram shown in FIG. 9 and is preferably performed continuously in the same chamber as the work function control metal film etching-1 504 shown in FIG. 8A.

[0065] The second protective insulating film 413 is isotropically etched from the structure shown in FIG. 8B to obtain the structure shown in FIG. 8C. Specifically, the second protective insulating film 413 is isotropically etched to remove the second protective insulating film 413 deposited on the region other than the sidewall of the organic film mask 410. In other words, the second protective insulating film 413 deposited on the region other than the sidewall of the organic film mask 410 is isotropically etched. This etching is performed under selective etching conditions for the hard mask 411, the work function metal 405, and the gate insulating film 404. For example, if the second protective insulating film 413 is made of SiO2, gases such as CF4 and C4F8, or mixtures of these gases with CH3F, H2, Ar, or similar gases, may be used. To ensure etching selectivity with the gate insulating film 404 made of a high-k film such as HfO2, the plasma etching conditions and gas flow rates may be adjusted. This etching is performed for a time that is one to two times the etching time required to etch the second protective insulating film 413 by the thickness thereof, under conditions that allow the protective insulating film 413 deposited on the sidewalls of the gate insulating film 404 to be removed. As shown in Example 2, when the first protective insulating film 412 and the second protective insulating film 413 are sufficiently thin and are formed by a plasma ALD method or a plasma CVD method, the adhesion between the second protective insulating film 413 and the organic film mask 410 is also increased via the first protective insulating film 412. Therefore, after the second protective insulating film 413 is etched and removed, as shown in FIG. 8C , the second protective insulating film 413 remains on the first protective insulating film 412. Furthermore, after this etching, the second protective insulating film 413 that fills the overhang region formed by the first protective insulating film 412 and the work function metal 405 also remains in the region covered by the hard mask 411. This step (eighth step) shown in FIG. 8C corresponds to second protective insulating film isotropic etching 506 in the process flow diagram shown in FIG. 9, and may be performed continuously in the chamber of the same apparatus following second protective insulating film deposition 505 shown in FIG. 8B.

[0066] Next, the work function metal 405 is etched from the structure shown in FIG. 8C to obtain the structure shown in FIG. 8D . Similar to the process shown in FIG. 3B of Example 1, etching of the work function metal 405 proceeds from the region farthest from the organic film mask 410. As shown in FIG. 8D , the taper angle of the work function metal 405 becomes gentler, and the surface of the organic film mask 410 becomes more easily exposed. In this process, the overhanging region formed by the first protective insulating film 412 and the work function metal 405 in the region covered by the hard mask 411 is filled with the second protective insulating film 413, so that the sidewalls of the work function metal 405 below the region covered by the hard mask 411 are protected by the second protective insulating film 413. Therefore, this process suppresses horizontal etching of the work function metal 405 in the region covered by the hard mask 411. In addition, in this step, the second protective insulating film 413 covers the first protective insulating film 412, thereby reducing the risk of exposing the organic film mask 410 in the region covered with the hard mask 411. This step (ninth step) shown in Fig. 8D corresponds to work function controlled metal film etching-2 507 in the process flow diagram shown in Fig. 9, and may be performed continuously in the chamber of the same apparatus following the second protective insulating film isotropic etching 506 shown in Fig. 8C.

[0067] From the structure shown in FIG. 8D , the organic film mask 410 embedded between the Si stacked channels 403 is etched and removed to obtain the structure shown in FIG. 8E . This etching is preferably performed under conditions equivalent to those of the process shown in FIG. 2F in Example 1. In this process, the organic film mask 410 below the region covered by the hard mask 411 is covered with the second protective insulating film 413, thereby reducing the risk of etching the organic film mask 410 below the region covered by the hard mask 411. This process (the 10th process) shown in FIG. 8E corresponds to the carbon mask etching 508 in the process flow diagram shown in FIG. 9 , and is preferably performed consecutively in the chamber of the same apparatus following the work function control metal film etching-2 507 shown in FIG. 8D .

[0068] The work function metal 405 is etched from the structure shown in FIG. 8E to obtain the structure shown in FIG. 8F. This etching is preferably performed under conditions equivalent to those of the process shown in FIG. 2G in Example 1. In this process, the sidewalls of the work function metal 405 under the region covered by the hard mask 411 are protected by the second protective insulating film 413, thereby reducing the risk of etching the work function metal 405 under the region. This process (the eleventh process) shown in FIG. 8E corresponds to the work function control metal film isotropic etching 509 in the process flow diagram shown in FIG. 9, and is preferably performed continuously in the same chamber as the carbon mask etching 508 shown in FIG. 8E.

[0069] 1, 301, 401: semiconductor substrate, 2, 302, 402: shallow trench isolation (STI) insulating film, 3, 303, 403: Si stacked channel, 4, 304, 404: high-k gate insulating film, 5, 305, 405: work function control metal (work function metal), 6: inner spacer, 7: gate sidewall spacer, 8: source / drain epitaxial layer, 9: interlayer insulating film, 10, 310, 410: organic film mask, 11, 311, 411: hard mask, 12: photoresist, 13: protective insulating film, 14: etching gas irradiation path during work function metal etching, 15: second work function metal, 16: gate buried metal, 312, 412: first protective insulating film, 313, 413: second protective insulating film, 101, 501: Hard mask / carbon mask vertical etching step, 102: Protective insulating film deposition step, 502: First protective insulating film deposition step, 103: Protective insulating film isotropic etching step, 503: First protective insulating film isotropic etching step, 104: Work function controlled metal film etching step, 504: Work function controlled metal film etching-1 step, 105: Carbon mask etching step, 106: Work function controlled metal film isotropic etching, 505: Second protective insulating film deposition step, 506: Second protective insulating film isotropic etching step, 507: Work function controlled metal film Metal film etching-2 step, 508: carbon mask etching step, 509: work function controlled metal film isotropic etching step, 201: processing chamber, 201A: upper region of processing chamber, 201B: lower region of processing chamber, 202: vacuum exhaust port, 203: window, 204: perforated plate, 205: gas source, 206: gas supply device, 207: gas inlet, 208: high frequency power supply for plasma generation, 209: waveguide, 210: magnetic field generating coil, 211: semiconductor substrate, 212: sample stage, 213: high frequency bias power supply, 220: control unit, 221: control signal

Claims

1. A method for manufacturing a semiconductor device having a gate region on a semiconductor substrate where a gate is formed, and a semiconductor laminate structure in which sheet-like semiconductor layers or wire-like semiconductor layers having a gate insulating film and a work function control metal deposited on a surface thereof are laminated within the gate region, the method comprising: a first step of etching an organic film mask formed so as to cover the semiconductor laminate structure and filling gaps between the laminated semiconductor layers in a direction perpendicular to the semiconductor substrate; a second step of depositing, after the first step, the work function control metal in exposed regions and a first insulating film on side walls of the organic film mask; a third step of removing, after the second step, the first insulating film in regions other than the side walls of the organic film mask by isotropic etching; a fourth step of removing, after the third step, the work function control metal exposed in locations other than the gaps; a fifth step of removing the exposed organic film mask after the fourth step; and a sixth step of removing, after the fifth step, the work function control metal in the gaps by isotropic etching.

2. A method for manufacturing a semiconductor device according to claim 1, wherein the first to sixth steps are carried out consecutively in the same plasma processing apparatus that forms the semiconductor device by plasma processing.

3. A method for manufacturing a semiconductor device according to claim 1, wherein the first insulating film is a silicon nitride film or a silicon carbonitride film.

4. A method for manufacturing a semiconductor device according to claim 1, wherein the fourth step is to remove the work function control metal exposed in areas other than the gap by repeating a cycle process of isotropic etching and anisotropic etching one or more times.

5. The method of manufacturing a semiconductor device according to claim 1, wherein the fourth step and the fifth step are repeated two or more times.

6. A method for manufacturing a semiconductor device according to claim 1, wherein the first insulating film is made of a plurality of types of films made of different materials.

7. A method for manufacturing a semiconductor device according to claim 6, wherein the first insulating film is composed of a lower insulating film in contact with the gate insulating film and an upper insulating film formed above the lower insulating film, the lower insulating film being a silicon nitride film or a silicon carbonitride film, and the upper insulating film being a silicon oxide film.

8. A method for manufacturing a semiconductor device according to claim 1, further comprising, after the fourth step, a seventh step of forming a second insulating film, and an eighth step of removing the second insulating film deposited on areas other than the sidewalls of the organic film mask by isotropic etching.

9. A method for manufacturing a semiconductor device according to claim 8, wherein the first insulating film in contact with the gate insulating film is a silicon nitride film or a silicon carbonitride film, and the second insulating film is a silicon oxide film.

10. A plasma processing method for plasma etching a work function control metal in a semiconductor laminate structure having a gate region on a semiconductor substrate where a gate is formed, the semiconductor laminate structure having sheet-like semiconductor layers or wire-like semiconductor layers on the surface of which a gate insulating film and a work function control metal are formed and laminated in the gate region, the method comprising: a first step of etching an organic film mask formed so as to cover the semiconductor laminate structure and filling gaps between the laminated semiconductor layers in a direction perpendicular to the semiconductor substrate; a second step of depositing, after the first step, the work function control metal in exposed regions and a first insulating film on side walls of the organic film mask; a third step of removing, after the second step, the first insulating film in regions other than the side walls of the organic film mask by isotropic etching; a fourth step of removing the work function control metal exposed in locations other than the gaps after the third step; and a fifth step of removing the exposed organic film mask after the fourth step. a sixth step of removing the work function control metal in the gap by isotropic etching after the fifth step.