Semiconductor device having channel layers with different thicknesses for improved performance and method of manufacturing thereof
The gate-all-around transistor structure with strategically positioned source/drain contacts and varying channel thicknesses addresses the incomplete gate coverage issue, enhancing conductivity and reducing short-channel effects in semiconductor devices.
KR1020260113974APending Publication Date: 2026-07-21TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information
- Authority / Receiving Office
- KR · KR
- Patent Type
- Applications
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2026-01-06
- Publication Date
- 2026-07-21
AI Technical Summary
Technical Problem
As semiconductor devices shrink to nanometer-scale technology nodes, gate control in transistors like FinFETs and GAA-FETs becomes less effective due to incomplete coverage of the channel's surfaces, leading to short-channel effects and drain-induced barrier degradation.
Method used
A gate-all-around transistor structure is designed with source/drain contacts formed below the channel layers, featuring varying channel thicknesses and a heavily doped region to enhance conductivity and reduce short-channel effects and drain-induced barrier lowering.
Benefits of technology
This configuration increases source/drain conductivity, reduces ohmic loss, and mitigates short-channel effects and drain-induced barrier degradation, improving device performance.
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Figure PAT00001_ABST
Abstract
A method for manufacturing a semiconductor device comprises the steps of alternately depositing a sacrificial layer and a channel layer on a substrate, such that a second channel layer below a first channel layer is thinner than the first channel layer; patterning a semiconductor stack to form a fin; resetting the fin to form a source / drain opening; and epitaxially depositing a semiconductor material within the source / drain opening to form a source / drain structure. The method comprises the steps of removing the sacrificial layer so that the surface of the channel layer is exposed; depositing a gate dielectric on the surface of the channel layer to form a gate electrode surrounding the channel layer and depositing a conductive material on the gate dielectric; and depositing an electrically conductive material on the source / drain structure within the source / drain opening to form a source / drain contact having a bottom surface lower than the bottom surface of the first channel layer.
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