Display device and electronic device including the same

Abstract

Embodiments of the present disclosure may provide a display device comprising a first metal layer and a second metal layer positioned perpendicularly to the first metal layer, clock lines to which a clock signal is input, side signal lines including a first metal layer positioned adjacent to the clock lines in a first direction and extending in a second direction, and stage circuits positioned adjacent to the side signal lines in a first direction and connected to the clock lines and the side signal lines, wherein at least one of the clock lines is folded at least once in a third direction opposite to the first direction in an opening where at least a portion of the first metal layer is removed. According to the display device and the electronic device including the same according to the embodiments of the present disclosure, visibility can be improved and images can be displayed at various refresh frame rates, while providing a narrow bezel.

Description

Technology Field

[0001] The embodiments of the present disclosure relate to a display device and an electronic device including the same. Background Technology

[0002] With the advancement of information technology, the importance of display devices, which serve as a medium connecting users and information, is being highlighted. In response to this, the use of display devices such as Liquid Crystal Displays (LCDs) and Organic Light Emitting Displays (OLEDs) is increasing.

[0003] The display device may be able to display video at various refresh frame rates. However, changes in brightness may be visible during this process.

[0004] In addition, the display device can provide natural images by lowering the resolution and increasing the refresh frame rate according to the user's choice, or provide high-quality images by increasing the resolution and lowering the refresh frame rate.

[0005] There is an increasing need to provide display devices with narrow bezels while offering the functions mentioned above. The problem to be solved

[0006] The technical problem to be solved is to provide a display device and an electronic device including the same that can improve visibility and display images at various refresh frame rates while providing a narrow bezel. means of solving the problem

[0007] Embodiments of the present disclosure may provide a display device comprising a first metal layer and a second metal layer positioned perpendicularly to the first metal layer, clock lines to which a clock signal is input, side signal lines including a first metal layer positioned adjacent to the clock lines in a first direction and extending in a second direction, and stage circuits positioned adjacent to the side signal lines in a first direction and connected to the clock lines and the side signal lines, wherein at least one of the clock lines is bent at least once in a third direction opposite to the first direction at an opening where at least a portion of the first metal layer is removed.

[0008] Among the stage circuits, the Nth stage circuit (N is an integer greater than or equal to 1) may include an Nth scan driving integrated circuit and an Nth sense driving integrated circuit. Clock wiring may include first to sixth clock wirings connected to the Nth stage circuit, and 13th to 18th clock wirings connected to the Nth stage circuit.

[0009] The first to sixth clock wires are sequentially positioned adjacently in the first direction, and the second metal layer of the first clock wire can be extended in the second direction and then extended in the second direction after being bent once.

[0010] The second metal layer of the third clock wiring can be extended in the second direction and then bent once, then extended in the third direction, then bent twice and then extended in the second direction, then extended in the second direction, then bent three times and then extended in the first direction.

[0011] The second metal layer of the third clock wiring may have an area extending in the second direction after secondary bending positioned so as to overlap with the opening of the second clock wiring in a vertical direction.

[0012] The second metal layer of the fifth clock wiring can be extended in the second direction, bent once, then extended in the third direction, extended in the third direction, bent twice, then extended in the second direction, extended in the second direction, bent three times, then extended in the first direction.

[0013] The area where the second metal layer of the third clock wiring is first bent and extends in the third direction, and the area where the second metal layer of the fifth clock wiring is first bent and extends in the third direction, may be located adjacent to each other in the first direction.

[0014] The second metal layer of the fifth clock wiring may have a region extending in the second direction after secondary bending positioned so as to overlap with the opening of the third clock wiring in a vertical direction.

[0015] The length of the area extending in the second direction after the first clock wiring is bent may be equal to the sum of the length of the area extending in the third direction after the second metal layer of the third clock wiring is bent once, and the length of the area extending in the first direction after the second metal layer of the third clock wiring is bent three times.

[0016] The second metal layer of the second clock wiring can be extended in the opposite direction of the second direction, and after being bent once, can be extended in the second direction.

[0017] Among the stage circuits, the N+1th stage circuit may include the N+1th scan driving integrated circuit and the N+1th sense driving integrated circuit. The clock wiring may include 7th to 12th clock wirings connected to the N+1th stage circuit, and 19th to 24th clock wirings connected to the N+1th stage circuit.

[0018] The stage circuit may include a plurality of output buffers configured to output clock signals input to clock wires. At least two of the transistors for controlling each of the plurality of output buffers may be controlled in response to a voltage applied to one node.

[0019] Embodiments of the present disclosure may provide an electronic device comprising a host that outputs a control signal and first image data, and a display device that displays an image based on the control signal and first image data, wherein the display device comprises a first metal layer and a second metal layer positioned in a vertically overlapping direction with the first metal layer, clock lines into which a clock signal provided based on the control signal is input, side signal lines including a first metal layer positioned adjacent to the clock lines in a first direction and extending in a second direction, and stage circuits positioned adjacent to the side signal lines in a first direction and connected to the clock lines and the side signal lines, wherein at least one of the clock lines is bent at least once in a third direction opposite to the first direction at an opening in which at least a portion of the first metal layer is removed.

[0020] Embodiments of the present disclosure include a first metal layer and a second metal layer positioned perpendicularly to the first metal layer, clock wires to which a clock signal is input, side signal wires including a first metal layer positioned adjacent to the clock wires in a first direction and extending in a second direction, and stage circuits positioned adjacent to the side signal wires in a first direction and connected to the clock wires and the side signal wires, wherein one of the clock wires located further from the stage circuits may have a first vertical width, and the other of the clock wires located closer to the stage circuits may have a second vertical width smaller than the first vertical width.

[0021] Among the stage circuits, the Nth stage circuit (N is an integer greater than or equal to 1) may include an Nth scan driving integrated circuit and an Nth sense driving integrated circuit. Clock wiring may include first and second clock wirings connected to the Nth stage circuit, and 13th and 14th clock wirings connected to the Nth stage circuit.

[0022] The second metal layer of each of the first clock wiring and the second clock wiring can be extended in the second direction and then extended in the second direction after being bent once. The length of the area where the first clock wiring is extended in the second direction may be longer than the length of the area where the second clock wiring is extended in the second direction.

[0023] The area where the first clock wiring extends in the second direction may have a first vertical width. The area where the second clock wiring extends in the second direction may have a second vertical width.

[0024] The second metal layer of each of the 13th clock wiring and the 14th clock wiring can be extended in the second direction and then extended in the second direction after being bent once. The length of the area where the 13th clock wiring is extended in the second direction may be longer than the length of the area where the 14th clock wiring is extended in the second direction.

[0025] The area where the 13th clock wiring extends in the second direction may have a first vertical width. The area where the 14th clock wiring extends in the second direction may have a second vertical width.

[0026] Any one of the side signal lines may have a first horizontal width in an area overlapping with any one of the clock lines located further away from the stage circuits. In an area overlapping with any one of the clock lines located closer to the stage circuits, it may have a second horizontal width greater than the first horizontal width. Effects of the invention

[0027] According to the display device and electronic device including the same according to the embodiments of the present disclosure, visibility can be improved and images can be displayed at various refresh frame rates while providing a narrow bezel. Brief explanation of the drawing

[0028] FIG. 1 is a system block diagram of a display device according to embodiments of the present disclosure. FIG. 2 is a conceptual diagram of a display area according to embodiments of the present disclosure. FIG. 3 is an example of a subpixel according to embodiments of the present disclosure. FIG. 4 is a diagram showing a sensing circuit in embodiments of the present disclosure. FIGS. 5A, FIGS. 5B, and FIGS. 5C are examples of driving methods in which the display device of FIG. 1 displays images at different frame rates. Figure 6a is an example of the timing of the first refresh frame rate. Figure 6b is an example of the timing of the second refresh frame rate. Figure 7 is an example of a scan driving circuit. FIG. 8 is an equivalent circuit diagram of a scan driving integrated circuit according to one embodiment. FIG. 9 is an example of a sense driving circuit. FIG. 10 is an equivalent circuit diagram of a sense driving integrated circuit according to one embodiment. FIG. 11 is a drawing showing at least a portion of a non-display area according to one embodiment of the present disclosure. FIG. 12 is a drawing showing at least a portion of a non-display area according to one embodiment of the present disclosure. FIG. 13 is a drawing showing at least a portion of a non-display area according to another embodiment of the present disclosure. FIG. 14 is a drawing showing at least a portion of a non-display area according to another embodiment of the present disclosure. FIG. 15 is a drawing showing the first region of FIG. 13. Figure 16 is a drawing showing the second region of Figure 13. Figure 17 is a drawing showing the third region of Figure 14. Specific details for implementing the invention

[0029] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0030] To clearly explain the present invention, parts unrelated to the explanation have been omitted, and the same reference numerals are assigned to identical or similar components throughout the specification. Accordingly, the reference numerals described above may also be used in other drawings.

[0031] Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present invention is not necessarily limited to what is illustrated. Thickness may be exaggerated in the drawings to clearly represent various layers and regions.

[0032] Furthermore, the expression "identical" in the explanation may mean "substantially identical." In other words, it may be an identicality to the extent that a person with ordinary knowledge would accept it as identical. Other expressions may also be those in which "substantially" has been omitted.

[0033] Terms such as first, second, a, b, etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0034] Terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are explained based on the directions indicated in the drawings.

[0035] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Additionally, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and are explicitly defined herein unless interpreted in an ideal or overly formal sense.

[0036] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0037] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0038] FIG. 1 is a system block diagram of a display device (100) according to embodiments of the present disclosure.

[0039] Referring to FIG. 1, a display device (100) according to embodiments of the present disclosure may include a display panel (110), a data driving circuit (120), a gate driving circuit (130), a timing controller (140), a power supply circuit (150), etc.

[0040] A plurality of pixels (PXL) are arranged in the display panel (110). A plurality of data lines (DL1 to DLn; n is an integer of 2 or more) electrically connected to the plurality of pixels (PXL), a plurality of gate lines (SL1 to SLm; m is an integer of 2 or more), a plurality of reference voltage lines (RVL1 to RVLh; h is an integer of 2 or more), etc. may be arranged in the display panel (110). One or more power lines configured to apply a power supply voltage (e.g., a first power supply voltage (ELVDD), a second power supply voltage (ELVSS), etc.) to the plurality of pixels (PXL) may be arranged in the display panel (110).

[0041] The display panel (110) may include a display area (AA) in which a plurality of pixels (PXL) are arranged, and a non-display area (NA) located in the surrounding area of ​​the display area (AA) (e.g., the edge of the display area (AA)).

[0042] The display panel (110) may be formed flat, but is not limited thereto. For example, the display panel (110) may include curved portions formed at the left and right ends. The curved portions may have a constant curvature or a varying curvature. Additionally, the display panel (110) may be formed flexibly so that it can be bent, curved, folded, or rolled.

[0043] A plurality of data lines (DL1 to DLn) may be arranged extending in a second direction (DR2) (e.g., a direction traversing from the upper side to the lower side of the display panel (110)). A plurality of gate lines (SL1 to SLm) may be arranged extending in a first direction (DR1) different from the second direction (DR2) (e.g., a direction traversing from the left side to the right side of the display panel (110)) in the display panel (110). A plurality of reference voltage lines (RVL1 to RVLh) may be arranged extending in a second direction (DR2) in the display panel (110), but are not limited thereto.

[0044] The data driving circuit (120) may include an output circuit (122) and a sensing circuit (124). According to an embodiment, the output circuit (122) and the sensing circuit (124) may be formed functionally separated within the same integrated circuit. According to an embodiment, the output circuit (122) and the sensing circuit (124) may each be formed on different integrated circuits.

[0045] The output circuit (122) is configured to supply data voltage to a plurality of data lines (DL1 to DLn). The output circuit (122) can generate a data voltage based on the second image data (DATA2) and a data driving circuit control signal (DCS), and output the generated data voltage to the plurality of data lines (DL1 to DLn) in time. The data driving circuit control signal (DCS) may include, for example, a source start pulse (SSP) signal, a source shift clock (SSC) signal, a source output enable (SOE) signal, etc.

[0046] The sensing circuit (124) is configured to input a reference voltage to a plurality of reference voltage lines (RVL1 to RVLh) in response to a data driving circuit control signal (DCS) and to sense the voltage of the plurality of reference voltage lines (RVL1 to RVLh). The sensing circuit (124) can convert the sensed voltage into a corresponding digital value (Dsen) and output the converted digital value (Dsen). The sensing circuit (124) may include one or more analog-to-digital converters (ADCs). The data driving circuit control signal (DCS) may include, for example, a reference voltage switching signal, a sampling control signal, a hold control signal, etc. A detailed description of the above signals will be provided later with reference to FIG. 4.

[0047] The data driving circuit (120) may be implemented as an integrated circuit formed separately from the display panel (110) (e.g., a source driver integrated circuit (SDIC)), or it may be formed together with the display panel (110) and formed in at least a portion of the non-display area (NA) of the display panel (110).

[0048] The gate driving circuit (130) is configured to output a gate signal (e.g., scan signal, sense signal) to a plurality of gate lines (SL1 to SLm) in response to a gate driving circuit control signal (SCS). The gate driving circuit (130) may be implemented as a Gated Driver Integrated Circuit (GDIC) formed separately from the display panel (110), or it may be formed together with the display panel (110) and formed in at least a portion of the non-display area (NA) of the display panel (110).

[0049] A timing controller (140) can be configured to control a data driving circuit (120) and a gate driving circuit (130). The timing controller (140) can generate and output control signals (DCS, SCS) for controlling the data driving circuit (120) and the gate driving circuit (130) based on a control signal (CS) (e.g., synchronization signal, clock signal, etc.) received from an external source (e.g., a host (HST)).

[0050] The timing controller (140) receives first image data (DATA1) from an external source (e.g., a host (HST)) and can align the received first image data (DATA1) in pixel rows. The timing controller (140) can convert the received first image data (DATA1) to match a preset interface (e.g., Low Voltage Differential Signaling (LVDS), embedded Display Port (eDP), etc.). The second image data (DATA2) output by the timing controller (140) to the data driving circuit (120) may be converted internally by the timing controller (140) according to the preset interface.

[0051] The timing controller (140) may be placed within the display device (100) as a logic or processor type. The timing controller (140) may include one or more registers.

[0052] The power supply circuit (150) is configured to output a constant voltage of a constant voltage level. The power supply circuit (150) can, for example, output a first power voltage (ELVDD) and a second power voltage (ELVSS) supplied to the display panel (110). The power supply circuit (150) may, for example, include a power management integrated circuit (PMIC).

[0053] The host (HST) may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. In one embodiment, the host (HST) may be provided divided into two or more parts from a functional or structural perspective. For example, the host (HST) may include a main processor in the form of a first driving chip that includes a central processing unit, and an auxiliary processor in the form of a second driving chip that includes a controller that receives a video signal from the main processor and processes the video signal to match the interface specifications of the display device (100). The host (HST) may output a first video data (DATA1) and a control signal (CS).

[0054] In FIG. 1, the driving circuits (120, 130, 140, 150) that supply signals, voltages, etc. to the display panel (110) are merely classified according to their functions. For example, the data driving circuit (120) and the timing controller (140) may be formed within a single integrated circuit. The data driving circuit (120) and the timing controller (140) may be classified according to their functions within a single integrated circuit.

[0055] The display device (100) according to the embodiments of the present disclosure can be used as a display screen for various products such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation systems, UMPCs (ultra-mobile personal computers), as well as portable electronic devices.

[0056] An electronic device (ED) according to embodiments of the present disclosure may include a host (HST) and a display device (100).

[0057] FIG. 2 is a conceptual diagram of a display area (AA) according to embodiments of the present disclosure.

[0058] Referring to FIG. 2, four pixels (PXL1, PXL2, PXL3, PXL4; hereinafter PXL1 to PXL4) arranged in a matrix type are illustrated as an example. At least two of the four pixels (PXL1 to PXL4) may be arranged adjacent to each other in the row direction or adjacent to each other in the column direction.

[0059] Any one of the four pixels (PXL1 to PXL4) (e.g., the first pixel (PXL1) located at the top left) may include three or more subpixels (SP1, SP2, SP3).

[0060] Three subpixels (SPX1, SPX2, SPX3) constituting a single pixel (e.g., a first pixel (PXL1)) may each be configured to emit light of different wavelength bands. For example, the first subpixel (SPX1) may be configured to emit light of a red wavelength band. For example, the second subpixel (SPX2) may be configured to emit light of a green wavelength band. For example, the third subpixel (SPX3) may be configured to emit light of a blue wavelength band. According to an embodiment, a single pixel (e.g., PXL1) may further include a white subpixel configured to emit white light. According to an embodiment, a single pixel (e.g., PXL1) may include two or more subpixels (e.g., two or more second subpixels (SPX2)) configured to emit green light.

[0061] The red wavelength band may be a wavelength band of about 600 nm (nanometer) to 750 nm. The green wavelength band may be a wavelength band of about 480 nm to 560 nm. The blue wavelength band may be a wavelength band of about 370 nm to 460 nm.

[0062] Below, an example is described in which each of the four pixels (PXL1 to PXL4) includes a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3). However, the embodiments of the present disclosure are not limited thereto.

[0063] In embodiments of the present disclosure, subpixels (SPX1, SPX2, SPX3) constituting a single pixel (e.g., a first pixel (PXL1)) may each be electrically connected to a corresponding data line. For example, the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) of the first pixel (PXL1) (or the third pixel (PXL3)) may each be electrically connected to three consecutive data lines (DL3k-2, DL3k-1, DL3k; k is an integer greater than or equal to 1). For example, the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) of the second pixel (PXL2) (or the fourth pixel (PXL4)) can each be electrically connected to three consecutive data lines (DL3(k+1)-2, DL3(k+1)-1, DL3(k+1)).

[0064] In embodiments of the present disclosure, subpixels (SPX1, SPX2, SPX3) constituting a single pixel (e.g., a first pixel (PXL1)) may be electrically connected to a reference voltage line. For example, the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) of the first pixel (PXL1) (or the third pixel (PXL3)) may be electrically connected to the k-th reference voltage line (RVLk). For example, the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) of the second pixel (PXL2) (or the fourth pixel (PXL4)) may be electrically connected to the (k+1)-th reference voltage line (RVL(k+1)). Although not illustrated, according to an embodiment, subpixels (SPX1, SPX2, SPX3) constituting a single pixel (e.g., a first pixel (PXL1)) may each be electrically connected to a different reference voltage line.

[0065] In embodiments of the present disclosure, subpixels (SPX1, SPX2, SPX3) constituting a single pixel (e.g., a first pixel (PXL1)) may be electrically connected to a single gate line. For example, the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) of the first pixel (PXL1) (or the second pixel (PXL2)) may be electrically connected to the i-th gate line (SLi) (where i is an integer greater than or equal to 1). For example, the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) of the third pixel (PXL3) (or the fourth pixel (PXL4)) may be electrically connected to the (i+1)-th gate line (SL(i+1)).

[0066] Referring to FIG. 2, the first pixel (PXL1) located at the top left and the second pixel (PXL2) located at the top right are electrically connected to the same i-th gate line (SLi). The first pixel (PXL1) and the second pixel (PXL2) are located in the same pixel row. Similarly, the third pixel (PXL3) located at the bottom left and the fourth pixel (PXL4) located at the bottom right are electrically connected to the same gate line (SL(i+1)). The third pixel (PXL3) and the fourth pixel (PXL4) are located in the same pixel row.

[0067] Referring to FIG. 2, the first pixel (PXL1) located at the top left and the third pixel (PXL3) located at the bottom left are electrically connected to the same data lines (DL3k-2, DL3k-1, DL3k). The first pixel (PXL1) and the third pixel (PXL3) are located in the same pixel column. Similarly, the second pixel (PXL2) located at the top right and the fourth pixel (PXL4) located at the bottom right are electrically connected to the same data lines (DL3(k+1)-2, DL3(k+1)-1, DL3k). The second pixel (PXL2) and the fourth pixel (PXL4) are located in the same pixel column.

[0068] In embodiments of the present disclosure, two or more pixel rows and two or more pixel columns may be located in the display area (AA).

[0069] FIG. 3 is an example of a subpixel (SPX) according to embodiments of the present disclosure.

[0070] A subpixel (SPX) according to embodiments of the present disclosure may include a light-emitting element (LE) and a pixel driving circuit (PXC) configured to supply a driving current to the light-emitting element (LE). The pixel driving circuit (PXC) may include one or more transistors and one or more capacitors.

[0071] For example, referring to FIG. 3, the pixel driving circuit (PXC) may include first to third pixel transistors (PTR1 to PTR3) and a storage capacitor (Cst).

[0072] A light-emitting element (LE) may include a first electrode (either an anode electrode and a cathode electrode), a second electrode (the other between an anode electrode and a cathode electrode), and a light-emitting layer. The light-emitting element (LE) may include an organic light-emitting diode having an organic light-emitting layer. The light-emitting element (LE) may include an inorganic light-emitting diode having an inorganic light-emitting layer.

[0073] Referring to FIG. 3, the first electrode (e.g., anode electrode) of the light-emitting element (LE) can be electrically connected to the second node (N2). The second electrode (e.g., cathode electrode) of the light-emitting element (LE) can be electrically connected to the second power line (PL2).

[0074] A second power supply voltage (ELVSS) is applied to the second power line (PL2). The second power supply voltage (ELVSS) may be, for example, a low potential power supply voltage or a ground voltage.

[0075] A first pixel transistor (PTR1) may be connected (e.g., electrically connected) between a first power line (PL1) and a second node (N2). The first pixel transistor (PTR1) may include a gate electrode, a first electrode (either a source electrode and a drain electrode), and a second electrode (the other of a source electrode and a drain electrode). The gate electrode of the first pixel transistor (PTR1) may be electrically connected to the second pixel transistor (PTR2) at the first node (N1). The first electrode (e.g., a drain electrode) of the first pixel transistor (PTR1) may be electrically connected to the first power line (PL1). A first power supply voltage (ELVDD) may be applied to the first electrode of the first pixel transistor (PTR1). The first power supply voltage (ELVDD) may be, for example, a high potential power supply voltage. The second electrode (e.g., source electrode) of the first pixel transistor (PTR1) can be electrically connected to a light-emitting element (LE) at the second node (N2). The first pixel transistor (PTR1) can receive a data voltage (Vdata) through the second pixel transistor (PTR2). A current (e.g., drain current or driving current) of a magnitude corresponding to the input data voltage (Vdata) can flow through the first pixel transistor (PTR1).

[0076] The second pixel transistor (PTR2) may be configured to switch the electrical connection between the data line (DLj) and the first node (N1). The operation timing of the second pixel transistor (PTR2) may be controlled by the i-th scan signal (SCAN[i]). The second pixel transistor (PTR2) is turned on in response to the i-th scan signal (SCAN[i]) at the turn-on level, and a data voltage (Vdata) (or a voltage corresponding to the data voltage (Vdata)) may be applied to the first node (N1).

[0077] The third pixel transistor (PTR3) can be configured to switch the electrical connection between the second node (N2) and the reference voltage line (RVLk). The operation timing of the third pixel transistor (PTR3) can be controlled by a sense signal (SENSE[i]). The third pixel transistor (PTR3) can be turned on in response to a sense signal (SENSE[i]) at a turn-on level. When the third pixel transistor (PTR3) is turned on, the voltage of the second node (N2) can be applied to the reference voltage line (RVLk). The voltage applied to the reference voltage line (RVLk) can be stored in the line capacitor (Cline).

[0078] Referring to FIG. 3, the first to third pixel transistors (PTR1 to PTR3) are all shown as being N-type transistors. In this case, the first to third pixel transistors (PTR1 to PTR3) may have a turn-on level voltage that is a high level voltage and a turn-off level voltage that is a low level voltage. According to an embodiment, at least one of the first to third pixel transistors (PTR1 to PTR3) may be a P-type transistor. In this case, the P-type transistor may have a turn-on level voltage that is a low level voltage and a turn-off level voltage that is a high level voltage.

[0079] At least one of the first to third pixel transistors (PTR1 to PTR3) may include an amorphous silicon (a-Si) semiconductor. At least one of the first to third pixel transistors (PTR1 to PTR3) may include a polycrystalline silicon (poly-Si) semiconductor. At least one of the first to third pixel transistors (PTR1 to PTR3) may include an oxide semiconductor.

[0080] A storage capacitor (Cst) may be configured to maintain a voltage difference between a first node (N1) and a second node (N2). The storage capacitor (Cst) may include one electrode electrically connected to the first node (N1) and the other electrode electrically connected to the second node (N2). The storage capacitor (Cst) may be formed as a physical capacitor element rather than a parasitic capacitor.

[0081] The i-th scan signal (SCAN[i]) may be applied to the i-th scan line (SCLi) (or the i-th first gate line (SCLi)). The sense signal (SENSE[i]) may be applied to the i-th sensing line (SNL[i]) (or the i-th second gate line (SNLi)). The i-th scan signal (SCAN[i]) and the sense signal (SENSE[i]) may be different signals. In this case, the i-th scan line (SCLi) and the i-th sensing line (SNLi) may be different lines. Referring together with FIG. 1, the i-th gate line (SLi) may include the i-th scan line (SCLi) and the i-th sensing line (SNLi).

[0082] The output circuit (122) can output a data voltage (Vdata) to the j-th data line (DLj). The sensing circuit (124) can receive an analog sensing voltage (Vsen) applied to the k-th reference voltage line (RVLk). The analog sensing voltage (Vsen) may be a voltage that reflects the characteristic value of the first pixel transistor (PTR1) (e.g., the threshold voltage of the first pixel transistor (PTR1)).

[0083] FIG. 4 is a drawing showing a sensing circuit (124) in embodiments of the present disclosure.

[0084] The sensing circuit (124) may be included in the data driving circuit (120). The sensing circuit (124) may receive an analog sensing voltage (Vsen) from the k-th reference voltage line (RVLk). The sensing circuit (124) may convert the input analog sensing voltage (Vsen) into a digital value (Dsen) and output it.

[0085] Referring to FIG. 4, the sensing circuit (124) may include a first switching element (SW1), a second switching element (SW2), a multiplexer (MUX), a sensing capacitor (Csen), an analog-to-digital converter (410), etc.

[0086] The first switching element (SW1) may be configured to switch the electrical connection between the third node (N3) and the k-th reference voltage line (RVLk). The operation timing of the first switching element (SW1) may be controlled by a reference voltage switching signal (SPRE). When the first switching element (SW1) is turned on in response to a turn-on level reference voltage switching signal (SPRE), a reference voltage (Vref) may be applied to the k-th reference voltage line (RVLk). The first switching element (SW1) may include, for example, a transistor.

[0087] The second switching element (SW2) may be configured to switch the electrical connection between the k-th reference voltage line (RVLk) and the sensing capacitor (Csen). The operation timing of the second switching element (SW2) may be controlled by a sampling control signal (SAMP). When the second switching element (SW2) is turned on by the sampling control signal (SAMP) at a turn-on level, an analog sensing voltage (Vsen) is applied to the sensing capacitor (Csen). The second switching element (SW2) may include, for example, a transistor.

[0088] The sensing capacitor (Csen) may include one electrode connected (e.g., electrically connected) to the second switching element (SW2) and the other electrode to which a constant voltage (or ground) is applied. A voltage corresponding to an analog sensing voltage (Vsen) may be stored in the one electrode of the sensing capacitor (Csen).

[0089] A multiplexer (MUX) may be configured to switch the electrical connection between a sensing capacitor (Csen) and an analog-to-digital converter (410). The multiplexer (MUX) may include two or more input terminals. The input terminals of the multiplexer (MUX) may be connected (e.g., electrically connected) to one electrode of the sensing capacitor (Csen). The operation timing of the multiplexer (MUX) may be controlled by a hold control signal (HOLD). When the multiplexer (MUX) is turned on by a turn-on level hold control signal (HOLD), the voltage stored in the sensing capacitor (Csen) (e.g., analog sensing voltage (Vsen)) may be input to the analog-to-digital converter (ADC).

[0090] An analog-to-digital converter (410) can be configured to convert an analog voltage into a digital voltage and output it. The analog-to-digital converter (410) receives an analog voltage (e.g., an analog sensing voltage (Vsen)) and can output a digital value (Dsen) corresponding to the input analog voltage.

[0091] Accordingly, embodiments of the present disclosure can convert and output an analog sensing voltage (Vsen) sensed at a subpixel (SPX) into a corresponding digital value (Dsen).

[0092] FIGS. 5A, FIGS. 5B, and FIGS. 5C are examples of driving methods in which the display device (100) of FIG. 1 displays images at different frame rates.

[0093] Referring to FIG. 5a, the period during which a turn-on level voltage is applied to the i-th scan line (SCLi) may correspond to a data writing period (or also referred to as a write period) (WP). When a frame is initiated (or switched), a data voltage (Vdata; see FIG. 3) may be input (or written, applied) to the subpixel. During the data writing period (WP), a data voltage for displaying an image of the corresponding frame may be input to the subpixel. The subpixel may store the input data voltage (e.g., stored in a storage capacitor) and emit light for at least a portion of the corresponding frame based on the stored data voltage.

[0094] The period during which a turn-on level voltage is applied to the sense line (SNLi) may correspond to an initialization period (IP). When a frame is initiated, a reference voltage (Vref; see FIG. 3) may be input to the subpixel. During the initialization period (IP), the reference voltage is input to the subpixel, and the light-emitting element (LE; see FIG. 3) of the subpixel does not emit light.

[0095] The period during which a turn-off level voltage is applied to the sense line (SNLi) may include a light emission period (LP). The subpixel may emit light during the light emission period (LP) based on the data voltage input during the data write period (WP).

[0096] Referring to FIG. 5a, the data write period (WP) and the initialization period (IP) may overlap at least partially. For example, the data write period (WP) and the initialization period (IP) may coincide. However, embodiments of the present disclosure are not limited thereto. For example, the data write period (WP) and the initialization period (IP) may not overlap with each other.

[0097] According to an embodiment, if the refresh frame rate (the frequency at which frames are switched, or the period during which data voltage is input to a subpixel) is reduced, the proportion of the initialization period (IP) within one frame period may also be reduced. In other words, the length of the non-emissive period during which the light-emitting element does not emit light within one frame period may be relatively reduced. In this case, as the refresh frame rate decreases, the brightness may be perceived by the user as increasing, or as the brightness may be perceived as decreasing as the refresh frame rate increases. Such increase or decrease in brightness may be perceived by the user as a blinking phenomenon (also called a flicker phenomenon).

[0098] Referring to FIG. 5b and FIG. 5c, to mitigate the flickering phenomenon, embodiments of the present disclosure may apply a turn-on level voltage (or a turn-on level sense signal) to the i-th sense line (SNLi) for at least a portion of the period during which a turn-off level voltage (or a turn-off level scan signal) is applied to the i-th scan line (SCLi). Accordingly, the light-emitting element of the subpixel may flicker within one frame period. A display device (100; see FIG. 1) according to embodiments of the present disclosure may control the light-emitting element so that no driving current flows when the refresh frame rate decreases (e.g., control the light-emitting element so that no driving current flows according to a preset period). Accordingly, the phenomenon in which abrupt changes in brightness are visible as the refresh frame rate changes may be mitigated. This may improve visibility.

[0099] Referring to FIG. 5b, the initialization period (IP) may be performed once within a frame period in a period that does not overlap with the data writing period (WP). Referring to FIG. 5c, the initialization period (IP) may be performed two or more times within a frame period in a period that does not overlap with the data writing period (WP).

[0100] Referring to FIGS. 5a through 5c, the refresh frame rate illustrated in FIG. 5a may be, for example, 240 Hz (Hertz). The refresh frame rate illustrated in FIG. 5b may be, for example, 80 Hz to 120 Hz. The refresh frame rate in FIG. 5c may be, for example, 60 Hz to 80 Hz. Embodiments of the present disclosure are not limited to those described above, and the presented refresh frame rates are merely examples.

[0101] FIG. 6a is an example of the timing of the first refresh frame rate (RF1). FIG. 6b is an example of the timing of the second refresh frame rate (RF2).

[0102] Referring to FIG. 6a, scan signals (e.g., turn-on level scan signals) can be sequentially output through the first to m scan lines (SCL1 to SCLm) at the first refresh frame rate (RF1). For example, the first turn-on level scan signal (SCAN[1]), the second scan signal (SCAN[2]), the third scan signal (SCAN[3]), the fourth scan signal (SCAN[4]), the fifth scan signal (SCAN[5]), and the sixth scan signal (SCAN[6]) can be sequentially output. Subsequently, the m-1st turn-on level scan signal (SCAN[m-1]) and the mth scan signal (SCAN[m]) can be sequentially output. Within one frame period, the first scan signal (SCAN[1]) to the mth scan signal (SCAN[m]) can be output.

[0103] The first scan signal (SCAN[1]) can be output to write a data voltage (Vdata[1]) to the corresponding subpixel. The second scan signal (SCAN[2]) can be output to write a corresponding data voltage (Vdata[2]) to the corresponding subpixel. Likewise, the third to m-th scan signals (SCAN[3] to SCAN[m]) can also be output to write data voltages (Vdata[3] to Vdata[m]) to the corresponding subpixels.

[0104] The first scan signal (SCAN[1]) may have at least a portion of the period of turn-on level overlap with the second scan signal (SCAN[2]), and the period of turn-on level overlap with the third to m-th scan signals (SCAN[3] to SCAN[m]). The second scan signal (SCAN[2]) may have at least a portion of the period of turn-on level overlap with the first scan signal (SCAN[1]) and the third scan signal (SCAN[3]), and the period of turn-on level overlap with the fourth to m-th scan signals (SCAN[4] to SCAN[m]).

[0105] In the embodiment of FIG. 6a, different data voltages corresponding to each of the subpixels connected to the first to m scan lines (SCL1 to SCLm) may be applied.

[0106] In one embodiment, such a first refresh frame rate (RF1) may be the same as the refresh frame rate described with reference to FIG. 5a above. For example, the first refresh frame rate (RF1) may be about 240 Hz, but the embodiments of the present disclosure are not limited thereto.

[0107] Meanwhile, in an embodiment where the first refresh frame rate (RF1) is the same as the refresh frame rate described with reference to FIG. 5a above, a plurality of sense lines (e.g., including the i-th sense line (SNLi) described through FIG. 3) can be driven similarly to a plurality of scan lines (SCL1 to SCLm) described through FIG. 6a.

[0108] Referring to FIG. 6a, a high-resolution image can be displayed at a first refresh frame rate (RF1) by embodiments of the present disclosure.

[0109] Referring to FIG. 6b, at least some of the scan signals (e.g., turn-on level scan signals) can be simultaneously output through the first to m scan lines (SCL1 to SCLm) at the second refresh frame rate (RF2). For example, the first turn-on level scan signal (SCAN[1]) and the second scan signal (SCAN[2]) can be simultaneously output. The third turn-on level scan signal (SCAN[3]) and the fourth scan signal (SCAN[4]) can be simultaneously output. The fifth turn-on level scan signal (SCAN[5]) and the sixth scan signal (SCAN[6]) can be simultaneously output. Subsequently, the m-1 turn-on level scan signal (SCAN[m-1]) and the m-th scan signal (SCAN[m]) can be simultaneously output. Within one frame period, at least two of the first scan signal (SCAN[1]) to the m-th scan signal (SCAN[m]) can be paired and output sequentially.

[0110] The first scan signal (SCAN[1]) can be output to write a data voltage (Vdata[1, 2]) to the corresponding subpixel. The second scan signal (SCAN[2]) can be output to write a corresponding data voltage (Vdata[1, 2]) to the corresponding subpixel. The third scan signal (SCAN[3]) can be output to write a data voltage (Vdata[3, 4]) to the corresponding subpixel. The fourth scan signal (SCAN[4]) can be output to write a corresponding data voltage (Vdata[3, 4]) to the corresponding subpixel. The fifth scan signal (SCAN[5]) can be output to write a data voltage (Vdata[5, 6]) to the corresponding subpixel. The sixth scan signal (SCAN[6]) can be output to write a corresponding data voltage (Vdata[5, 6]) to the corresponding subpixel. Likewise, the m-1th scan signal (SCAN[m-1]) can be output to write the data voltage (Vdata[m-1, m]) to the corresponding subpixel. The mth scan signal (SCAN[m]) can be output to write the corresponding data voltage (Vdata[m-1, m]) to the corresponding subpixel.

[0111] Here, the first scan signal (SCAN[1]) is identical to the second scan signal (SCAN[2]), and at least a portion of the period of turn-on level may overlap with the third scan signal (SCAN[3]) and the fourth scan signal (SCAN[4]). On the other hand, the period of turn-on level may not overlap with the fifth scan signal (SCAN[5]) and the sixth scan signal (SCAN[6]). Likewise, the second scan signal (SCAN[2]) is identical to the first scan signal (SCAN[1]), and at least a portion of the period of turn-on level may overlap with the third scan signal (SCAN[3]) and the fourth scan signal (SCAN[4]). On the other hand, the period of turn-on level may not overlap with the fifth scan signal (SCAN[5]) and the sixth scan signal (SCAN[6]).

[0112] In the embodiment of FIG. 6b, the same data voltage may be applied to at least two of the subpixels connected to the first to m scan lines (SCL1 to SCLm).

[0113] In one embodiment, such a second refresh frame rate (RF2) may be about twice the first refresh frame rate (RF1). For example, the second refresh frame rate (RF2) may be about 480 Hz, but the embodiments of the present disclosure are not limited thereto.

[0114] Meanwhile, in an embodiment where the second refresh frame rate (RF2) is approximately twice the first refresh frame rate (RF1) described with reference to FIG. 6a, a plurality of sense lines (e.g., including the i-th sense line (SNLi) described through FIG. 3) can be driven similarly to a plurality of scan lines (SCL1 to SCLm) described through FIG. 6b.

[0115] Referring to FIG. 6b, an image having half the resolution of the embodiment of FIG. 6a can be displayed by the embodiments of the present disclosure at a second refresh frame rate (RF2) that is more than twice as fast as the embodiment of FIG. 6a.

[0116] Referring collectively to the aforementioned FIGS. 5a to 6b, a display device (100; see FIG. 1) according to embodiments of the present disclosure can display images at a wide variety of refresh frame rates.

[0117] For example, based on a refresh frame rate of approximately 240 Hz as described in FIGS. 5a and 6a, an image with a refresh frame rate lower than this can be displayed through the driving method described in FIGS. 5b and 5c. And, an image with a refresh frame rate higher than this can be displayed through the driving method described in FIG. 6b.

[0118] FIG. 7 is an example of a scan driving circuit (710).

[0119] The scan driving circuit (710) may include a plurality of scan driving integrated circuits. In FIG. 7, for convenience of explanation, the scan driving circuit (710) is shown to include four scan driving integrated circuits (7101 to 7104), but embodiments of the present disclosure are not limited thereto.

[0120] Each of the scan driving integrated circuits (7101 to 7104) corresponds to a stage of the scan driving circuit (710). Each of the scan driving integrated circuits (7101 to 7104) outputs two or more scan signals, and for example, an embodiment is illustrated in which each of the scan driving integrated circuits (7101 to 7104) outputs six scan signals. However, the embodiments of the present disclosure are not limited thereto, and each of the scan driving integrated circuits (7101 to 7104) may be configured to output more than six scan signals.

[0121] At least one of the scan driving integrated circuits (7101 to 7104) can receive at least six of the twelve scan clock signals (SC_CLK1 to SC_CLK12). At least one of the scan driving integrated circuits (7101 to 7104) can receive a carry clock signal (CR_CLK). At least one of the scan driving integrated circuits (7101 to 7104) can receive a start signal (VST) or receive a carry signal from a preceding scan driving integrated circuit. At least one of the scan driving integrated circuits (7101 to 7104) can receive a carry signal from a succeeding scan driving integrated circuit.

[0122] The scan driving circuit (710) may include a first scan driving integrated circuit (7101), a second scan driving integrated circuit (7102), an Nth scan driving integrated circuit (7103) (where N is an integer greater than or equal to 1), and a Kth scan driving integrated circuit (7104) (where K is an integer greater than or equal to 1).

[0123] The first scan drive integrated circuit (7101) can receive the first to sixth scan clock signals (SC_CLK1 to SC_CLK6) among the twelve scan clock signals (SC_CLK1 to SC_CLK12). The first scan drive integrated circuit (7101) can receive a carry clock signal (CR_CLK). The first scan drive integrated circuit (7101) can receive a start signal (VST). The first scan drive integrated circuit (7101) can receive a carry signal (CR[2]) from the subsequent second scan drive integrated circuit (7102).

[0124] The first scan driving integrated circuit (7101) can output the first through sixth scan signals (SCAN[1] through SCAN[6]). The first scan driving integrated circuit (7101) can output a carry signal (CR[1]).

[0125] The second scan drive integrated circuit (7102) can receive the 7th to 12th scan clock signals (SC_CLK7 to SC_CLK12) among the twelve scan clock signals (SC_CLK1 to SC_CLK12). The second scan drive integrated circuit (7102) can receive a carry clock signal (CR_CLK). The second scan drive integrated circuit (7102) can receive a carry signal (CR[1]) from the preceding first scan drive integrated circuit (7101). The second scan drive integrated circuit (7102) can receive a carry signal (CR[3]) from the following third scan drive integrated circuit.

[0126] The second scan driving integrated circuit (7102) can output the 7th to 12th scan signals (SCAN[7] to SCAN

[12] ). The second scan driving integrated circuit (7102) can output a carry signal (CR[2]).

[0127] The Nth scan driving integrated circuit (7103) can receive the first to sixth scan clock signals (SC_CLK1 to SC_CLK6) among the twelve scan clock signals (SC_CLK1 to SC_CLK12). The Nth scan driving integrated circuit (7103) can receive a carry clock signal (CR_CLK). The Nth scan driving integrated circuit (7103) can receive a carry signal (CR[N-1]) from the preceding N-1st scan driving integrated circuit. The Nth scan driving integrated circuit (7103) can receive a carry signal (CR[N+1]) from the subsequent N+1th scan driving integrated circuit.

[0128] The Nth scan driving integrated circuit (7103) can output the i-th to i+5th scan signals (SCAN[i] to SCAN[i+5]). The Nth scan driving integrated circuit (7103) can output a carry signal (CR[N]).

[0129] The Kth scan driving integrated circuit (7104) can receive the 7th to 12th scan clock signals (SC_CLK7 to SC_CLK12) among the twelve scan clock signals (SC_CLK1 to SC_CLK12). The Kth scan driving integrated circuit (7104) can receive a carry clock signal (CR_CLK). The Kth scan driving integrated circuit (7104) can receive a carry signal (CR[K-1]) from the preceding K-1st scan driving integrated circuit. The Kth scan driving integrated circuit (7104) can receive a carry signal (CR[K+1]) from the succeeding K+1st scan driving integrated circuit.

[0130] The K-th scan driving integrated circuit (7104) can output m-5th to m-th scan signals (SCAN[m-5] to SCAN[m]). The K-th scan driving integrated circuit (7104) can output a carry signal (CR[K]).

[0131] In the drawings below, starting from Figure 8, the configuration and driving method of the Nth scan driving integrated circuit (7103) are described in more detail using the Nth scan driving integrated circuit (7103) as an example. The configuration and driving method of the Nth scan driving integrated circuit (7103) can be similarly applied to other scan driving integrated circuits included in the scan driving circuit (710).

[0132] FIG. 8 is an equivalent circuit diagram of a scan driving integrated circuit (800) according to one embodiment.

[0133] Referring to FIG. 8, a scan driving integrated circuit (800) according to embodiments of the present disclosure may include one or more terminals, one or more transistors, and one or more capacitors. Below, the configuration of a scan driving integrated circuit (800) according to one embodiment is described.

[0134] The first transistor (TR1) may be configured to switch the electrical connection between the second power terminal (822) and the first node (SN1) in response to a signal input to the first carry terminal (811). A start signal (VST) or a carry signal (CR[N-1]) from the previous stage may be input to the first carry terminal (811). A second high voltage (VGH2) may be applied to the second power terminal (822). The second high voltage (VGH2) may be the turn-on level voltage of the 16 transistors (T16a to T16f). In one embodiment, the first transistor (TR1) may have a double-gate structure in which two transistors are connected in series with each other while sharing a gate electrode. However, embodiments of the present disclosure are not limited thereto, and the first transistor (TR1) may be implemented as a single transistor.

[0135] The second transistor (TR2) may be configured to switch the electrical connection between the first power terminal (821) and the first node (SN1) in response to a signal input to the third carry terminal (813). The carry signal (CR[N+1]) of the next stage may be input to the third carry terminal (813). A first high voltage (VGH1) may be applied to the first power terminal (821). The voltage level of the first high voltage (VGH1) may be lower than the voltage level of the second power voltage (VGH2). For example, the first high voltage (VGH1) may be the turn-off level voltage of the 16 transistors (T16a to T16f). The voltage level of the first high voltage (VGH1) may be higher than the voltage level of the first low voltage (VSS1).

[0136] The third transistor (TR3) can be configured to switch the electrical connection between the second power terminal (822) and the second node (SN2) in response to a signal input to the first carry terminal (811).

[0137] The fourth transistor (TR4) may include a gate electrode connected to the first carry terminal (811). The fourth transistor (TR4) may be configured to switch the electrical connection between the third transistor (TR3) and the first carry terminal (811). When a start signal (VST) or a carry signal (CR[N-1]) from the previous stage is input, the third transistor (TR3) and the fourth transistor (TR4) may be turned on together. By doing so, a second power supply voltage (VGH2) is applied to the second node (SN2), and the eighth transistor (TR8), the ninth transistor (TR9), the fourteenth transistor (TR14), and the fifteenth transistor (TR15) may be turned on.

[0138] The first to fourth transistors (TR1 to TR4) can form a pre-charge section.

[0139] The fifth transistor (TR5) may be configured to switch the electrical connection between the first power terminal (821) and the first node (SN1) in response to the voltage applied to the fourth node (SN4). When the fifth transistor (TR5) is turned on, a current path may be formed from the first node (SN1) through the fifth transistor (TR5) toward the first power terminal (821). By doing so, the voltage of the first node (SN1) may be discharged.

[0140] The sixth transistor (TR6) may be configured to switch the electrical connection between the first power terminal (821) and the fifth node (SN5) in response to a voltage input to the first power terminal (821). The first high voltage (VGH1) input to the first power terminal (821) may be the turn-on level voltage of the sixth transistor (TR6). In one embodiment, the sixth transistor (TR6) may have a double-gate structure in which two transistors are connected in series with each other while sharing a gate electrode. However, embodiments of the present disclosure are not limited thereto, and the sixth transistor (TR6) may be implemented as a single transistor.

[0141] The seventh transistor (TR7) may be configured to switch the electrical connection between the first power terminal (821) and the third node (SN3) in response to the voltage applied to the fifth node (SN5). When the seventh transistor (TR7) is turned on, a voltage corresponding to the first high voltage (VGH1) is applied to the third node (SN3), thereby turning on the eleventh transistor (TR11), the twelfth transistor (TR12), the thirteenth transistors (TR13a to TR13f), and the eighth transistor (TR18).

[0142] The eighth transistor (TR8) may be configured to switch the electrical connection between the fourth power terminal (824) and the third node (SN3) in response to a voltage applied to the second node (SN2). A second low voltage (VSS2) may be applied to the fourth power terminal (824). When the eighth transistor (TR8) is turned on, the second low voltage (VSS2) is applied to the third node (SN3) so that the tenth transistor (TR10), the eleventh transistor (TR11), the twelfth transistor (TR12), the thirteenth transistors (TR13a to TR13f), and the eighth transistor (TR18) may be turned off.

[0143] The ninth transistor (TR9) may be configured to switch the electrical connection between the third power terminal (823) and the fifth node (SN5) in response to a voltage applied to the second node (SN2). A first low voltage (VSS1) may be applied to the third power terminal (823). The eighth transistor (TR8) and the ninth transistor (TR9) may be turned on together in response to the voltage at the second node (SN2). When the ninth transistor (TR9) is turned on, the first low voltage (VSS1) is applied to the fifth node (SN5), causing the seventh transistor (TR7) to be turned off. This allows the first power terminal (821) and the third node (SN3) to be electrically isolated.

[0144] The tenth transistor (TR10) may be configured to switch the electrical connection between the second node (SN2) and the fourth power terminal (824) in response to the voltage applied to the third node (SN3). When the tenth transistor (TR10) is turned on, a second low voltage (VSS2) may be applied to the second node (SN2). The second low voltage (VSS2) may be applied to one electrode of the first capacitor (C1) electrically connected to the second node (SN2). By doing so, the voltage of the second node (SN2) may be discharged. The tenth transistor (TR10) may have a double-gate structure in which two transistors are connected in series while sharing a gate electrode. However, embodiments of the present disclosure are not limited thereto, and the tenth transistor (TR10) may be implemented as a single transistor.

[0145] The 6th to 10th transistors (TR6 to TR10) can form an inverter with the 2nd node (SN2) as the input node and the 3rd node (SN3) as the output node.

[0146] The eleventh transistor (TR11) may be configured to switch the electrical connection between the fourth node (SN4) and the fourth power terminal (824) in response to the voltage of the third node (SN3). When the eleventh transistor (TR11) is turned on, a current path may be formed from the fourth node (SN4) through the eleventh transistor (TR11) to the fourth power terminal (824). By doing so, the voltage of the fourth node (SN4) may be discharged.

[0147] The 12th transistor (TR12) may be configured to switch the electrical connection between the second carry terminal (812) and the fourth power terminal (824) in response to the voltage of the third node (SN3). The carry signal (CR[N]) of the current stage may be output to the second carry terminal (812). When the 12th transistor (TR12) is turned on, the second low voltage (VSS2) may be output through the second carry terminal (812).

[0148] The thirteenth transistors (TR13a to TR13f) may be configured to switch the electrical connection between the scan output terminals (841 to 846) and the third power terminal (823) in response to the voltage of the third node (SN3). In one embodiment, the thirteenth transistors (TR13a to TR13f) are composed of six transistors, which may include the a-thirteenth transistor (TR13a), the b-thirteenth transistor (TR13b), the c-thirteenth transistor (TR13c), the d-thirteenth transistor (TR13d), the e-thirteenth transistor (TR13e), and the f-thirteenth transistor (TR13f). However, embodiments of the present disclosure are not limited thereto, and the thirteenth transistors (TR13a to TR13f) may be implemented to include more than six transistors or fewer transistors.

[0149] The a-three-three transistors (TR13a) can be configured to switch the electrical connection between the first scan output terminal (841) and the third power terminal (823) that output the i-th scan signal (SCAN[i]).

[0150] The b-th 13th transistor (TR13a) can be configured to switch the electrical connection between the second scan output terminal (842) and the third power terminal (823) that output the i+1th scan signal (SCAN[i+1]).

[0151] The c-13th transistor (TR13a) can be configured to switch the electrical connection between the third scan output terminal (843) and the third power terminal (823) that output the i+2th scan signal (SCAN[i+2]).

[0152] The d-13th transistor (TR13d) can be configured to switch the electrical connection between the 4th scan output terminal (844) and the 3rd power terminal (823) that output the i+3rd scan signal (SCAN[i+3]).

[0153] The e-13th transistor (TR13e) can be configured to switch the electrical connection between the 5th scan output terminal (845) and the 3rd power terminal (823) that outputs the i+4th scan signal (SCAN[i+4]).

[0154] The f-th 13th transistor (TR13f) can be configured to switch the electrical connection between the 6th scan output terminal (846) and the 3rd power terminal (823) that outputs the i+5th scan signal (SCAN[i+5]).

[0155] When the 13th transistors (TR13a to TR13f) are turned on, a first low voltage (VSS1) can be output through the scan output terminals (841 to 846).

[0156] The 11th transistor (TR11), the 12th transistor (TR12), and the 13th transistors (TR13a to TR13f) can form a pull-down section.

[0157] The 14th transistor (TR14) may be configured to switch the electrical connection between the first clock terminal (831) and the fourth node (SN4) in response to the voltage applied to the second node (SN2). A boosting clock signal (BCLK) may be applied to the first clock terminal (831). When the 14th transistor (TR14) is turned on, the first clock terminal (831) may be electrically connected to the fourth node (SN4) via the 14th transistor (TR14). When the boosting clock signal (BCLK) is applied to the fourth node (SN4), the voltage of the second node (SN2) may be raised (or boosted) by the coupling effect of the first capacitor (C1).

[0158] The first capacitor (C1) may include one electrode connected to the second node (SN2) and the other electrode connected to the fourth node (SN4). The first capacitor (C1) may be configured to maintain a voltage difference between the second node (SN2) and the fourth node (SN4). The first capacitor (C1) may be pre-charged by the second high voltage (VGH2). When the voltage of the fourth node (SN4) rises due to the boosting clock signal (BCLK), the voltage of the second node (SN2) may rise due to the coupling effect of the first capacitor (C1).

[0159] The 14th transistor (TR14) and the 1st capacitor (C1) can form a boosting section.

[0160] The 15th transistor (TR15) may be configured to switch the electrical connection between the second clock terminal (832) and the second carry terminal (812) in response to the voltage of the second node (SN2). A carry clock signal (CR_CLK) may be input to the second clock terminal (832). When the 15th transistor (TR15) is turned on, the carry clock signal (CR_CLK) may be output as the current stage carry signal (CR[N]) through the second carry terminal (812). The 15th transistor (TR15) may function as an output buffer for outputting the current stage carry signal (CR[N]).

[0161] The 16th transistors (TR16a to TR16f) may be configured to switch the electrical connection between the second capacitors (C2a to C2f) and the second node (SN2) in response to the voltage of the first node (SN1). In one embodiment, the 16th transistors (TR16a to TR16f) are composed of six transistors, which may include the a-16th transistor (TR16a), the b-16th transistor (TR16b), the c-16th transistor (TR16c), the d-16th transistor (TR16d), the e-16th transistor (TR16e), and the f-16th transistor (TR16f). However, embodiments of the present disclosure are not limited thereto, and the 16th transistors (TR16a to TR16f) may be implemented to include more than six transistors or fewer transistors.

[0162] The a-16th transistor (TR16a) can be configured to switch the electrical connection between the a-2nd capacitor (C2a) and the second node (SN2).

[0163] The b-16th transistor (TR16b) can be configured to switch the electrical connection between the b-2nd capacitor (C2b) and the 2nd node (SN2).

[0164] The c-16th transistor (TR16c) can be configured to switch the electrical connection between the c-2nd capacitor (C2c) and the 2nd node (SN2).

[0165] The d-16th transistor (TR16d) can be configured to switch the electrical connection between the d-2nd capacitor (C2d) and the 2nd node (SN2).

[0166] The e-16th transistor (TR16e) can be configured to switch the electrical connection between the e-2nd capacitor (C2e) and the 2nd node (SN2).

[0167] The f-16th transistor (TR16f) can be configured to switch the electrical connection between the f-2nd capacitor (C2f) and the 2nd node (SN2).

[0168] When the 16th transistors (TR16a to TR16f) are turned on, the Q nodes (Qa to Qf) are connected to the second node (SN2), thereby providing pre-charged and boosted voltages to the Q nodes (Qa to Qf). When the 16th transistors (T16a to T16f) are turned off, the electrical connection between the Q nodes (Qa to Qf) and the second node (SN2) is isolated, thereby preventing the voltage of adjacent Q nodes from fluctuating while individual voltages are applied to each of the Q nodes (Qa to Qf).

[0169] The second capacitors (C2a to C2f) may be configured to maintain a potential difference between the Q nodes (Qa to Qf) and the fourth node (SN4). In one embodiment, the second capacitors (C2a to C2f) are composed of six capacitors, which may include a second capacitor (C2a), a second capacitor (C2b), a second capacitor (C2c), a second capacitor (C2d), a second capacitor (C2e), and a second capacitor (C2f). However, embodiments of the present disclosure are not limited thereto, and the second capacitors (C2a to C2f) may be implemented to include more than six capacitors or fewer capacitors.

[0170] The a-2nd capacitor (C2a) may include one electrode connected to the aQ node (Qa) and the other electrode connected to the 4th node (SN4).

[0171] The b-2nd capacitor (C2b) may include one electrode connected to the bQ node (Qb) and the other electrode connected to the 4th node (SN4).

[0172] The c-2nd capacitor (C2c) may include one electrode connected to the cQ node (Qc) and the other electrode connected to the 4th node (SN4).

[0173] The d-2nd capacitor (C2d) may include one electrode connected to the dQ node (Qd) and the other electrode connected to the 4th node (SN4).

[0174] The e-2nd capacitor (C2e) may include one electrode connected to the eQ node (Qe) and the other electrode connected to the 4th node (SN4).

[0175] The f-2nd capacitor (C2f) may include one electrode connected to the fQ node (Qf) and the other electrode connected to the 4th node (SN4).

[0176] The second capacitors (C2a to C2f) can perform the function of controlling the i-th to i+5th scan signals (SCAN[i] to SCAN[i+5]) to be stably output through the scan output terminals (841 to 846) by maintaining the voltage of the Q nodes (Qa to Qf).

[0177] The 17th transistors (TR17a to TR17f) may be configured to switch the electrical connection between the 3rd to 8th clock terminals (833 to 838) and the 1st to 6th scan output terminals (841 to 846) in response to a corresponding voltage among the Q nodes (Qa to Qf). The 3rd to 8th clock terminals (833 to 838) may receive the 1st to 6th scan clock signals (SC_CLK1 to SC_CLK6). In one embodiment, the 17th transistors (TR17a to TR17f) are composed of six transistors, which may include the a-17th transistor (TR17a), the b-17th transistor (TR17b), the c-17th transistor (TR17c), the d-17th transistor (TR17d), the e-17th transistor (TR17e), and the f-17th transistor (TR17f). However, embodiments of the present disclosure are not limited thereto, and the 17th transistors (TR17a to TR17f) may be implemented to include more than six transistors or fewer transistors.

[0178] The a-17th transistor (TR17a) can be configured to switch the electrical connection between the third clock terminal (833) and the first scan output terminal (841).

[0179] The b-17th transistor (TR17b) can be configured to switch the electrical connection between the 4th clock terminal (834) and the 2nd scan output terminal (842).

[0180] The c-17th transistor (TR17c) can be configured to switch the electrical connection between the 5th clock terminal (835) and the 3rd scan output terminal (843).

[0181] The d-17th transistor (TR17d) can be configured to switch the electrical connection between the 6th clock terminal (836) and the 4th scan output terminal (844).

[0182] The e-17th transistor (TR17e) can be configured to switch the electrical connection between the 7th clock terminal (837) and the 5th scan output terminal (845).

[0183] The f-17th transistor (TR17f) can be configured to switch the electrical connection between the 8th clock terminal (838) and the 6th scan output terminal (846).

[0184] The 17th transistors (TR17a to TR17f) can function as output buffers for outputting the i-th to i+5th scan signals (SCAN[i] to SCAN[i+5]).

[0185] The 18th transistor (TR18) may be configured to switch the electrical connection between the first node (SN1) and the third power terminal (823) in response to the voltage of the third node (SN3). When the 18th transistor (TR18) is turned on, a current path may be formed from the first node (SN1) through the 18th transistor (TR18) to the third power terminal (823). By doing so, the voltage of the first node (SN1) may be discharged. The 18th transistor (TR18) may have a double-gate structure in which two transistors are connected in series with each other while sharing a gate electrode. However, embodiments of the present disclosure are not limited thereto, and the 18th transistor (TR18) may be implemented as a single transistor.

[0186] The 19th transistor (TR19) may be configured to switch the electrical connection between the second node (SN2) and the fourth power terminal (824) in response to a signal input to the third carry terminal (813). When the 19th transistor (TR19) is turned on, the voltage of the second node (SN2) may be lowered to the second low voltage (VSS2). By doing so, the first capacitor (C1) may be discharged. The 19th transistor (TR19) may have a double-gate structure in which two transistors are connected in series with each other while sharing a gate electrode. However, embodiments of the present disclosure are not limited thereto, and the 19th transistor (TR19) may be implemented as a single transistor.

[0187] Accordingly, the i-th to i+5th scan signals (SCAN[i] to SCAN[i+5]) can be output through the first to sixth output terminals (841 to 846). And, the Nth carry signal (CR[N]) can be output.

[0188] FIG. 9 is an example of a sense driving circuit (910).

[0189] The sense driving circuit (910) may include a plurality of sense driving integrated circuits. In FIG. 9, for convenience of explanation, the sense driving circuit (910) is shown to include four sense driving integrated circuits (9101 to 9104), but embodiments of the present disclosure are not limited thereto.

[0190] Each of the sense driving integrated circuits (9101 to 9104) corresponds to a stage of the sense driving circuit (910). Each of the sense driving integrated circuits (9101 to 9104) outputs two or more sense signals, and for example, an embodiment is illustrated in which each of the sense driving integrated circuits (9101 to 9104) outputs six sense signals. However, embodiments of the present disclosure are not limited thereto, and each of the sense driving integrated circuits (9101 to 9104) may be configured to output more than six sense signals.

[0191] At least one of the sense driving integrated circuits (9101 to 9104) can receive at least six of the twelve sense clock signals (SS_CLK1 to SS_CLK12). At least one of the sense driving integrated circuits (9101 to 9104) can receive a carry clock signal (CR_CLK). At least one of the sense driving integrated circuits (9101 to 9104) can receive a start signal (VST) or receive a carry signal from a preceding sense driving integrated circuit. At least one of the sense driving integrated circuits (9101 to 9104) can receive a carry signal from a succeeding sense driving integrated circuit.

[0192] The sense driving circuit (910) may include a first sense driving integrated circuit (9101), a second sense driving integrated circuit (9102), an Nth sense driving integrated circuit (9103) (where N is an integer greater than or equal to 1), and a Kth sense driving integrated circuit (9104) (where K is an integer greater than or equal to 1).

[0193] The first sense driving integrated circuit (9101) can receive the first to sixth sense clock signals (SS_CLK1 to SS_CLK6) among the twelve sense clock signals (SS_CLK1 to SS_CLK12). The first sense driving integrated circuit (9101) can receive a carry clock signal (CR_CLK). The first sense driving integrated circuit (9101) can receive a start signal (VST). The first sense driving integrated circuit (9101) can receive a carry signal (CR[2]) from the subsequent second sense driving integrated circuit (9102).

[0194] The first sense driving integrated circuit (9101) can output the first through sixth sense signals (SENSE[1] through SENSE[6]). The first sense driving integrated circuit (9101) can output a carry signal (CR[1]).

[0195] The second sense driving integrated circuit (9102) can receive the 7th to 12th sense clock signals (SS_CLK7 to SS_CLK12) among the twelve sense clock signals (SS_CLK1 to SS_CLK12). The second sense driving integrated circuit (9102) can receive a carry clock signal (CR_CLK). The second sense driving integrated circuit (9102) can receive a carry signal (CR[1]) from the preceding first sense driving integrated circuit (9101). The second sense driving integrated circuit (9102) can receive a carry signal (CR[3]) from the following third sense driving integrated circuit.

[0196] The second sense driving integrated circuit (9102) can output the 7th to 12th sense signals (SENSE[7] to SENSE

[12] ). The second sense driving integrated circuit (9102) can output a carry signal (CR[2]).

[0197] The Nth sense driving integrated circuit (9103) can receive the first to sixth sense clock signals (SS_CLK1 to SS_CLK6) among the twelve sense clock signals (SS_CLK1 to SS_CLK12). The Nth sense driving integrated circuit (9103) can receive a carry clock signal (CR_CLK). The Nth sense driving integrated circuit (9103) can receive a carry signal (CR[N-1]) from the preceding N-1st sense driving integrated circuit. The Nth sense driving integrated circuit (9103) can receive a carry signal (CR[N+1]) from the subsequent N+1th sense driving integrated circuit.

[0198] The Nth sense driving integrated circuit (9103) can output the i-th to i+5th sense signals (SENSE[i] to SENSE[i+5]). The Nth sense driving integrated circuit (9103) can output a carry signal (CR[N]).

[0199] The Kth sense driving integrated circuit (9104) can receive the 7th to 12th sense clock signals (SS_CLK7 to SS_CLK12) among the twelve sense clock signals (SS_CLK1 to SS_CLK12). The Kth sense driving integrated circuit (9104) can receive a carry clock signal (CR_CLK). The Kth sense driving integrated circuit (9104) can receive a carry signal (CR[K-1]) from the preceding K-1st sense driving integrated circuit. The Kth sense driving integrated circuit (9104) can receive a carry signal (CR[K+1]) from the succeeding K+1st sense driving integrated circuit.

[0200] The Kth sense driving integrated circuit (9104) can output m-5th to mth sense signals (SENSE[m-5] to SENSE[m]). The Kth sense driving integrated circuit (9104) can output a carry signal (CR[K]).

[0201] In the drawings below, starting from Figure 10, the configuration and driving method of the Nth sense driving integrated circuit (9103) are described in more detail as an example. The configuration and driving method of the Nth sense driving integrated circuit (9103) can be similarly applied to other sense driving integrated circuits included in the sense driving circuit (910).

[0202] FIG. 10 is an equivalent circuit diagram of a sense driving integrated circuit (1000) according to one embodiment.

[0203] Referring to FIG. 10, a sense driving integrated circuit (1000) according to embodiments of the present disclosure may include one or more terminals, one or more transistors, and one or more capacitors. Below, the configuration of a sense driving integrated circuit (1000) according to one embodiment is described.

[0204] The first transistor (TR1) may be configured to switch the electrical connection between the second power terminal (1022) and the first node (SN1) in response to a signal input to the first carry terminal (1011). A start signal (VST) or a carry signal (CR[N-1]) from the previous stage may be input to the first carry terminal (1011). A second high voltage (VGH2) may be applied to the second power terminal (1022). The second high voltage (VGH2) may be the turn-on level voltage of the 16 transistors (T16a to T16f). In one embodiment, the first transistor (TR1) may have a double-gate structure in which two transistors are connected in series with each other while sharing a gate electrode. However, embodiments of the present disclosure are not limited thereto, and the first transistor (TR1) may be implemented as a single transistor.

[0205] The second transistor (TR2) may be configured to switch the electrical connection between the first power terminal (1021) and the first node (SN1) in response to a signal input to the third carry terminal (1013). The carry signal (CR[N+1]) of the next stage may be input to the third carry terminal (1013). A first high voltage (VGH1) may be applied to the first power terminal (1021). The voltage level of the first high voltage (VGH1) may be lower than the voltage level of the second power voltage (VGH2). For example, the first high voltage (VGH1) may be the turn-off level voltage of the 16 transistors (T16a to T16f). The voltage level of the first high voltage (VGH1) may be higher than the voltage level of the first low voltage (VSS1).

[0206] The third transistor (TR3) can be configured to switch the electrical connection between the second power terminal (1022) and the second node (SN2) in response to a signal input to the first carry terminal (1011).

[0207] The fourth transistor (TR4) may include a gate electrode connected to the first carry terminal (1011). The fourth transistor (TR4) may be configured to switch the electrical connection between the third transistor (TR3) and the first carry terminal (1011). When a start signal (VST) or a carry signal (CR[N-1]) from the previous stage is input, the third transistor (TR3) and the fourth transistor (TR4) may be turned on together. By doing so, a second power supply voltage (VGH2) is applied to the second node (SN2), and the eighth transistor (TR8), the ninth transistor (TR9), the fourteenth transistor (TR14), and the fifteenth transistor (TR15) may be turned on.

[0208] The first to fourth transistors (TR1 to TR4) can form a pre-charge section.

[0209] The fifth transistor (TR5) may be configured to switch the electrical connection between the first power terminal (1021) and the first node (SN1) in response to the voltage applied to the fourth node (SN4). When the fifth transistor (TR5) is turned on, a current path may be formed from the first node (SN1) through the fifth transistor (TR5) toward the first power terminal (1021). By doing so, the voltage of the first node (SN1) may be discharged.

[0210] The sixth transistor (TR6) may be configured to switch the electrical connection between the first power terminal (1021) and the fifth node (SN5) in response to a voltage input to the first power terminal (1021). The first high voltage (VGH1) input to the first power terminal (1021) may be the turn-on level voltage of the sixth transistor (TR6). In one embodiment, the sixth transistor (TR6) may have a double-gate structure in which two transistors are connected in series with each other while sharing a gate electrode. However, the embodiments of the present disclosure are not limited thereto, and the sixth transistor (TR6) may be implemented as a single transistor.

[0211] The seventh transistor (TR7) may be configured to switch the electrical connection between the first power terminal (1021) and the third node (SN3) in response to a voltage applied to the fifth node (SN5). When the seventh transistor (TR7) is turned on, a voltage corresponding to the first high voltage (VGH1) is applied to the third node (SN3), thereby turning on the eleventh transistor (TR11), the twelfth transistor (TR12), the thirteenth transistors (TR13a to TR13f), and the eighth transistor (TR18).

[0212] The eighth transistor (TR8) may be configured to switch the electrical connection between the fourth power terminal (1024) and the third node (SN3) in response to a voltage applied to the second node (SN2). A second low voltage (VSS2) may be applied to the fourth power terminal (1024). When the eighth transistor (TR8) is turned on, the second low voltage (VSS2) is applied to the third node (SN3) so that the tenth transistor (TR10), the eleventh transistor (TR11), the twelfth transistor (TR12), the thirteenth transistors (TR13a to TR13f), and the eighth transistor (TR18) may be turned off.

[0213] The ninth transistor (TR9) may be configured to switch the electrical connection between the third power terminal (1023) and the fifth node (SN5) in response to a voltage applied to the second node (SN2). A first low voltage (VSS1) may be applied to the third power terminal (1023). The eighth transistor (TR8) and the ninth transistor (TR9) may be turned on together in response to the voltage at the second node (SN2). When the ninth transistor (TR9) is turned on, the first low voltage (VSS1) is applied to the fifth node (SN5), causing the seventh transistor (TR7) to be turned off. This allows the first power terminal (1021) and the third node (SN3) to be electrically isolated.

[0214] The tenth transistor (TR10) may be configured to switch the electrical connection between the second node (SN2) and the fourth power terminal (1024) in response to the voltage applied to the third node (SN3). When the tenth transistor (TR10) is turned on, a second low voltage (VSS2) may be applied to the second node (SN2). The second low voltage (VSS2) may be applied to one electrode of the first capacitor (C1) electrically connected to the second node (SN2). By doing so, the voltage of the second node (SN2) may be discharged. The tenth transistor (TR10) may have a double-gate structure in which two transistors are connected in series while sharing a gate electrode. However, embodiments of the present disclosure are not limited thereto, and the tenth transistor (TR10) may be implemented as a single transistor.

[0215] The 6th to 10th transistors (TR6 to TR10) can form an inverter with the 2nd node (SN2) as the input node and the 3rd node (SN3) as the output node.

[0216] The eleventh transistor (TR11) may be configured to switch the electrical connection between the fourth node (SN4) and the fourth power terminal (1024) in response to the voltage of the third node (SN3). When the eleventh transistor (TR11) is turned on, a current path may be formed from the fourth node (SN4) through the eleventh transistor (TR11) to the fourth power terminal (1024). By doing so, the voltage of the fourth node (SN4) may be discharged.

[0217] The 12th transistor (TR12) may be configured to switch the electrical connection between the second carry terminal (1012) and the fourth power terminal (1024) in response to the voltage of the third node (SN3). The carry signal (CR[N]) of the current stage may be output to the second carry terminal (1012). When the 12th transistor (TR12) is turned on, the second low voltage (VSS2) may be output through the second carry terminal (1012).

[0218] The thirteenth transistors (TR13a to TR13f) may be configured to switch the electrical connection between the sense output terminals (1041 to 1046) and the third power terminal (1023) in response to the voltage of the third node (SN3). In one embodiment, the thirteenth transistors (TR13a to TR13f) are composed of six transistors, which may include a-thirteenth transistor (TR13a), b-thirteenth transistor (TR13b), c-thirteenth transistor (TR13c), d-thirteenth transistor (TR13d), e-thirteenth transistor (TR13e), and f-thirteenth transistor (TR13f). However, embodiments of the present disclosure are not limited thereto, and the thirteenth transistors (TR13a to TR13f) may be implemented to include more than six transistors or fewer transistors.

[0219] The a-three-three transistors (TR13a) can be configured to switch the electrical connection between the first sense output terminal (1041) and the third power terminal (1023) that output the i-th sense signal (SENSE[i]).

[0220] The b-th 13th transistor (TR13a) can be configured to switch the electrical connection between the second sense output terminal (1042) and the third power terminal (1023) that output the i+1th sense signal (SENSE[i+1]).

[0221] The c-13th transistor (TR13a) can be configured to switch the electrical connection between the third sense output terminal (1043) and the third power terminal (1023) that outputs the i+2th sense signal (SENSE[i+2]).

[0222] The d-13th transistor (TR13d) can be configured to switch the electrical connection between the 4th sense output terminal (1044) and the 3rd power terminal (1023) that output the i+3rd sense signal (SENSE[i+3]).

[0223] The e-13th transistor (TR13e) can be configured to switch the electrical connection between the 5th sense output terminal (1045) which outputs the i+4th sense signal (SENSE[i+4]) and the 3rd power terminal (1023).

[0224] The f-th 13th transistor (TR13f) can be configured to switch the electrical connection between the 6th sense output terminal (1046) which outputs the i+5th sense signal (SENSE[i+5]) and the 3rd power terminal (1023).

[0225] When the 13th transistors (TR13a to TR13f) are turned on, a first low voltage (VSS1) can be output through the sense output terminals (1041 to 1046).

[0226] The 11th transistor (TR11), the 12th transistor (TR12), and the 13th transistors (TR13a to TR13f) can form a pull-down section.

[0227] The 14th transistor (TR14) may be configured to switch the electrical connection between the first clock terminal (1031) and the fourth node (SN4) in response to the voltage applied to the second node (SN2). A boosting clock signal (BCLK) may be applied to the first clock terminal (1031). When the 14th transistor (TR14) is turned on, the first clock terminal (1031) may be electrically connected to the fourth node (SN4) via the 14th transistor (TR14). When the boosting clock signal (BCLK) is applied to the fourth node (SN4), the voltage of the second node (SN2) may be raised (or boosted) due to the coupling effect of the first capacitor (C1).

[0228] The first capacitor (C1) may include one electrode connected to the second node (SN2) and the other electrode connected to the fourth node (SN4). The first capacitor (C1) may be configured to maintain a voltage difference between the second node (SN2) and the fourth node (SN4). The first capacitor (C1) may be pre-charged by the second high voltage (VGH2). When the voltage of the fourth node (SN4) rises due to the boosting clock signal (BCLK), the voltage of the second node (SN2) may rise due to the coupling effect of the first capacitor (C1).

[0229] The 14th transistor (TR14) and the 1st capacitor (C1) can form a boosting section.

[0230] The 15th transistor (TR15) may be configured to switch the electrical connection between the second clock terminal (1032) and the second carry terminal (1012) in response to the voltage of the second node (SN2). A carry clock signal (CR_CLK) may be input to the second clock terminal (1032). When the 15th transistor (TR15) is turned on, the carry clock signal (CR_CLK) may be output as the current stage carry signal (CR[N]) through the second carry terminal (1012). The 15th transistor (TR15) may function as an output buffer for outputting the current stage carry signal (CR[N]).

[0231] The 16th transistors (TR16a to TR16f) may be configured to switch the electrical connection between the second capacitors (C2a to C2f) and the second node (SN2) in response to the voltage of the first node (SN1). In one embodiment, the 16th transistors (TR16a to TR16f) are composed of six transistors, which may include the a-16th transistor (TR16a), the b-16th transistor (TR16b), the c-16th transistor (TR16c), the d-16th transistor (TR16d), the e-16th transistor (TR16e), and the f-16th transistor (TR16f). However, embodiments of the present disclosure are not limited thereto, and the 16th transistors (TR16a to TR16f) may be implemented to include more than six transistors or fewer transistors.

[0232] The a-16th transistor (TR16a) can be configured to switch the electrical connection between the a-2nd capacitor (C2a) and the second node (SN2).

[0233] The b-16th transistor (TR16b) can be configured to switch the electrical connection between the b-2nd capacitor (C2b) and the 2nd node (SN2).

[0234] The c-16th transistor (TR16c) can be configured to switch the electrical connection between the c-2nd capacitor (C2c) and the 2nd node (SN2).

[0235] The d-16th transistor (TR16d) can be configured to switch the electrical connection between the d-2nd capacitor (C2d) and the 2nd node (SN2).

[0236] The e-16th transistor (TR16e) can be configured to switch the electrical connection between the e-2nd capacitor (C2e) and the 2nd node (SN2).

[0237] The f-16th transistor (TR16f) can be configured to switch the electrical connection between the f-2nd capacitor (C2f) and the 2nd node (SN2).

[0238] When the 16th transistors (TR16a to TR16f) are turned on, the Q nodes (Qa to Qf) are connected to the second node (SN2), thereby providing pre-charged and boosted voltages to the Q nodes (Qa to Qf). When the 16th transistors (T16a to T16f) are turned off, the electrical connection between the Q nodes (Qa to Qf) and the second node (SN2) is isolated, thereby preventing the voltage of adjacent Q nodes from fluctuating while individual voltages are applied to each of the Q nodes (Qa to Qf).

[0239] The second capacitors (C2a to C2f) may be configured to maintain a potential difference between the Q nodes (Qa to Qf) and the fourth node (SN4). In one embodiment, the second capacitors (C2a to C2f) are composed of six capacitors, which may include a second capacitor (C2a), a second capacitor (C2b), a second capacitor (C2c), a second capacitor (C2d), a second capacitor (C2e), and a second capacitor (C2f). However, embodiments of the present disclosure are not limited thereto, and the second capacitors (C2a to C2f) may be implemented to include more than six capacitors or fewer capacitors.

[0240] The a-2nd capacitor (C2a) may include one electrode connected to the aQ node (Qa) and the other electrode connected to the 4th node (SN4).

[0241] The b-2nd capacitor (C2b) may include one electrode connected to the bQ node (Qb) and the other electrode connected to the 4th node (SN4).

[0242] The c-2nd capacitor (C2c) may include one electrode connected to the cQ node (Qc) and the other electrode connected to the 4th node (SN4).

[0243] The d-2nd capacitor (C2d) may include one electrode connected to the dQ node (Qd) and the other electrode connected to the 4th node (SN4).

[0244] The e-2nd capacitor (C2e) may include one electrode connected to the eQ node (Qe) and the other electrode connected to the 4th node (SN4).

[0245] The f-2nd capacitor (C2f) may include one electrode connected to the fQ node (Qf) and the other electrode connected to the 4th node (SN4).

[0246] The second capacitors (C2a to C2f) can perform the function of controlling the i-th to i+5th sense signals (SENSE[i] to SENSE[i+5]) to be stably output through the sense output terminals (1041 to 1046) by maintaining the voltage of the Q nodes (Qa to Qf).

[0247] The 17th transistors (TR17a to TR17f) may be configured to switch the electrical connection between the 3rd to 8th clock terminals (1033 to 1038) and the 1st to 6th sense output terminals (1041 to 1046) in response to a corresponding voltage among the Q nodes (Qa to Qf). The 3rd to 8th clock terminals (1033 to 1038) may receive the 1st to 6th sense clock signals (SS_CLK1 to SS_CLK6). In one embodiment, the 17th transistors (TR17a to TR17f) are composed of six transistors, which may include the a-17th transistor (TR17a), the b-17th transistor (TR17b), the c-17th transistor (TR17c), the d-17th transistor (TR17d), the e-17th transistor (TR17e), and the f-17th transistor (TR17f). However, embodiments of the present disclosure are not limited thereto, and the 17th transistors (TR17a to TR17f) may be implemented to include more than six transistors or fewer transistors.

[0248] The a-17th transistor (TR17a) can be configured to switch the electrical connection between the third clock terminal (1033) and the first sense output terminal (1041).

[0249] The b-17th transistor (TR17b) can be configured to switch the electrical connection between the 4th clock terminal (1034) and the 2nd sense output terminal (1042).

[0250] The c-17th transistor (TR17c) can be configured to switch the electrical connection between the 5th clock terminal (1035) and the 3rd sense output terminal (1043).

[0251] The d-17th transistor (TR17d) can be configured to switch the electrical connection between the 6th clock terminal (1036) and the 4th sense output terminal (1044).

[0252] The e-17th transistor (TR17e) can be configured to switch the electrical connection between the 7th clock terminal (1037) and the 5th sense output terminal (1045).

[0253] The f-17th transistor (TR17f) can be configured to switch the electrical connection between the 8th clock terminal (1038) and the 6th sense output terminal (1046).

[0254] The 17th transistors (TR17a to TR17f) can function as output buffers for outputting the i-th to i+5th sense signals (SENSE[i] to SENSE[i+5]).

[0255] The 18th transistor (TR18) may be configured to switch the electrical connection between the first node (SN1) and the third power terminal (1023) in response to the voltage of the third node (SN3). When the 18th transistor (TR18) is turned on, a current path may be formed from the first node (SN1) through the 18th transistor (TR18) to the third power terminal (1023). By doing so, the voltage of the first node (SN1) may be discharged. The 18th transistor (TR18) may have a double-gate structure in which two transistors are connected in series with each other while sharing a gate electrode. However, embodiments of the present disclosure are not limited thereto, and the 18th transistor (TR18) may be implemented as a single transistor.

[0256] The 19th transistor (TR19) may be configured to switch the electrical connection between the second node (SN2) and the fourth power terminal (1024) in response to a signal input to the third carry terminal (1013). When the 19th transistor (TR19) is turned on, the voltage of the second node (SN2) may be lowered to the second low voltage (VSS2). By doing so, the first capacitor (C1) may be discharged. The 19th transistor (TR19) may have a double-gate structure in which two transistors are connected in series with each other while sharing a gate electrode. However, embodiments of the present disclosure are not limited thereto, and the 19th transistor (TR19) may be implemented as a single transistor.

[0257] Accordingly, the i-th to i+5th sense signals (SENSE[i] to SENSE[i+5]) can be output through the first to sixth output terminals (1041 to 1046). And, the Nth carry signal (CR[N]) can be output.

[0258] FIG. 11 is a drawing showing at least a portion of a non-display area (NA) according to one embodiment of the present disclosure. FIG. 12 is a drawing showing at least a portion of a non-display area (NA) according to one embodiment of the present disclosure.

[0259] Referring to FIGS. 11 and 12, various wirings placed in a non-display area (NA), an Nth scan drive integrated circuit (7103), an N+1th scan drive integrated circuit (7105), an Nth sense drive circuit (9103), and an N+1th sense drive integrated circuit (9105) are shown. The Nth scan drive integrated circuit (7103) and the Nth sense drive circuit (9103) can form an Nth stage circuit (1100). The N+1th scan drive integrated circuit (7105) and the N+1th sense drive integrated circuit (9105) can form an N+1th stage circuit (1200).

[0260] In the non-display area (NA), the first to 24 clock lines (WR1 to WR24), the first to 5 side signal lines (SPL1 to SPL5), and stage circuits (1100, 1200) may be sequentially arranged in the first direction (DR1).

[0261] A start signal (VST) and power voltages (VSS1, VSS2, VGH1, VGH2) may be applied to the first to fifth side signal wires (SPL1 to SPL5). For example, a start signal (VST) may be applied to the first side signal wire (SPL1). A first high voltage (VGH1) may be applied to the second side signal wire (SPL2). A second high voltage (VGH2) may be applied to the third side signal wire (SPL3). A first low voltage (VSS1) may be applied to the fourth side signal wire (SPL4). A second low voltage (VSS2) may be applied to the fifth side signal wire (SPL5).

[0262] First to twelfth scan clock signals (SC_CLK1 to SC_CLK12) and first to twelfth sense clock signals (SS_CLK1 to SS_CLK12) may be input to the first to twelfth clock lines (WR1 to WR24). In one embodiment, first to twelfth scan clock signals (SC_CLK1 to SC_CLK12) may be input to the first to twelfth clock lines (WR1 to WR12), and first to twelfth sense clock signals (SS_CLK1 to SS_CLK12) may be input to the thirteenth to twenty-fourth clock lines (WR13 to WR24). However, the embodiments of the present disclosure are not limited thereto. For example, first to twelfth sense clock signals (SS_CLK1 to SS_CLK12) may be input to first to twelfth clock lines (WR1 to WR12), and first to twelfth scan clock signals (SC_CLK1 to SC_CLK12) may be input to thirteenth to twenty-fourth clock lines (WR13 to WR24). For convenience of explanation, an embodiment in which first to twelfth scan clock signals (SC_CLK1 to SC_CLK12) are input to first to twelfth clock lines (WR1 to WR12) and first to twelfth sense clock signals (SS_CLK1 to SS_CLK12) are input to thirteenth to twenty-fourth clock lines (WR13 to WR24) will be described below.

[0263] Each of the first to twelfth clock wires (WR1 to WR12) may receive a corresponding one of the first to twelfth scan clock signals (SC_CLK1 to SC_CLK12). For example, referring to FIGS. 11 and 12, the first scan clock signal (SC_CLK1) may be received in the first clock wire (WR1). The second scan clock signal (SC_CLK2) may be received in the second clock wire (WR2). The third scan clock signal (SC_CLK3) may be received in the third clock wire (WR3). The fourth scan clock signal (SC_CLK4) may be received in the fourth clock wire (WR4). The fifth scan clock signal (SC_CLK5) may be received in the fifth clock wire (WR5). The sixth scan clock signal (SC_CLK6) may be received in the sixth clock wire (WR6). The 7th scan clock signal (SC_CLK7) can be input to the 7th clock wire (WR7). The 8th scan clock signal (SC_CLK8) can be input to the 8th clock wire (WR8). The 9th scan clock signal (SC_CLK9) can be input to the 9th clock wire (WR9). The 10th scan clock signal (SC_CLK10) can be input to the 10th clock wire (WR10). The 11th scan clock signal (SC_CLK11) can be input to the 11th clock wire (WR11). The 12th scan clock signal (SC_CLK12) can be input to the 12th clock wire (WR12).

[0264] Each of the 13th to 24th clock wires (WR13 to WR24) may receive a corresponding one of the 1st to 12th sense clock signals (SS_CLK1 to SS_CLK12). For example, referring to FIGS. 11 and 12, the 13th clock wire (WR13) may receive a 1st sense clock signal (SS_CLK1). The 14th clock wire (WR14) may receive a 2nd sense clock signal (SS_CLK2). The 15th clock wire (WR15) may receive a 3rd sense clock signal (SS_CLK3). The 16th clock wire (WR16) may receive a 4th sense clock signal (SS_CLK4). The 17th clock wire (WR17) may receive a 5th sense clock signal (SS_CLK5). The 6th sense clock signal (SS_CLK6) can be input to the 18th clock wire (WR18). The 7th sense clock signal (SS_CLK7) can be input to the 19th clock wire (WR19). The 8th sense clock signal (SS_CLK8) can be input to the 20th clock wire (WR20). The 9th sense clock signal (SS_CLK9) can be input to the 21st clock wire (WR21). The 10th sense clock signal (SS_CLK10) can be input to the 22nd clock wire (WR22). The 11th sense clock signal (SS_CLK11) can be input to the 23rd clock wire (WR23). The 12th sense clock signal (SS_CLK12) can be input to the 24th clock wire (WR24).

[0265] In one embodiment, the first to 24 clock lines (WR1 to WR24) may be positioned adjacently in a first direction (DR1) in sequence. However, embodiments of the present disclosure are not limited thereto, and the arrangement of the first to 24 clock lines (WR1 to WR24) within the non-display area (NA) may be changed according to the design of a person skilled in the art.

[0266] Each of the first to 24 clock lines (WR1 to WR24) may have a dual wiring structure. For example, each of the first to 24 clock lines (WR1 to WR24) may include a first metal layer (MTL1) and a second metal layer (MTL2) positioned perpendicularly to each other. In one embodiment, the first metal layer (MTL1) and the second metal layer (MTL2) of the first to 24 clock lines (WR1 to WR24) may be electrically connected by contacting each other directly or indirectly. Each of the first metal layer (MTL1) and the second metal layer (MTL2) may extend in a second direction (DR2) overall. In one embodiment, the first metal layer (MTL1) may be located on top of the second metal layer (MTL2). In another embodiment, the first metal layer (MTL1) may be located on bottom of the second metal layer (MTL2). By doing so, the resistance of the first to 24 clock wires (WR1 to WR24) can be reduced.

[0267] The second metal layer (MTL2) included in the first to 24 clock wires (WR1 to WR24) may be extended and bent into an opening (OPN) region where at least a portion of the first metal layer (MTL1) is removed, and may be extended in a first direction (DR1) toward the stage circuits (1100, 1200). The region where the second metal layer (MTL2) is bent corresponds to the bending region (BDA), and the bending region (BDA) may overlap at least a portion with the region where the opening (OPN) of the first metal layer (MTL1) is located.

[0268] Meanwhile, the distance from each of the first to 24 clock lines (WR1 to WR24) extending in the second direction (DR2) to the stage circuits (1100, 1200) may differ. If the distance from each of the first to 24 clock lines (WR1 to WR24) to the stage circuits (1100, 1200) differs, the resistance of each line will differ. Accordingly, the degree of voltage drop due to IR drop in each of the first to 24 clock lines (WR1 to WR24) will differ, and the magnitude of the signal output from the stage circuits (1100, 1200) may differ.

[0269] Embodiments of the present disclosure may be configured such that the degree of voltage drop is similar to each other by bending a clock wiring located close to the stage circuits (1100, 1200) in a direction away from the stage circuits (1100, 1200) (e.g., a third direction (DR3)). The third direction (DR3) may, for example, be the opposite direction to the first direction (DR1).

[0270] Referring to FIG. 11, first to sixth clock wires (WR1 to WR6) and thirteenth to eighteenth clock wires (WR13 to WR18) connected to the Nth stage circuit (1100) are shown.

[0271] In one embodiment, among the first to sixth clock lines (WR1 to WR6), the odd-numbered clock lines may be extended in the direction of the bending area (BDA) located on the upper side, and the even-numbered clock lines may be extended in the direction of the bending area (BDA) located on the lower side. For example, the first clock line (WR1), the third clock line (WR3), and the fifth clock line (WR5) may be extended in the direction of the bending area (BDA) located on the upper side, and the second clock line (WR2), the fourth clock line (WR4), and the sixth clock line (WR6) may be extended in the direction of the bending area (BDA) located on the lower side. However, embodiments of the present disclosure are not limited thereto, and the odd-numbered clock lines may be extended in the direction of the bending area (BDA) located on the lower side, and the even-numbered clock lines may be extended in the direction of the bending area (BDA) located on the upper side.

[0272] Below, the odd-numbered clock wires among the 1st to 6th clock wires (WR1 to WR6) are described.

[0273] The first clock wiring (WR1) can be extended in the second direction (DR2) from the bending region (BDA) of the second metal layer (MTL2), and can be bent once and extended in the first direction (DR1).

[0274] The third clock wiring (WR3) can be extended in the second direction (DR2) from the bending region (BDA) of the second metal layer (MTL2), extended in the third direction (DR3) by a first bend, extended in the second direction (DR2) by a second bend, and extended in the first direction (DR1) by a third bend. The region where the third clock wiring (WR3) is extended in the second direction (DR2) by a second bend may overlap with the opening (OPN) provided in the first metal layer (MTL1) of the second clock wiring (WR2).

[0275] The fifth clock wiring (WR5) can be extended in the second direction (DR2) from the bending region (BDA) of the second metal layer (MTL2), bent once to extend to the third direction (DR3), bent a second time to extend to the second direction (DR2), and bent a third time to extend to the first direction (DR1). The region where the fifth clock wiring (WR5) is bent a second time to extend to the second direction (DR2) can overlap with the opening (OPN) provided in the first metal layer (MTL1) of the third clock wiring (WR3).

[0276] In one embodiment, the length of the area where the second metal layer (MTL2) of the first clock wiring (WR1) is first bent and extended in the first direction (DR1) may be substantially the same as the sum of the length of the area where the second metal layer (MTL2) of the third clock wiring (WR3) is first bent and extended in the third direction (DR3) and the length of the area where the third clock wiring (WR3) is third bent and extended in the first direction (DR1).

[0277] Similarly, the length of the area where the second metal layer (MTL2) of the first clock wire (WR1) is first bent and extended in the first direction (DR1) may be substantially the same as the sum of the length of the area where the second metal layer (MTL2) of the fifth clock wire (WR5) is first bent and extended in the third direction (DR3) and the length of the area where the fifth clock wire (WR5) is third bent and extended in the first direction (DR1).

[0278] Meanwhile, the area where the third clock wire (WR3) is first bent and extended to the third direction (DR3) and the area where the fifth clock wire (WR5) is first bent and extended to the third direction (DR3) may be located adjacent to each other in the first direction (DR1).

[0279] In one embodiment, among the 13th to 18th clock lines (WR13 to WR18), the odd-numbered clock lines may be extended in the direction of the bending area (BDA) located on the upper side, and the even-numbered clock lines may be extended in the direction of the bending area (BDA) located on the lower side. For example, the 13th clock line (WR13), the 15th clock line (WR15), and the 17th clock line (WR17) may be extended in the direction of the bending area (BDA) located on the upper side, and the 14th clock line (WR14), the 16th clock line (WR16), and the 18th clock line (WR18) may be extended in the direction of the bending area (BDA) located on the lower side. However, embodiments of the present disclosure are not limited thereto, and the odd-numbered clock lines may be extended in the direction of the bending area (BDA) located on the lower side, and the even-numbered clock lines may be extended in the direction of the bending area (BDA) located on the upper side.

[0280] Below, the odd-numbered clock wires among the 13th to 18th clock wires (WR13 to WR18) are described.

[0281] The 13th clock wiring (WR13) can be extended in the second direction (DR2) from the bending region (BDA) of the second metal layer (MTL2), and can be bent once to extend in the first direction (DR1).

[0282] The 15th clock wiring (WR15) can be extended in a second direction (DR2) from a bending region (BDA) where the second metal layer (MTL2) is bent, extended in a third direction (DR3), bent again to extend in a second direction (DR2), and bent a third time to extend in a first direction (DR1). The region where the 15th clock wiring (WR15) is bent again to extend in a second direction (DR2) can overlap with an opening (OPN) provided in the first metal layer (MTL1) of the 14th clock wiring (WR14).

[0283] The 17th clock wiring (WR17) can be extended in a second direction (DR2) from a bending region (BDA) where the second metal layer (MTL2) is bent, extended in a third direction (DR3), bent again to extend in a second direction (DR2), and bent a third time to extend in a first direction (DR1). The region where the 17th clock wiring (WR17) is bent again to extend in a second direction (DR2) can overlap with an opening (OPN) provided in the first metal layer (MTL1) of the 16th clock wiring (WR16).

[0284] In one embodiment, the length of the area where the second metal layer (MTL2) of the 13th clock wire (WR13) is bent and extended in the first direction (DR1) may be substantially the same as the sum of the length of the area where the second metal layer (MTL2) of the 15th clock wire (WR15) is bent once and extended in the third direction (DR3) and the length of the area where the 15th clock wire (WR15) is bent three times and extended in the first direction (DR1).

[0285] Similarly, the length of the area where the second metal layer (MTL2) of the 13th clock wire (WR13) is bent and extended in the first direction (DR1) may be substantially the same as the sum of the length of the area where the second metal layer (MTL2) of the 17th clock wire (WR17) is bent once and extended in the third direction (DR3) and the length of the area where the 17th clock wire (WR17) is bent three times and extended in the first direction (DR1).

[0286] Meanwhile, the area where the 15th clock wire (WR15) is first bent and extended to the third direction (DR3) and the area where the 17th clock wire (WR17) is first bent and extended to the third direction (DR3) may be located adjacent to each other in the first direction (DR1).

[0287] On the other hand, on the first direction (DR1) from the area where the third clock wire (WR3) is first bent and extends to the third direction (DR3), the area where the fifth clock wire (WR5) is first bent and extends to the third direction (DR3), the area where the 15th clock wire (WR15) is first bent and extends to the third direction (DR3), and the area where the 17th clock wire (WR17) is first bent and extends to the third direction (DR3) may all be located. By doing so, seven horizontal wires including the second metal layer (MTL2) are located in one bent area (BDA), thereby minimizing the size of the bent area (BDA).

[0288] Below, the even-numbered clock wires among the 1st to 6th clock wires (WR1 to WR6) are described.

[0289] The second clock wiring (WR2) can be extended in the opposite direction of the second direction (DR2) from the bending region (BDA) of the second metal layer (MTL2), and can be bent once and extended to the first direction (DR1).

[0290] The fourth clock wiring (WR4) can be extended in the opposite direction of the second direction (DR2) at the bending region (BDA) of the second metal layer (MTL2), bent once to extend to the third direction (DR3), bent a second time to extend in the opposite direction of the second direction (DR2), and bent a third time to extend to the first direction (DR1). The region where the fourth clock wiring (WR4) is bent a second time to extend in the opposite direction of the second direction (DR2) may overlap with the opening (OPN) provided in the first metal layer (MTL1) of the third clock wiring (WR3).

[0291] The sixth clock wiring (WR6) can be extended in the opposite direction of the second direction (DR2) at the bending region (BDA) of the second metal layer (MTL2), bent once to extend to the third direction (DR3), bent a second time to extend in the opposite direction of the second direction (DR2), and bent a third time to extend to the first direction (DR1). The region where the sixth clock wiring (WR6) is bent a second time to extend in the opposite direction of the second direction (DR2) may overlap with the opening (OPN) provided in the first metal layer (MTL1) of the fourth clock wiring (WR4).

[0292] In one embodiment, the length of the area where the second metal layer (MTL2) of the second clock wiring (WR2) is first bent and extended in the first direction (DR1) may be substantially the same as the sum of the length of the area where the second metal layer (MTL2) of the fourth clock wiring (WR4) is first bent and extended in the third direction (DR3) and the length of the area where the fourth clock wiring (WR4) is third bent and extended in the first direction (DR1).

[0293] Similarly, the length of the area where the second metal layer (MTL2) of the second clock wiring (WR2) is bent and extended in the first direction (DR1) may be substantially the same as the sum of the length of the area where the second metal layer (MTL2) of the sixth clock wiring (WR6) is bent once and extended in the third direction (DR3) and the length of the area where the sixth clock wiring (WR6) is bent three times and extended in the first direction (DR1).

[0294] Meanwhile, the area where the third clock wire (WR3) is first bent and extended to the third direction (DR3) and the area where the fifth clock wire (WR5) is first bent and extended to the third direction (DR3) may be located adjacent to each other in the first direction (DR1).

[0295] Below, the even-numbered clock wires among the 13th to 18th clock wires (WR13 to WR18) are described.

[0296] The 14th clock wiring (WR14) can be extended in the opposite direction of the second direction (DR2) at the bending region (BDA) of the second metal layer (MTL2), and can be bent once and extended to the first direction (DR1).

[0297] The 16th clock wiring (WR16) can be extended in the opposite direction of the second direction (DR2) at the bending region (BDA) of the second metal layer (MTL2), bent once to extend to the third direction (DR3), bent twice to extend to the second direction (DR2), and bent a third time to extend to the first direction (DR1). The region where the 16th clock wiring (WR16) is bent twice to extend to the second direction (DR2) may overlap with the opening (OPN) provided in the first metal layer (MTL1) of the 15th clock wiring (WR15).

[0298] The 18th clock wiring (WR18) can be extended in the opposite direction of the second direction (DR2) at the bending region (BDA) of the second metal layer (MTL2), bent once to extend to the third direction (DR3), bent a second time to extend in the opposite direction of the second direction (DR2), and bent a third time to extend to the first direction (DR1). The region where the 18th clock wiring (WR18) is bent a second time to extend to the second direction (DR2) may overlap with the opening (OPN) provided in the first metal layer (MTL1) of the 17th clock wiring (WR17).

[0299] In one embodiment, the length of the area where the second metal layer (MTL2) of the 14th clock wire (WR14) is bent and extended in the first direction (DR1) may be substantially the same as the sum of the length of the area where the second metal layer (MTL2) of the 16th clock wire (WR16) is bent once and extended in the third direction (DR3) and the length of the area where the 16th clock wire (WR16) is bent three times and extended in the first direction (DR1).

[0300] Similarly, the length of the area where the second metal layer (MTL2) of the 14th clock wire (WR14) is bent and extended in the first direction (DR1) may be substantially the same as the sum of the length of the area where the second metal layer (MTL2) of the 18th clock wire (WR18) is bent once and extended in the third direction (DR3) and the length of the area where the 18th clock wire (WR18) is bent three times and extended in the first direction (DR1).

[0301] Meanwhile, the area where the 16th clock wire (WR16) is first bent and extended to the third direction (DR3) and the area where the 18th clock wire (WR18) is first bent and extended to the third direction (DR3) may be located adjacent to each other in the first direction (DR1).

[0302] On the other hand, on the first direction (DR1) from the area where the fourth clock wire (WR4) is first bent and extends to the third direction (DR3), the area where the sixth clock wire (WR6) is first bent and extends to the third direction (DR3), the area where the 16th clock wire (WR16) is first bent and extends to the third direction (DR3), and the area where the 18th clock wire (WR18) is first bent and extends to the third direction (DR3) may all be located. By doing so, seven horizontal wires including the second metal layer (MTL2) are located in one bent area (BDA), thereby minimizing the size of the bent area (BDA). Additionally, the difference in resistance between the first to sixth clock wires (WR1 to WR6) and the difference in resistance between the 13th to 18th clock wires (WR13 to WR18) may be reduced.

[0303] Referring to FIG. 12, in at least part of the non-display area (NA), the 7th to 12th clock wires (WR7 to WR12) and the 19th to 24th clock wires (WR19 to WR24) can be connected to the N+1th stage circuit (1200).

[0304] The 7th to 12th clock wires (WR7 to WR12) may be connected to the N+1th stage circuit (1200) in a manner similar to how the 1st to 6th clock wires (WR1 to WR6) are connected to the Nth stage circuit (1100). The 19th to 24th clock wires (WR19 to WR24) may be connected to the N+1th stage circuit (1200) in a manner similar to how the 13th to 18th clock wires (WR13 to WR18) are connected to the Nth stage circuit (1100).

[0305] Accordingly, the description of the 7th to 12th clock wires (WR7 to WR12) is replaced by the description of the 1st to 6th clock wires (WR1 to WR6) mentioned above, and the description of the 19th to 24th clock wires (WR19 to WR24) is replaced by the description of the 13th to 18th clock wires (WR13 to WR18) mentioned above.

[0306] By doing so, the size of the bending area (BDA) can be minimized. Additionally, the difference in resistance between the 7th to 12th clock lines (WR7 to WR12) can be reduced, and the difference in resistance between the 19th to 24th clock lines (WR19 to WR24) can be reduced.

[0307] Referring to FIGS. 11 and 12, by increasing the area of ​​the region where the first metal layer (MTL1) and the second metal layer (MTL2) overlap in each of the first to 24 clock lines (WR1 to WR24), the overall resistance of the first to 24 clock lines (WR1 to WR24) can be reduced, which may be advantageous in terms of power consumption.

[0308] The first to fifth side signal wires (SP1 to SP5) may include a first metal layer (MTL1).

[0309] FIG. 13 is a drawing showing at least a portion of a non-display area (NA) according to another embodiment of the present disclosure. FIG. 14 is a drawing showing at least a portion of a non-display area (NA) according to another embodiment of the present disclosure.

[0310] Referring to FIG. 13, the first to 24 clock wires (WR1 to WR24) are arranged, but compared with FIG. 11 and FIG. 12 described above, the arrangement of the first to 12 clock wires (WR1 to WR12) may be different.

[0311] For example, starting from the left end of the non-display area (NA), the 7th to 12th clock lines (WR7 to WR12) may be arranged sequentially adjacently in the first direction (DR1), and the 1st to 6th clock lines (WR1 to WR6) may be arranged sequentially adjacently in the first direction (DR1). From the 6th clock line (WR6) to the first direction (DR1), the 13th to 24th clock lines (WR13 to WR24) may be arranged sequentially.

[0312] Referring to FIG. 13, a second metal layer (MTL2) of any one of the first to sixth clock wires (WR1 to WR6) and a second metal layer (MTL2) of any one of the thirteenth to eighteenth clock wires (WR13 to WR18) may be paired and extended in a second direction (DR2). The second metal layer (MTL2) extended in the second direction (DR2) may be bent in a first direction (DR1) within an opening (OPN) of the first metal layer (MTL1) and connected to the Nth stage (1100).

[0313] For example, the 6th clock wire (WR6) and the 13th clock wire (WR13) can form a pair. The 5th clock wire (WR5) and the 14th clock wire (WR14) can form a pair. The 4th clock wire (WR4) and the 15th clock wire (WR15) can form a pair. The 3rd clock wire (WR3) and the 16th clock wire (WR16) can form a pair. The 2nd clock wire (WR2) and the 17th clock wire (WR17) can form a pair. The 1st clock wire (WR1) and the 18th clock wire (WR18) can form a pair.

[0314] The second metal layer (MTL2) of each of the two paired clock lines extends in the first direction (DR1) and can be positioned in a vertically overlapping direction with the first to fifth side signal lines (SPL1 to SPL5).

[0315] Referring to FIG. 14, a second metal layer (MTL2) of any one of the 7th to 12th clock wires (WR7 to WR12) and a second metal layer (MTL2) of any one of the 19th to 24th clock wires (WR19 to WR24) may be paired and extended in a second direction (DR2). The second metal layer (MTL2) extended in the second direction (DR2) may be bent in a first direction (DR1) within an opening (OPN) of the first metal layer (MTL1) and connected to the N+1th stage (1200).

[0316] For example, the 12th clock wire (WR12) and the 19th clock wire (WR19) can form a pair. The 11th clock wire (WR11) and the 20th clock wire (WR20) can form a pair. The 10th clock wire (WR10) and the 21st clock wire (WR21) can form a pair. The 9th clock wire (WR9) and the 22nd clock wire (WR22) can form a pair. The 8th clock wire (WR8) and the 23rd clock wire (WR23) can form a pair. The 7th clock wire (WR7) and the 24th clock wire (WR24) can form a pair.

[0317] The second metal layer (MTL2) of each of the two paired clock lines extends in the first direction (DR1) and can be positioned in a vertically overlapping direction with the first to fifth side signal lines (SPL1 to SPL5).

[0318] In the above embodiment, the first to 24 clock lines (WR1 to WR24) are paired, and in each of the regions where the second metal layer (MTL2) extends in the first direction (DR1), two horizontal lines may be located.

[0319] Meanwhile, referring to FIGS. 13 and 14, among the first to twelfth clock wires (WR1 to WR12), the sixth clock wire (WR6) is located relatively close to the stage circuits (1100, 1200). Conversely, the seventh clock wire (WR7) is located relatively far from the stage circuits (1100, 1200). Accordingly, to reduce the difference in resistance values ​​caused by this, the width of the first to twelfth clock wires (WR1 to WR12) in the second direction (DR2) may differ from one another depending on the length of the second metal layer (MTL2) extending in the first direction (DR1). For example, the width of the first to twelfth clock wires (WR1 to WR12) in the second direction (DR2) may become smaller as the length of the second metal layer (MTL2) extending in the first direction (DR1) increases.

[0320] Likewise, among the 13th to 24th clock wires (WR13 to WR24), the 12th clock wire (WR12) is located relatively close to the stage circuits (1100, 1200). Conversely, the 13th clock wire (WR13) is located relatively far from the stage circuits (1100, 1200). Accordingly, to reduce the difference in resistance values ​​caused by this, the width of the 13th to 24th clock wires (WR13 to WR24) in the second direction (DR2) may differ from one another depending on the length of the second metal layer (MTL2) extending in the first direction (DR1). For example, the width of the 13th to 24th clock wires (WR13 to WR24) in the second direction (DR2) may become smaller as the length of the second metal layer (MTL2) extending in the first direction (DR1) increases.

[0321] FIG. 15 is a drawing showing the first region (AR1) of FIG. 13. FIG. 16 is a drawing showing the second region (AR2) of FIG. 13. FIG. 17 is a drawing showing the third region (AR3) of FIG. 14.

[0322] The first to third regions (AR1 to AR3) are regions that overlap in the vertical direction with the lateral signal lines (SPL1 to SP5). The following description refers to the aforementioned FIGS. 13 and FIGS. 14 together.

[0323] Referring to FIG. 15, the first region (AR1) is a region where the second metal layer (MTL2) of the sixth clock wire (WR6) and the second metal layer (MTL2) of the thirteenth clock wire (WR13) extend in the first direction (DR1).

[0324] The sixth clock wire (WR6) is the clock wire located closest to the stage circuits (1100, 1200) among the first to twelfth clock wires (WR1 to WR12). In the above case, the width of the sixth clock wire (WR6) in the second direction (DR2) may have a twelfth vertical width (WD12). This may be the smallest value among the widths of the second metal layer (MTL2) extending in the first direction (DR1) in each of the first to twelfth clock wires (WR1 to WR12).

[0325] The 13th clock wire (WR13) is the clock wire located furthest from the stage circuits (1100, 1200) among the 13th to 24th clock wires (WR13 to WR24). In the above case, the width of the 13th clock wire (WR13) in the second direction (DR2) may have a first vertical width (WD1). This may be the largest value among the widths of the second metal layer (MTL2) extending in the first direction (DR1) in each of the 13th to 24th clock wires (WR13 to WR24).

[0326] Meanwhile, each of the first to fifth side signal lines (SPL1 to SPL5) may be provided with a predetermined groove (GRV) in the first metal layer (MTL1). By such a groove (GRV), the area of ​​the region where the first metal layer (MLT1) of each of the first to fifth side signal lines (SPL1 to SPL5) overlaps with the second metal layer (MTL2) of the first to 24 clock lines (WR1 to WR24) can be controlled.

[0327] Referring to FIG. 15, in the area where at least one of the first to fifth side signal wires (SPL1 to SPL5) overlaps with the sixth clock wire (WR6), the width in the first direction (DR1) may be the 12th horizontal width (SD12). Accordingly, the area of ​​the region where the sixth clock wire (WR6) and at least one of the first to fifth side signal wires (SPL1 to SPL5) overlap may be defined as the value obtained by multiplying the 12th vertical width (WD12) and the 12th horizontal width (SD12).

[0328] In addition, in the area where at least one of the first to fifth side signal wires (SPL1 to SPL5) overlaps with the 13th clock wire (WR13), the width in the first direction (DR1) may be the first horizontal width (SD1). Accordingly, the area of ​​the region where the 13th clock wire (WR13) and at least one of the first to fifth side signal wires (SPL1 to SPL5) overlap may be defined as the value obtained by multiplying the first vertical width (WD1) and the first horizontal width (SD1).

[0329] In the above embodiment, the value obtained by multiplying the 12th vertical width (WD12) and the 12th horizontal width (SD12) may be equal to the value obtained by multiplying the 1st vertical width (WD1) and the 1st horizontal width (SD1). Accordingly, the capacitance values ​​formed by the 1st to 5th side signal wires (SPL1 to SPL5) of the 6th clock wire (WR6) and the 13th clock wire (WR13) can be controlled to be substantially the same.

[0330] Referring to FIG. 16, the second region (AR2) is a region where the second metal layer (MTL2) of the fifth clock wiring (WR5) and the second metal layer (MTL2) of the fourth clock wiring (WR14) extend in the first direction (DR1).

[0331] The fifth clock wire (WR5) is the clock wire located second closest to the stage circuits (1100, 1200) among the first to twelfth clock wires (WR1 to WR12). In the above case, the width of the fifth clock wire (WR5) in the second direction (DR2) may have a first vertical width (WD11). This may be the second smallest value among the widths of the second metal layer (MTL2) extending in the first direction (DR1) in each of the first to twelfth clock wires (WR1 to WR12).

[0332] The 14th clock wire (WR14) is the clock wire located second furthest from the stage circuits (1100, 1200) among the 13th to 24th clock wires (WR13 to WR24). In the above case, the width of the 14th clock wire (WR14) in the second direction (DR2) may have a second vertical width (WD2). This may be the second largest value among the widths of the second metal layer (MTL2) extending in the first direction (DR1) in each of the 13th to 24th clock wires (WR13 to WR24).

[0333] Referring to FIG. 16, in the area where at least one of the first to fifth side signal wires (SPL1 to SPL5) overlaps with the fifth clock wire (WR5), the width in the first direction (DR1) may be the eleventh horizontal width (SD11). Accordingly, the area of ​​the region where the fifth clock wire (WR5) and at least one of the first to fifth side signal wires (SPL1 to SPL5) overlap may be defined as the value obtained by multiplying the eleventh vertical width (WD11) and the eleventh horizontal width (SD11).

[0334] In addition, in the area where at least one of the first to fifth side signal lines (SPL1 to SPL5) overlaps with the fourth clock line (WR14), the width in the first direction (DR1) may be the second horizontal width (SD2). Accordingly, the area of ​​the region where the fourth clock line (WR14) and at least one of the first to fifth side signal lines (SPL1 to SPL5) overlap may be defined as the value obtained by multiplying the second vertical width (WD2) and the second horizontal width (SD2).

[0335] In the above embodiment, the value obtained by multiplying the 11th vertical width (WD11) and the 11th horizontal width (SD11) may be equal to the value obtained by multiplying the 2nd vertical width (WD2) and the 2nd horizontal width (SD2). Accordingly, the capacitance values ​​formed by the 1st to 5th side signal wires (SPL1 to SPL5) of the 5th clock wire (WR5) and the 14th clock wire (WR14) can be controlled to be substantially the same.

[0336] Referring to FIG. 17, the third region (AR3) is a region where the second metal layer (MTL2) of the 7th clock wiring (WR7) and the second metal layer (MTL2) of the 24th clock wiring (WR24) extend in the first direction (DR1).

[0337] The seventh clock wire (WR7) is the clock wire located furthest from the stage circuits (1100, 1200) among the first to twelfth clock wires (WR1 to WR12). In the above case, the width of the seventh clock wire (WR7) in the second direction (DR2) may have a first vertical width (WD1). This may be the largest value among the widths of the second metal layer (MTL2) extending in the first direction (DR1) in each of the first to twelfth clock wires (WR1 to WR12).

[0338] The 24th clock wire (WR24) is the clock wire located closest to the stage circuits (1100, 1200) among the 13th to 24th clock wires (WR13 to WR24). In the above case, the width of the 24th clock wire (WR24) in the second direction (DR2) may have a 12th vertical width (WD12). This may be the smallest value among the widths of the second metal layer (MTL2) extending in the first direction (DR1) in each of the 13th to 24th clock wires (WR13 to WR24).

[0339] Referring to FIG. 17, in the area where at least one of the first to fifth side signal wires (SPL1 to SPL5) overlaps with the seventh clock wire (WR7), the width in the first direction (DR1) may be the first horizontal width (SD1). Accordingly, the area of ​​the region where the seventh clock wire (WR7) and at least one of the first to fifth side signal wires (SPL1 to SPL5) overlap may be defined as the value obtained by multiplying the first vertical width (WD1) and the first horizontal width (SD1).

[0340] In addition, in the area where at least one of the first to fifth side signal wires (SPL1 to SPL5) overlaps with the 24th clock wire (WR24), the width in the first direction (DR1) may be the 12th horizontal width (SD12). Accordingly, the area of ​​the region where the 24th clock wire (WR24) and at least one of the first to fifth side signal wires (SPL1 to SPL5) overlap may be defined as the value obtained by multiplying the 12th vertical width (WD12) and the 12th horizontal width (SD12).

[0341] Accordingly, the width in the second direction (DR2) of each of the areas where the two horizontal lines described in the aforementioned FIGS. 13 and 14 are arranged can be substantially the same.

[0342] In the above embodiment, the magnitude of the capacitance formed in the region where each of the first to twelfth clock lines (WR1 to WR12) overlaps with the first to fifth side signal lines (SPL1 to SPL5) can all be controlled to be the same (or substantially the same). Also, the magnitude of the capacitance formed in the region where each of the thirteenth to twenty-fourth clock lines (WR13 to WR24) overlaps with the first to fifth side signal lines (SPL1 to SPL5) can all be controlled to be the same (or substantially the same).

[0343] Accordingly, the resistance between the first to twelfth clock lines (WR1 to WR12) can be configured to be substantially the same, and the resistance between the thirteenth to twenty-fourth clock lines (WR13 to WR24) can be configured to be substantially the same.

[0344] In addition, the capacitance values ​​between the first to 24th clock wires (WR1 to WR24) can be configured to be substantially the same.

[0345] Accordingly, the time delay values ​​that may occur in the first to twelfth clock lines (WR1 to WR12) can be controlled substantially equally. Likewise, the time delay values ​​that may occur in the thirteenth to twenty-fourth clock lines (WR13 to WR24) can be controlled substantially equally. Accordingly, the display quality can be improved.

[0346] Furthermore, according to embodiments of the present disclosure, a narrow bezel of a display device (100; see FIG. 1) or a display panel (110; see FIG. 1) can be implemented by eliminating the space provided between the clock signal wires (WR1 to WR24) and the stage circuits (1100, 1200) to make the lengths of the clock signal wires (WR1 to WR24) equal.

[0347] The drawings and detailed description of the invention referenced so far are merely exemplary of the invention and are used only for the purpose of explaining the invention, not to limit the meaning or the scope of the invention as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0348] 100: Display device 110: Display panel 120: Data driving circuit 130: Gate driving circuit 140: Timing Controller 150: Power supply circuit 710: Scan driving circuit 800: Scan driver integrated circuit 910: Sense driving circuit 1000: Sense driver integrated circuit 1100, 1200: Stage circuit WR1, ..., WR24: Clock wiring SPL1, ..., SPL5: Side signal wiring ED: Electronic device

Claims

Claim 1 A display device comprising: clock wires to which a clock signal is input, including a first metal layer and a second metal layer positioned in a vertical direction overlapping the first metal layer; side signal wires including the first metal layer extending in a second direction and positioned adjacent to the clock wires in a first direction; and stage circuits positioned adjacent to the side signal wires in the first direction and connected to the clock wires and the side signal wires, wherein at least one of the clock wires is bent at least once in a third direction opposite to the first direction at an opening where at least a portion of the first metal layer is removed. Claim 2 A display device according to claim 1, wherein the Nth stage circuit (N is an integer greater than or equal to 1) among the stage circuits comprises an Nth scan driving integrated circuit and an Nth sense driving integrated circuit, and the clock wiring comprises first to sixth clock wirings connected to the Nth stage circuit; and 13th to 18th clock wirings connected to the Nth stage circuit. Claim 3 In paragraph 2, the first to sixth clock wires are sequentially positioned adjacently in the first direction, and the second metal layer of the first clock wire extends in the second direction and is first bent, and then extends in the second direction. Claim 4 In paragraph 3, the second metal layer of the third clock wiring is extended in the second direction and then bent once, then extended in the third direction, then extended in the second direction and then bent twice, then extended in the second direction, and then extended in the first direction after being bent three times in the second direction. Claim 5 In claim 4, the second metal layer of the third clock wiring is a display device in which the region extending in the second direction after the second bending is positioned to overlap with the opening of the second clock wiring in a vertical direction. Claim 6 In claim 4, the second metal layer of the fifth clock wiring extends in the second direction and is bent once, then extends in the third direction, extends in the third direction and is bent twice, then extends in the second direction, and extends in the second direction and is bent three times, then extends in the first direction. Claim 7 In claim 6, the area where the second metal layer of the third clock wiring is first bent and extends in the third direction, and the area where the second metal layer of the fifth clock wiring is first bent and extends in the third direction are a display device located adjacent to the first direction. Claim 8 In claim 6, the second metal layer of the fifth clock wiring is a display device in which the region extending in the second direction after the second bending is positioned to overlap with the opening of the third clock wiring in a vertical direction. Claim 9 A display device according to claim 4, wherein the length of the region extending in the second direction after the first clock wiring is bent is the same as the sum of the length of the region extending in the third direction after the second metal layer of the third clock wiring is bent first, and the length of the region extending in the first direction after the second metal layer of the third clock wiring is bent third. Claim 10 In paragraph 3, the second metal layer of the second clock wiring is a display device that extends in the opposite direction of the second direction, is first bent, and then extends in the second direction. Claim 11 A display device according to paragraph 2, wherein the N+1th stage circuit among the stage circuits comprises an N+1th scan driving integrated circuit and an N+1th sense driving integrated circuit, and the clock wiring comprises 7th to 12th clock wirings connected to the N+1th stage circuit; and 19th to 24th clock wirings connected to the N+1th stage circuit. Claim 12 In claim 1, the stage circuit comprises a plurality of output buffers configured to output clock signals input to the clock wires, and at least two of the transistors for controlling each of the plurality of output buffers are controlled in response to a voltage applied to one node. Claim 13 An electronic device comprising: a host that outputs a control signal and first image data; and a display device that displays an image based on the control signal and the first image data, wherein the display device comprises: clock wires to which a clock signal provided based on the control signal is input, the first metal layer and a second metal layer positioned in a vertical direction overlapping the first metal layer; side signal wires to which the first metal layer is positioned adjacent to the clock wires in a first direction and extends in a second direction; and stage circuits to which the clock wires and the side signal wires are connected, the side signal wires and the side signal wires are positioned adjacent to the side signal wires in the first direction. At least one of the clock wires is such that the second metal layer is bent at least once in a third direction opposite to the first direction at an opening where at least a portion of the first metal layer is removed. Claim 14 A display device comprising: clock wires to which a clock signal is input, including a first metal layer and a second metal layer positioned in a vertical direction overlapping the first metal layer; side signal wires including the first metal layer that is positioned adjacent to the clock wires in a first direction and extends in a second direction; and stage circuits that are positioned adjacent to the side signal wires in the first direction and connected to the clock wires and the side signal wires, wherein one of the clock wires located further from the stage circuits has a first vertical width, and the other of the clock wires located closer to the stage circuits has a second vertical width smaller than the first vertical width. Claim 15 In claim 14, the Nth stage circuit (where N is an integer greater than or equal to 1) among the stage circuits comprises an Nth scan driving integrated circuit and an Nth sense driving integrated circuit, and the clock wiring comprises first and second clock wirings connected to the Nth stage circuit; and 13th and 14th clock wirings connected to the Nth stage circuit. Claim 16 A display device according to claim 15, wherein the second metal layer of each of the first clock wiring and the second clock wiring is extended in the second direction and then bent in the second direction, and the length of the area where the first clock wiring is extended in the second direction is longer than the length of the area where the second clock wiring is extended in the second direction. Claim 17 A display device according to claim 16, wherein the area where the first clock wiring extends in the second direction has the first vertical width, and the area where the second clock wiring extends in the second direction has the second vertical width. Claim 18 A display device according to claim 17, wherein the second metal layer of each of the 13th clock wiring and the 14th clock wiring is extended in the second direction and then bent in the second direction, and the length of the area where the 13th clock wiring is extended in the second direction is longer than the length of the area where the 14th clock wiring is extended in the second direction. Claim 19 A display device according to claim 18, wherein the area where the 13th clock wiring extends in the second direction has the first vertical width, and the area where the 14th clock wiring extends in the second direction has the second vertical width. Claim 20 A display device according to claim 14, wherein any one of the side signal lines has a first horizontal width in an area overlapping with any one of the clock lines located further away from the stage circuits, and has a second horizontal width greater than the first horizontal width in an area overlapping with any one of the clock lines located closer to the stage circuits.

Images