Pixel of image sensor and method of manufacturing the same

Abstract

A pixel of an image sensor comprises a photoelectric conversion region disposed on the lower side of a semiconductor substrate, a floating diffusion region disposed on the upper side of the semiconductor substrate, a transmission gate, and a pixel transistor. The transmission gate comprises a lower transmission gate disposed on the semiconductor substrate and an upper transmission gate disposed on the lower transmission gate. The pixel gate comprises a first source-drain region and a second source-drain region disposed on the upper side of the semiconductor substrate, and a pixel gate disposed on the semiconductor substrate between the first source-drain region and the second source-drain region. The pixel gate comprises a lower pixel gate and an upper pixel gate disposed on the lower pixel gate. By adopting a dual-gate structure including a lower gate and an upper gate having a smaller size than the lower gate, the electrical characteristics of the pixel and the image sensor can be improved by reducing the coupling capacitance between the gate and other components.

Description

Technology Field

[0001] The present invention relates to a semiconductor integrated circuit, and more specifically, to a pixel of an image sensor and a method for manufacturing an image sensor. Background Technology

[0002] A CMOS image sensor is a solid-state imaging device using a Complementary Metal-Oxide Semiconductor (CMOS). Compared to CCD image sensors that have high-voltage analog circuits, CMOS image sensors have the advantages of lower manufacturing costs and lower power consumption due to their small size, so they are mainly installed in electronic products including portable devices such as smartphones and digital cameras.

[0003] The pixel array constituting a CMOS image sensor includes a photoelectric conversion element, such as a photodiode, for each pixel. The photoelectric conversion element generates an electrical signal that varies according to the amount of incident light, and the CMOS image sensor can process this electrical signal to synthesize an image. Recently, due to the demand for high-resolution images, the pixels constituting the CMOS image sensor are required to be smaller. As this demand for miniaturization increases, incident light may not be properly sensed, or noise may occur due to interference between the integrated elements. The problem to be solved

[0004] One objective of the present invention to solve the above-mentioned problems is to provide a pixel of an image sensor having improved electrical characteristics.

[0005] In addition, one objective of the present invention is to provide a method for manufacturing an image sensor comprising a pixel having improved electrical characteristics. means of solving the problem

[0006] To achieve the above objective, a pixel of an image sensor according to embodiments of the present invention comprises a photoelectric conversion region disposed on the lower part of a semiconductor substrate, a floating diffusion region disposed on the upper part of the semiconductor substrate, a transmission gate, and a pixel transistor. The transmission gate comprises a lower transmission gate disposed on the semiconductor substrate and an upper transmission gate disposed on the lower transmission gate. The pixel gate comprises a first source-drain region and a second source-drain region disposed on the upper part of the semiconductor substrate, and a pixel gate disposed on the semiconductor substrate between the first source-drain region and the second source-drain region. The pixel gate comprises a lower pixel gate and an upper pixel gate disposed on the lower pixel gate.

[0007] To achieve the above objective, a method for manufacturing an image sensor including a pixel according to embodiments of the present invention comprises the steps of: forming a gate insulating layer on a semiconductor substrate; performing a first deposition process to form a first poly layer on the insulating layer; patterning the first poly layer to simultaneously form a lower transmission gate and a lower pixel gate; performing a second deposition process to form a second poly layer on the lower transmission gate and the lower pixel gate; and patterning the second poly layer to simultaneously form an upper transmission gate and an upper pixel gate on the lower transmission gate and the lower pixel gate.

[0008] To achieve the above objective, an image sensor according to embodiments of the present invention comprises a pixel array including a plurality of pixels that collect photocharges generated by incident light and perform a sensing operation, a row driving unit that drives the pixel array in a row-by-row manner, and a control unit that controls the pixel array and the row driving unit. Each pixel of the plurality of pixels comprises a photoelectric conversion region disposed on the lower part of a semiconductor substrate, a floating diffusion region disposed on the upper part of the semiconductor substrate, a transmission gate including a lower transmission gate disposed on the semiconductor substrate and an upper transmission gate disposed on the lower transmission gate, a first source-drain region and a second source-drain region disposed on the upper part of the semiconductor substrate, and a pixel gate disposed on the semiconductor substrate between the first source-drain region and the second source-drain region. The pixel gate comprises a pixel transistor including a lower pixel gate and an upper pixel gate disposed on the lower pixel gate. Effects of the invention

[0009] A pixel of an image sensor according to embodiments of the present invention can improve the electrical characteristics of the pixel and the image sensor by adopting a dual gate structure including a lower gate and an upper gate having a size smaller than that of the lower gate, thereby reducing the coupling capacitance between the gate and other components.

[0010] In addition, the pixels of the image sensor according to the embodiments of the present invention can efficiently improve the electrical characteristics of the pixels and the image sensor without excessive changes to the existing design by changing only the size and position of the upper gate while maintaining the layout of the lower gate. Brief explanation of the drawing

[0011] FIG. 1 is a vertical cross-sectional view showing a pixel of an image sensor according to embodiments of the present invention. FIG. 2 is a diagram showing a gate included in a pixel of an image sensor according to embodiments of the present invention. FIGS. 3a to 3l are cross-sectional views illustrating a method for manufacturing an image sensor according to embodiments of the present invention. FIGS. 4a and 4b are drawings showing embodiments of the arrangement of an upper gate in a pixel of an image sensor according to embodiments of the present invention. FIG. 5a is a block diagram showing an image sensor according to embodiments of the present invention. FIG. 5b is a circuit diagram showing one embodiment of a unit circuit included in an image sensor according to embodiments of the present invention. FIG. 5c is a timing diagram showing an example of the sensing operation of an image sensor according to embodiments of the present invention. FIG. 6 is a drawing showing an example of the configuration of pixels and a readout circuit according to embodiments of the present invention. FIG. 7 is a drawing showing one embodiment of the layout of an image sensor according to embodiments of the present invention. Figure 8 is a cross-sectional view showing a vertical structure along the line A1-A1' of Figure 7. Figure 9 is a drawing showing an enlarged view of the CX1 portion of Figure 8. FIG. 10 is a plan view showing the CX2 portion of FIG. 7 as seen from the first vertical level of FIG. 8. FIG. 11 is a plan view showing part CX2 of FIG. 7 as seen from the second vertical level of FIG. 8. FIGS. 12a and 12b are drawings showing embodiments of a pixel element isolation film included in an image sensor according to embodiments of the present invention. FIGS. 13 to 20 are cross-sectional views illustrating a method for manufacturing an image sensor according to embodiments of the present invention. FIG. 21 is a perspective view showing an image sensor according to embodiments of the present invention. FIG. 22 is a block diagram showing an electronic device according to embodiments of the present invention. FIG. 23 is a block diagram showing a camera module included in the electronic device of FIG. 22. Specific details for implementing the invention

[0012] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are given the same reference numerals, and redundant descriptions of identical components are omitted.

[0013] FIG. 1 is a vertical cross-sectional view showing a pixel of an image sensor according to embodiments of the present invention, and FIG. 2 is a drawing showing a gate included in a pixel of an image sensor according to embodiments of the present invention.

[0014] FIG. 1 illustrates a single pixel surrounded by a pixel element isolation film (120) that defines a plurality of pixels. The pixel element isolation film (120) may be formed inside a pixel trench penetrating the semiconductor substrate (110) from the upper surface or first surface (110F1) of the semiconductor substrate (110) to the lower surface or second surface (110F2).

[0015] Referring to FIG. 1, the pixel (PX) of the image sensor may include a photoelectric conversion region (PD), a floating diffusion region (FD), a transmission gate (TG), and a pixel transistor (PXT) formed using a semiconductor substrate (110). FIG. 1 illustrates only the components for explaining embodiments of the present invention for convenience of illustration and explanation, and more detailed configurations of the image sensor and pixel will be described later with reference to FIG. 5a to 12b.

[0016] A photoelectric conversion region (PD), such as a photodiode, can be placed on the lower part of the semiconductor substrate (11), and a floating diffusion region (FD) can be placed on the upper part of the semiconductor substrate (110). For example, if the semiconductor substrate (110) has a P-type conductivity, the photoelectric conversion region (PD) and the floating diffusion region (FD) may have an N-type conductivity.

[0017] A transmission gate (TG) may include a lower transmission gate (150) disposed on a semiconductor substrate (100) and an upper transmission gate (151) disposed on the lower transmission gate (150). FIG. 1 illustrates that the lower transmission gate (150) is a vertical transmission gate comprising a horizontal portion disposed on the upper surface of the semiconductor substrate (110) and a vertical portion extending into the interior of the semiconductor substrate (110), but embodiments of the present invention are not limited thereto. According to embodiments, the lower transmission gate (150) may be implemented as a planar type that does not include the vertical portion.

[0018] The pixel transistor (PXT) may include a first source-drain region (SD1), a second source-drain region (SD1), and a pixel gate (PG). For example, if the semiconductor substrate (110) has a P-type conductivity, the first source-drain region (SD1) and the second source-drain region (SD1) may have an N-type conductivity. The pixel transistor (PXT) may correspond to a reset transistor (RX), a select transistor (SX), or a source follower transistor (SF) as described below.

[0019] A first source-drain region (SD1) and a second source-drain region (SD1) are disposed on the upper surface of a semiconductor substrate (110), and a pixel gate (PG) may be disposed on the semiconductor substrate (110) between the first source-drain region (SD1) and the second source-drain region (SD1). The pixel gate (PG) may include a lower pixel gate (140) disposed on the semiconductor substrate (100) and an upper pixel gate (141) disposed on the lower pixel gate (140). Although a planar type lower pixel gate (140) is shown in FIG. 1, according to embodiments, the lower pixel gate (140) may be implemented as a vertical transmission gate including a horizontal portion and a vertical portion, such as the lower transmission gate (150) shown in FIG. 1.

[0020] A gate insulating layer (142) is disposed on the upper surface of a semiconductor substrate (110), and gate structures such as a transmission gate (TG) and a pixel gate (PG) can be disposed on the gate insulating layer (142). Meanwhile, components such as a pixel transistor (PXT) and a floating diffusion region (FD) can be isolated from each other by a device isolation film (STI) disposed on the upper surface of the semiconductor substrate (110).

[0021] Each vertical contact (CA) may be disposed on the upper pixel gate (141) and upper transmission gate (151) to which a signal is applied. The upper pixel gate (141) and the upper transmission gate (151) may be connected to metal lines (MPT) disposed in the metal layer (ML) through the vertical contacts (CA). Additionally, junctions (SD1, SD2, FD) to which voltage is applied or voltage is detected may be connected to metal lines (MPT) disposed in the metal layer (ML) through the vertical contacts (CB).

[0022] FIG. 2 illustrates a gate (GT) corresponding to a pixel gate (PG) and a planar type transmission gate (TG). As described above with reference to FIG. 1, the gate (GT) may include a lower gate (GB) and an upper gate (GU). The lower gate (GB) corresponds to the lower pixel gate (140) and lower transmission gate (150) of FIG. 1, and the upper gate (GU) corresponds to the upper pixel gate (141) and upper transmission gate (151) of FIG. 1.

[0023] Referring to FIG. 2, the size (h2) in the horizontal direction parallel to the upper surface of the semiconductor substrate (110) of the upper gate (GU) may be smaller than the size (h1) in the horizontal direction of the lower gate (GB). In other words, referring again to FIG. 1, the size (h2) in the horizontal direction of the upper transmission gate (151) may be smaller than the size (h1) in the horizontal direction of the lower transmission gate (150), and the size (h2) in the horizontal direction of the upper pixel gate (141) may be smaller than the size (h1) in the horizontal direction of the lower transmission gate (140).

[0024] In one embodiment, the thickness (t2) in the vertical direction perpendicular to the upper surface of the semiconductor substrate (110) of the upper gate (GU) may be greater than the thickness (t1) in the vertical direction of the lower gate (GB). In other words, referring again to FIG. 1, the thickness (t2) in the vertical direction of the upper transmission gate (151) may be greater than the thickness (t1) in the vertical direction of the lower transmission gate (150), and the thickness (t2) in the vertical direction of the upper pixel gate (141) may be greater than the thickness (t1) in the vertical direction of the lower pixel gate (140).

[0025] The horizontal position of the upper gate (GU) on the lower gate (GB) can be determined by considering the relationship with adjacent components. Embodiments regarding the arrangement of the upper gate (GU) on the lower gate (GB) will be described later with reference to FIGS. 4a and 4b.

[0026] In this way, the pixel (PX) of the image sensor according to the embodiments of the present invention can improve the electrical characteristics of the pixel and the image sensor by adopting a dual gate structure including a lower gate (GB) and an upper gate (GU) having a size smaller than that of the lower gate (GB), thereby reducing the coupling capacitance between the gate and other components.

[0027] In addition, the pixel (PX) of the image sensor according to the embodiments of the present invention can efficiently improve the electrical characteristics of the pixel and the image sensor without excessive changes to the existing design by changing only the size and position of the upper gate (GU) while maintaining the layout of the lower gate (GB).

[0028] FIGS. 3a to 3l are cross-sectional views illustrating a method for manufacturing an image sensor according to embodiments of the present invention.

[0029] Referring to FIGS. 3a and 3b, a first mask (MSK1) is formed on the upper surface of a semiconductor substrate (110) (i.e., the first surface (110F1) of FIG. 1), and the first mask (MSK1) is used as an etching mask to form an opening (150B) corresponding to a vertical portion of a lower transmission gate (150) extending from the upper surface of the semiconductor substrate (110) into the interior of the semiconductor substrate (110). Afterward, the first mask (MSK1) can be removed.

[0030] Referring to FIG. 3c, a gate insulating layer (142) can be formed on the upper surface of the semiconductor substrate (110) and on the inner wall of the opening (150B), and a first deposition process can be performed to form a first poly layer (PC1) on the gate insulating layer (142). The thickness (t1) of the first poly layer (PC1) can be set to be as small as possible within a range that can sufficiently fill the opening (150B). The horizontal portion of the lower transmission gate (150) positioned on the upper surface of the semiconductor substrate (110) and the vertical portion extending into the interior of the semiconductor substrate (110) can be formed simultaneously by the first deposition process. The thickness (t1) of the first poly layer (PC1) corresponds to the thickness in the vertical direction of the lower gate (GB) described with reference to FIG. 2.

[0031] Referring to FIGS. 3d and 3e, a second mask (MSK2) is formed on a first polylayer (PC1), and the first polylayer (PC1) is patterned using the second mask (MSK2) as an etching mask to form a lower pixel gate (140) and a lower transmission gate (150). In this way, the lower pixel gate (140) and the lower transmission gate (150) can be formed simultaneously by patterning the first polylayer (PC1) formed by the first deposition process. As described above, the lower transmission gate (150) may include a horizontal portion (HG) disposed on the upper surface of the semiconductor substrate (110) and a vertical portion (VG) extending into the interior of the semiconductor substrate (110).

[0032] Referring to FIG. 3f, a third mask (MSK3) is formed on the gate insulating layer (142), and a first ion implantation process (IMP1) is performed using the third mask (MSK3) as an ion implantation mask to simultaneously dope the lower pixel gate (140) and the lower transmission gate (150). Afterward, the third mask (MSK3) is removed to form the lower pixel gate (140) and the lower transmission gate (150) doped with impurities as shown in FIG. 3g.

[0033] Referring to FIG. 3h, a second deposition process can be performed to form a second polylayer (PC2) on the gate insulating layer (142), the lower pixel gate (140), and the lower transmission gate (150). The thickness (t2) of the second polylayer (PC2) can be set to be as small as possible within the range where a vertical contact (CA) can be formed. The thickness (t2) of the second polylayer (PC2) corresponds to the thickness in the vertical direction of the upper gate (GB) described with reference to FIG. 2. As shown in FIG. 1, the vertical contact (CA) can be formed by penetrating a portion of the upper pixel gate (141) and the upper transmission gate (151). Taking this into consideration, the thickness (t2) of the second polylayer (PC2) can be set to be greater than the thickness of the first polylayer (PC1).

[0034] Referring to FIGS. 3i and 3j, a fourth mask (MSK4) is formed on the second polylayer (PC2), and the second polylayer (PC2) is patterned using the fourth mask (MSK4) as an etching mask to form an upper pixel gate (141) and an upper transmission gate (151). In this way, the upper pixel gate (141) and the upper transmission gate (151) can be formed simultaneously by patterning the second polylayer (PC2) formed by the second deposition process.

[0035] Afterward, the fourth mask (MSK4) can be removed and a fifth mask (MSK5) can be formed on the gate insulating layer (142), the lower pixel gate (140), and the lower transmission gate (150). The upper pixel gate (141) and the upper transmission gate (151) can be simultaneously doped by performing a second ion implantation process (IMP2) using the fifth mask (MSK5) as an ion implantation mask. Afterward, the fifth mask (MSK5) can be removed to form the pixel gate (PG) and transmission gate (TG) doped with impurities as shown in FIG. 3k.

[0036] In this way, the vertical portion extending into the semiconductor substrate (110) of the lower transmission gate (150) can be efficiently doped by the first ion implantation process (IMP1) of FIG. 3f. Subsequently, the upper transmission gate (151) for the vertical contact (CA) can be efficiently doped by the second ion implantation process (IMP2) of FIG. 3j. According to the embodiments, at least one of the impurity type and doping concentration of the second ion implantation process (IMP2) may be different from the impurity type and doping concentration of the first ion implantation process (IMP1).

[0037] In one embodiment, as shown in FIG. 3L, a sixth mask (MSK6) can be formed after forming the upper pixel gate (141) and the upper transmission gate (151). The lower pixel gate (140), the upper pixel gate (141), the lower transmission gate (150), and the upper transmission gate (151) can be doped simultaneously by performing a single ion implantation process (IMP) using the sixth mask (MSK) as an ion implantation mask.

[0038] FIGS. 4a and 4b are drawings showing embodiments of the arrangement of an upper gate in a pixel of an image sensor according to embodiments of the present invention.

[0039] In one embodiment, the upper gate (GU) of FIG. 2 may be positioned on the end further from the pixel element isolation film for isolation from neighboring pixels among the two ends in the horizontal direction of the lower gate (GB). For example, as shown in FIG. 4a, a pixel element isolation film (120) for isolating a first pixel (PX1) and a second pixel (PX2) may be positioned inside a semiconductor substrate (110), and pixel gates (PG1, PG2) may be positioned adjacent to the pixel element isolation film (120). In this case, the upper pixel gate (141) of the first pixel (PX1) may be positioned on the end further from the pixel element isolation film (120) among the two ends of the lower pixel gate (140). Additionally, the upper pixel gate (146) of the second pixel (PX2) may be positioned on the end further from the pixel element isolation film (120) among the two ends of the lower pixel gate (145). Accordingly, by reducing the opposing area of ​​the sidewalls of the lower pixel gates (140, 145) located relatively close together and placing the upper pixel gates (141, 146) with a relatively large opposing area far apart, the coupling capacitance between the pixel gates (PG1, PG2) can be reduced. By reducing the coupling capacitance, interference of signals and / or voltages associated with the pixel gates (PG1, PG2) can be reduced and electrical characteristics can be improved.

[0040] In one embodiment, as shown in FIG. 4b, the upper transmission gate (151) may be positioned on the end further from the floating diffusion region (FD) among the two ends in the horizontal direction of the lower transmission gate (150). Thus, the coupling capacitance between the floating diffusion region (FD) and the transmission gate (TG) can be reduced, and the conversion gain of the floating diffusion region (FD) can be increased.

[0041] FIG. 5a is a block diagram showing an image sensor according to embodiments of the present invention.

[0042] Referring to FIG. 5a, the image sensor (600) may include a pixel array (620), a row driver (630), an Analog-to-Digital Conversion (ADC) unit (640), a column driver (650), a controller (660), and a reference voltage generator (REF) (670).

[0043] The pixel array (620) includes a plurality of pixels (700) that are each coupled to column lines (COL) and detect incident light to generate analog signals through the column lines (COL). The plurality of pixels may be arranged in a matrix form consisting of a plurality of rows and a plurality of columns. The pixel array (620) may have a structure in which various unit patterns are repeatedly arranged in a first horizontal direction (DR1) and a second horizontal direction (DR2).

[0044] A row driving unit (630) is connected to each row of the pixel array (620) and can generate a driving signal to drive each row. For example, the row driving unit (630) can drive the plurality of pixels included in the pixel array (620) on a row-by-row basis.

[0045] The analog-to-digital converter (640) is connected to each column of the pixel array (620) and converts an analog signal output from the pixel array (620) into a digital signal. The analog-to-digital converter (640) includes a plurality of analog-to-digital converters (641) and can perform a column ADC that converts analog signals output from each column line (COL) into digital signals in parallel (i.e., simultaneously).

[0046] According to an embodiment, the analog-to-digital converter (640) may include a correlated double sampling (CDS) unit for extracting an effective signal component. In one embodiment, the correlated double sampling unit may perform analog double sampling to extract the effective image component based on the difference between an analog reset signal representing a reset component and an analog image signal representing an image component. In another embodiment, the correlated double sampling unit may perform digital double sampling to extract the difference between the two digital signals as the effective image component after converting the analog reset signal and the analog image signal into digital signals, respectively. In yet another embodiment, the correlated double sampling unit may perform dual correlated double sampling, which performs both the analog double sampling and the digital double sampling.

[0047] The column drive unit (650) can sequentially output digital signals from the analog-to-digital converter (640) as output data (Dout).

[0048] The control unit (660) can control the row drive unit (630), the analog-to-digital converter (640), the column drive unit (650), and the reference signal generator (670). The control unit (660) can provide control signals, such as clock signals and timing control signals, required for the operation of the row drive unit (630), the analog-to-digital converter (640), the column drive unit (650), and the reference signal generator (670). In one embodiment, the control unit (660) may include a logic control circuit, a phase lock loop (PLL) circuit, a timing control circuit, and a communication interface circuit.

[0049] The reference signal generation unit (670) can generate a reference signal or a ramp signal having a voltage level that gradually increases or decreases and provide it to the analog-to-digital converter (640).

[0050] FIG. 5b is a circuit diagram showing one embodiment of a unit circuit included in an image sensor according to embodiments of the present invention.

[0051] Referring to FIG. 5b, a unit circuit (700a) corresponding to a single pixel or subpixel may include a photodiode (PD) as a photoelectric conversion element, and may include a transfer transistor (TX) for data reading, a reset transistor (RX), a source follower transistor (SF), and a select transistor (SX).

[0052] The photocharge generated in the photodiode (PD) is transferred to the floating diffusion region (FD) through the transfer transistor (TX). For example, when the transfer control signal (TG) has a first level (e.g., a high level), the transfer transistor (TX) is turned on, and the photocharge generated in the photodiode (PD) can be transferred to the floating diffusion region (FD) through the turned-on transfer transistor (TX).

[0053] The source follower transistor (SF) acts as a source follower buffer amplifier and can amplify a signal corresponding to the charge charged in the floating diffusion region (FD). The select transistor (SX) can transmit the amplified signal, i.e., the pixel signal (Vout), to the column line (COL) in response to the select signal (SEL).

[0054] The floating diffusion region (FD) can be reset by a reset transistor (RX). For example, the reset transistor (RX) can discharge the photocharge stored in the floating diffusion region (FD) in response to a reset signal (RS) at a constant period for Correlated Double Sampling (CDS) operation.

[0055] The reset transistor (RX), source follower transistor (SF), and select transistor (SX) may be distributed among a plurality of pixels or subpixels as described below with reference to FIG. 7. The aforementioned pixel transistor (PXT) may correspond to the reset transistor (RX), source follower transistor (SF), or select transistor (SX).

[0056] FIG. 5b illustrates a unit circuit comprising one photodiode (PD) and four transistors (TX, RX, DX, SX), but embodiments according to the present invention are not limited thereto. In one embodiment, additional transistors may be included in the unit circuit to implement multiple conversion gains, and in this case, the aforementioned pixel transistor (PXT) may correspond to such additional transistors.

[0057] FIG. 5c is a timing diagram showing an example of the sensing operation of an image sensor according to embodiments of the present invention.

[0058] FIG. 5c illustrates a sensing interval (tRPR) corresponding to a sensing operation for one pixel or subpixel. This sensing operation can be performed simultaneously in parallel for multiple pixels corresponding to the same transmission control signal (TG).

[0059] Referring to FIGS. 5a, 5b and 5c, at time t1, the row driver (630) provides a row selection signal (SEL) activated to a logic high level to the pixel array (620) to select one pixel row among a plurality of pixel rows included in the pixel array (620).

[0060] At time t2, the row driver (630) provides a reset control signal (RS) to the selected pixel row, and the control unit (660) provides an up-down control signal (UD) having a logic high level to a plurality of counters included in the analog-to-digital converter (641). At this time, the pixel signal (Vout) output by the pixel array (620) becomes a first analog signal representing a reset component.

[0061] At time t3, the control unit (660) provides a count enable signal (CNT_EN) having a logic high level to the reference signal generator (670), and the reference signal generator (670) begins to decrease the voltage level of the reference signal (Vref) by a slope (a) of a constant magnitude. In addition, the control unit (660) provides a count clock signal (CLKC) to a plurality of counters, and each of the plurality of counters starts a down-counting operation synchronized with the count clock signal (CLKC).

[0062] At time t4, the voltage levels of the reference signal (Vref) and the pixel signal (Vout) become equal, and the comparison signal (CMP) output from the comparator included in the analog-to-digital converter (641) transitions to a logic low level, and the down-counting operation ends. At this time, the counter stores a counting value (-2) corresponding to the reset component (Vrst).

[0063] At time t5, when the count enable signal (CNT_EN) is disabled to a logic low level, the reference signal generator (70) is disabled. The interval from time t3 to time t5 represents the maximum interval for counting the reset component (Vrst) and can be set to correspond to the number of appropriate clock cycles according to the characteristics of the image sensor.

[0064] At time t6, the row driver (630) provides a transmission control signal (TG) to the selected pixel row, and the control unit (660) provides an up-down control signal (UD) having a logic low level to the counters. At this time, the pixel signal (Vout) output by the pixel array (620) becomes a second analog signal representing an image component according to the incident light.

[0065] At time t7, the control unit (660) again provides a count enable signal (CNT_EN) having a logic high level to the reference signal generator (670), and the reference signal generator (670) begins to decrease the voltage level of the reference voltage (Vref) with a slope (a) of the same magnitude as at time t3. Additionally, the control unit (660) provides a count clock signal (CLKC) to the counters, and each of the counters starts an up-counting operation synchronized with the count clock signal (CLKC).

[0066] At time t8, the voltage levels of the reference signal (Vref) and the pixel signal (Vout) become equal, and the comparison signal (CMP) output from the comparator transitions to a logic low level, thereby terminating the up-counting operation. Finally, a digital value (Vsig=15) corresponding to the difference between the first analog signal representing the reset component (Vrst=2) and the second analog signal representing the image component (Vrst+Vsig=17) according to the incident light is stored in the counter, and the digital value (Vsig=15) is output as a digital signal (DS) representing the effective component of the incident light.

[0067] At time t9, when the count enable signal (CNT_EN) is disabled to a logic low level, the reference signal generator (670) is disabled. The interval from time t7 to time t9 represents the maximum interval for counting image components (Vrst+Vsig) and can be set to correspond to an appropriate number of clock cycles depending on the characteristics of the image sensor.

[0068] At time t10, the row driver (630) provides a row selection signal (SEL) disabled at a logic low level to the pixel array (620) to deselect the selected pixel row. Additionally, each of the counters resets the stored counting value.

[0069] Afterwards, the image sensor (600) outputs a digital signal row by row while repeating the operation described above for other rows.

[0070] For the purpose of facilitating an understanding of the present invention, the configuration and sensing operation of an exemplary image sensor have been described with reference to FIGS. 5a to 5c, but the embodiments of the present invention are not limited thereto.

[0071] FIG. 6 is a drawing showing an example of the configuration of pixels and a readout circuit according to embodiments of the present invention.

[0072] FIG. 6 illustrates four subpixels and a readout circuit shared by the four subpixels. The subpixels may each include photoelectric conversion regions (PD1, PD2, PD3, PD4) and transfer transistors (TX1, TX2, TX3, TX4). The readout circuit may include a reset transistor (RX), a select transistor (SX), and a source follower transistor (SF). The reset transistor (RX) may include a reset gate (RG) (see FIG. 7), the select transistor (SX) may include a select gate (SEL) (see FIG. 7), the source follower transistor (SF) may include a source follower gate (SFG) (see FIG. 7), and the transfer transistors (TX1, TX2, TX3, TX4) may include a transfer gate (TG).

[0073] The photoelectric conversion regions (PD1, PD2, PD3, PD4) can each be connected to a floating diffusion region (FD) through transfer transistors (TX1, TX2, TX3, TX4). The photoelectric conversion regions (PD1, PD2, PD3, PD4) can generate and accumulate photocharges in proportion to the amount of light incident from the outside, and photodiodes, phototransistors, photogates, pinned photodiodes (PPD), and combinations thereof may be used.

[0074] The transfer gate (TG) can transfer charges generated in the photoelectric conversion regions (PD1, PD2, PD3, PD4) to the floating diffusion region (FD). The floating diffusion region (FD) can receive and accumulate the charges generated in the photoelectric conversion regions (PD1, PD2, PD3, PD4). The source follower transistor (SF) can be controlled according to the amount of photocharges accumulated in the floating diffusion region (FD).

[0075] The reset transistor (RX) can periodically reset the charges accumulated in the floating diffusion region (FD). The drain electrode of the reset transistor (RX) is connected to the floating diffusion region (FD), and the source electrode is connected to the power supply voltage (VDD1). When the reset transistor (RX) is turned on, the power supply voltage (VDD1) connected to the source electrode of the reset transistor (RX) is delivered to the floating diffusion region (FD). When the reset transistor (RX) is turned on, the charges accumulated in the floating diffusion region (FD) are discharged, and the floating diffusion region (FD) can be reset.

[0076] The source follower transistor (SF) is connected to a current source (not shown) located outside of multiple pixels (PX) and functions as a source follower buffer amplifier, amplifying potential changes in the floating diffusion region (FD) and outputting them to the output line (VOUT).

[0077] The select transistor (SX) can select multiple pixels (PX) on a row-by-row basis, and when the select transistor (SX) is turned on, the power supply voltage (VDD2) can be delivered to the source electrode of the drive transistor (SF).

[0078] FIG. 7 is a drawing showing an example of the layout of an image sensor according to embodiments of the present invention, and FIG. 8 is a cross-sectional view showing a vertical structure along the line A1-A1' of FIG. 7. FIG. 9 is a drawing showing an enlarged view of the CX1 portion of FIG. 8, FIG. 10 is a plan view showing the CX2 portion of FIG. 7 viewed from the first vertical level (LV1) of FIG. 8, and FIG. 11 is a plan view showing the CX2 portion of FIG. 7 viewed from the second vertical level (LV2) of FIG. 8.

[0079] Referring to FIGS. 7 to 11, the active pixel region (APR) includes a plurality of pixels (PX), and a plurality of photoelectric conversion regions (PD) may be disposed within each of the plurality of pixels (PX). In the active pixel region (APR), the plurality of pixels (PX) may be arranged in a matrix shape, forming columns and rows along a first direction (X) parallel to the upper surface of the semiconductor substrate (110) and a second direction (Y) perpendicular to the first direction and parallel to the upper surface of the semiconductor substrate (110).

[0080] A semiconductor substrate (110) may include a first surface (110F1) and a second surface (110F2) that are opposite to each other. Here, for convenience, the surface of the semiconductor substrate (110) on which a color filter (186) is disposed on the upper side is referred to as the second surface (110F2), and the surface opposite to the second surface (110F2) is referred to as the first surface (110F1). However, the technical concept of the present invention is not limited thereto.

[0081] In exemplary embodiments, the semiconductor substrate (110) may include a p-type substrate. For example, the semiconductor substrate (110) may include any one of Si, Ge, SiGe, SiC, GaAs, InAs, and InP. For example, the semiconductor substrate (110) may be made of a p-type silicon substrate. In exemplary embodiments, the semiconductor substrate (110) may include a p-type bulk substrate and a p-type or n-type epitaxial layer grown thereon. In other embodiments, the semiconductor substrate (110) may include an n-type bulk substrate and a p-type or n-type epitaxial layer grown thereon. Alternatively, the semiconductor substrate (110) may be made of an organic plastic substrate. A well region (114) may be disposed within the semiconductor substrate (110) adjacent to the first surface (110F1) of the semiconductor substrate (110). The well region (114) may be a region doped with p-type impurities.

[0082] In the active pixel area (APR), a plurality of pixels (PX) may be arranged in a matrix form within the semiconductor substrate (110). A plurality of photoelectric conversion regions (PD) may be disposed within each of the plurality of pixels (PX). The plurality of photoelectric conversion regions (PD) may be regions where light incident from the second surface (110F2) of the semiconductor substrate (110) is converted into an electrical signal. The plurality of photoelectric conversion regions (PD) may be regions containing n-type impurities.

[0083] A pixel element isolation film (120) is disposed within a semiconductor substrate (110) in an active pixel area (APR), and a plurality of pixels (PX) may be defined by the pixel element isolation film (120). A plurality of photoelectric conversion regions (PD) may be disposed within a single pixel (PX) surrounded by the pixel element isolation film (120). For example, as shown in FIG. 7, a single pixel (PX) may include first to fourth sub-pixel areas (SPX-1, SPX-2, SPX-3, SPX-4), and first to fourth photoelectric conversion regions (PD1, PD2, PD3, PD4) may be disposed within each of the first to fourth sub-pixel areas (SPX-1, SPX-2, SPX-3, SPX-4). A floating diffusion region (FD) may be disposed in the central region of a single pixel (PX). The first to fourth sub-pixel regions (SPX-1, SPX-2, SPX-3, SPX-4) may share a single floating diffusion region (FD), and four photoelectric conversion regions (PD) may be disposed adjacent to the floating diffusion region (FD).

[0084] A pixel element isolation layer (120) may be formed inside a pixel trench (1220T) that penetrates the semiconductor substrate (110) from a first surface (110F1) to a second surface (110F2) of the semiconductor substrate (110). The pixel element isolation layer (120) may include an insulating layer (122) formed conformally on the sidewall of the pixel trench (120T), a conductive layer (124) that fills the inside of the pixel trench (120T) on the insulating layer (122), and an upper insulating layer (126).

[0085] In exemplary embodiments, the insulating layer (122) may include a metal oxide such as hafnium oxide, aluminum oxide, tantalum oxide, etc. In this case, the insulating layer (122) may act as a negative fixed charge layer, but the technical concept of the present invention is not limited thereto. In other embodiments, the insulating layer (122) may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. The conductive layer (124) may include at least one of doped polysilicon, metal, metal silicide, metal nitride, or metal-containing film.

[0086] In exemplary embodiments, the pixel element separator (120) may include a lateral extension (120e) extending in a first direction (X) and a second direction (Y) toward the center of the pixel (PX). The lateral extension (120e) may be positioned between two sub-pixel regions (SPX) positioned along the first direction (X) and between two sub-pixel regions (SPX) positioned along the second direction (Y).

[0087] In exemplary embodiments, the lateral extension portion (120e) positioned in the central region of the pixel (PX) may extend from the second surface (110F2) of the semiconductor substrate (110) to a level lower than the first surface (110F1) of the semiconductor substrate (110) without completely penetrating the semiconductor substrate (110). Accordingly, the lateral extension portion (120e) positioned in the central region of the pixel (PX) may vertically overlap with the second floating diffusion region (FD2) positioned adjacent to the first surface (110F1) of the semiconductor substrate (110) in the central region of the pixel (PX).

[0088] As illustrated exemplarily in FIG. 8, a device isolation film (112) defining an active region (AC) may be formed on a first surface (110F1) of a semiconductor substrate (110). The device isolation film (112) may be disposed within a device isolation trench (112T) formed to a predetermined depth on the first surface (110F1) of the semiconductor substrate (110) and may include an insulating material.

[0089] Pixel transistors (PXT) constituting a pixel circuit may be disposed on the active region (AC). The pixel transistors (PXT) may include a source follower gate (SFG), a select gate (SEL), and a reset gate (RG). On the semiconductor substrate (110), a ground region (GND) and a floating diffusion region (FD) may be defined by a device isolation film (112). The ground region (GND), the floating diffusion region (FD), and the active region (AC) may be disposed spaced apart from each other by the device isolation film (112).

[0090] In some exemplary embodiments, as illustrated in FIG. 7, a first subpixel (SPX-1), a second subpixel (SPX-2), a third subpixel (SPX-3), and a fourth subpixel (SPX-4) may be arranged in a matrix shape. In some exemplary embodiments, the first subpixel (SPX-1) and the second subpixel (SPX-2) may include a transmission gate (TG) and a source follower gate (SF), the third subpixel (SPX-3) may include a transmission gate (TG) and a reset gate (RG), and the fourth subpixel (SPX-4) may include a transmission gate (TG) and a select gate (SEL). However, what is illustrated in FIG. 7 corresponds to the layout of transistors according to some embodiments, and the layout of transistors or the shape of the active region is not limited thereto.

[0091] In exemplary embodiments, a transmission gate (TG) may comprise transmission transistors (TX1–TX4) (see FIG. 6), and the transmission transistors (TX1–TX4) may be configured to transfer charges generated in photoelectric conversion regions (PD1–PD4) to a floating diffusion region (FD). A reset gate (RG) may comprise a reset transistor (RX) (see FIG. 6), and the reset transistor (RX) may be configured to periodically reset the charges stored in the floating diffusion region (FD). A source follower gate (SFG) may comprise a source follower transistor (SF) (see FIG. 6), and the source follower transistor (SF) may act as a source follower buffer amplifier and be configured to buffer a signal according to the charges charged in the floating diffusion region. The select gate (SEL) can be configured with a select transistor (SX) (see FIG. 6), and the select transistor (SX) can perform switching and addressing functions for selecting a pixel (PX).

[0092] A pixel transistor (PXT) may include a gate insulating layer (142) disposed on a first surface (110F1) of a semiconductor substrate (110), a pixel gate electrode (PG) disposed on the gate insulating layer (142), and a source / drain region (SD). The pixel gate electrode (PG) may include a lower pixel gate (140) and an upper pixel gate (141). A spacer (144) may be disposed on the sidewall of the lower pixel gate (140), and no spacer may be disposed on the sidewall of the upper pixel gate (141). A source / drain region (SD) may be disposed inside the semiconductor substrate (110) disposed on the side of the lower pixel gate (140).

[0093] In exemplary embodiments, the pixel gate electrode (PG) may comprise at least one of doped polysilicon, metal, metal silicide, metal nitride, or metal-containing film. The gate insulating layer (142) may comprise silicon oxide or metal oxide. The source / drain region (SD) may be a region doped with n-type impurities.

[0094] The transmission gate (TG) may have a vertical buried gate structure, for example, a dual-type buried gate structure. As the transmission gate (TG) has a dual-type buried gate structure, the effective channel area between the semiconductor substrate (110) and the transmission gate (TG) may be increased. In exemplary embodiments, the transmission gate (TG) may include a lower transmission gate and an upper transmission gate (GU) as described above. The lower transmission gate may include a first buried gate (GB1), a second buried gate (GB2), and a gate connection (GC), and the first buried gate (GB1) and the second buried gate (GB2) may be spaced apart from each other and arranged to extend in a vertical direction (Z) toward the interior of the semiconductor substrate (110).

[0095] As illustrated exemplarily in FIG. 9, the first buried gate opening (GBH1) and the second buried gate opening (GBH2) may be spaced apart from each other and extend into the semiconductor substrate (110) from the first surface (110F1) of the semiconductor substrate (110), and the bottom portions of the first buried gate opening (GBH1) and the second buried gate opening (GBH2) may be surrounded by a photoelectric conversion region (PD). A gate insulating layer (142) may extend from the first surface (110F1) of the semiconductor substrate (110) onto the inner wall of the first buried gate opening (GBH1) and the inner wall of the second buried gate opening (GBH2). The portion of the gate insulation layer (142) disposed on the inner wall of the first buried gate opening (GBH1) and the inner wall of the second buried gate opening (GBH2) may be referred to as the buried gate insulation layer (BGI).

[0096] The first buried gate (GB1) can fill the interior of the first buried gate opening (GBH1) on the buried gate insulating layer (BGI), and the upper surface of the first buried gate (GB1) can be placed at a higher level than the first surface (110F1) of the semiconductor substrate (110). For example, the first buried gate (GB1) includes a first part (P1) placed inside the first buried gate opening (GBH1), and a second part (P2) connected to the first part (P1) and having an upper surface placed in the same plane as the upper surface of the gate connection part (GC), and a spacer (144) can be placed on the side wall of the second part (P2).

[0097] The second buried gate (GB2) can fill the interior of the second buried gate opening (GBH2) on the buried gate insulating layer (BGI), and the upper surface of the second buried gate (GB2) can be placed at a higher level than the first surface (110F1) of the semiconductor substrate (110). For example, the second buried gate (GB2) includes a first part (P3) placed inside the second buried gate opening (GBH2), and a second part (P4) connected to the first part (P3) and having an upper surface placed in the same plane as the upper surface of the gate connection part (GC), and a spacer (144) can be placed on the side wall of the second part (P2).

[0098] The first part (P1) and the third part (P3) correspond to the vertical part of the lower transmission gate described above, and the second part (P2), the gate connection part (GC), and the fourth part (P4) correspond to the horizontal part of the lower transmission gate described above.

[0099] The gate connection portion (GC) may be integrally connected to the first buried gate (GB1) and the second buried gate (GB2) between the first buried gate (GB1) and the second buried gate (GB2). In exemplary embodiments, the gate connection portion (GC) may be positioned between the second portion (P2) of the first buried gate (GB1) and the second portion (P2) of the second buried gate (GB2), and the upper surface of the gate connection portion (GC) may be positioned at a level higher than the upper surface of the first buried gate (GB1) and the upper surface of the second buried gate (GB2). The bottom surface of the gate connection portion (GC) may be positioned at a vertical level higher than the bottom surface of the first buried gate (GB1) and the bottom surface of the second buried gate (GB2), and the bottom surface of the gate connection portion (GC) may be in contact with the upper surface of the gate insulating layer (142).

[0100] The second part (P2) of the first landfill gate (GB1) may have a first width (w11) along the first horizontal direction (D1), the gate connection part (GC) may have a second width (w12) along the first horizontal direction (D1), and the second part (P4) of the second landfill gate (GB2) may have a first width (w13) along the first horizontal direction (D1), and the first width (w11), the second width (w12), and the third width (w13) may be the same as each other. Accordingly, the first landfill gate (GB1), the gate connection part (GC), and the second landfill gate (GB2) may have a line shape extending along the second horizontal direction (D2), and the side walls of the first landfill gate (GB1), the gate connection part (GC), and the second landfill gate (GB2) may be connected to each other on the same plane (i.e., in a straight line).

[0101] As the gate connection portion (GC) is integrally connected to the first buried gate (GB1) and the second buried gate (GB2) between the first buried gate (GB1) and the second buried gate (GB2), the transmission gate (TG) may include a single portion that merges two portions separated from each other at a vertical level lower than the first surface (110F1) of the semiconductor substrate (110) (i.e., a first portion (P1) of the first buried gate (GB1) and a first portion (P3) of the second buried gate (GB2), and the first buried gate (GB1) and the second buried gate (GB2) at a vertical level higher than the first surface (110F1) of the semiconductor substrate (110) (e.g., the first buried gate (GB1) and the second buried gate (GB2) are connected to each other by the gate connection portion (GC)). For example, the transmission gate (TG) can be referred to as a dual-type buried gate structure in that it includes two parts separated from each other at a vertical level lower than the first surface (110F1) of the semiconductor substrate (110).

[0102] A spacer (144) may be disposed on the sidewall of the lower transmission gate (GB1, GC, GB2), and may not be disposed on the sidewall of the upper transmission gate (GU). The spacer (144) may be disposed on the sidewall of the second part (P2) of the first buried gate (GB1) which is disposed at a level higher than the first surface (110F1) of the semiconductor substrate (110), the sidewall of the second part (P2) of the second buried gate (GB2) which is disposed at a level higher than the first surface (110F1) of the semiconductor substrate (110), and the sidewall of the gate connection part (GC). The bottom surface of the spacer (144) may be in contact with the upper surface of the gate insulating layer (142) and may be disposed to surround the entire sidewall portion of the transmission gate (TG) which is disposed at a level higher than the first surface (110F1) of the semiconductor substrate (110). The spacer (144) may have a first width (w21) along the first horizontal direction (D1), and the first width (w21) may be in the range of about 20 to 50 nm, but is not limited thereto.

[0103] The floating diffusion region (FD) may be spaced apart in a horizontal direction (e.g., the first horizontal direction (D1) or the second horizontal direction (D2)) from the sidewall of the transmission gate (TG) (e.g., the sidewall of the first burial gate (GB1) and the sidewall of the second burial gate (GB2)) on one side of the transmission gate (TG).

[0104] In exemplary embodiments, the floating diffusion region (FD) may include a first floating diffusion region (FD1) and a second floating diffusion region (FD2). The second floating diffusion region (FD2) may be placed in the center region of the pixel (PX) and may be shared by the first to fourth subpixels (SPX-1 to SPX-4). The first floating diffusion region (FD1) may be placed between the second floating diffusion region (FD2) and the transmission gate (TG). For example, the first floating diffusion region (FD1) placed within the first fourth subpixel (SPX-1) may include a first portion of a rectangular planar shape that is placed adjacent to the second floating diffusion region (FD2) and extends along the first horizontal direction (D1), and a second portion of a trapezoidal planar shape that is placed adjacent to the transmission gate (TG) and widens as the distance from the transmission gate (TG) decreases.

[0105] As illustrated in FIG. 9, the first floating diffusion region (FD1) may be spaced apart by a first distance (d11) along the first horizontal direction (D1) from one sidewall of the first buried gate (GB1) or from one sidewall of the first buried gate opening (GBH1), and may be spaced apart by a second distance (d12) along the first horizontal direction (D1) from one sidewall of the second buried gate (GB2) or from one sidewall of the first buried gate opening (GBH1). For example, the second distance (d12) may be the same as the first distance (d11) or may have a value approximate to the first distance (d11) due to reasons such as tolerances occurring in the manufacturing process. In exemplary embodiments, the first distance (d11) and the second distance (d12) may be in the range of about 20 to 50 nm, but are not limited thereto.

[0106] An intrinsic semiconductor region (IA) that planarly surrounds a first buried gate (GB1) and a second buried gate (GB2) may be disposed on the semiconductor substrate (110). The intrinsic semiconductor region (IA) may be disposed between a transmission gate (TG) and a first floating diffusion region (FD1). The intrinsic semiconductor region (IA) may refer to a region that is not doped or injected with an intentional dopant, and may refer to a region containing carriers (electrons and holes) inherent within the semiconductor substrate (110).

[0107] As illustrated in FIG. 11, the intrinsic semiconductor region (IA) may include a first region (IA1) surrounding the first buried gate (GB1), a second region (IA2) surrounding the second buried gate (GB2), and a third region (IA3) positioned between the first buried gate (GB1) and the second buried gate (GB2). For example, the first region (IA1) may be positioned to be vertically overlapping with a portion of the spacer (144) positioned on the side wall of the first buried gate (GB1), and the second region (IA2) may be positioned to be vertically overlapping with a portion of the spacer (144) positioned on the side wall of the second buried gate (GB2). The third region (IA3) may be positioned to be vertically overlapping with a portion of the spacer (144) positioned on both side walls of the gate connection (GC). The intrinsic semiconductor region (IA) may correspond to regions that are masked by the transfer gate (TG) and spacer (144) in the process for ion implanting a dopant into the first floating diffusion region (FD1) and thus cannot be ion implanted into the semiconductor substrate (110).

[0108] The intrinsic semiconductor region (IA) has a second width (w22) along the first horizontal direction (D1), and the second width (w22) may be in the range of about 20 to 50 nm, but is not limited thereto. The second width (w22) of the intrinsic semiconductor region (IA) may be the same as the first width (w21) of the spacer (144), or may have a value approximately equal to the first width (w21) due to reasons such as tolerances occurring in the manufacturing process.

[0109] By surrounding the sidewalls of the first buried gate (GB1) and the second buried gate (GB2) with an intrinsic semiconductor region (IA), direct contact between the sidewalls of the first buried gate (GB1) and the second buried gate (GB2) and the first floating diffusion region (FD1) can be prevented. Accordingly, the occurrence of trap sites caused by dopants that may occur when the first floating diffusion region (FD1) directly contacts the sidewalls of the first buried gate (GB1) and the second buried gate (GB2) can be prevented, and noise generation caused by such trap sites can be prevented.

[0110] A buried insulating layer (160) may be disposed on a first surface (110F1) of a semiconductor substrate (110). The buried insulating layer (160) may cover a ground region (GND), a floating diffusion region (FD), a device isolation layer (112), a pixel gate electrode (PG), and a transmission gate (TG). In exemplary embodiments, the buried insulating layer (160) may include silicon nitride or silicon oxynitride.

[0111] A contact (162) penetrating a buried insulating layer (160) may be disposed on a first surface (110F1) of a semiconductor substrate (110). For example, the contact (162) may penetrate the buried insulating layer (160) and be electrically connected to an active region (ACT), a transmission gate (TG), and a pixel gate electrode (PG).

[0112] In exemplary embodiments, a contact (162) may be disposed on the upper surface of the transmission gate (TG). Although the contact (162) is exemplarily shown to be disposed in a position that vertically overlaps with the second buried gate (GB2), in other embodiments it may be disposed on the first buried gate (GB1), and in other embodiments it may be disposed on the gate connection (GC).

[0113] As the transmission gate (TG) has a dual gate structure at a level lower than the first surface (110F1) of the semiconductor substrate (110) and has an integrated structure in which the dual gates are merged into one at a level higher than the first surface (110F1) of the semiconductor substrate (110), it may be unnecessary to form contacts for each of the first buried gate (GB1) and the second buried gate (GB2). That is, compared to a transmission gate having a dual gate structure having two separate contacts, only one contact (162) is required on the transmission gate (TG) according to exemplary embodiments, so the parasitic capacitance between the contact (162) and the floating diffusion region (FD), and the parasitic capacitance between the wiring layer (172) above the contact (162) and the floating diffusion region (FD) can be reduced. Thus, the conversion gain of the image sensor (100) can be improved.

[0114] An upper wiring structure (170) may be disposed on the buried insulating layer (160). The upper wiring structure (170) may be formed as a stacked structure of multiple layers. The upper wiring structure (170) may include a wiring layer (172) and an insulating layer (174) surrounding the wiring layer (172). The wiring layer (172) may include at least one of polysilicon, metal, metal silicide, metal nitride, or metal-containing film, whether or not doped with impurities. For example, the wiring layer (172) may include tungsten, aluminum, copper, tungsten silicide, titanium silicide, tungsten nitride, titanium nitride, doped polysilicon, etc. The insulating layer (174) may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0115] A rear insulating layer (182) may be disposed on a second surface (110F2) of a semiconductor substrate (110). The rear insulating layer (182) may be disposed over substantially the entire area of ​​the second surface (110F2) of the semiconductor substrate (110), and the rear insulating layer (182) may be in contact with the upper surface of a pixel element isolation film (130) disposed at the same level as the second surface (110F2) of the semiconductor substrate (110). In exemplary embodiments, the rear insulating layer (182) may include a metal oxide such as hafnium oxide, aluminum oxide, tantalum oxide, etc. In other embodiments, the rear insulating layer (182) may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant material, etc.

[0116] A passivation layer (184) may be disposed on the rear insulating layer (182), and a color filter (186) and a microlens (188) may be disposed on the passivation layer (184). Optionally, a support substrate (not shown) may be further disposed on the first surface (110F1) of the semiconductor substrate (110).

[0117] Generally, as the size of the pixel (PX) decreases, the size of the mask for the ion implantation process used to form the floating diffusion region (FD) also decreases, making it prone to defects during the mask patterning process. When the transmission gate is formed first and the floating diffusion region (FD) is formed subsequently, the floating diffusion region (FD) is formed to come into contact with the inner wall of the transmission gate trench, which leads to the formation of trap sites caused by dopants and induces noise.

[0118] However, according to exemplary embodiments, a floating diffusion region (FD) can be formed at a position spaced apart from the sidewalls of the first and second buried gates (GB1, GB2) by using a spacer (144) placed on the sidewall of the transmission gate (TG) as a self-alignment mask. Accordingly, noise generation by dopants that may occur when the floating diffusion region (FD) is formed adjacent to the sidewalls of the buried gates (GB1, GB2) can be reduced, and the number of contacts (162) and the length of the wiring layer (172) can be reduced compared to the case where the two buried gates (GB1, GB2) are electrically isolated from each other, so parasitic capacitance is reduced and the conversion gain of the image sensor (100) can be increased.

[0119] FIGS. 12a and 12b are drawings illustrating embodiments of a pixel element isolation film included in an image sensor according to embodiments of the present invention. Hereinafter, descriptions that overlap with the foregoing description are omitted.

[0120] In one embodiment, as shown in FIG. 12a, the lateral extension (120e) of the pixel element isolation film (120) can be completely removed in the vertical direction (Z) from the first surface (110F1) to the second surface (110F2) of the semiconductor substrate (110) in the portion corresponding to the central region (CREG) on the central vertical line (VLZ).

[0121] In another embodiment, as shown in FIG. 12b, the lateral extension (120e) of the pixel element isolation film (120) may have only a portion removed from the front surface (110F1) of the semiconductor substrate (110) corresponding to the central region (CREG) on the central vertical line (VLZ).

[0122] A floating diffusion region (FD) can be placed in a central region (CREG) where a lateral extension (120e) of the pixel element isolation film (120) is removed. Electrons can pass between subpixels through the central region (CREG), and this can be controlled by a potential profile formed on the semiconductor substrate (100) according to the removed length and manufacturing process.

[0123] FIGS. 13 to 20 are cross-sectional views illustrating a method for manufacturing an image sensor according to embodiments of the present invention. Hereinafter, descriptions that overlap with FIGS. 11 are omitted.

[0124] Referring to FIG. 13, a semiconductor substrate (110) is provided. A photoelectric conversion region (PD) can be formed within the semiconductor substrate (110) by an ion implantation process.

[0125] Subsequently, a pixel element isolation film (120) can be formed extending from the first surface (110F1) of the semiconductor substrate (110) into the semiconductor substrate (110). The pixel element isolation film (120) may include a lateral extension portion (120e), and the lateral extension portion (120e) may not be formed up to a predetermined height from the first surface (110F1) of the semiconductor substrate (110) in the center region of the pixel (PX).

[0126] Subsequently, a portion of the first surface (110F1) of the semiconductor substrate (110) is removed to form a device isolation trench (112T), and an insulating material is filled into the device isolation trench (112T) to form a device isolation film (112). An active region (AC), a ground region (GND), and a preliminary floating diffusion region (FDP) can be defined by the device isolation film (112).

[0127] Referring to FIG. 14, a first mask (M10) is formed on a first surface (110F1) of a semiconductor substrate (110), and the first mask (M10) is used as an etching mask to form a first buried gate opening (GBH1) and a second buried gate opening (GBH2) extending from the first surface (110F1) of the semiconductor substrate (110) into the semiconductor substrate (110).

[0128] The first buried gate opening (GBH1) and the second buried gate opening (GBH2) are positioned adjacent to a preliminary floating diffusion region (FDP), and the bottom portions of the first buried gate opening (GBH1) and the second buried gate opening (GBH2) may be surrounded by a photoelectric conversion region (PD). Subsequently, the first mask (M10) can be removed.

[0129] Referring to FIG. 15, a gate insulating layer (142) can be formed on the first surface (110F1) of the semiconductor substrate (110) and on the inner wall of the first buried gate opening (GBH1) and the second buried gate opening (GBH2).

[0130] Subsequently, a first deposition process can be performed on the gate insulating layer (142) to form a gate electrode layer (140L) (the aforementioned first poly layer (PC1)) that fills the first buried gate opening (GBH1) and the second buried gate opening (GBH2). The gate electrode layer (140L) can be formed with an appropriate thickness to sufficiently fill the first buried gate opening (GBH1) and the second buried gate opening (GBH2).

[0131] Afterwards, a second mask (M20) can be formed on the gate electrode layer (140L).

[0132] Referring to FIG. 16, a second mask (M20) can be used as an etching mask to pattern the gate electrode layer (140L) to form a lower pixel gate (140) and a lower transmission gate (GB1, GC, GB2).

[0133] In exemplary embodiments, the lower transmission gate (GB1, GC, GB2) may include a first buried gate (GB1) disposed inside a first buried gate opening (GBH1), a second buried gate (GB2) disposed inside a second buried gate opening (GBH2), and a first gate connection (GC) disposed between the first buried gate (GB1) and the second buried gate (GB2) on a first surface (110F1) of the semiconductor substrate (110). The first buried gate (GB1) and the second buried gate (GB2) may be disposed spaced apart from each other and extended in a vertical direction (Z) toward the interior of the semiconductor substrate (110).

[0134] Afterwards, a second deposition process can be performed to form a gate electrode layer (141L) (the second poly layer (PC2) described above). Then, a third mask (M30) can be formed on the gate electrode layer (141L), and the gate electrode layer (141L) can be patterned using the third mask (M30) as an etching mask to form an upper pixel gate (141) and an upper transmission gate (GU) as shown in FIG. 17.

[0135] Referring to FIGS. 18a and 18b, an ion implantation mask (M40) covering a lower pixel gate (140) and a lower transmission gate (TG) can be formed on a first surface (110F1) of a semiconductor substrate (110). The ion implantation mask (M40) may have an opening (M40H) that exposes a central region of a pixel (PX). The opening (M40H) may be positioned to vertically overlap with a plurality of transmission gates (TG), a spacer (144), and a preliminary floating diffusion region (FDP).

[0136] As the ion implantation mask (M40) has a relatively large opening (M30H), patterning defects in the ion implantation mask (M40) formation process can be prevented.

[0137] Referring to FIG. 19, first and second floating diffusion regions (FD1, FD2) can be formed by injecting a dopant into the area exposed at the opening (M40H) of the ion implantation mask (M30). The first and second floating diffusion regions (FD1, FD2) may have different dopant levels, and the ion implantation process for forming the first and second floating diffusion regions (FD1, FD2) may be performed sequentially.

[0138] According to exemplary embodiments, a dopant may not be injected into the semiconductor substrate (110) covered by a plurality of transmission gates (TG) and spacers (144), and accordingly, an intrinsic semiconductor region (IA) may be formed around the plurality of transmission gates (TG).

[0139] Referring to Fig. 20, the ion implantation mask (M40) can be removed.

[0140] Subsequently, a buried insulating layer (160) covering a pixel gate (PG) and a transmission gate (TG) can be formed on the gate insulating layer (142). Subsequently, a contact (162) electrically connected to an active region (ACT), a transmission gate (TG), and a pixel gate electrode (PG) can be formed by penetrating the buried insulating layer (160).

[0141] Referring again to FIG. 8, a portion of the thickness is removed from the second surface (110F2) of the semiconductor substrate (110), and a rear insulating layer (182) and a passivation layer (184) are formed on the second surface (110F2) of the semiconductor substrate (110), and a color filter (186) and a microlens (188) can be formed on the passivation layer (184).

[0142] FIG. 21 is a perspective view showing an image sensor according to embodiments of the present invention.

[0143] Referring to FIG. 21, the image sensor (100) may be a stacked image sensor comprising a first chip (C1) and a second chip (C2) stacked in a vertical direction. The first chip (C1) may include an active pixel area (APR) and a first pad area (PDR1), and the second chip (C2) may include a peripheral circuit area (PCR) and a second pad area (PDR2).

[0144] A plurality of first pads (PAD1) in the first pad area (PDR1) may be configured to transmit and receive electrical signals to and from external devices, etc. The peripheral circuit area (PCR) may include a logic circuit block (LC) and may include a plurality of CMOS transistors. The peripheral circuit area (PCR) may provide a constant signal to each active pixel (PX) in the active pixel area (APR) or control the output signal at each active pixel (PX). The first pads (PAD1) in the first pad area (PDR1) may be electrically connected by a via structure (VS) of the second pads (PAD2) in the second pad area (PDR2).

[0145] FIG. 22 is a block diagram showing an electronic device according to embodiments of the present invention, and FIG. 23 is a block diagram showing a camera module included in the electronic device of FIG. 22.

[0146] Referring to FIG. 22, the electronic device (1000) may include a camera module group (1100), an application processor (1200), a PMIC (1300), and an external memory (1400).

[0147] The camera module group (1100) may include a plurality of camera modules (1100a, 1100b, 1100c). Although the drawing shows an embodiment in which three camera modules (1100a, 1100b, 1100c) are arranged, the embodiments are not limited thereto. In some embodiments, the camera module group (1100) may be modified to include only two camera modules. Also, in some embodiments, the camera module group (1100) may be modified to include n camera modules (n is a natural number greater than or equal to 4).

[0148] Hereinafter, with reference to FIG. 23, the detailed configuration of the camera module (1100b) will be described in more detail, but the following description may be applied equally to other camera modules (1100a, 1100b) according to the embodiment.

[0149] Referring to FIG. 23, the camera module (1100b) may include a prism (1105), an optical path folding element (OPFE, hereinafter referred to as "OPFE") (1110), an actuator (1130), an image sensing device (1140), and a storage unit (1150).

[0150] The prism (1105) can modify the path of light (L) incident from the outside by including a reflective surface (1107) of a light-reflecting material.

[0151] In some embodiments, the prism (1105) can change the path of light (L) incident in a first direction (X) to a second direction (Y) perpendicular to the first direction (X). Additionally, the prism (1105) can change the path of light (L) incident in the first direction (X) to a second direction (Y) perpendicular to the first direction (X) by rotating the reflective surface (1107) of the light-reflecting material in direction A around the central axis (1106) or by rotating the central axis (1106) in direction B. At this time, the OPFE (1110) can also move in a third direction (Z) perpendicular to the first direction (X) and the second direction (Y).

[0152] In some embodiments, as illustrated, the maximum rotation angle of the prism (1105) in the A direction may be 15 degrees or less in the plus (+) A direction and greater than 15 degrees in the minus (-) A direction, but the embodiments are not limited thereto.

[0153] In some embodiments, the prism (1105) can move in the plus (+) or minus (-) B direction by about 20 degrees, or between 10 and 20 degrees, or between 15 and 20 degrees, where the angle of movement can be moved by the same angle in the plus (+) or minus (-) B direction, or by a nearly similar angle within a range of about 1 degree.

[0154] In some embodiments, the prism (1105) can move the reflective surface (1106) of the light-reflecting material in a third direction (e.g., Z direction) parallel to the extension direction of the central axis (1106).

[0155] OPFE (1110) may include, for example, groups of m (where m is a natural number) optical lenses. The m lenses can be moved in a second direction (Y) to change the optical zoom ratio of the camera module (1100b). For example, when the basic optical zoom ratio of the camera module (1100b) is Z, moving the m optical lenses included in the OPFE (1110) may change the optical zoom ratio of the camera module (1100b) to 3Z or 5Z or an optical zoom ratio of 5Z or more.

[0156] The actuator (1130) can move the OPFE (1110) or the optical lens (hereinafter referred to as the optical lens) to a specific position. For example, the actuator (1130) can adjust the position of the optical lens so that the image sensor (1142) is positioned at the focal length of the optical lens for accurate sensing.

[0157] The image sensing device (1140) may include an image sensor (1142), control logic (1144), and memory (1146). The image sensor (1142) can sense an image of a sensing target using light (L) provided through an optical lens. The control logic (1144) can control the overall operation of the camera module (1100b). For example, the control logic (1144) can control the operation of the camera module (1100b) according to a control signal provided through a control signal line (CSLb).

[0158] The memory (1146) can store information necessary for the operation of the camera module (1100b), such as calibration data (1147). The calibration data (1147) may include information necessary for the camera module (1100b) to generate image data using light (L) provided from the outside. The calibration data (1147) may include, for example, information regarding the degree of rotation described above, information regarding the focal length, information regarding the optical axis, etc. If the camera module (1100b) is implemented in the form of a multi-state camera in which the focal length changes according to the position of the optical lens, the calibration data (1147) may include focal length values ​​for each position (or state) of the optical lens and information related to auto-focusing.

[0159] The storage unit (1150) can store image data sensed through the image sensor (1142). The storage unit (1150) may be placed outside the image sensing device (1140) and may be implemented in a stacked form with the sensor chip constituting the image sensing device (1140). In some embodiments, the storage unit (1150) may be implemented as an EEPROM (Electrically Erasable Programmable Read-Only Memory), but the embodiments are not limited thereto.

[0160] Referring to FIGS. 22 and 23, in some embodiments, each of a plurality of camera modules (1100a, 1100b, 1100c) may include an actuator (1130). Accordingly, each of the plurality of camera modules (1100a, 1100b, 1100c) may include identical or different calibration data (1147) according to the operation of the actuator (1130) included therein.

[0161] In some embodiments, one of the plurality of camera modules (1100a, 1100b, 1100c) camera module (e.g., 1100b) is a camera module in the form of a folded lens including the previously described prism (1105) and OPFE (1110), and the remaining camera modules (e.g., 1100a, 1100b) may be camera modules in the form of a vertical camera module that do not include the prism (1105) and OPFE (1110), but the embodiments are not limited thereto.

[0162] In some embodiments, one of the plurality of camera modules (1100a, 1100b, 1100c) (e.g., 1100c) may be a vertical depth camera that extracts depth information using, for example, IR (Infrared Ray). In this case, the application processor (1200) may generate a 3D depth image by merging image data provided from this depth camera with image data provided from another camera module (e.g., 1100a or 1100b).

[0163] In some embodiments, at least two of the plurality of camera modules (1100a, 1100b, 1100c) may have different field of view angles. In this case, for example, the optical lenses of at least two of the plurality of camera modules (1100a, 1100b, 1100c) may be different from each other, but are not limited thereto.

[0164] Additionally, in some embodiments, the field of view of each of the plurality of camera modules (1100a, 1100b, 1100c) may be different from each other. In this case, the optical lenses included in each of the plurality of camera modules (1100a, 1100b, 1100c) may also be different from each other, but are not limited thereto.

[0165] In some embodiments, each of the plurality of camera modules (1100a, 1100b, 1100c) may be physically separated from one another. That is, instead of the plurality of camera modules (1100a, 1100b, 1100c) dividing and using the sensing area of ​​a single image sensor (1142), an independent image sensor (1142) may be placed inside each of the plurality of camera modules (1100a, 1100b, 1100c).

[0166] Referring again to FIG. 22, the application processor (1200) may include an image processing device (1210), a memory controller (1220), and an internal memory (1230). The application processor (1200) may be implemented separately from a plurality of camera modules (1100a, 1100b, 1100c). For example, the application processor (1200) and the plurality of camera modules (1100a, 1100b, 1100c) may be implemented separately from each other as separate semiconductor chips.

[0167] The image processing device (1210) may include a plurality of sub-image processors (1212a, 1212b, 1212c), an image generator (1214), and a camera module controller (1216).

[0168] The image processing device (1210) may include a plurality of sub-image processors (1212a, 1212b, 1212c) corresponding to the number of camera modules (1100a, 1100b, 1100c).

[0169] Image data generated from each camera module (1100a, 1100b, 1100c) can be provided to corresponding sub-image processors (1212a, 1212b, 1212c) via separate image signal lines (ISLa, ISLb, ISLc). For example, image data generated from camera module (1100a) can be provided to sub-image processor (1212a) via image signal line (ISLa), image data generated from camera module (1100b) can be provided to sub-image processor (1212b) via image signal line (ISLb), and image data generated from camera module (1100c) can be provided to sub-image processor (1212c) via image signal line (ISLc). Such image data transmission can be performed, for example, using a Camera Serial Interface (CSI) based on MIPI (Mobile Industry Processor Interface), but the embodiments are not limited thereto.

[0170] Meanwhile, in some embodiments, a single sub-image processor may be arranged to correspond to a plurality of camera modules. For example, the sub-image processor (1212a) and the sub-image processor (1212c) are not implemented separately as illustrated, but are integrated into a single sub-image processor, and image data provided from the camera module (1100a) and the camera module (1100c) may be selected through a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor.

[0171] Image data provided to each sub-image processor (1212a, 1212b, 1212c) may be provided to an image generator (1214). The image generator (1214) may generate an output image using image data provided from each sub-image processor (1212a, 1212b, 1212c) according to image generating information or a mode signal.

[0172] Specifically, the image generator (1214) can generate an output image by merging at least some of the image data generated from camera modules (1100a, 1100b, 1100c) having different viewing angles according to image generation information or a mode signal. Additionally, the image generator (1214) can generate an output image by selecting any one of the image data generated from camera modules (1100a, 1100b, 1100c) having different viewing angles according to image generation information or a mode signal.

[0173] In some embodiments, the image generation information may include a zoom signal (or zoom factor). Additionally, in some embodiments, the mode signal may be a signal based, for example, on a mode selected by a user.

[0174] When the image generation information is a zoom signal (zoom factor) and each camera module (1100a, 1100b, 1100c) has a different viewing angle (angle of view), the image generator (1214) can perform different operations depending on the type of zoom signal. For example, if the zoom signal is a first signal, the image data output from the camera module (1100a) and the image data output from the camera module (1100c) can be merged, and then an output image can be generated using the merged image signal and the image data output from the camera module (1100b) that was not used for merging. If the zoom signal is a second signal different from the first signal, the image generator (1214) can generate an output image by selecting one of the image data output from each camera module (1100a, 1100b, 1100c) without performing such image data merging. However, the embodiments are not limited thereto, and the method of processing image data can be modified as needed.

[0175] In some embodiments, the image generator (1214) receives multiple image data with different exposure times from at least one of a plurality of sub-image processors (1212a, 1212b, 1212c) and performs HDR (high dynamic range) processing on the multiple image data to generate merged image data with increased dynamic range.

[0176] The camera module controller (1216) can provide control signals to each camera module (1100a, 1100b, 1100c). The control signals generated from the camera module controller (1216) can be provided to the corresponding camera modules (1100a, 1100b, 1100c) through separate control signal lines (CSLa, CSLb, CSLc).

[0177] One of the plurality of camera modules (1100a, 1100b, 1100c) may be designated as a master camera (e.g., 1100b) according to image generation information including a zoom signal or a mode signal, and the remaining camera modules (e.g., 1100a, 1100c) may be designated as slave cameras. This information may be included in a control signal and provided to the corresponding camera modules (1100a, 1100b, 1100c) through separate control signal lines (CSLa, CSLb, CSLc).

[0178] The camera module operating as a master and slave may be changed according to the zoom factor or operation mode signal. For example, if the field of view of the camera module (1100a) is wider than the field of view of the camera module (1100b) and the zoom factor indicates a low zoom magnification, the camera module (1100b) may operate as a master and the camera module (1100a) may operate as a slave. Conversely, if the zoom factor indicates a high zoom magnification, the camera module (1100a) may operate as a master and the camera module (1100b) may operate as a slave.

[0179] In some embodiments, the control signal provided from the camera module controller (1216) to each camera module (1100a, 1100b, 1100c) may include a sync enable signal. For example, if the camera module (1100b) is a master camera and the camera modules (1100a, 1100c) are slave cameras, the camera module controller (1216) may transmit a sync enable signal to the camera module (1100b). The camera module (1100b) that receives this sync enable signal may generate a sync signal based on the received sync enable signal and provide the generated sync signal to the camera modules (1100a, 1100c) through a sync signal line (SSL). The camera module (1100b) and camera modules (1100a, 1100c) can be synchronized with this sync signal to transmit image data to the application processor (1200).

[0180] In some embodiments, a control signal provided from a camera module controller (1216) to a plurality of camera modules (1100a, 1100b, 1100c) may include mode information according to a mode signal. Based on this mode information, the plurality of camera modules (1100a, 1100b, 1100c) may operate in a first operation mode and a second operation mode with respect to the sensing speed.

[0181] A plurality of camera modules (1100a, 1100b, 1100c) can, in a first operating mode, generate an image signal at a first speed (e.g., generate an image signal at a first frame rate) and encode it at a second speed higher than the first speed (e.g., encode an image signal at a second frame rate higher than the first frame rate), and transmit the encoded image signal to an application processor (1200). At this time, the second speed may be 30 times or less of the first speed.

[0182] The application processor (1200) stores the received image signal, that is, the encoded image signal, in a memory (1230) provided internally or in a storage (1400) outside the application processor (1200), and subsequently reads the encoded image signal from the memory (1230) or the storage (1400) to decode it, and can display image data generated based on the decoded image signal. For example, a corresponding sub-processor among a plurality of sub-processors (1212a, 1212b, 1212c) of the image processing device (1210) can perform decoding, and can also perform image processing on the decoded image signal.

[0183] A plurality of camera modules (1100a, 1100b, 1100c) can generate an image signal at a third speed lower than a first speed in a second operation mode (e.g., generate an image signal at a third frame rate lower than a first frame rate) and transmit the image signal to an application processor (1200). The image signal provided to the application processor (1200) may be an unencoded signal. The application processor (1200) may perform image processing on the received image signal or store the image signal in memory (1230) or storage (1400).

[0184] The PMIC (1300) can supply power, such as power voltage, to each of the plurality of camera modules (1100a, 1100b, 1100c). For example, the PMIC (1300) can supply first power to the camera module (1100a) through a power signal line (PSLa), supply second power to the camera module (1100b) through a power signal line (PSLb), and supply third power to the camera module (1100c) through a power signal line (PSLc), under the control of the application processor (1200).

[0185] The PMIC (1300) can generate power corresponding to each of the plurality of camera modules (1100a, 1100b, 1100c) and adjust the power level in response to a power control signal (PCON) from the application processor (1200). The power control signal (PCON) may include power adjustment signals for each operating mode of the plurality of camera modules (1100a, 1100b, 1100c). For example, the operating mode may include a low power mode, and in this case, the power control signal (PCON) may include information about the camera module operating in the low power mode and the power level being set. The power levels provided to each of the plurality of camera modules (1100a, 1100b, 1100c) may be the same or different from each other. Additionally, the power level may be changed dynamically.

[0186] As described above, the pixel according to the embodiments of the present invention and the pixel can improve the electrical characteristics of the pixel and image sensor by adopting a dual gate structure including a lower gate and an upper gate having a size smaller than the lower gate, thereby reducing the coupling capacitance between the gate and other components.

[0187] In addition, the pixels of the image sensor according to the embodiments of the present invention can efficiently improve the electrical characteristics of the pixels and the image sensor without excessive changes to the existing design by changing only the size and position of the upper gate while maintaining the layout of the lower gate. Industrial applicability

[0188] Embodiments of the present invention can be usefully applied to devices and systems including image sensors. In particular, embodiments of the present invention can be more usefully applied to electronic devices such as computers, laptops, cellular phones, smartphones, MP3 players, Personal Digital Assistants (PDA), Portable Multimedia Players (PMP), digital TVs, digital cameras, portable game consoles, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, autonomous driving devices, etc.

[0189] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

Claim 1 A pixel of an image sensor comprising: a photoelectric conversion region disposed on the lower part of a semiconductor substrate; a floating diffusion region disposed on the upper part of the semiconductor substrate; a transmission gate including a lower transmission gate disposed on the semiconductor substrate and an upper transmission gate disposed on the lower transmission gate; and a pixel gate disposed on the semiconductor substrate between a first source-drain region and a second source-drain region disposed on the upper part of the semiconductor substrate and a first source-drain region and a second source-drain region, wherein the pixel gate comprises a pixel transistor including a lower pixel gate and an upper pixel gate disposed on the lower pixel gate. Claim 2 A pixel of an image sensor according to claim 1, characterized in that the size of the upper transmission gate in the horizontal direction parallel to the upper surface of the semiconductor substrate is smaller than the size of the lower transmission gate in the horizontal direction, and the size of the upper pixel gate in the horizontal direction is smaller than the size of the lower transmission gate in the horizontal direction. Claim 3 A pixel of an image sensor according to claim 1, characterized in that the thickness of the upper transmission gate in the vertical direction perpendicular to the upper surface of the semiconductor substrate is greater than the thickness of the lower transmission gate in the vertical direction, and the thickness of the upper pixel gate in the vertical direction is greater than the thickness of the lower pixel gate in the vertical direction. Claim 4 A pixel of an image sensor according to claim 1, wherein the lower transmission gate and the lower pixel gate are simultaneously formed by patterning a first polylayer formed by a first deposition process, and the upper transmission gate and the upper pixel gate are simultaneously formed by patterning a second polylayer formed by a second deposition process performed after the first deposition process. Claim 5 A pixel of an image sensor according to claim 1, wherein the lower transmission gate and the lower pixel gate are simultaneously doped by a first ion implantation process, and the upper transmission gate and the upper pixel gate are simultaneously doped by a second ion implantation process performed after the first ion implantation process. Claim 6 A pixel of an image sensor according to claim 1, characterized in that a vertical contact is disposed on the upper transmission gate and the upper pixel gate, respectively. Claim 7 A pixel of an image sensor according to claim 1, wherein the upper transmission gate is positioned on the end further from the floating diffusion region among the two ends in the horizontal direction of the lower transmission gate. Claim 8 A pixel of an image sensor according to claim 1, wherein the upper pixel gate is disposed on the end further from the pixel element isolation film for isolation from neighboring pixels among the two ends in the horizontal direction of the lower pixel gate. Claim 9 A pixel of an image sensor according to claim 1, wherein the lower transmission gate has a buried gate structure comprising a horizontal portion disposed on the upper surface of the semiconductor substrate and a vertical portion extending into the interior of the semiconductor substrate, wherein the horizontal portion and the vertical portion of the lower transmission gate are simultaneously formed by a first deposition process, and the upper transmission gate is formed by a second deposition process performed after the first deposition process. Claim 10 A method for manufacturing an image sensor including pixels, comprising: forming a gate insulating layer on a semiconductor substrate; performing a first deposition process to form a first poly layer on the insulating layer; patterning the first poly layer to simultaneously form a lower transmission gate and a lower pixel gate; performing a second deposition process to form a second poly layer on the lower transmission gate and the lower pixel gate; and patterning the second poly layer to simultaneously form an upper transmission gate and an upper pixel gate on the lower transmission gate and the lower pixel gate.

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