Integrated circuit devices including contact power rail structures for three-dimensional stacked field-effect transistor structures and methods of forming the same

Abstract

An integrated circuit device comprises a substrate, a lower transistor on a first surface of the substrate, an upper gate structure located on the lower transistor and extending in a first lateral direction parallel to the first surface of the substrate, an upper transistor including an upper source / drain region adjacent to the upper gate structure in a second lateral direction orthogonal to the first lateral direction, a rear power transfer network structure located on a second surface of the substrate opposite to the first surface and including a rear power rail, and a contact power rail structure electrically connecting the upper source / drain region to the rear power rail. The contact power rail structure overlaps with the upper gate structure in the first lateral direction.

Description

Technology Field

[0001] The present disclosure generally relates to the field of integrated circuit devices, and more specifically to integrated circuit devices including three-dimensional (3D) transistor stacks and methods for forming the same. Background Technology

[0002] Integrated circuit devices may include various active components formed on the front surface of the device. For example, transistors may be formed on the front surface of an integrated circuit device, a semiconductor chip, or a wafer (generally referred to as an integrated circuit device in this disclosure). Such transistors are, for example, two-dimensional (2D) planar structures, FinFETs (fin field-effect transistors), GAA (gate-all-around) structures, MBCFETs. TM Various structures such as (multi-bridge channel FET) structures and / or stacked transistor structures (e.g., three-dimensional stacked FET (3DSFET) structures) may be provided.

[0003] Integrated circuit devices can receive power and data signals from one or more external sources (e.g., power and data sources). Some integrated circuit devices can receive power and data signals through front conductive structures that can provide power delivery networks. For example, an integrated circuit device may include a frontside power delivery network (FSPDN) structure having one or more components formed during the back-end-of-line (BEOL) portion of device manufacturing, and conductive structures for data signals may be located on the same side as the FSPDN structure of the integrated circuit devices. Recently, backside power delivery network (BSPDN) structures that use the back of an integrated circuit device as a power delivery network have also been proposed. The problem to be solved

[0004] One objective of the present disclosure is to provide an integrated circuit device with improved performance and reliability.

[0005] One objective of the present disclosure is to provide a method for forming the integrated circuit device. means of solving the problem

[0006] Exemplary embodiments of the present disclosure provide integrated circuit devices comprising a transistor stack of a lower transistor and an upper transistor, and a back power delivery network (BSPDN) structure electrically connected to said transistor stack. A contact power rail structure may be used to electrically connect the upper source / drain region of the upper transistor to the back power rail of the BSPDN structure. According to exemplary embodiments of the present disclosure, the contact power rail structure may have a line (or rail) shape in a plan view. For example, the line (or rail) shape of the contact power rail structure may increase the width and cross-sectional area as well as the contact area with the back power rail. Therefore, the configuration of the contact power rail structure may advantageously reduce contact resistance with the back power rail, alleviate current concentration by distributing current more uniformly over a wider area, and reduce voltage drop while delivering back power to the upper transistor.

[0007] According to some embodiments of the present disclosure, an integrated circuit device comprises a substrate, a lower transistor on a first surface of the substrate, an upper gate structure located on the lower transistor and extending in a first lateral direction parallel to the first surface of the substrate, and an upper source / drain region adjacent to the upper gate structure in a second lateral direction orthogonal to the first lateral direction, a back power transfer network (BSPDN) structure located on a second surface of the substrate opposite to the first surface and including a back power rail, and a contact power rail structure electrically connecting the upper / source / drain region to the back power rail, wherein the contact power rail structure overlaps with the upper gate structure in the first lateral direction.

[0008] According to some embodiments of the present disclosure, an integrated circuit device comprises a substrate, a lower transistor on a first surface of the substrate, an upper gate structure located on the lower transistor and extending in a first lateral direction parallel to the first surface of the substrate, and an upper source / drain region adjacent to the upper gate structure in a second lateral direction orthogonal to the first lateral direction, a rear power transfer network structure located on a second surface of the substrate opposite to the first surface and including a rear power rail, and a contact power rail structure electrically connecting the upper source / drain region to the rear power rail, wherein the width of the contact power rail structure in the second lateral direction is greater than the width of the upper source / drain region in the second lateral direction.

[0009] According to some embodiments of the present disclosure, a method for forming an integrated circuit device comprises the steps of: forming a lower channel layer and an upper channel layer spaced apart in a vertical direction; forming a lower source / drain region on the side of the lower channel layer and an upper source / drain region on the side of the upper channel layer; forming a contact power rail structure that overlaps with at least one of the lower channel layer or the upper channel layer in a first lateral direction orthogonal to the vertical direction; and forming a rear power transmission network (BSPDN) structure including a rear power rail on the lower surface of the contact power rail structure, wherein the contact power rail structure electrically connects the upper source / drain region to the rear power rail.

[0010] Other devices, apparatuses, and / or methods according to exemplary embodiments will become more apparent to those skilled in the art upon reviewing the drawings and detailed description below. In addition to all combinations of the above embodiments, all such additional embodiments are incorporated into this description, fall within the scope of this disclosure, and are intended to be protected by the appended claims. Effects of the invention

[0011] An integrated circuit device according to embodiments of the present disclosure may include contact power rail structures having a line (or rail) shape. The contact power rail structures can increase the width and cross-sectional area as well as the contact area with the rear power rail. Accordingly, the contact resistance with the rear power rail can be advantageously reduced, current concentration can be mitigated, and voltage drop can be reduced, thereby improving the performance and reliability of the integrated circuit device. In addition, the configuration of the contact power rail structures provides design flexibility for the rear power rail, which can enable optimized power transfer for the BSPDN structure and / or improved layout efficiency for the integrated circuit device. Brief explanation of the drawing

[0012] FIG. 1a is a schematic block diagram showing a transistor stack of an integrated circuit device according to some embodiments. FIG. 1b is a schematic plan view showing an integrated circuit device according to some embodiments. FIG. 1c is a schematic cross-sectional view taken along the line AA' of FIG. 1b. FIG. 1d is a schematic cross-sectional view taken along the line BB' of FIG. 1b. FIGS. 2a and 2b are schematic plan views showing rear power rails of integrated circuit devices according to some embodiments. FIGS. 3a, FIGS. 3b, FIGS. 3c, FIGS. 3d, FIGS. 3e, FIGS. 3f, and FIGS. 3g are schematic cross-sectional views illustrating methods for forming integrated circuit devices according to some embodiments. FIG. 4 is a flowchart illustrating a method for forming an integrated circuit device according to some embodiments. FIG. 5 is a schematic plan view showing an integrated circuit device according to a comparative example. Specific details for implementing the invention

[0013] Exemplary embodiments are described with reference to the accompanying drawings, which may include plan and cross-sectional views that are schematic drawings of ideal embodiments (and intermediate structures). The sizes and relative dimensions of layers and regions may be exaggerated for clarity. Additionally, variations in the shapes of the drawings may be expected, for example, due to manufacturing techniques and / or tolerances. The same reference numerals may be used to refer to the same or similar elements in various embodiments.

[0014] Integrated circuit devices may include stacked transistor structures (e.g., three-dimensional stacked field-effect transistor (3DSFET) structures) in which a lower transistor and an upper transistor are stacked vertically on the front surface of a substrate. Stacked transistor structures (i.e., transistor stacks) can improve the performance and power efficiency of the integrated circuit device by increasing integration density and enabling continuous scaling through vertical integration of transistors.

[0015] Integrated circuit devices may include backside power delivery network (BSPDN) structures that use the back side of the substrate as a power delivery network. In a BSPDN structure, the backside power rail may be formed on the back side rather than the front side of the device. Thus, the backside power rail may be located on the opposite side of the substrate from the active components (e.g., transistors). In some integrated circuit devices, upper structures containing conductive elements for data signals may be located on the front side of the device, and thus the BSPDN structure and the conductive elements for data signals may be located on opposite sides of the substrate. BSPDN structures can improve, for example, power rail efficiency, voltage drop (i.e., IR drop), high power delivery performance, and scaling of standard cell height.

[0016] Some integrated circuit devices may include stacked transistor structures and BSPDN structures. For these devices, it may be advantageous to configure the BSPDN structure to supply power to both the lower and upper transistors of the transistor stack. For example, backside power delivery to the lower and upper transistors can eliminate the frontside power delivery network (FSPDN) structure (i.e., the front power track), thereby increasing integration density and reducing standard cell height. Despite these advantages, the contact structure electrically connecting the upper transistor to the BSPDN structure may exhibit high resistance. For instance, in a transistor stack, the contact structure may have a relatively high height (or thickness) to connect the upper transistor and the BSPDN structure, resulting in a longer electrical path and increased resistance. The contact structure may also have a relatively narrow width and a high aspect ratio, which can cause manufacturing difficulties and lead to increased resistance. The resistance of the contact structure causes a higher voltage drop during back-end power transfer to the upper transistor, which can reduce the performance and reliability of the integrated circuit device.

[0017] According to exemplary embodiments of the present disclosure, integrated circuit devices are provided that include contact power rail structures having a line (or rail) shape in a plan view. The line (or rail) shape of the contact power rail structures can increase the width and cross-sectional area as well as the contact area with the rear power rail. Therefore, the configuration of the contact power rail structures can advantageously reduce contact resistance with the rear power rail, alleviate current crowding by distributing current more uniformly over a wider area, and reduce voltage drop while delivering rear power to the upper transistor. Thus, the performance and reliability of the integrated circuit device can be improved.

[0018] Some exemplary embodiments of the present disclosure are described in more detail below with reference to the accompanying drawings.

[0019] FIG. 1a is a schematic block diagram showing a transistor stack of an integrated circuit device according to some embodiments.

[0020] Referring to FIG. 1a, an integrated circuit device (100) comprises a substrate (110) and a transistor stack (101) on a first surface (S1) (i.e., front) of the substrate (110). The substrate (110) may extend in a first direction (Y) (which may be referred to as a first lateral direction) and a second direction (X) (which may be referred to as a second lateral direction). The first direction (Y) and the second direction (X) may be substantially parallel to the first surface (S1) and / or the second surface (S2) (i.e., back) of the substrate (110). For example, the first direction (Y) may intersect the second direction (X). In some embodiments, the first direction (Y) may be orthogonal (or perpendicular) to the second direction (X). As used in the present disclosure, the first surface (S1) and the second surface (S2) of the substrate (110) may also be referred to as the “upper surface” and the “lower surface” of the substrate (110), respectively.

[0021] The first surface (S1) of the substrate (110) is opposite to the second surface (S2) in a third direction (Z) (which may be referred to as a vertical direction). The third direction (Z) may be substantially perpendicular to the first surface (S1) and / or the second surface (S2) of the substrate (110). For example, the third direction (Z) may intersect the first direction (Y) and the second direction (X).

[0022] In some embodiments, the substrate (110) may include insulating material(s) or be formed of insulating material(s) and thus may be referred to as a back insulating structure. For example, the insulating material(s) included in the substrate (110) may help reduce parasitic capacitance and / or leakage current paths associated with the back contact structure (148) (described in more detail below). In some embodiments, the substrate (110) may include silicon oxide, silicon nitride, silicon nitride, silicon carbonitride, silicon boron nitride, silicon boron carbonitride, and / or a low dielectric constant material. The low dielectric constant material may include, for example, fluorine-doped silicon oxide, organosilicate glass, carbon-doped oxide, porous silicon dioxide, porous organosilicate glass, spin-on organic polymer dielectrics, and / or spin-on silicon-based polymer dielectrics. In some embodiments, the substrate (110) may comprise insulating material(s), but the present disclosure is not limited thereto. In some embodiments, the substrate (110) may comprise or be formed of semiconductor material(s), such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium phosphide (GaP), gallium arsenide (GaAs), silicon carbide (SiC), silicon-germanium carbide (SiGeC) and / or indium phosphide (InP). For example, the substrate (110) may be insulating layer(s), a bulk substrate (e.g., a bulk silicon wafer), and / or a semiconductor-on-insulator (SOI) substrate.

[0023] The transistor stack (101) comprises a lower transistor (Tb) having a stack of lower semiconductor channel layers (120b) and an upper transistor (Ta) having a stack of upper semiconductor channel layers (120a). The channel layers (120a, 120b) may comprise, for example, semiconductor material(s) (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC and / or InP). In some embodiments, the channel layers (120a, 120b) may be nanosheets having a thickness in the range of about 1 nm to about 100 nm in the third direction (Z), or nanowires having a circular or elliptical cross-section having a diameter in the range of about 1 nm to 100 nm.

[0024] The lower transistor (Tb) and the upper transistor (Ta) are stacked vertically in a third direction (Z) on the substrate (110). The lower transistor (Tb) is located on the substrate (110) and may be located between the upper transistor (Ta) and the substrate (110) in the third direction (Z). For example, the upper transistor (Ta) may be located on the lower transistor (Tb) and may overlap with the lower transistor (Tb) in the third direction (Z). As used in this disclosure, “element (A) overlaps with element (B) in a certain direction” (or a similar expression) means that there exists at least one straight line extending in that direction and intersecting both element (A) and element (B). In some embodiments, the lower transistor (Tb) and the upper transistor (Ta) may be vertically stacked field-effect transistors (FETs). Accordingly, the transistor stack (101) (including upper and lower transistors (Ta, Tb)) may also be referred to in the present disclosure as a “three-dimensional stacked field-effect transistor (3DSFET) structure.”

[0025] The transistor stack (101) may also include an isolation region (130), such as a middle dielectric isolation (MDI) region. In some embodiments, the isolation region (130) may serve as a spacer between the upper and lower transistors (Ta, Tb). Thus, the isolation region (130) may also be referred to as a spacer.

[0026] A plurality of lower channel layers (120b) of the lower transistor (Tb) are located between a pair of lower source / drain (S / D) regions (140) electrically connected to the lower channel layers (120b) in the second direction (X). Likewise, a plurality of upper channel layers (120a) of the upper transistor (Ta) are located between a pair of upper source / drain regions (150) electrically connected to the upper channel layers (120a) in the second direction (X). The lower source / drain regions (140) may be located between the upper source / drain regions (150) and the substrate (110) in the third direction (Z). The sides of the lower channel layers (120b) may be in contact with the lower source / drain regions (140) (e.g., directly above), and the sides of the upper channel layers (120a) may be in contact with the upper source / drain regions (150) (e.g., directly above).

[0027] Each of the lower source / drain regions (140) and the upper source / drain regions (150) may comprise a semiconductor layer (e.g., a silicon (Si) layer, a silicon carbide (SiC) layer and / or a silicon germanium (SiGe) layer) and may further comprise dopants within the semiconductor layer. For example, each of the source / drain regions (140, 150) may comprise an epitaxial semiconductor layer having dopants (i.e., impurities). In some embodiments, the upper source / drain regions (150) may comprise a semiconductor material different from that of the lower source / drain regions (140). For example, the upper source / drain regions (150) may comprise silicon germanium and the lower source / drain regions (140) may comprise silicon or silicon carbide, or vice versa. In some other embodiments, the upper source / drain regions (150) may include the same semiconductor material as the lower source / drain regions (140). The upper source / drain regions (140) may be located on the substrate (110), and the upper source / drain regions (150) may be located on the lower source / drain regions (140).

[0028] In some embodiments, the lower source / drain regions (140) have a first conductivity type, and the upper source / drain regions (150) have a second conductivity type. As used in this disclosure, the terms “first conductivity type” and “second conductivity type” are used to denote n-type or p-type, and the first conductivity type and the second conductivity type are different from each other. Thus, if the first region of the device has a first conductivity type and the second region of the device has a second conductivity type, this means that the first region has an n-type conductivity type and the second region has a p-type conductivity type, or that the first region has a p-type conductivity type and the second region has an n-type conductivity type. For example, the lower source / drain regions (140) may contain n-type impurities (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.) and the upper source / drain regions (150) may contain p-type impurities (e.g., boron (B), gallium (Ga), indium (In), etc.), and the opposite case may also be included.

[0029] The upper and lower transistors (Ta, Tb) may be stacked in a third direction (Z) on the substrate (110). In some embodiments, the lower transistor (Tb) and the upper transistor (Ta) may have complementary conductivity types to form a complementary metal-oxide-semiconductor (CMOS) structure. For example, the lower transistor (Tb) may have a first conductivity type, and the upper transistor (Ta) may have a second conductivity type. In some embodiments, the upper and lower transistors (Ta, Tb) may be PMOS and NMOS transistors, respectively, and vice versa. Also, although described with reference to the lower transistor (Tb) and the upper transistor (Ta), the transistor stack (101) is not limited to an array of two transistors and may include additional transistors stacked vertically on the substrate (110) in some other embodiments. For convenience of illustration, only one transistor stack (101) is shown in FIG. 1a. However, it will be understood that in some embodiments, the integrated circuit device (100) may include two, three, four or more transistor stacks (101).

[0030] FIG. 1b is a schematic plan view (or layout view) showing an integrated circuit device according to some embodiments. For convenience of explanation, FIG. 1b shows only some elements of the integrated circuit device (100). The line A-A' cuts the gate cut region (132), the lower source / drain region (140), and the upper source / drain region (150) in the first direction (Y). The line B-B' cuts the gate cut region (132) and the first gate structure (170-1) in the first direction (Y). FIG. 1c is a schematic cross-sectional view cut along the line AA' of FIG. 1b. FIG. 1d is a schematic cross-sectional view cut along the line BB' of FIG. 1b.

[0031] Referring to FIGS. 1b, 1c, and 1d, the integrated circuit device (100) comprises a plurality of first gate structures (170-1) and a plurality of second gate structures (170-2) extending in a first direction (Y) (i.e., longitudinal direction). Each first gate structure (170-1) is located on the upper channel layers (120a) of the upper transistor (Ta) and the lower channel layers (120b) of the lower transistor (Tb). In some embodiments, each gate structure (170) may comprise an upper gate structure (170a) and a lower gate structure (170b). As used in the present disclosure, similar elements may be referred to individually by the whole reference numeral (e.g., first gate structure (170-1)) and collectively by the first part of the reference numeral (e.g., gate structures (170)).

[0032] The upper transistor (Ta) comprises upper channel layers (120a), each upper gate structure (170a) on the upper channel layers (120a), and a pair of upper source / drain regions (150) located on opposite sides of each upper gate structure (170a) in a second direction (X). The lower transistor (Tb) comprises lower channel layers (120b), each lower gate structure (170b) on the lower channel layers (120b), and a pair of lower source / drain regions (140) located on opposite sides of each lower gate structure (170b) in a second direction (X). The lower transistor (Tb) and the upper transistor (Ta) constitute a transistor stack (101) (see FIG. 1a) of an integrated circuit device (100).

[0033] A pair of upper source / drain regions (150) may be spaced apart from each other with an upper gate structure (170a) in between (e.g., in a second direction (X)). A pair of lower source / drain regions (140) may be spaced apart from each other with a lower gate structure (170b) in between (e.g., in a second direction (X)). In some embodiments, the lengths of the lower source / drain regions (140) in the first direction (Y) may be longer than the lengths of the upper source / drain regions (150) in the first direction (Y), and thus, as shown in FIG. 1b and FIG. 1c, parts of the lower source / drain regions (140) may not overlap with the upper source / drain regions (150) in the third direction (Z).

[0034] The upper channel layers (120a) may be located between a pair of upper source / drain regions (150) (e.g., in a second direction (X)) and are electrically connected to the pair of upper source / drain regions (150). As illustrated in FIG. 1d, the upper channel layers (120a) may be spaced apart from each other in a third direction (Z) with an upper gate structure (170a) in between. FIG. 1d illustrates three upper channel layers (120a), but embodiments of the present disclosure are not limited thereto. In some embodiments, the integrated circuit device (100) may include more than three or fewer than three upper channel layers (120a).

[0035] Lower channel layers (120b) may be located between a pair of lower source / drain regions (140) (e.g., in a second direction (X)) and are electrically connected to a pair of lower source / drain regions (140). As illustrated in FIG. 1d, the lower channel layers (120b) may be spaced apart from each other in a third direction (Z) with a lower gate structure (170b) in between. FIG. 1d illustrates two lower channel layers (120b), but embodiments of the present disclosure are not limited thereto. In some embodiments, the integrated circuit device (100) may include more than two or fewer than two lower channel layers (120b).

[0036] An upper gate structure (170a) may be located on the upper channel layers (120a) of an upper transistor (Ta), and a lower gate structure (170b) may be located on the lower channel layers (120b) of a lower transistor (Tb). The upper gate structure (170a) includes a gate insulator (172) and an upper conductive gate (174a). The upper conductive gate (174a) may be located between the upper channel layers (120a) in a third direction (Z). The upper conductive gate (174a) may be spaced apart from the upper source / drain regions (150) in a second direction (X) with the gate insulator (172) in between. The lower gate structure (170b) includes a gate insulator (172) and a lower conductive gate (174b). The lower conductive gate (174b) may be located between the lower channel layers (120b) in a third direction (Z). The lower conductive gate (174b) can be spaced apart from the lower source / drain regions (140) in the second direction (X) with the gate insulator (172) in between.

[0037] An upper gate structure (170a) may surround the upper channel layers (120a). That is, the upper gate structure (170a) (e.g., upper conductive gate (174a)) may be located on the upper, lower, and side surfaces of each upper channel layer (120a). A gate insulator (172) may be located between each upper channel layer (120a) and the upper conductive gate (174a) and may separate the upper conductive gate (174a) from the upper channel layers (120a). It will be understood that as used in this disclosure, “element (A) surrounds element (B)” (or a similar expression) means that element (A) surrounds element (B) at least partially, but does not necessarily mean that element (A) surrounds element (B) completely.

[0038] The lower gate structure (170b) can surround the lower channel layers (120b). That is, the lower gate structure (170b) (e.g., the lower conductive gate (174b)) can be located on the upper, lower, and side surfaces of each lower channel layer (120b). A gate insulator (172) can be located between each lower channel layer (120b) and the lower conductive gate (174b), and can separate the lower conductive gate (174b) from the lower channel layers (120b).

[0039] The upper conductive gate (174a) and the lower conductive gate (174b) may each comprise a metallic material (e.g., tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), cobalt (Co) and / or ruthenium (Ru)) and / or a semiconductor material. In some embodiments, the upper conductive gate (174a) and the lower conductive gate (174b) may each comprise a metal layer and work function layer(s) (e.g., titanium nitride (TiN) layer, tantalum nitride (TaN) layer, titanium aluminum (TiAl) layer, titanium carbide (TiC) layer, titanium aluminum carbide (TiAlC) layer, titanium aluminum nitride (TiAlN) layer and / or tungsten nitride (WN) layer). For example, the work function layer(s) may be provided between the metal layer and the gate insulator (172). In some embodiments, the work function layer(s) may separate the metal layer from the gate insulator (172). In some embodiments, the upper conductive gate (174a) and the lower conductive gate (174b) may comprise the same metal material. In some other embodiments, the upper conductive gate (174a) and the lower conductive gate (174b) may comprise different metal materials. In some embodiments, the upper and lower conductive gates (174a, 174b) may be configured as a single integrated structure (e.g., formed by the same process or the same series of processes), but the present disclosure is not limited thereto.

[0040] As illustrated in FIG. 1d, the upper gate structure (170a) (e.g., upper conductive gate (174a)) and the lower gate structure (170b) (e.g., lower conductive gate (174b)) can be electrically contacted with each other (i.e., electrically connected with each other) and can share an interface (174_I) (shown as a dashed line in FIG. 1d). In some embodiments, a common gate signal can be applied to both the upper conductive gate (174a) and the lower conductive gate (174b) (e.g., through the upper gate contact (178)). In some other embodiments, unlike illustrated, the isolation region (130) can separate (e.g., electrically isolate) the upper conductive gate (174a) from the lower conductive gate (174b), so that the upper and lower conductive gates (174a, 174b) can be configured to receive separate gate signals.

[0041] The gate insulator (172) extends between the upper channel layers (120a) and the upper conductive gate (174a), and between the lower channel layers (120b) and the lower conductive gate (174b). The gate insulator (172) surrounds the upper and lower conductive gates (174a, 174b) and can isolate (i.e., insulate) the upper and lower conductive gates (174a, 174b) from the upper and lower channel layers (120a, 120b), respectively. In some embodiments, the gate insulator (172) may also extend over the substrate (110) (i.e., the first surface (S1) of the substrate (110)) and the shallow trench isolation (STI) region (116) (described in more detail below), as shown in FIG. 1d. The gate insulator (172) may comprise a single layer or multiple layers (e.g., a silicon oxide layer and / or a high dielectric constant material layer). For example, the high dielectric constant material layer may comprise aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium zirconium oxide (HfZrO4), titanium dioxide (TiO2), scandium oxide (Sc2O3), yttrium oxide (Y2O3), lanthanum oxide (La2O3), lutetium oxide (Lu2O3), niobium pentoxide (Nb2O5), and / or tantalum pentoxide (Ta2O5).

[0042] As illustrated in FIG. 1b, gate structures (170) may be extended in the longitudinal direction (i.e., vertical direction) in the first direction (Y) and spaced apart in the second direction (X). The first gate structures (170-1) may be adjacent to the second gate structures (170-2) in the first direction (Y). A gate cut region (132) (described in more detail below) may separate the first and second gate structures (170-1, 170-2) adjacent in the first direction (Y). In some embodiments, the pair of first gate structures (170-1) located outermost in the second direction (X) may be electrically non-functional dummy gate structures (e.g., inactive gate structures) and may be formed to replicate the physical structure of the active first gate structure (170-1) between them, but the present disclosure is not limited thereto. Likewise, in some embodiments, the pair of second gate structures (170-2) located outermost in the second direction (X) may be electrically non-functional dummy gate structures (e.g., inactive gate structures) and may be formed to replicate the physical structure of the active second gate structure (170-2) between them, but the present disclosure is not limited thereto.

[0043] The isolation region (130) may be a spacer that separates (i.e., electrically isolates) the lower channel layers (120b) of the lower transistor (Tb) from the upper channel layers (120a) of the upper transistor (Ta). The isolation region (130) may be located between the upper gate structure (170a) and the lower gate structure (170b) (e.g., in the third direction (Z)). In some embodiments, the isolation region (130) may be located between the lower and upper source / drain regions (140, 150) (e.g., in the third direction (Z)), as shown in FIG. 1c. The isolation region (130) may include one or more isolation layers comprising insulating material(s) (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon boron nitride and / or low dielectric constant materials).

[0044] In some embodiments, the lower channel layers (120b) may be wider than the upper channel layers (120a) in the first direction (Y). For example, in some embodiments, the lower channel layers (120b) may be at least twice as wide as the upper channel layers (120a) in the first direction (Y). In some embodiments, the isolation region (130) may have the same width as the lower channel layers (120b) in the first direction (Y). In some other embodiments, unlike what is illustrated, the isolation region (130) may have the same width as the upper channel layers (120a) in the first direction (Y).

[0045] STI regions (116) may be formed adjacent to the substrate (110) on opposite sides of the upper and lower transistors (Ta, Tb) (e.g., in the first direction (Y)). The STI regions (116) may comprise one or more layers comprising, for example, insulating material(s) (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon boron nitride and / or low dielectric constant material). For example, the STI regions (116) may define active regions of the integrated circuit device (100) and isolate (e.g., electrically isolate) adjacent transistor stacks (101) (see FIG. 1a). FIG. 1c and FIG. 1d show that the STI regions (116) comprise a single layer, but in some embodiments, the STI regions (116) may comprise multiple layers.

[0046] The integrated circuit device (100) further comprises an interlayer insulating layer (152) on (i.e., surrounding) the lower and upper source / drain regions (140, 150). For example, the interlayer insulating layer (152) may be located between the substrate (110) and the upper structure (138) (described in more detail below) in a third direction (Z). The interlayer insulating layer (152) may comprise, for example, insulating material(s) (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon boron nitride and / or low dielectric constant materials). FIGS. 1c and 1d illustrate the interlayer insulating layer (152) as a single layer, but in some embodiments, the interlayer insulating layer (152) may comprise a plurality of layers.

[0047] In some embodiments, the upper gate contact (178) extends into the interlayer insulating layer (152) and can electrically connect the lower gate structure (170b) (e.g., lower conductive gate (174b)) and the upper gate structure (170a) (e.g., upper conductive gate (174a)) to the upper structure (138). The upper gate contact (178) may comprise a metal layer or material including, for example, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), cobalt (Co), and / or ruthenium (Ru). In some other embodiments, unlike what is illustrated, the upper gate contact (178) may be formed below (i.e., on the back side) the upper and lower gate structures (170a, 170b).

[0048] The integrated circuit device (100) further comprises an upper structure (138) (which may be referred to as a BEOL structure) on the upper and lower transistors (Ta, Tb). The upper structure (138) may include elements formed during the middle-of-line (MOL) and / or back-end-of-line (BEOL) portions of the device manufacturing. For convenience of explanation, the elements of the upper structure (138) are not specifically illustrated in FIG. 1c and FIG. 1d. As illustrated in FIG. 1c and FIG. 1d, the upper structure (138) is provided on a first surface (S1) (i.e., the front) of the substrate (110).

[0049] The upper structure (138) may include conductive elements (e.g., wire(s) and / or via(s)) and insulating elements (e.g., interlayer insulating layer(s) and / or spacer(s)). For example, the upper structure (138) may include interlayer insulating layers, conductive wires (e.g., metal wires) provided within the interlayer insulating layers and stacked in a third direction (Z), and conductive via plugs (e.g., rapid via plugs), each of which may electrically connect two conductive wires spaced apart from each other in a third direction (Z). The conductive elements of the upper structure (138) may be electrically connected, for example, to lower source / drain regions (140), upper source / drain regions (150), and / or gate structures (170).

[0050] An upper transistor (Ta) (comprising upper channel layers (120a), a pair of upper source / drain regions (150), and an upper gate structure (170a)) and a lower transistor (Tb) (comprising lower channel layers (120b), a pair of lower source / drain regions (140), and a lower gate structure (170b)) are provided on a first surface (S1) (e.g., front) of a substrate (110). The integrated circuit device (100) further includes a rear power delivery network (BSPDN) structure (142) on a second surface (S2) (i.e., rear) of the substrate (110). The BSPDN structure (142) may include a rear insulator (146) and a plurality of rear power rails (144) provided within the rear insulator (146). The rear power rails (144) may comprise a metal layer or material including, for example, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), cobalt (Co) and / or ruthenium (Ru). The rear insulator (146) may comprise one or more layers including, for example, insulating material(s) (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon boronitride and / or low dielectric constant materials).

[0051] The rear power rails (144) may be extended in a second direction (X) (i.e., vertically). Each rear power rail (144) may be electrically connected to a power source having a predetermined voltage (e.g., drain voltage (VDD) and / or source voltage (VSS)). In some embodiments, at least one lower source / drain region (140) of the lower transistor (Tb) may be electrically connected to a power source through a rear contact structure (148) (described in more detail below) and a rear power rail (144), as shown in FIG. 1c. That is, the lower source / drain region (140) may receive the drain voltage (VDD) or source voltage (VSS) through the rear contact structure (148) and the rear power rail (144). Additionally, at least one upper source / drain region (150) of the upper transistor (Ta) may be electrically connected to a power source through an upper source / drain contact (156), a contact power rail structure (122) (described in more detail below), and a rear power rail (144), as shown in FIG. 1C. That is, the upper source / drain region (150) may receive a drain voltage (VDD) or a source voltage (VSS) through the upper source / drain contact (156), the contact power rail structure (122), and the rear power rail (144). As used in this disclosure, the rear power rail (144) electrically connected to the contact power rail structure (122) may be referred to as the “first rear power rail,” and the rear power rail (144) electrically connected to the rear contact structure (148) may be referred to as the “second rear power rail.” For example, the BSPDN structure (142) may include a power delivery network having a wiring network used to deliver power (e.g., source / drain voltages) to the rear power rails (144).

[0052] For convenience of explanation, the BSPDN structure (142) is illustrated in FIG. 1c and FIG. 1d as comprising only rear power rails (144) and a rear insulator (146). However, embodiments of the present disclosure are not limited thereto, and the BSPDN structure (142) may comprise various other elements (e.g., power wire(s), via(s), interlayer insulation(s), etc.) (typically included). For example, the BSPDN structure (142) may comprise conductive via plug(s) and / or conductive wire(s) electrically connected to one or more rear power rails (144) to facilitate power transfer. That is, although illustrated as comprising rear power rails (144) and a rear insulator (146), it will be understood that the BSPDN structure (142) may comprise one or more conductive layers (e.g., metal layers) stacked in a third direction (Z) to provide rear power transfer. Conductive layers may be included in interlayer insulating layers, and conductive via plugs (e.g., metal via plugs) may electrically connect the conductive layers to each other in a third direction (Z). For example, the back insulator (146) is shown as a single layer, but in some embodiments, the back insulator (146) may include a plurality of interlayer insulating layers stacked (e.g., in the third direction (Z)) on the second surface (S2) of the substrate (110). The conductive layers may include one or more conductive wires (e.g., metal wires). In some embodiments, an interposed structure (not shown) is provided between the substrate (110) and the BSPDN structure (142) to separate the substrate (110) from the BSPDN structure (142). The BSPDN structure (142) may increase power transfer efficiency, reduce the area used for power transfer, and / or improve the voltage drop of the integrated circuit device (100).

[0053] The rear contact structure (148) may be configured to transmit a drain voltage (VDD) or a source voltage (VSS) from the BSPDN structure (142) (i.e., the rear power rail (144)) to the lower source / drain region (140) of the lower transistor (Tb). The rear contact structure (148) may be located between the rear power rail (144) and the lower source / drain region (140) (e.g., in a third direction (Z)). For example, the rear contact structure (148) may extend into the substrate (110) and electrically connect the BSPDN structure (142) (i.e., the rear power rail (144)) to the lower source / drain region (140). In some embodiments, one or more conductive plugs (not specifically illustrated) may be provided between the rear contact structure (148) and the rear power rail (144), but the present disclosure is not limited thereto. For example, the back contact structure (148) and the conductive plug(s) may comprise the same materials and may be integrated into a monolithic or single structure, that is, a structure formed by the same process or the same series of processes without structurally or visually separated interfaces. The back contact structure (148) may comprise a metal layer or material, for example, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), cobalt (Co) and / or ruthenium (Ru). Although not specifically illustrated, the back contact structures (148) may be used in some embodiments to electrically connect both lower source / drain regions (140) of the lower transistor (Tb) to the BSPDN structure (142), but the present disclosure is not limited thereto.

[0054] The integrated circuit device (100) further includes an upper source / drain contact (156) (shown as a dashed box in FIG. 1b) and a contact power rail structure (122). The upper source / drain contact (156) may be located on the upper source / drain region (150) of the upper transistor (Ta) and may be in contact with the upper source / drain region (150) (e.g., electrically). For example, the upper source / drain contact (156) may be in contact with the upper surface of the upper source / drain region (150) (e.g., directly above the upper surface). The upper source / drain contact (156) is electrically connected to the upper source / drain region (150) and the contact power rail structure (122) (i.e., electrically connected thereto). For example, the upper source / drain contact (156) may extend in a first direction (Y), as shown in FIG. 1b and FIG. 1c, to electrically connect the upper source / drain region (150) to the contact power rail structure (122). The upper source / drain contact (156) may include a metal layer or material, for example, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), cobalt and / or ruthenium (Ru).

[0055] The contact power rail structure (122) may be configured to transfer a drain voltage (VDD) or a source voltage (VSS) from the BSPDN structure (142) (i.e., from the rear power rail (144)) to the upper source / drain region (150) of the upper transistor (Ta). That is, the contact power rail structure (122) may electrically connect the BSPDN structure (142) (i.e., the rear power rail (144)) to the upper source / drain region (150). For example, the contact power rail structure (122) may be a vertically conductive structure that electrically connects the rear power rail (144) to the upper source / drain region (150). As used in this disclosure, “element (X) electrically connects element (Y) to element (Z)” (or a similar expression) means that element (X) facilitates the electrical connection between element (Y) and element (Z), but does not mean that element (X) is the only element facilitating the electrical connection (i.e., other intermediate elements facilitating the electrical connection may exist). For example, a contact power rail structure (122) may be electrically connected to an upper source / drain region (150) through an upper source / drain contact (156). Although not specifically illustrated, the contact power rail structure (122) may be used in some embodiments to electrically connect all upper source / drain regions of an upper transistor (Ta) to a BSPDN structure, and in some embodiments to electrically connect the upper source / drain region(s) of other upper transistors to a BSPDN structure (142), but this disclosure is not limited thereto.

[0056] The contact power rail structure (122) may extend into the STI region (116) and be electrically connected to the rear power rail (144). In some embodiments, the contact power rail structure (122) may be surrounded by the STI region (116) and an interlayer insulation layer (152). The contact power rail structure (122) may include a metal layer or material, for example, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), cobalt (Co) and / or ruthenium (Ru). Although FIGS. 1b, 1c, and 1d show the contact power rail structure (122) as comprising a single conductive layer, in some embodiments, the contact power rail structure (122) may include multiple conductive layers.

[0057] In some embodiments, the contact power rail structure (122) may be formed in the gate cut area (132) as shown in FIG. 1b. For example, the contact power rail structure (122) may extend in a second direction (X) within the gate cut area (132). The gate cut area (132) may separate (e.g., electrically isolate) the first and second gate structures (170-1, 170-2) adjacent in the first direction (Y). In other words, the upper and lower gate structures (170a, 170b) of the first gate structure (170-1) may be separated by the gate cut area (132) from the upper and lower gate structures (170a, 170b) adjacent in the first direction (Y) of the second gate structure (170-2). For example, the first gate structure (170-1) may be adjacent to and spaced apart from the second gate structure (170-2) in the first direction (Y) with the contact power rail structure (122) in between. The gate cut area (132) extends in the second direction (X) and can separate the first gate structure (170-1) and the second gate structure (170-2) in the first direction (Y) and electrically isolate them.

[0058] The gate cut region (132) includes a contact insulating layer (124) (which may be referred to as a gate cut insulating layer) and a contact insulating liner (126) (which may be referred to as a gate cut insulating liner). In some embodiments, the contact power rail structure (122) may be extended to the contact insulating layer (124) and the contact insulating liner (126). For example, the contact insulating layer (124) and the contact insulating liner (126) may help to electrically isolate the contact power rail structure (122) from the gate structure (170) to prevent an unintended electrical connection (i.e., an electrical short circuit) between them.

[0059] The contact insulating layer (124) and the contact insulating liner (126) may be located between the contact power rail structure (122) and the gate structures (170) in the first direction (Y). For example, the contact insulating layer (124) may be located between the contact insulating liner (126) and the contact power rail structure (122) in the first direction (Y). The contact insulating layer (124) may be located on the opposing sides of the contact power rail structure (122) in the first direction (Y). For example, the contact insulating layer (124) may extend in the second direction (X) on the opposing sides of the contact power rail structure (122). The contact insulating liner (126) may also be located on the opposing sides of the contact power rail structure (122) in the first direction (Y). For example, the contact insulation liner (126) may extend in a second direction (X) on the opposing sides of the contact power rail structure (122). In some embodiments, the contact insulation layer (124) may be in contact with the opposing sides of the contact power rail structure (122) in a first direction (Y) (e.g., directly above), and the contact insulation liner (126) may be in contact with the contact insulation layer (124) (e.g., directly above).

[0060] In some embodiments, the contact insulating layer (124) and the contact insulating liner (126) may extend into the STI region (116). For example, the contact insulating layer (124) and the contact insulating liner (126) may be surrounded by the STI region (116) and the interlayer insulating layer (152). The contact insulating layer (124) and the contact insulating liner (126) may comprise, for example, insulating material(s) (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon carbonitride and / or low dielectric constant material). In some embodiments, the contact insulating layer (124) may comprise a first insulating material, and the contact insulating liner (126) may comprise a second insulating material different from the first insulating material. For example, the contact insulating layer (124) may comprise an oxide material and the contact insulating liner (126) may comprise a nitride material, but the embodiments are not limited thereto.

[0061] As illustrated in FIG. 1b, the contact power rail structure (122) may have a line (or rail) shape in a plan view. That is, the contact power rail structure (122) may have an elongated shape extending in a second direction (X). Thus, the contact power rail structure (122) may overlap with two or more gate structures (170) in a first direction (Y). In other words, the contact power rail structure (122) may extend between the first and second gate structures (170-1, 170-2) on opposite sides of the gate cut area (132). As illustrated in FIG. 1d, the contact power rail structure (122) may overlap with the lower gate structure (170b) of the lower transistor (Tb) and the upper gate structure (170a) of the upper transistor (Ta) in a first direction (Y). Additionally, the contact power rail structure (122) may overlap the lower channel layers (120b) of the lower transistor (Tb) and the upper channel layers (120a) of the upper transistor (Ta) in the first direction (Y). The contact power rail structure (122) may also overlap the pair of lower source / drain regions (140) of the lower transistor (Tb) and the pair of upper source / drain regions (150) of the upper transistor (Ta) in the first direction (Y), as illustrated in FIG. 1b and FIG. 1c.

[0062] Width (W) in the second direction (X) of the contact power rail structure (122) CPR ) is the width (W) in the second direction (X) of each lower source / drain region (140) and each upper source / drain region (150) as illustrated in FIG. 1b. S / D It can be larger than ). For example, the width (W) of the contact power rail structure (122) CPR ) is the width (W) of each lower source / drain area (140) and each upper source / drain area (150). S / D It can be at least twice as large as ). In some embodiments, the width (W) of the contact power rail structure (122) CPR) can be substantially the same as the width of the contact insulating layer (124) and the width of the contact insulating liner (126) in the second direction (X).

[0063] The line (or rail) shape of the contact power rail structure (122) can increase the width and cross-sectional area of ​​the contact power rail structure (122), as well as the contact area with the rear power rail (144) and the upper source / drain contact (156). Thus, the configuration of the contact power rail structure (122) can advantageously reduce the contact resistance with the rear power rail (144) and the upper source / drain contact (156), alleviate current crowding by distributing the current more evenly over a wider area, and reduce the voltage drop during rear power transfer to the upper source / drain region (150) of the upper transistor (Ta). Thus, the performance and reliability of the integrated circuit device (100) can be improved.

[0064] In some embodiments, the integrated circuit device (100) may further include a polycrystalline silicon (polysilicon) layer (128) and a blocking layer (134) between the contact power rail structure (122) in the first direction (Y) and the upper and lower conductive gates (174a, 174b) of the upper and lower transistors (Ta, Tb), as shown in FIG. 1d. The polysilicon layer (128) and the blocking layer (134) may also be located between the contact power rail structure (122) in the first direction (Y) and the upper and lower channel layers (120a, 120b) of the upper and lower transistors (Ta, Tb). For example, the polysilicon layer (128) and the blocking layer (134) can help electrically isolate the contact power rail structure (122) from the upper and lower channel layers (120a, 120b) and the gate structures (170) to prevent unintended electrical connection (i.e., electrical short circuit) between them.

[0065] The polysilicon layer (128) may be located between the contact power rail structure (122) and the blocking layer (134) in the first direction (Y). The blocking layer (134) may be located between the upper and lower channel layers (120a, 120b) and the polysilicon layer (128) in the first direction (Y). For example, the polysilicon layer (128) and the blocking layer (134) may extend to the sides of the upper and lower channel layers (120a, 120b). In some embodiments, the contact insulation layer (124), the contact insulation liner (126), the polysilicon layer (128), and the blocking layer (134) may be sequentially laminated on the sides of the contact power rail structure (122) in the first direction (Y). For example, the polysilicon layer (128) may be in contact with the contact insulation liner (126) (for example, it may be directly above it).

[0066] In some embodiments, the polysilicon layer (128) may be part of the polysilicon remaining during the replacement metal gate (RMG) process for forming gate structures (170) (described in more detail below) (i.e., polysilicon that was not removed). The upper and lower channel layers (120a, 120b) may comprise a semiconductor material different from the polysilicon layer (128) (e.g., single-crystal silicon (Si), Ge, SiGe, GaP, GaAs, SiC, SiGeC and / or InP). The blocking layer (134) may comprise insulating material(s) (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon boron nitride and / or low dielectric constant materials). In some embodiments, the blocking layer (134) may comprise an oxide material (e.g., silicon oxide).

[0067] FIGS. 2a and 2b are schematic plan views (or layout views) showing rear power rails of integrated circuit devices according to some embodiments. For convenience of explanation, repetitive descriptions of elements similar to those described above may be omitted.

[0068] Referring to FIG. 2a, the integrated circuit device (100a) may include rear power rails (144) (shown by dashed lines) extending in a second direction (X) (i.e., extending in the longitudinal direction). As shown in FIG. 2a, according to some embodiments, each rear power rail (144) electrically connected to a contact power rail structure (122) may extend continuously in the second direction (X) from the lower surface of the contact power rail structure (122).

[0069] Referring to FIG. 2b, the integrated circuit device (100b) may include rear power rails (144) (shown by dashed lines) extending in a second direction (X) (i.e., extending in the longitudinal direction). As shown in FIG. 2b, according to some embodiments, each rear power rail (144) electrically connected to a contact power rail structure (122) may extend discontinuously in the second direction (X) from the lower surface of the contact power rail structure (122). That is, as shown in FIG. 2b, each rear power rail (144) may include a first part (144-1) (which may also be referred to as the first segment) and a second part (144-2) (which may also be referred to as the second segment) that are all electrically connected to the contact power rail structure (122) and spaced apart from each other in the second direction (X). Returning to Fig. 1d while continuing to refer to Fig. 2b, it will be understood that in Fig. 1d, the rear power rail (144) is shown below (and electrically connected to) the contact power rail structure (122), but this rear power rail (144) may not be visible in the cross-sectional view of Fig. 1d if it has the configuration shown in the plan view of Fig. 2b.

[0070] Referring to FIGS. 2a and 2b, the line (or rail) shape of the contact power rail structure (122) allows the rear power rail (144) to include a number of discontinuous sections (e.g., sections (144-1, 144-2)), each section may remain electrically connected to the contact power rail structure (122) due to its elongated shape (see FIG. 2b) or, alternatively, allow the rear power rail (144) to extend continuously below the contact power rail structure (122) (see FIG. 2a). Thus, the configuration of the contact power rail structure (122) provides design flexibility for the rear power rail (144), which can enable optimized power delivery to the BSPDN structure (144) and / or improved layout efficiency for integrated circuit devices.

[0071] FIGS. 3a, 3b, 3c, 3d, 3e, 3f, and 3g are schematic cross-sectional views illustrating a method of forming integrated circuit devices according to some embodiments. In particular, FIGS. 3a, 3b, 3c, 3d, 3e, 3f, and 3g are schematic cross-sectional views corresponding to the line B-B' in FIG. 1b. FIG. 4 is a flowchart illustrating a method of forming an integrated circuit device according to some embodiments. For convenience of explanation, repetitive descriptions of elements similar to those described above may be omitted.

[0072] Referring to FIG. 3a and FIG. 4, upper and lower channel layers (120a, 120b) can be formed that are stacked and spaced apart in a third direction (Z) (i.e., vertical direction) (block (405) of FIG. 4). In some embodiments, the upper and lower channel layers (120a, 120b) can be alternately stacked with sacrificial channel layers (321p) in the third direction (Z). For example, the lower channel layers (120b) can be alternately stacked with the lower layers of the sacrificial channel layers (321p) in the third direction (Z), and the upper channel layers (120a) can be alternately stacked with the upper layers of the sacrificial channel layers (321p) in the third direction (Z). The upper channel layers (120a) can be positioned on the lower channel layers (120b) in the third direction (Z).

[0073] The upper and lower channel layers (120a, 120b) may be semiconductor layers. In some embodiments, the upper and lower channel layers (120a, 120b) may comprise, for example, silicon (e.g., silicon layers). The sacrificial channel layers (321p) may have etch selectivity with respect to the upper and lower channel layers (120a, 120b) (i.e., may exhibit etch selectivity), so that the sacrificial channel layers (321p) may be selectively removed in a subsequent operation. In some embodiments, the sacrificial channel layers (321p) may comprise, for example, silicon germanium (e.g., silicon germanium layers).

[0074] In some embodiments, upper and lower channel layers (120a, 120b) may be formed on a semiconductor substrate (310). The semiconductor substrate (310) may comprise semiconductor material(s) (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC and / or InP). For example, the semiconductor substrate (310) may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc. Although FIG. 3a illustrates the semiconductor substrate (310) as a single layer, in some embodiments, the semiconductor substrate (310) may comprise a plurality of layers (e.g., a plurality of semiconductor layers). In some other embodiments, the upper and lower channel layers (120a, 120b) may be formed on the substrate (110) described above with reference to FIGS. 1a to 1d.

[0075] An isolation region (130) may be formed between the upper channel layers (120a) and the lower channel layers (120b). The isolation region (130) may be a spacer that separates (i.e., electrically isolates) the lower channel layers (120b) from the upper channel layers (120a). A shallow trench isolation (STI) region (116) may be formed adjacent to the semiconductor substrate (310) and may be located on opposite sides of the stack of the upper and lower channel layers (120a, 120b) and the sacrificial channel layers (321p) (e.g., in the first direction (Y)).

[0076] A white blocking layer (134p) may be formed on the upper and lower channel layers (120a, 120b). The sacrificial blocking layer (134p) may be located on top of the stack of the upper and lower channel layers (120a, 120b) and the sacrificial channel layers (321p), and may extend to the sides of the stack. The sacrificial blocking layer (134p) may also be formed on the STI region (116). The sacrificial blocking layer (134p) may comprise, for example, insulating material(s) (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon boron nitride and / or low dielectric constant material). In some embodiments, the sacrificial blocking layer (134p) may comprise an oxide material (e.g., silicon oxide).

[0077] Referring further to FIGS. 3a and FIGS. 4, a sacrificial gate layer (128p) may be formed on the upper and lower channel layers (120a, 120b) (block (410) of FIG. 4). The sacrificial gate layer (128p) may surround the stack of the upper and lower channel layers (120a, 120b) and the sacrificial channel layers (321p). For example, the sacrificial gate layer (128p) may be located on top of the stack of the upper and lower channel layers (120a, 120b) and the sacrificial channel layers (321p), and may extend to the sides of the stack. A sacrificial blocking layer (134p) may be located between the sacrificial gate layer (128p) and the stack of the upper and lower channel layers (120a, 120b) and the sacrificial channel layers (321p). In some embodiments, the sacrificial gate layer (128p) may comprise, for example, polysilicon (e.g., a polysilicon layer). The sacrificial gate layer (128p) may be replaced at least partially with metal in subsequent operations.

[0078] Referring to FIGS. 1a, FIGS. 1b, FIGS. 3a and FIGS. 4, a pair of lower source / drain regions (140) may be formed on mutually opposing sides of lower channel layers (120b), and a pair of upper source / drain regions (150) may be formed on mutually opposing sides of upper channel layers (120a) (block (415) of FIG. 4). For example, the lower source / drain regions (140) may be formed by performing an epitaxial growth process using the lower channel layers (120b) as a seed layer, and the lower source / drain regions (140) may be epitaxially grown from mutually opposing sides of the lower channel layers (120b) (e.g., in a second direction (X)). Similarly, upper source / drain regions (150) may be formed by performing an epitaxial growth process using upper channel layers (120a) as a seed layer, and the upper source / drain regions (150) may be epitaxially grown from mutually opposing sides of the upper channel layer (120a) (e.g., in a second direction (X)). In some embodiments, an interlayer insulating layer (152) may be formed on (i.e., to surround) the lower and upper source / drain regions (140, 150) (see FIG. 1c).

[0079] Referring to FIG. 3b and FIG. 4, a trench (340) may be formed in the sacrificial gate layer (128p) (block (420) in FIG. 4). For example, the trench (340) may be formed through the sacrificial gate layer (128p) to separate the sacrificial gate layer (128p) into distinct parts (e.g., parts (128p-1, 128p-2)) along a first direction (Y). As shown in FIG. 3b, the trench (340) may separate the sacrificial gate layer (128p) into a first part (128p-1) and a second part (128p-2) spaced apart in the first direction (Y). In some embodiments, the trench (340) may extend to the sacrificial blocking layer (134p) and the STI region (116). For example, an etching process (e.g., dry etching and / or wet etching) may be performed to form a trench (340) in the sacrificial gate layer (128p).

[0080] The trench (340) may extend adjacent to the stack of upper and lower channel layers (120a, 120b) and sacrificial channel layers (321p). For example, the trench (340) may overlap with the upper and lower channel layers (120a, 120b) in a first direction (Y). In some embodiments, the trench (340) may extend in a second direction (X) (i.e., into the page of FIG. 3b) in a longitudinal direction (i.e., vertical direction). For example, the trench (340) may correspond to the area where the gate cut region (132) (see FIG. 1b) is formed in a subsequent operation.

[0081] Referring to FIG. 3c and FIG. 4, a contact insulating liner (126) and a contact insulating layer (124) may be formed in a trench (340) (block (425) in FIG. 4). For example, the contact insulating liner (126) may be formed on the inner walls and bottom surface of the trench (340) (see FIG. 3b) (e.g., may be formed conformally). The contact insulating layer (124) may be formed within the trench (340) on the contact insulating liner (126) and, in some embodiments, may substantially fill the remaining portion of the trench (340). For example, the contact insulating liner (126) and the contact insulating layer (124) may be formed (i.e., deposited) within the trench (340) using a deposition process. The contact insulating liner (126) and the contact insulating layer (124) may include the gate cut region (132) described above with reference to FIG. 1b.

[0082] Referring to FIG. 3d and FIG. 4, the sacrificial gate layer (128p) can be removed at least partially (block (430) in FIG. 4). For example, the sacrificial gate layer (128p) can be selectively removed using a selective etching process (e.g., selective wet etching and / or dry etching).

[0083] In some embodiments, the sacrificial gate layer (128p) may be partially removed without removing the entire sacrificial gate layer (128p) to form a polysilicon layer (128) adjacent to the upper and lower channel layers (120a, 120b) (e.g., in the first direction (Y)). For example, the unremoved portion (i.e., the unstriped portion) of the sacrificial gate layer (128p) may form the polysilicon layer (128). The polysilicon layer (128) may be located on the sides of the upper and lower channel layers (120a, 120b) in the first direction (Y). For example, the polysilicon layer (128) may be located between the contact insulating layer (124) and the upper and lower channel layers (120a, 120b) in the first direction (Y). The polysilicon layer (128) may also be located between the contact insulation liner (126) and the upper and lower channel layers (120a, 120b) in the first direction (Y). In some embodiments, the polysilicon layer (128) may be in contact with the contact insulation liner (126) and the sacrificial blocking layer (134p) (e.g., directly above them). For example, the polysilicon layer (128) may help to electrically isolate the upper and lower channel layers (120a, 120b) from the contact power rail structure (122) formed in a subsequent operation.

[0084] Referring to FIG. 3e and FIG. 4, sacrificial channel layers (321p) can be removed (block (435) in FIG. 4). For example, sacrificial channel layers (321p) between adjacent layers of the upper channel layers (120a) and between adjacent layers of the lower channel layers (120b) can be selectively removed without removing the upper and lower channel layers (120a, 120b). In some embodiments, a selective etching process (e.g., selective wet etching and / or dry etching) may be performed to remove the sacrificial channel layers (321p). By removing the sacrificial channel layers (321p), spaces (or openings) may be formed between adjacent layers of the upper channel layers (120a) and between adjacent layers of the lower channel layers (120b).

[0085] The sacrificial blocking layer (134p) may also be removed at least partially. In some embodiments, the sacrificial blocking layer (134p) may be partially removed without removing the entire sacrificial blocking layer (134p) to form a blocking layer (134) on the sides of the upper and lower channel layers (120a, 120b). For example, the unremoved portion (i.e., the unstripped portion) of the sacrificial blocking layer (134p) may form the blocking layer (134). For example, the blocking layer (134) may help to electrically isolate the upper and lower channel layers (120a, 120b) from the contact power rail structure (122) formed in a subsequent operation.

[0086] Referring to FIG. 3f and FIG. 4, a first gate structure (170-1) may be formed on upper and lower channel layers (120a, 120b) (block (440) of FIG. 4). In some embodiments, forming the first gate structure (170-1) may include forming an upper gate structure (170a) on the upper channel layers (120a) and forming a lower gate structure (170b) on the lower channel layers (120b). For example, forming the upper and lower gate structures (170a, 170b) may include forming a gate insulator (172) on the upper and lower channel layers (120a, 120b) and forming upper and lower conductive gates (174a, 174b) on the gate insulator (172). In some embodiments, the gate insulator (172) may also be formed on the semiconductor substrate (310) and the STI region (116).

[0087] As described above, forming the first gate structure (170-1) may include forming a sacrificial gate layer (128p) and then replacing at least a portion of the sacrificial gate layer (128p) with metal-conducting gates (174a, 174b). Thus, the first gate structure (170-1) may be formed using a replacement metal gate (RMG) process. In some embodiments, the second gate structure (170-2) may also be formed using an RMG process as shown in FIG. 3f. For example, the first gate structure (170-1) and the second gate structure (170-2) may be adjacent to each other in a first direction (Y) and separated from each other in a first direction (Y) by a contact insulating layer (124) and a contact insulating liner (126).

[0088] As illustrated in FIG. 3f, an upper gate structure (170a) may surround upper channel layers (120a), and a lower gate structure (170b) may surround lower channel layers (120b). For example, an upper conductive gate (174a) may extend to the upper, lower, and side surfaces of each upper channel layer (120a). A lower conductive gate (174b) may extend to the upper, lower, and side surfaces of each lower channel layer (120b). In some embodiments, the upper and lower conductive gates (174a, 174b) may be formed by depositing one or more conductive layers (e.g., a metal layer and / or a work function layer(s), the upper portion of these layers may form the upper conductive gate (174a), and the lower portion of these layers may form the lower conductive gate (174b). For example, the upper and lower conductive gates (174a, 174b) may be integrated into a monolithic or single structure, that is, the same process or the same series of processes (e.g., without structurally or visually separated interfaces), but the embodiments are not limited thereto. Thus, the upper and lower conductive gates (174a, 174b) may have a common interface (174_I) (shown as a dashed line in FIG. 3f).

[0089] Referring to FIG. 3g and FIG. 4, a contact power rail structure (122) may be formed in a contact insulation layer (124) (block (445) in FIG. 4). For example, the contact power rail structure (122) may extend into the contact insulation layer (124). In some embodiments, the contact power rail structure (122) also extends to the lower part of the contact insulation liner (126). The contact power rail structure (122) may extend in a second direction (X) (i.e., extend in the longitudinal direction) (see FIG. 1b) and may overlap with the upper and lower channel layers (120a, 120b) in a first direction (Y).

[0090] In some embodiments, forming the contact power rail structure (122) may include forming a trench (or opening) in the contact insulating layer (124) and forming the contact power rail structure (122) in the trench. For example, an etching process (e.g., dry etching and / or wet etching) may be performed to form a trench in the contact insulating layer (124), and a deposition process may be used to form (i.e., deposit) the contact power rail structure (122) in the trench within the contact insulating layer (124).

[0091] As illustrated in FIG. 3g, the contact power rail structure (122) may overlap with the upper and lower gate structures (170a, 170b) in the first direction (Y). The contact insulating layer (124) and the contact insulating liner (126) may be located on opposite sides of the contact power rail structure (122) in the first direction (Y). For example, the contact insulating layer (124) and the contact insulating liner (126) may help to electrically isolate the contact power rail structure (122) from the upper and lower gate structures (170a, 170b) (e.g., upper and lower conductive gates (174a, 174b)). The polysilicon layer (128) and the blocking layer (134) may be located between the contact power rail structure (122) and the upper and lower channel layers (120a, 120b) in the first direction (Y). For example, the polysilicon layer (128) and the blocking layer (134) may help to electrically isolate the contact power rail structure (122) from the upper and lower channel layers (120a, 120b).

[0092] Referring to FIG. 4 and again to FIG. 1b, FIG. 1c and FIG. 1d, an upper source / drain contact (156) can be formed on an upper source / drain region (150) and a contact power rail structure (122) (block (450) in FIG. 4). The upper source / drain contact (156) can be electrically connected to the upper source / drain region (150) and the contact power rail structure (122). For example, the upper source / drain contact (156) can be formed during the middle-of-line (MOL) portion of device manufacturing.

[0093] In some embodiments, the upper gate contact (178) may be formed on the upper and lower gate structures (170a, 170b). For example, the upper gate contact (178) may be formed during the middle-of-line (MOL) portion of device manufacturing.

[0094] The upper structure (138) may be formed on the upper and lower transistors (Ta, Tb). For example, the upper structure (138) may include elements formed during the middle-of-line (MOL) and / or back-end-of-line (BEOL) portions of device manufacturing. The upper structure (138) may include conductive elements (e.g., wire(s) and / or via plug(s)) and insulating elements (e.g., interlayer insulating(s) and / or spacer(s).

[0095] In some embodiments, the semiconductor substrate (310) may be at least partially removed and replaced with the substrate (110). For example, the semiconductor substrate (310) may be selectively removed using an optional etching process (e.g., optional wet etching and / or dry etching). A rear contact structure (148) may be formed on the substrate (110) and on the underside of the lower source / drain region (140). For example, the rear contact structure (148) may extend into the substrate (110) to make contact (e.g., electrical contact) with the lower source / drain region (140).

[0096] Referring further to FIG. 1b, FIG. 1c, FIG. 1d and FIG. 4, a BSPDN structure (142) may be formed on a second surface (S2) (i.e., the rear surface) of a substrate (110) (block (455) of FIG. 4). For example, the BSPDN structure (142) may be formed on the lower surfaces of the lower source / drain regions (140). The BSPDN structure (142) may include a rear insulator (146) and a plurality of rear power rails (144) formed on the rear insulator (146).

[0097] In some embodiments, forming the BSPDN structure (142) includes forming a first rear power rail (144) on the lower surface of the contact power rail structure (122). Also, in some embodiments, forming the BSPDN structure (142) may include forming a second rear power rail (144) on the lower surface of the rear contact structure (148). For example, the second rear power rail (144) may be adjacent to the first rear power rail (144) (e.g., in the first direction (Y)). The contact power rail structure (122) may electrically connect the upper source / drain region (150) of the upper transistor (Ta) to the first rear power rail (144), as shown in FIG. 1c. Additionally, the rear contact structure (148) can electrically connect the lower source / drain region (140) of the lower transistor (Tb) to the second rear power rail (144), as shown in FIG. 1c. Thus, the integrated circuit device (100) shown in FIG. 1b to 1d can be formed.

[0098] As illustrated in FIG. 1b, the contact power rail structure (122) may have a line (or rail) shape in a plan view. The line (or rail) shape can increase the width and cross-sectional area of ​​the contact power rail structure (122), as well as the contact area with the rear power rail (144) and the upper source / drain contact (156). Thus, the configuration of the contact power rail structure (122) can advantageously reduce the contact resistance with the rear power rail (144) and the upper source / drain contact (156), alleviate current concentration by distributing the current more evenly over a wider area, and reduce the voltage drop while delivering rear power to the upper source / drain region (150) of the upper transistor (Ta). Thus, the performance and reliability of the integrated circuit device (100) can be improved. The configuration of the contact power rail structure (122) can also provide design flexibility for the rear power rail (144), enabling optimized power delivery for the BSPDN structure (142) and / or improved layout efficiency for the integrated circuit device.

[0099] FIG. 5 is a schematic plan view (or layout view) showing an integrated circuit device according to a comparative example. For convenience of explanation, repetitive descriptions of elements similar to those described above may be omitted.

[0100] Referring to FIG. 5, the integrated circuit device (100c) may include a contact power structure (122c) having a square shape in a plan view. For example, the contact power structure (122c) may resemble a via and have a relatively high height (or thickness) in the third direction (Z) and a relatively narrow width in the second direction (X), so that the aspect ratio of the contact power structure (122c) may be relatively high. The square shape not only reduces the width and cross-sectional area of ​​the contact power structure (122c), but also reduces the contact area with the rear power rail (not shown) and the upper source / drain contact (156). Thus, the configuration of the contact power structure (122c) may increase the contact resistance with the rear power rail and the upper source / drain contact (156), and may increase current concentration and voltage drop during rear power transfer.

[0101] Unless otherwise defined, all terms used in this disclosure have the same meaning as generally understood by a person skilled in the art. Furthermore, all terms should be interpreted in a meaning consistent with the relevant technology and the context of this disclosure, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in this disclosure.

[0102] In the foregoing description, exemplary embodiments may be described with reference to regions of specific conductivity types. It will be seen that in each of the above embodiments, devices of opposite conductivity types can be formed by simply reversing the conductivity of the n-type and p-type layers. Thus, it will be seen that the present disclosure can encompass both n-channel and p-channel devices for each different device structure.

[0103] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the embodiments. Singular forms are intended to include plural forms unless clearly otherwise indicated in the context. The terms “comprising” and / or “comprising” specify the presence of the specified features, steps, actions, elements, components, and / or groups, but do not exclude the presence or addition of one or more other features, steps, actions, elements, components, and / or groups.

[0104] Throughout this disclosure, terms such as “first,” “second,” “third,” etc., may be used to describe various elements, but it will be understood that these elements are not to be limited by these terms. Rather, these terms are used merely to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. The term “and / or” as used in this disclosure includes any combination of one or more of the related and listed items.

[0105] The terms “enclose,” “cover,” or “fill” as used in this disclosure may not mean to completely enclose, cover, or fill the described elements or layers, but may mean, for example, to partially enclose, cover, or fill the described elements or layers. With respect to “overlapping” in a particular direction, the described components or layers may be at least partially obscured from one another when viewed from a line extending in a particular direction or from a plane perpendicular to a particular direction.

[0106] When an element, such as a layer, region, or substrate, is described as being “on” or “above” another element, it should be understood that this may mean it is directly above or extends directly above the other element, or that intervening elements may be present. Conversely, when an element is described as being “on” or extending “directly above” another element, no intervening elements are present. Additionally, when an element is described as being “connected” or “coupled” to another element, it should be understood that this may mean it is directly connected or coupled to the other element, or that intervening elements may be present. Conversely, when an element is described as being “directly connected” or “directly coupled” to another element, no intervening elements are present. The term “connected” may include physical and / or electrical connections.

[0107] Spatially relative terms such as “below,” “above,” “top,” “bottom,” “top surface,” “bottom surface,” or “side” may be used in this disclosure to describe the relationship between one element, layer, or region and another element, layer, or region based on a reference frame (e.g., a substrate), as illustrated in the drawings. These terms should be understood as intended to encompass various orientations of the device in addition to the orientations illustrated in the drawings.

[0108] Exemplary embodiments are described with reference to the drawings attached herein, which may include cross-sectional views that are schematic drawings of ideal embodiments (and intermediate structures). Many different forms and embodiments are possible without departing from the teachings of this disclosure. Accordingly, this disclosure should not be interpreted as being limited to the exemplary embodiments described herein. Accordingly, a person skilled in the art will understand that various changes in form and detail are possible without departing from the scope defined in this disclosure. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Also, the shapes in the drawings may vary, for example, due to manufacturing techniques and / or tolerances.

[0109] Embodiments of the present disclosure are also described with reference to manufacturing operations and flowcharts. It will be understood that the steps illustrated in the manufacturing operations and flowcharts do not need to be performed in the illustrated order.

[0110] The subject matter disclosed above should be regarded as exemplary rather than limiting, and the appended claims are intended to encompass all modifications, improvements, and other embodiments falling within the scope of this disclosure. Accordingly, to the maximum extent permitted by law, the scope of this disclosure shall be determined by the broadest permissible interpretation of the claims below and their equivalents, and shall not be limited or restricted by the detailed description above. Explanation of the symbols

[0111] 120a: Upper channel layers 120b: Lower channel layers 122: Contact Power Rail Structure 124: Contact insulation layer 126: Contact insulation liner 132: Gate Cut Area 140: Lower source / drain areas 150: Upper source / drain areas 156: Upper source / drain contact 170-1: First gate structures 170-2: Second Gate Structures

Claims

Claim 1 An integrated circuit device comprising: a substrate; a lower transistor on a first surface of the substrate; an upper transistor on the lower transistor—the upper transistor comprises an upper gate structure extending in a first lateral direction parallel to the first surface of the substrate and an upper source / drain region adjacent to the upper gate structure in a second lateral direction orthogonal to the first lateral direction—a rear power transfer network (BSPDN) structure on a second surface of the substrate facing the first surface—the BSPDN structure comprises a rear power rail—and a contact power rail structure electrically connecting the upper source / drain region to the rear power rail, wherein the contact power rail structure overlaps with the upper gate structure in the first lateral direction. Claim 2 An integrated circuit device according to claim 1, further comprising a contact insulating layer on opposite sides of the contact power rail structure in the first lateral direction, wherein the contact insulating layer is located between the contact power rail structure and the upper gate structure in the first lateral direction. Claim 3 An integrated circuit device according to claim 2, further comprising a contact insulating liner on the opposing sides of the contact power rail structure in the first lateral direction, wherein the contact insulating layer is located between the contact rail structure and the contact insulating liner in the first lateral direction. Claim 4 An integrated circuit device according to claim 3, wherein the contact insulating layer comprises a first insulating material, and the contact insulating liner comprises a second insulating material different from the first insulating material. Claim 5 The integrated circuit device according to claim 1, further comprising a gate cut area separating adjacent gate structures in the first lateral direction, wherein the contact power rail structure extends within the gate cut area. Claim 6 An integrated circuit device according to claim 5, wherein the gate cut region comprises: a contact insulating layer on the opposing sides of the contact power rail structure in the first lateral direction; and a contact insulating liner on the opposing sides of the contact power rail structure in the first lateral direction, with the contact insulating layer in between. Claim 7 The integrated circuit device according to claim 1, wherein the upper gate structure is included in the first gate structure, and the integrated circuit device further includes a second gate structure spaced apart from the first gate structure in the first lateral direction with the contact power rail structure in between. Claim 8 An integrated circuit device according to claim 1, further comprising a polysilicon layer located between the contact power rail structure and the upper gate structure in the first lateral direction, wherein the upper gate structure comprises a metal material. Claim 9 In claim 1, the rear power rail is a first rear power rail, and The above BSPDN structure further includes a second rear power rail adjacent to the first rear power rail, and the lower transistor includes a lower source / drain region, and An integrated circuit device further comprising a rear contact structure that extends to the substrate and electrically connects the lower source / drain region to the second rear power rail. Claim 10 An integrated circuit device according to claim 1, wherein the lower transistor comprises a lower gate structure extending in the first lateral direction and a lower source / drain region adjacent to the lower gate structure in the second lateral direction, and the contact power rail structure overlaps with the lower gate structure in the first lateral direction. Claim 11 In claim 1, the rear power rail is an integrated circuit device that extends continuously from the lower surface of the contact power rail structure in the second lateral direction. Claim 12 An integrated circuit device according to claim 1, wherein the rear power rail extends discontinuously from the lower surface of the contact power rail structure, and the rear power rail comprises: a first portion electrically connected to the contact power rail structure; and a second portion electrically connected to the contact power rail structure and spaced apart from the first portion in the second lateral direction. Claim 13 An integrated circuit device according to claim 1, further comprising an upper source / drain contact on the upper source / drain region, wherein the upper source / drain contact is electrically connected to the upper source / drain region and the contact power rail structure. Claim 14 An integrated circuit device comprising: a substrate; a lower transistor on a first surface of the substrate; an upper transistor on the lower transistor—the upper transistor comprises an upper gate structure extending in a first lateral direction parallel to the first surface of the substrate and an upper source / drain region adjacent to the upper gate structure in a second lateral direction orthogonal to the first lateral direction—a rear power transfer network (BSPDN) structure on a second surface of the substrate facing the first surface—the BSPDN structure comprises a rear power rail—and a contact power rail structure electrically connecting the upper source / drain region to the rear power rail, wherein the width of the contact power rail structure in the second lateral direction is greater than the width of the upper source / drain region in the second lateral direction. Claim 15 In claim 14, the gate cut area separating adjacent gate structures in the first lateral direction is further included, and the contact power rail structure extends into the gate cut area, and The gate cut region is an integrated circuit device comprising a contact insulating layer located between the contact power rail structure and the upper gate structure in the first lateral direction. Claim 16 A method for forming an integrated circuit device comprising: a step of forming a lower channel layer and an upper channel layer—the lower and upper channel layers being spaced apart in a vertical direction—; a step of forming a lower source / drain region on the side of the lower channel layer and an upper source / drain region on the side of the upper channel layer; a step of forming a contact power rail structure that overlaps with at least one of the lower channel layer or the upper channel layer in a first lateral direction orthogonal to the vertical direction; and a step of forming a rear power transmission network (BSPDN) structure including a rear power rail on the lower surface of the contact power rail structure, wherein the contact power rail structure electrically connects the upper source / drain region to the rear power rail. Claim 17 A method for forming an integrated circuit device according to claim 16, further comprising: forming a sacrificial gate layer that at least partially surrounds the lower and upper channel layers; and partially removing the sacrificial gate layer without removing the entire sacrificial gate layer to form a polysilicon layer adjacent to the upper and lower channel layers, wherein the polysilicon layer is located between the contact power rail structure and the lower and upper channel layers in the first lateral direction. Claim 18 A method for forming an integrated circuit device according to claim 16, further comprising the steps of: forming a sacrificial gate layer that at least partially surrounds the lower and upper channel layers; forming a trench in the sacrificial gate layer; forming a contact insulating liner on the inner sidewalls and lower surface of the trench; and forming a contact insulating layer on the trench and the contact insulating liner, wherein the step of forming the contact power rail structure comprises forming the contact power rail structure on the contact insulating layer, and wherein the contact insulating liner and the contact insulating layer are located on opposite sides of the contact power rail structure in the first lateral direction. Claim 19 A method for forming an integrated circuit device according to claim 16, further comprising: forming a sacrificial gate layer that at least partially surrounds the lower and upper channel layers; forming a trench penetrating the sacrificial gate layer to separate the sacrificial gate layer into distinct portions along the first lateral direction; and forming a contact insulating layer within the trench, wherein the contact power rail structure extends into the contact insulating layer. Claim 20 A method for forming an integrated circuit device according to claim 19, further comprising the step of removing at least partially the sacrificial gate layer—the gate structure comprising a lower gate structure that at least partially surrounds the lower channel layer and an upper gate structure that at least partially surrounds the upper channel layer—wherein the contact power rail structure overlaps with the lower and upper gate structures in the first lateral direction.

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