Stacked semiconductor device including gate etch structure

Abstract

A semiconductor device is provided. The semiconductor device may include a first channel structure, a first source / drain region on the first channel structure, wherein the first source / drain region and the first channel structure are connected in a first direction, a gate structure on the first channel structure, and a first gate-etch structure that is on the first channel structure and includes an insulating material. The first gate-etch structure is connected to the first channel structure in a second direction intersecting the first direction, and the first gate-etch structure does not extend beyond the length of the first channel structure in the first direction along the side of the first source / drain region extending in the first direction.

Description

Technology Field

[0001] Devices consistent with exemplary embodiments of the present disclosure relate to a semiconductor device comprising one or more gate etching structures. Background Technology

[0002] In response to the increased demand for semiconductor devices with high device density and performance, stacked field-effect transistor (FET) devices are introduced. The stacked semiconductor device comprises a first FET at a first level and a second FET at a second level higher than the first level, and each of the two FETs may be a fin field-effect transistor (FinFET), a nanosheet transistor, a forksheet transistor, or any other type of FET. A stacked semiconductor device formed of FinFETs, nanosheet transistors, or forksheet transistors may also be referred to as a 3D-stacked semiconductor device.

[0003] A FinFET comprises, as a channel structure, one or more fin structures protruding from a substrate and a gate structure surrounding at least three surfaces of each of the fin structures. A nanosheet transistor features, as a channel structure, one or more nanosheet channel layers stacked or arranged vertically on a substrate and a gate structure surrounding all four surfaces of each of the nanosheet channel layers. Nanosheet transistors are also referred to as gate-all-around (GAA) transistors or multi-bridge channel field-effect transistors (MBCFETs). A forksheet transistor is a combination of two nanosheet transistors with an isolation wall between them. In a forksheet transistor, the nanosheet channel layers of each nanosheet transistor are formed on each side of the isolation wall and pass through a gate structure parallel to the isolation wall.

[0004] In addition to stacked semiconductor devices, a backside power distribution network (BSPDN) structure formed on the back of the semiconductor device is introduced to address heavy traffic of signal lines and power rails, high device density, and increased contact resistance between structural elements of the stacked semiconductor device on the front of the semiconductor device. Here, the front refers to the side on which a transistor structure, including a channel structure, a gate structure, and source / drain regions, is formed with respect to the substrate of the semiconductor device, and the back refers to the side opposite to the front. The BSPDN structure may include backside metal lines, such as buried power rails connected to a voltage source and buried signal lines connected to other circuit elements. Additionally, the BSPDN structure may include backside contact plugs that connect active elements, such as source / drain regions of the semiconductor device, to buried power rails or signal lines through the back of the semiconductor device. In embodiments, the BSPDN structure may be more useful for stacked semiconductor devices.

[0005] Meanwhile, because stacked semiconductor devices are formed with a high aspect ratio within a very dense region, they present various problems, including difficulties in manufacturing and implementing low-power devices and low-resistance / capacitance devices.

[0006] The information disclosed in this background section is technical information that was already known to the inventors prior to achieving the embodiments of this application or was obtained in the process of achieving the embodiments described herein. Therefore, the disclosed information may include information that does not constitute prior art already known to the public. The problem to be solved

[0007] According to embodiments of the present disclosure, a stacked semiconductor device including a gate etching structure is provided. means of solving the problem

[0008] The present disclosure provides a stacked semiconductor device in which one or more gate-etched structures are formed to reduce the size or volume of the gate structure and the lower channel structure, to reduce the capacitance between at least the gate structure and the source / drain regions, and also to realize a low-power semiconductor device.

[0009] According to an aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a first channel structure, a first source / drain region on the first channel structure, wherein the first source / drain region and the first channel structure are connected in a first direction, a gate structure on the first channel structure, and a first gate-etch structure on the first channel structure. The first gate-etch structure may include an insulating material. The first gate-etch structure may be connected to the first channel structure in a second direction intersecting the first direction, and the first gate-etch structure may not extend beyond the length of the first channel structure in the first direction along the side of the first source / drain region extending in the first direction.

[0010] According to an aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a first channel structure, a first source / drain region on the first channel structure, wherein the first source / drain region and the first channel structure are connected in a first direction, a first gate structure on the first channel structure, and a first gate-etch structure on the first channel structure. The first gate-etch structure may include an insulating material. The first gate-etch structure may be connected to the first channel structure in a second direction intersecting the first direction, and the length of the first gate-etch structure may be equal to the length of the first gate structure in the first direction.

[0011] According to an aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a first gate structure and a second gate structure adjacent to each other in a first direction, wherein the first gate structure and the second gate structure extend in a second direction intersecting the first direction, a source / drain region between the first gate structure and the second gate structure, and a gate-etch structure that is above the first gate structure among the first gate structure and the second gate structure and comprises an insulating material.

[0012] According to an aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method may include the steps of forming a first channel structure, forming a first source / drain region and a first source / drain region on the first channel structure such that the first channel structure is connected in a first direction, forming a first gate structure on the first channel structure, and forming a first gate-etch structure on the first gate structure such that the first gate-etch structure is connected to the first channel structure in a second direction intersecting the first direction, and the first gate-etch structure is not extended beyond the length of the first channel structure in the first direction along the side of the first source / drain region extending in the first direction. Effects of the invention

[0013] According to embodiments of the present disclosure, a stacked semiconductor device including a gate etching structure is provided.

[0014] In addition, according to embodiments of the present disclosure, by forming one or more gate-etched structures within a semiconductor device, the size or volume of the gate structure and the lower channel structure is reduced, the capacitance between the gate structure and the source / drain regions is reduced, and a low-power semiconductor device can be realized. Brief explanation of the drawing

[0015] Exemplary embodiments of the present disclosure will be more clearly understood from the detailed description that follows, together with the accompanying drawings. FIGS. 1a to 1d illustrate a stacked semiconductor device having different channel widths and different source / drain region widths according to one or more embodiments. FIGS. 2a to 2d illustrate a stacked semiconductor device comprising a gate-etched structure according to one or more embodiments. FIGS. 3a to 3d illustrate a stacked semiconductor device comprising vertically overlapping gate-etched structures according to one or more embodiments. FIGS. 4a to 4d illustrate a stacked semiconductor device comprising gate-etched structures that are not vertically overlapped, according to one or more embodiments. FIGS. 5a to 5l illustrate intermediate semiconductor devices obtained after each step of manufacturing a stacked semiconductor device including gate-etched structures according to one or more embodiments. FIGS. 6a and 6b are flowcharts for manufacturing a stacked semiconductor device including gate-etched structures according to one or more embodiments. FIG. 7 is a schematic block diagram illustrating an electronic device comprising one or more stacked semiconductor devices including one or more gate-etched structures according to one or more embodiments. Specific details for implementing the invention

[0016] All embodiments of the present disclosure described herein are exemplary embodiments and, therefore, the present disclosure is not limited thereto and may be realized in various other forms. Each of the embodiments provided in the following description does not exclude the possibility that it may be associated with one or more features of other examples or other embodiments that are provided in the present specification or that are not provided in the present specification but are consistent with the present disclosure. For example, even if matters described in a particular example or embodiment are not described in another example or embodiment, unless otherwise stated, such matters may be understood to be related to or combined with other examples or embodiments. Furthermore, all descriptions of the principles, aspects, examples, and embodiments of the present disclosure should be understood to include structural and functional equivalents. Furthermore, such equivalents should be understood to include not only currently well-known equivalents but also equivalents to be developed in the future, that is, all elements invented to perform the same functions regardless of structure. For example, the channel layers, sacrifice layers, and isolation layers described herein may take other types or forms as long as the present disclosure is applicable.

[0017] If an element, component, layer, pattern, structure, region, or similar thing of a semiconductor device (collectively referred to as an “element”) is referred to as “over,” “on,” “on,” “below,” “under,” “below,” “connected,” or “combined” with respect to another element of the semiconductor device, there may be element(s) that can be directly over, over, on, below, under, or connected to, or that intervene with respect to, the other element. In contrast, if an element of a semiconductor device is referred to as “directly over,” “directly on,” “directly on,” “directly below,” “directly under,” “directly beneath,” “directly connected,” or “directly combined” with respect to another element of the semiconductor device, there are no intervene elements. Similar reference numbers refer to similar elements throughout this disclosure.

[0018] Spatially relative terms such as “over,” “above,” “on,” “top,” “below,” “under,” “bottom,” “lower,” “left,” “right,” “lower-left,” “lower-right,” “upper-left,” “upper-right,” “center,” “middle,” and similar may be used herein for convenience of description to explain the relationship between one element and another element(s) as described in the drawings. It will be understood that spatially relative terms are intended to include other directions of the semiconductor device in use or operation in addition to the directions depicted in the drawings. For example, if the semiconductor device is flipped in the drawings, the element described as “below” or “under” of another element will face “above” of the other element. Thus, the term “below” may include all directions of up and down. The semiconductor device may be positioned in other directions (rotated 90 degrees or in other directions), and the spatially relative descriptors used herein are interpreted accordingly. Another For example, elements referred to as “left” elements and “right” elements may be “right” elements and “left” elements when the device or structure containing these elements is positioned in a different direction.

[0019] Terms “first,” “second,” “third,” “fourth,” “fifth,” “sixth,” etc. may be used in this specification to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used to distinguish one element from another. Accordingly, the first element described in the descriptions of the embodiments may be referred to as the second element in the descriptions of other elements or one or more claims, and conversely, without departing from the teachings of this disclosure.

[0020] As used herein, expressions such as “at least one” modify the entire list of elements when preceding a list of elements, and do not modify the individual elements of the list. For example, the expression “at least one of a, b, and c” should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all a, b, and c.

[0021] In this specification, terms including “substantially” or “approximately” may be used. In one or more examples, if parameter X is specified as being substantially identical to parameter Y, the term “substantially” may be understood as X being within 10% of Y. In one or more examples, if parameter is specified as being approximately X, the term “approximately” may be understood as being within 10% of X. Additionally, if the term “identical” is used to compare parameters of two or more elements, the term may include parameters that are “substantially identical.”

[0022] If the term “contact” is used to describe two metal elements, for example, a metal line and a via structure, it will be understood that a barrier metal layer, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN), may be formed between the two metal elements. Additionally, if the metal contact structure is described as being formed on or in contact with the surface of a source / drain region, it will be understood that a silicide layer, such as cobalt silicide (CoSi2), nickel silicide (NiSi2), titanium silicide (TiSi2), or tungsten silicide (WSi2), may be formed between the metal contact structure and the surface of the source / drain region, but is not limited thereto.

[0023] It will also be understood that even if a specific step or action for manufacturing a device or structure is described after another step or action, such step or action may be performed before the other step or action unless the other step or action is described as being performed before the said step or action.

[0024] Many embodiments are described herein with reference to cross-sectional drawings, which are schematic descriptions of the embodiments (and intermediate structures). Accordingly, variations from the shapes of the descriptions are expected, for example, as a result of manufacturing techniques and / or tolerances. Accordingly, the embodiments should not be interpreted as being limited to the specific shapes of the regions described herein, but include, for example, variations of shapes arising from the manufacturing process. The various regions described in the drawings are by nature schematic, and the shapes of the regions are not intended to describe the actual shapes of the regions of the device and are not intended to limit the scope of the disclosure. Additionally, in the drawings, the sizes and relative sizes of the layers and regions may be exaggerated for clarity.

[0025] For the sake of brevity, traditional elements, structures, or layers of semiconductor devices including nanosheet transistors, and the materials forming them, may or may not be described in detail herein. For example, specific isolation layers or structures of a semiconductor device and the materials forming them may be omitted from this specification unless such layers and structures relate to novel features of the embodiments. Additionally, descriptions of materials forming well-known structural elements of a semiconductor device may be omitted from this specification unless such materials relate to novel features of the embodiments. In this specification, the terms “isolation” and “insulation” relate to electrical insulation or separation between structures, layers, components, or regions in the corresponding device or structure.

[0026] FIGS. 1a through 1d illustrate a stacked semiconductor device having different channel widths and different source / drain region widths according to one or more embodiments. FIG. 1a is a top view of the stacked semiconductor device, and FIGS. 1b through 1d are cross-sectional views of the stacked semiconductor device of FIG. 1a taken along the lines I-I', II-II', and III-III' shown in FIG. 1a, respectively.

[0027] It is understood that FIG. 1a illustrates only selected elements formed on the front surface of a stacked semiconductor device, such as active patterns including source / drain regions, source / drain contact structures, and gate structures, and therefore, some structural elements, such as metal lines formed vertically above or below the active patterns, are not illustrated for the sake of simplicity. Additionally, to aid in a better understanding of the stacked semiconductor device, FIG. 1b illustrates channel structures of the stacked semiconductor device as seen in a cross-sectional view taken along line II-II' using a dashed line, and FIG. 1c illustrates source / drain regions of the stacked semiconductor device as seen in a cross-sectional view taken along line III-III' using a dashed line.

[0028] Referring to FIGS. 1a through 1d, the stacked semiconductor device (10) may include a first active pattern (110) and a second active pattern (120) extended in the D1 direction. The second active pattern (120) may be stacked on the first active pattern (110) formed on the back isolation layer (101) in the D3 direction intersecting the D1 direction and the D2 direction, and may partially overlap the first active pattern (110) in the D3 direction. The first active pattern (110) may partially overlap the second active pattern (120) and may have a greater width than the second active pattern (120) in the D2 direction. The stacked semiconductor device (10) may also be formed with a plurality of gate structures (150) arranged in the D1 direction and extending in the D2 direction across the active patterns (110 and 120).

[0029] The D1 direction refers to the channel-length direction through which current flows between two source / drain regions connected to each other via a channel structure, the D2 direction is the channel-height direction or cell-height direction, and the D3 direction is the channel-thickness direction. The D1 direction and the D2 direction may each be referred to as horizontal directions, and the D3 direction may be referred to as vertical directions.

[0030] The rear isolation layer (101) can be formed by replacing a silicon (Si)-based substrate and may include at least one rear contact plug (104) and a plurality of rear metal lines (109). The rear isolation layer (101) may be formed of a low-k material such as silicon oxide (e.g., SiO2), but is not limited thereto.

[0031] The stacked semiconductor device (10) may be formed with a first field-effect transistor (FET), which is an n-type field-effect transistor (NFET) in the first level or lower stack, and a second FET, which is a p-type field-effect transistor (PFET) in the second level or upper stack above the first level in the D3 direction. The first FET and the second FET may be formed based on a first active pattern (110) and a second active pattern (120), respectively, together with a corresponding gate structure (150). However, the present disclosure is not limited thereto. According to one or more other embodiments, each of the first FET and the second FET may be either p-type or n-type for forming the stacked semiconductor device (10). Hereinafter, it is assumed that the first FET is an NFET and the second FET is a PFET.

[0032] A first active pattern (110) for a first FET can form a first channel structure (112) and first source / drain regions (113) at a first level. The first channel structure (112) may include a plurality of first nanosheet layers epitaxially grown from a silicon-based substrate underneath, and thus, the first nanosheet layers may also be formed of silicon (Si). In the fabrication of a stacked semiconductor device (10), the silicon-based substrate may be wholly or partially replaced by a back isolation layer (101). However, the stacked semiconductor device (10) may include a bottom diffusion isolation (BDI) layer (105) between the first source / drain regions (113) and the silicon-based structures (112), and the BDI layer (105) is formed to suppress current leakage from the first source / drain regions (113) or the first channel structure (112) to the silicon-based substrate or the back isolation structure (101). The BDI layer (105) may be formed of an insulating material or a dielectric material such as SiBCN, SiCN, SiOC, SiOCN, Si3N4, etc.

[0033] The first n-type source / drain regions (113) can be epitaxially grown from the first nanosheet layers of the first channel structure (112) and can be formed of silicon doped with n-type impurities (e.g., phosphorus (P), arsenic (As), or antimony (Sb). The first channel structure (112) can be surrounded by a gate structure (150) that controls the current flow between the first source / drain regions (113) through the first channel structure (112). The gate structure (150) may include a gate dielectric layer surrounding the first nanosheet layers, a first one-function metal layer formed on the gate dielectric layer, and a gate electrode formed on the first one-function metal layer. Accordingly, the first channel structure (112), comprising first nanosheet layers, first source / drain regions (113), and a gate structure (150), can form a first FET as an NFET implemented by a nanosheet transistor at the first level. The gate electrode of the gate structure (150) may be formed of a metal such as tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), or an alloy thereof, but is not limited thereto.

[0034] A second active pattern (120) for a second FET may form a second channel structure (122) and second source / drain regions (123) at a second level. The second channel structure (122) may include a plurality of second nanosheet layers also epitaxially grown from a silicon-based substrate, and thus, the second nanosheet layers may also be formed of silicon. The second source / drain regions (123) may be epitaxially grown from the second nanosheet layers of the second channel structure (122) and may be formed of silicon germanium (SiGe) doped with p-type impurities (e.g., boron (B), gallium (Ga), or indium (In). The second channel structure (122) may be surrounded by a gate structure (150) that controls the current flow between the second source / drain regions (123) through the second channel structure (122). A gate dielectric layer surrounding a first channel structure (122) may be extended to also surround a second channel structure (122), and a second one-function metal layer may be formed on the extended portion of the gate dielectric layer. Additionally, a gate electrode on the first one-function metal layer may be extended to surround the second one-function metal layer. Thus, a second channel structure (122) comprising second nanosheet layers, second source / drain regions (123), and a gate structure (150) may form a second FET as a PFET implemented by a nanosheet transistor at a second level.

[0035] In this specification, the first nanosheet layers and the second nanosheet layers may also be referred to as the first channel layers and the second channel layers, respectively. The first channel structure (112) comprising the first nanosheet layers and the second channel structure (122) comprising the second nanosheet layers may be isolated from each other through an intermediate isolation layer (115), and the intermediate isolation layer (115) may be formed of an insulating material or dielectric material such as SiBCN, SiCN, SiOC, SiOCN, Si3N4, etc., similar to the materials forming the BDI layer (105), but is not limited thereto.

[0036] As previously described, the second active pattern (120) has a smaller width than the first active pattern (110) in the D2 direction. Accordingly, the second nanosheet layers forming the second channel structure (122) of the second FET may have a smaller width than the first nanosheet layers forming the first channel structure (112) of the first FET in the D2 direction, and the second channel structure (122) may only partially overlap with the first channel structure (112) in the D3 direction.

[0037] For example, the left sides of the second nanosheet layers may be aligned with or coplanar with the left sides of the first nanosheet layers in the D3 direction, but the right sides of the second nanosheet layers may not be aligned with or coplanar with the right sides of the first nanosheet layers in the D3 direction. Accordingly, the second source / drain regions (123) epitaxially grown from the second nanosheet layers may be formed to have a smaller width than the first source / drain regions (113) epitaxially grown from the first nanosheet layers in the D2 direction. Accordingly, the right side of the first source / drain region (113) may not be overlapped by the second source / drain region (123), but the left side of the first source / drain region (113) may be overlapped by the second source / drain region (123). This difference in width between the source / drain regions can provide free space on the upper surface of the first source / drain region (113) that is not vertically overlapped by the second source / drain region (123), and thus other circuit elements such as the front contact plug (114) can be formed vertically through this space and come into contact with at least a portion of the upper surface of the first source / drain region (113).

[0038] A front isolation layer (116) may be formed on the front surface of a semiconductor device (100) to isolate the stacked semiconductor device (10) from other semiconductor devices. The front isolation layer (116), like the back isolation layer (101), may be formed from a low-k dielectric material such as silicon oxide (e.g., SiO2), but is not limited thereto.

[0039] As illustrated in FIG. 1b, a BSPDN structure comprising at least one rear contact plug (104) and rear metal lines (109) may be formed on the rear surface of a semiconductor device (100). The rear contact plug (104) may be formed on the lower surface of one of the first source / drain regions (113) of the first FET and may be connected to a rear metal line (109) embedded in the rear isolation layer (101). The rear contact plug (104) may connect the first source / drain region (113), which is n-type, to a negative voltage source (VSS or ground) or other circuit element through the rear metal line (109). The rear contact plug (104) may take the form of a pillar as a via structure that vertically connects two metal lines extending in the D1 or D2 direction from different vertical levels in the D3 direction, for example. In contrast, the rear metal line (109) may extend in the D1 direction beyond the length of the first source / drain region (113). Additionally, one of the second source / drain regions (123) of the second FET may be connected to the rear metal line (109) via the front contact plug (106) and two via structures (107 and 108). This rear metal line (109) may connect the second source / drain region (123) to a positive voltage source (VDD) or other circuit element.

[0040] As illustrated in FIG. 1d, the other first source / drain region (113) of the first FET and the other second source / drain region (123) of the second FET may be connected to respective voltage sources or other circuit elements through other front contact plugs (114, 117) and respective front metal lines (119). As illustrated in FIG. 1c, the gate contact plug (118) may be connected to another front metal line (119) formed on the gate structure (150) to receive a gate input signal for the stacked semiconductor device (10).

[0041] The rear contact plug (104), via structures (107, 108), front contact plugs (106, 114, 117), and metal lines (109, 119) may be formed of the same metal or other metals, and the other metals may be, for example, tungsten (W), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), etc., or alloys thereof.

[0042] The aforementioned structural features of the channel structures and source / drain regions can be provided to address the increasing demands for high device density and enhanced device performance in stacked semiconductor devices. Since the front contact plug (114) is formed on the upper surface of the first source / drain region (113) through non-overlapping free space, the stacked semiconductor device (10) can achieve an area gain and have reduced contact resistance compared to a stacked semiconductor device in which the front contact plug is formed on the side or lower surface of the lower source / drain region when the lower source / drain region (corresponding to the first source / drain region (113)) and the upper source / drain region (corresponding to the second source / drain region (123)) have the same width.

[0043] In a stacked semiconductor device (10), a second channel structure (122) forming a second FET may have a number of nanosheet layers greater than the number of first channel structures forming a first FET so that the two FETs may have the same or substantially the same effective channel width (Weff). For example, the second channel structure (122) may have three nanosheet layers, but the first channel structure (112) may have two nanosheet layers.

[0044] Different channel widths and nanosheet layers, that is, different numbers of channel layers, can facilitate the optimization of stacked semiconductor devices in terms of device performance such as current rate, workload distribution, power efficiency, contact resistance, capacitance, thermal control, structural stability, as well as area gain for high-density semiconductor devices.

[0045] Meanwhile, the stacked semiconductor device (10) described above may be formed differently to further improve device performance and to achieve a low-power semiconductor device as described below.

[0046] FIGS. 2a through 2d illustrate a stacked semiconductor device comprising a gate-etched structure according to one or more embodiments. FIG. 2a is a top view of the stacked semiconductor device, and FIGS. 2b through 2d are cross-sectional views of the stacked semiconductor device of FIG. 2a taken along the lines I-I', II-II', and III-III' shown in FIG. 2a, respectively.

[0047] Referring to FIGS. 2a to 2d, which correspond to FIGS. 1a to 1d respectively, the stacked semiconductor device (20) may be formed with the same structural elements that form the stacked semiconductor device (10), and thus redundant descriptions thereof may be omitted from the specification. For example, the first active pattern (210) including a first channel structure (212) and first source / drain regions (213), the second active pattern (220) including a second channel structure (222) and second source / drain regions (223), and the gate structures (250) of the stacked semiconductor device (20) may be identical to the corresponding structural elements of the stacked semiconductor device of FIGS. 1a to 1d. Additionally, the stacked semiconductor device (20) may include a rear isolation layer (201), a BDI layer (205), an intermediate isolation layer (215), a front isolation layer (216), rear metal lines (209), front metal lines (219), a rear contact plug (204), via structures (207, 208), front contact plugs (206, 214, 217), and a gate contact plug (218), which may be identical to the corresponding structural elements of the stacked semiconductor device (10).

[0048] However, unlike the stacked semiconductor device (10), the stacked semiconductor device (20) may include, but is not limited to, a gate-etched structure (280) that can be formed from an insulating material or dielectric material such as silicon nitride (e.g., Si3N4). The gate-etched structure (280) may be formed in a space provided by etching the right portion of the first channel structure (212) and the right portion of the gate structure (250) surrounded by the right portion of the gate structure (250) in the D3 direction, in an area where the first channel structure (212) is not overlapped by the second channel structure (222). Thus, as shown in FIG. 2b, the lower portion of the gate-etched structure (280) may come into contact with the first channel structure (212). For example, the lower portion of the gate-etching structure (280) may be connected to the first channel structure (212) in the D2 direction by contacting the first nanosheet layers forming the first channel structure (212).

[0049] The lower portion of the gate-etch structure (280) may occupy the space provided by etching portions of internal spacers that isolate the gate structure (250) from the first source / drain regions (213) in a non-overlapping region. That is, the length of the gate-etch structure (280) may be equal to the length of the gate structure (250) in the D1 direction, and the lower portion of the gate-etch structure (280) may be connected to the first source / drain regions (213) by contacting them in the D1 direction. However, the gate-etch structure (280) may be formed so as not to extend beyond the length of the first channel structure (212) in the D1 direction along the sides of the first source / drain regions (213) extending in the D1 direction.

[0050] The gate-etch structure (280) may be formed to occupy the space provided by etching the right portion of the first channel structure (212), and thus, the length of the gate-etch structure (280) may be equal to the length of the first channel structure (212) in the D1 direction, and the two sides of the gate-etch structure (280) opposite in the first direction (e.g., D1 direction) may each be in the same plane or aligned with the first channel structures (212), that is, the two sides of the first nanosheet layers opposite in the first direction and the two sides of the gate structure (250) opposite in the first direction.

[0051] Additionally, the gate-etch structure (280) may be formed such that the right side of the first channel structure (212), for example, the right side of each of the first nanosheet layers forming the first channel structure (212), contacts the lower portion of the gate-etch structure (280). That is, the channel width of the first channel structure (212) may be reduced compared to the channel width of the first channel structure (112) of the stacked semiconductor device (10). Accordingly, the effective channel width (Weff) of the first FET of the stacked semiconductor device (20) may be reduced by the gate-etch structure (280). Additionally, the size of the gate structure (250) may be reduced by the gate-etch structure (280). Therefore, the power consumption of the stacked semiconductor device (20) may be reduced, and thus a low-power semiconductor device can be achieved. For example, the width of the first channel structure (212) is reduced to form a low-power NFET, but the width of the second channel structure (222) is maintained for a high-power PFET, so that the stacked semiconductor device (20) can be used to implement a NOR gate. However, the width of each of the first nanosheet layers may still be greater than the width of each of the second nanosheet layers in the D2 direction.

[0052] As the gate-etched structure (280) is formed in the manner described above, each of the first nanosheet layers of the first channel structure (212) may be surrounded by the gate structure (250) only on the top, left, and bottom surfaces, but each of the second nanosheet layers of the second channel structure (222) may be surrounded by the gate structure (250) on all four surfaces, namely the top, left, right, and bottom surfaces.

[0053] The gate-etch structure (280) may be formed in a non-overlapping region such that at least a portion of the gate structure (250) is formed in the D2 direction between the upper portion of the gate-etch structure (280) and the second channel structure (222) comprising the second nanosheet layers. At least a portion of this gate structure (250) may include a portion of the gate electrode of the gate structure (250) and / or a portion of the second one-function metal layer of the gate structure (250). However, at least another portion of the gate structure (250) on the right side of the second channel structure (222) may be removed, and thus, the capacitance created between the gate structure (250) and the adjacent source / drain regions (213 and 223) may be reduced, which may contribute to an improvement in the performance of the stacked semiconductor device (20).

[0054] The gate-etch structure (280) can be formed in the space provided by etching the right portion of the gate structure (250) from top to bottom, and thus, the upper and lower surfaces of the gate-etch structure (280) can be horizontally aligned with or in the same plane as the upper and lower surfaces of the gate structure (250).

[0055] The formation of the gate-etched structure (280) described above does not limit the present disclosure.

[0056] FIGS. 3a through 3d illustrate a stacked semiconductor device comprising vertically overlapping gate-etched structures according to one or more embodiments. FIG. 3a is a top view of the stacked semiconductor device, and FIGS. 3b through 3d are cross-sectional views of the stacked semiconductor device of FIG. 3a taken along the lines I-I', II-II', and III-III' shown in FIG. 3a, respectively.

[0057] Referring to FIGS. 3a to 3d, which correspond to FIGS. 2a to 2d respectively, the stacked semiconductor device (30) may be formed with the same or similar structural elements forming the stacked semiconductor device (20), and thus redundant descriptions thereof may be omitted from the specification. For example, a first active pattern (310) including a first channel structure (312) and first source / drain regions (313) of the stacked semiconductor device (30) and a second active pattern (320) including a second channel structure (322) and second source / drain regions (323) may be identical to the corresponding structural elements of the stacked semiconductor device (20) of FIGS. 2a to 2d. Additionally, the stacked semiconductor device (30) may include a rear isolation layer (301), a BDI layer (305), an intermediate isolation layer (315), a front isolation layer (316), rear metal lines (309), front metal lines (319), a rear contact plug (304), via structures (307, 308), front contact plugs (306, 314, 317), and a gate contact plug (318), which may be identical to the corresponding structural elements of the stacked semiconductor device (20).

[0058] However, the stacked semiconductor device (20) includes a gate structure (250) formed with a single piece gate electrode that surrounds both a first one-function metal layer on a first channel structure (212) and a second one-function metal layer on a second channel structure (222), but the stacked semiconductor device (30) may include a first gate structure (350A) and a second gate structure (350B) formed in other steps, for example, in a back process and a front process, respectively. A first gate structure (350A) may include a first gate dielectric layer surrounding first nanosheet layers, a first one-functional metal layer on the first gate dielectric layer, and a first gate electrode on the first one-functional metal layer, and a second gate structure (350B) may include a second gate dielectric layer surrounding second nanosheet layers, a second one-functional metal layer on the second gate dielectric layer, and a second gate electrode on the second one-functional metal layer.

[0059] The first gate electrode and the second gate electrode may be formed of the same metal or metal alloy and connected to each other to form two gate structures (350A and 350B) as a common gate structure (350). Still, however, if the two gate structures (350A and 350B) are formed at different stages and times, a connection surface, interface, or junction may be formed between the two gate electrodes of the two gate structures (350A and 350B).

[0060] Additionally, the stacked semiconductor device (20) includes a gate-etch structure (280) formed in a space provided by etching the right portion of the gate structure (250) from top to bottom, but the stacked semiconductor device (30) may include a first gate-etch structure (380) and a second gate-etch structure (390) formed in spaces provided by etching the right portion of the first gate structure (350A) at the first level and the right portion of the second gate structure (350B) at the second level, respectively.

[0061] The gate-etch structure (280) of the stacked semiconductor device (20) is a single-piece isolation structure formed by a single deposition step, but even if the second gate-etch structure (390) can overlap with the first gate-etch structure (380) in the D3 direction, the gate-etch structures (380 and 390) may be two different separate isolation structures formed by etching two gate structures (350A and 350B) in two different steps. The two gate-etch structures (380 and 390) may be formed from the same insulating material or dielectric material forming the gate-etch structure (280), or may be formed from different insulating materials or dielectric materials.

[0062] The first gate-etch structure (380) is separated from the second gate-etch structure (390), but the first gate-etch structure (380) and the second gate-etch structure (390) may each have structural shapes similar to the lower and upper portions of the gate-etch structure (280) of the stacked semiconductor device (20).

[0063] For example, the lower surface of the first gate-etch structure (380) may be horizontally coplanar or aligned with the lower surface of the first gate structure (350A), and the upper surface of the second gate-etch structure (390) may be horizontally coplanar or aligned with the upper surface of the second gate structure (350B). Additionally, the upper surface of the first gate-etch structure (380) may be formed at a level above the upper surface of the first channel structure (312), for example, above the upper surface of the topmost first nanosheet layer of the first channel structure (312), and the lower surface of the second gate-etch structure (390) may be formed at a level below the lower surface of the second channel structure (322), for example, below the lower surface of the bottommost second nanosheet layer of the second channel structure (322).

[0064] The first gate-etch structure (380) can come into contact with the first channel structure (312). For example, the first gate-etch structure (380) can be connected to the first channel structure (312) by coming into contact with the first nanosheet layers forming the first channel structure (312) in the D2 direction.

[0065] The first gate-etch structure (380) may occupy the space provided by etching portions of internal spacers that isolate the gate structure (350) from the first source / drain regions (313) in a non-overlapping region where the first channel structure (312) is not overlapped by the second channel structures (322) in the D3 direction. That is, the length of the first gate-etch structure (380) may be equal to the length of the first gate structure (350A) in the D1 direction, and the first gate-etch structure (380) may be connected to the first source / drain regions (313) by contacting the first source / drain regions (313) in the D1 direction. Additionally, the length of the second gate-etch structure (390) may be equal to the length of the second gate structure (350B) and may be equal to the length of the first gate structure (350A) in the D1 direction. However, the first gate-etch structure (380) may be formed so as not to extend beyond the length of the first channel structure (312) in the D1 direction along the sides of the first source / drain regions (313) extending in the D1 direction.

[0066] The first gate-etch structure (380) may be formed to occupy the space provided by etching the right portion of the first channel structure (312), and thus, the length of the first gate-etch structure (380) may be the same as the length of the first channel structure (312) in the D1 direction. That is, in the stacked semiconductor device (30), the gate structures (350A, 350B), the gate-etch structures (380, 390), and the channel structures (312, 322) may have the same length in the D1 direction.

[0067] Additionally, two sides of the first gate-etch structure (380) opposite in the first direction (e.g., D1 direction) may be coplanar or aligned with each of the two sides of the first channel structures (312), i.e., each of the first nanosheet layers opposite in the first direction, two sides of the first gate structure (350A) opposite in the first direction, two sides of the second gate-etch structure (390) opposite in the first direction, two sides of the second gate structure (350B) opposite in the first direction, and two sides of the second channel structures (322), i.e., each of the second nanosheet layers opposite in the first direction.

[0068] Additionally, the first gate-etch structure (380) may be formed such that the right side of the first channel structure (312), for example, the right side of each of the first nanosheet layers forming the first channel structure (312), contacts the first gate-etch structure (380). That is, the channel width of the first channel structure (312) may be reduced compared to the channel width of the first channel structure (112) of the stacked semiconductor device (10). Accordingly, the effective channel width (Weff) of the first FET of the stacked semiconductor device (30) may be reduced by the first gate-etch structure (380). Additionally, the size of the gate structure (350) may be reduced by the first gate-etch structure (380). Therefore, the power consumption of the stacked semiconductor device (30) may be reduced, and thus a low-power semiconductor device can be achieved. However, the width of each of the first nanosheet layers may still be greater than the width of each of the second nanosheet layers in the D2 direction.

[0069] As the gate-etched structures (380 and 390) are formed in the manner described above, each of the first nanosheet layers of the first channel structure (312) may be surrounded by the first gate structure (350A) only on the top, left, and bottom surfaces, but each of the second nanosheet layers of the second channel structure (322) may be surrounded by the second gate structure (350B) on all four surfaces, namely the top, left, right, and bottom surfaces.

[0070] The second gate-etch structure (390) may be formed in a non-overlapping region such that at least a portion of the second gate structure (350B) can be formed between the second gate-etch structure (390) and the second channel structure (322) which includes second nanosheet layers in the D2 direction. At least a portion of this second gate structure (350B) may include a portion of the second gate electrode and / or a portion of the second one-function metal layer. However, since at least another portion of the second gate structure (350B) is removed to the right of the second channel structure (322), the capacitance generated between the second gate structure (350B) and the adjacent source / drain regions (313 and 323) is reduced, which can contribute to an improvement in device performance.

[0071] Although the first gate-etch structure (380) and the second gate-etch structure (390) are formed to be separated from each other in the stacked semiconductor device (30) as these two isolation structures are formed in two different steps, e.g., a back process and a front process, the two gate-etch structures (380 and 390) may be formed to be connected to each other in the D3 direction to have the same shape as the gate-etch structure (280) of the stacked semiconductor device (20).

[0072] The formation of the gate-etched structures (380 and 390) described above does not limit the present disclosure.

[0073] FIGS. 4a through 4d illustrate a stacked semiconductor device comprising gate-etched structures that are not vertically overlapped, according to one or more embodiments. FIG. 4a is a top view of the stacked semiconductor device, and FIGS. 4b through 4d are cross-sectional views of the stacked semiconductor device of FIG. 4a taken along the lines I-I', II-II', and III-III' shown in FIG. 4a, respectively.

[0074] Referring to FIGS. 4a to 4d, which correspond to FIGS. 3a to 3d respectively, the stacked semiconductor device (40) may be formed with the same or similar structural elements forming the stacked semiconductor device (30), and thus redundant descriptions thereof may be omitted from the specification. For example, the first active pattern (410) including the first channel structure (412) and first source / drain regions (413) of the stacked semiconductor device (40), the second active pattern (420) including the second channel structure (422) and second source / drain regions (423), and the gate structure (450) including the first gate structure (450A) and the second gate structure (450B) may be identical to the corresponding structural elements of the stacked semiconductor device (30) of FIGS. 3a to 3d. Additionally, the stacked semiconductor device (40) may include a rear isolation layer (401), a BDI layer (405), an intermediate isolation layer (415), a front isolation layer (416), rear metal lines (409), front metal lines (419), a rear contact plug (404), via structures (407, 408), front contact plugs (406, 414, 417), and a gate contact plug (418), which may be identical to the corresponding structural elements of the stacked semiconductor device (30).

[0075] However, the stacked semiconductor device (30) may include a first gate-etch structure (380) on the right side of the first gate structure (350A) as a second gate-etch structure (390), but even though two isolation structures are formed at the first level and the second level of the stacked semiconductor device (40), the stacked semiconductor device (40) may include a first gate-etch structure (480) on the left side of the first gate structure (450A) and a second gate-etch structure (490) on the right side of the second gate structure (450B). The first gate-etch structure (480) may be formed in the space provided by etching the left side of the first gate structure (450A) at the first level, but the second gate-etch structure (490) may be formed in the space provided by etching the right side of the second gate structure (450B) at the second level. Still, the two gate-etched structures (480 and 490) can each be formed from the same insulating or dielectric materials that form the gate-etched structures (380 and 390).

[0076] The second gate-etch structure (490) may be formed at the same location where the first gate-etch structure (390) is formed and in the same manner, and thus, a description thereof may be omitted from this specification. However, the first gate-etch structure (480) may be formed at a location opposite to the first gate-etch structure (380) of the stacked semiconductor device (30). That is, the first gate-etch structure (480) may be in contact with the left side of the first channel structure (412), for example, with each of the left sides of the first nanosheet layers of the first channel structure (412). Additionally, as illustrated in FIG. 4c, the left side of the second gate structure (450B) may be in the same plane as or aligned perpendicularly with the left side of the first gate-etch structure (480), and the right side of the first gate-etch structure (480) may be superimposed by the second channel structure (422) in the D3 direction.

[0077] Still, the lower surface of the first gate-etch structure (480) may be horizontally coplanar or aligned with the lower surface of the first gate structure (450A), and the upper surface of the first gate-etch structure (480) may be formed at a level above the upper surface of the first channel structure (412), for example, the upper surface of the top first nanosheet layer of the first channel structure (412).

[0078] The first gate-etch structure (480) may occupy the space provided by etching portions of internal spacers that isolate the gate structure (450) from the first source / drain regions (413) in the overlapping region where the first channel structure (412) is overlapped by the second channel structures (422) in the D3 direction. That is, the length of the first gate-etch structure (480) may be the same as the length of the first gate structure (450A) in the D1 direction, and the first gate-etch structure (480) may be connected to the first source / drain regions (413) by contacting the first source / drain regions (413) in the D1 direction. Additionally, the length of the second gate-etch structure (490) may be the same as the length of the second gate structure (450B) and may be the same as the length of the first gate structure (450A) in the D1 direction. However, the first gate-etch structure (480) may be formed so as not to extend beyond the length of the first channel structure (412) in the D1 direction along the sides of the first source / drain regions (413) extending in the D1 direction.

[0079] The first gate-etch structure (480) may be formed to occupy the space provided by etching the left portion of the first channel structure (412), and thus, the length of the first gate-etch structure (480) may be the same as the length of the first channel structure (412) in the D1 direction. That is, in the stacked semiconductor device (40), the gate structures (450A, 450B), the gate-etch structures (480, 490), and the channel structures (412, 422) may have the same length in the D1 direction.

[0080] Additionally, two sides of the first gate-etch structure (480) opposite in the first direction (e.g., D1 direction) may be coplanar or aligned with each of the two sides of the first channel structures (412), i.e., each of the first nanosheet layers opposite in the first direction, two sides of the first gate structure (450A) opposite in the first direction, two sides of the second gate-etch structures (490) opposite in the first direction, two sides of the second gate structure (450B) opposite in the first direction, and two sides of the second channel structures (422), i.e., each of the second nanosheet layers opposite in the first direction.

[0081] Additionally, the first gate-etch structure (480) may be formed such that the left side of the first channel structure (412), for example, the left side of each of the first nanosheet layers forming the first channel structure (412), contacts the first gate-etch structure (480). That is, the channel width of the first channel structure (412) may be reduced compared to the channel width of the first channel structure (112) of the stacked semiconductor device (10). Accordingly, the effective channel width (Weff) of the first FET of the stacked semiconductor device (40) may be reduced by the first gate-etch structure (480). Additionally, the size of the gate structure (450) formed by the first gate structure (450A) and the second gate structure (450B) may be reduced by the first gate-etch structure (480) and the second gate-etch structure (490), respectively. Therefore, the power consumption of the stacked semiconductor device (40) can be reduced, and thus a low-power semiconductor device can be achieved. However, the width of each of the first nanosheet layers may still be greater than the width of each of the second nanosheet layers in the D2 direction.

[0082] As the gate-etched structures (480 and 490) are formed in the manner described above, each of the first nanosheet layers of the first channel structure (412) may be surrounded by the first gate structure (450A) only on the top, right, and bottom surfaces, but each of the second nanosheet layers of the second channel structure (422) may be surrounded by the second gate structure (450B) on all four surfaces, namely the top, left, right, and bottom surfaces.

[0083] Meanwhile, as illustrated in FIG. 4a and FIG. 4c, the formation of a first gate-etch structure (480) on the left side of a first channel structure (412) in a stacked semiconductor device (40) can facilitate a reduction in channel resistance or diffusion resistance compared to a stacked semiconductor device (30) on the right side of the first channel structures (312) and a stacked semiconductor device (20) on the right side of the first channel structures (212) where the lower part of the gate-etch structure (280) is located. This is because, as indicated by the respective arrows in FIG. 2a, FIG. 3a, and FIG. 4a, the current path between the first source / drain regions (413) and the front contact plug (414) formed on the other first source / drain region (413) in the stacked semiconductor device (40) may be shorter than the current path between the first source / drain regions (313) and the front contact plug (314) formed on the other first source / drain region (313) in the stacked semiconductor device (30) and the current path between the first source / drain regions (213) and the front contact plug (214) formed on the other first source / drain region (213) in the stacked semiconductor device (20).

[0084] For example, in a stacked semiconductor device (30), a first gate-etch structure (380) in contact with a first source / drain region (313) can force some of the carriers from the right portion (in the D2 direction) of the first source / drain region (313) to bypass the first gate-etch structure (380) and reach the front contact plug (314) as indicated by the arrow shown in FIG. 3a, because the first gate-etch structure (380) and the front contact plug (314) are formed on the right portion (in the D2 direction) of the first channel structure (312) and on the right portion (in the D2 direction) of the other first source / drain region (313) where the front contact plug (314) is formed (Fig. 3d), respectively. In contrast, in the stacked semiconductor device (40), some carriers from the right portion of the first source / drain region (413) can move directly toward the front contact plug (414) without being blocked by the first gate-etch structure (480) as indicated by the arrow shown in FIG. 4a. This is because the first gate-etch structure (480) is formed on the left side of the first channel structure (412), but the front contact plug (414) is formed on the right side of the other first source / drain region (413).

[0085] The following is a method for manufacturing a stacked semiconductor device comprising gate-etched structures according to one or more embodiments.

[0086] FIGS. 5a to 5l illustrate intermediate semiconductor devices obtained after each step of manufacturing a stacked semiconductor device including gate-etched structures according to one or more embodiments.

[0087] A stacked semiconductor device manufactured through the steps described below with reference to FIGS. 5a through 5l may be identical to the stacked semiconductor device (40) illustrated in FIGS. 4a through 4d. That is, redundant descriptions, including those regarding materials and structures, may be omitted, and the same reference numerals may be used in FIGS. 5a through 5l and the descriptions thereof. Here, FIGS. 5a through 5l are cross-sectional views corresponding to FIG. 4c, and thus, it is understood that descriptions forming the structural elements illustrated in FIGS. 4b and 4d may be omitted.

[0088] Referring to FIG. 5a, an intermediate semiconductor device (40') can be formed by epitaxially growing a plurality of semiconductor layers, also referred to as nanosheet layers, on a substrate (401').

[0089] Semiconductor layers may be epitaxially grown from a substrate (401') in the order of a first channel stack (lower channel stack) including a lower sacrificial layer (405'), first sacrificial layers (411) and first channel layers (412) stacked vertically in an alternating manner, an intermediate sacrificial layer (415'), and a second channel stack (upper channel stack) including second sacrificial layers (421) and second channel layers (422) stacked vertically in an alternating manner on the intermediate sacrificial layer (415'). The first channel layers (412) and second channel layers (422) described herein with reference to FIGS. 5a through 5l may be referred to as a first channel structure (412) including first nanosheet layers and a second channel structure (422) including second nanosheet layers, respectively, as described with reference to FIGS. 4a through 4d.

[0090] The substrate (401') and channel layers (412 and 422) are formed of silicon (Si), but the sacrificial layers (405', 411, 415' and 421) may each be formed of silicon germanium (SiGe) having their respective Ge concentrations. The lower sacrificial layer (405') and the intermediate sacrificial layer (415') may have a higher Ge concentration than the first and second sacrificial layers (411 and 421). For example, the intermediate sacrificial layer (415') may have a Ge concentration of 40-45%, and the first and second sacrificial layers (411 and 421) may have a Ge concentration of 25-30%.

[0091] Referring to FIG. 5b, the intermediate semiconductor device (40') can be patterned such that a second channel stack formed of second sacrifice layers (421), a second channel layer (422), and an intermediate sacrifice layer (415') in the D2 direction has a smaller width than a first channel stack formed of a lower sacrifice layer (405'), first sacrifice layers (411), and first channel layers (412).

[0092] In this step, the patterning of the intermediate semiconductor device (40') can be performed such that the first channel stack is partially overlapped by the second channel stack in the D3 direction. For example, the left sides of the first channel stack, the intermediate sacrifice layer (415'), and the second channel stack may be aligned perpendicularly to each other or coplanar, but the right side of the first channel stack is not vertically overlapped by the second channel stack, so that the patterning can be performed to form a non-overlapping region on the right side. Here, the first channel stack and the second channel stack of the intermediate semiconductor device (40') can each form the first active pattern (410) and the second active pattern (420) shown in FIG. 4a.

[0093] In this step, patterning of the intermediate semiconductor device (40') can be performed, for example, through dry etching, for example, reactive ion etching (RIE), but is not limited thereto.

[0094] Referring to FIG. 5c, a first dummy gate structure (450A') and a second dummy gate structure (450B') having a dummy separation layer (402) between them can be formed to surround the first channel stack and the second channel stack, respectively, and additionally, the lower sacrifice layer (405') and the intermediate sacrifice layer (415') can be removed and replaced by the BDI layer (405) and the intermediate isolation layer (415), respectively.

[0095] The first dummy gate structure (450A') may be formed to surround the first channel stack, for example, through a planarization, for example, chemical-mechanical polishing (CMP) operation, after chemical vapor deposition (CVD) of polysilicon (p-Si) or amorphous silicon (a-Si), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), or a combination thereof, but is not limited thereto.

[0096] Subsequently, a dummy isolation layer (402) comprising an isolation material such as SiBCN, SiCN, SiOC, SiOCN, SiN, Si3N4, etc., may be formed at the level of an intermediate sacrifice layer (415'), for example, via ALD or PEALD, to isolate the first dummy gate structure (450A') from the second dummy gate structure (450B') to be formed in the next step. Here, the dummy isolation layer (402) may be formed from an isolation material such as SiBCN, SiCN, SiOC, SiOCN, SiN, Si3N4, etc.

[0097] The second dummy gate structure (450B') can be formed in the same or similar manner as the formation of the first dummy gate structure (450A') using the same material as the material forming the first dummy gate structure (450A') to surround the second channel stack of the intermediate semiconductor device (40').

[0098] Additionally, the lower sacrificial layer (405') and the intermediate sacrificial layer (415') can be removed and replaced by the BDI layer (405) and the intermediate isolation layer (415), respectively. The removal of the lower sacrificial layer (405') and the intermediate sacrificial layer (415') can be performed by wet etching using an etchant, for example, an ammonia-peroxide mixture, and the etchant removes the lower sacrificial layer (405') and the intermediate sacrificial layer (415') of SiGe having a high Ge concentration while the channel layers (412 and 422) of silicon (Si) and the sacrificial layers (411 and 421) of SiGe having a low Ge concentration are not attacked or are attacked minimally by the etchant. Subsequently, an isolation material such as SiBCN, SiCN, SiOC, SiOCN, SiN, Si3N4, etc., can fill the spaces from which the lower sacrificial layer (405') and the intermediate sacrificial layer (415') have been removed, thereby forming a BDI layer (405) and an intermediate isolation layer (415). The formation of the BDI layer (405) and the intermediate isolation layer (415) can be performed, for example, via ALD or PEALD, but is not limited thereto. The BDI layer (405) and the intermediate isolation layer (415) can be formed from isolation materials that are the same as or different from the materials forming the dummy isolation layer (402).

[0099] The BDI layer (405) may be formed to suppress current leakage from the first channel structure (412) and the first source / drain regions (413) to be formed from the first channel structures (412). The intermediate isolation layer (415) may be formed to isolate the first channel structure (412) and the second channel structure (422), respectively, to be formed from the first channel stack and the second channel stack of the intermediate semiconductor device (40').

[0100] Referring to FIG. 5d, the intermediate semiconductor device (40') can be patterned to form spaces in which first source / drain regions (413) and second source / drain regions (423) on the first source / drain regions (413) are formed.

[0101] In this step, the second channel stack and the first channel stack, that is, the second active pattern (420) and the first active pattern (410) under the second channel stack and the first channel stack as illustrated in FIG. 4a, may be patterned by dry etching or wet etching between the gate structures (450) as illustrated in FIG. 4a, for example, to form spaces (S) (indicated by dashed lines in FIG. 5d) in which the first source / drain regions (413) and the second source / drain regions (423) will be formed in the next step.

[0102] After patterning the second channel stack and the first channel stack, the substrate (401') exposed beneath the spaces (S) formed by these patterning operations may be patterned to form a placeholder recess and a placeholder structure inside. The placeholder structure may be formed to secure a space for a rear contact plug (404) (Fig. 4b) connected to the lower surface of one of the first source / drain regions (413) to be formed in the next step. The patterning operations forming the spaces (S) and the placeholder recess may be performed, for example, through dry etching or wet etching. The placeholder structure may be epitaxially grown from the substrate (401') forming the inner surfaces of the placeholder recess. The placeholder structure may be formed of silicon germanium (SiGe).

[0103] Referring to FIG. 5e, the first source / drain regions (413) and the second source / drain regions (423) can be formed in the spaces (S) obtained by the patterning of the first channel stack and the second channel stack of the intermediate semiconductor device (40') in the previous step (Fig. 5d).

[0104] The first source / drain regions (413) can be epitaxially grown from the first channel layers (412) of the first channel stack while the first sacrifice layers (411) are covered by internal spacers formed on the sides in the D1 direction, and the second source / drain regions (423) can be epitaxially grown from the second channel layers (422) of the second channel stack while the second sacrifice layers (421) are covered by internal spacers formed on the sides in the D1 direction. When epitaxial growth of source / drain regions (413 and 423) is performed, n-type impurities such as phosphorus (P), arsenic (As), antimony (Sb), etc. can be doped into the epitaxial structure for the first source / drain regions (413), and p-type impurities such as boron (B), gallium (Ga), or indium (In), etc. can be doped into the epitaxial structure for the second source / drain regions (423).

[0105] Referring to FIG. 5f, the second dummy gate structure (450B') and the second sacrifice layers (421) can be removed and replaced by the second gate structure (450B), and thus the second channel layers (422) are surrounded by the second gate structure (450B).

[0106] The second dummy gate structure (450B') and the second sacrifice layers (421) may be removed, for example, by dry or wet etching, but are not limited thereto, and the second channel layers (422) may be released as the second channel structure (422). Additionally, the space provided by the removal of the second dummy gate structure (450B') and the second sacrifice layers (421) may be filled with a metal or metal alloy forming the second gate structure (450B), for example, by CVD, PVD, ALD, PEALD, etc., or a combination thereof, but is not limited thereto.

[0107] In this step, an etching solution such as HBr / Cl2 / O2 plasma for dry etching or tetramethylammonium hydroxide (TMAH) for wet etching may be used to remove a second dummy gate structure (450B') formed of a-Si or p-Si and a second sacrificial layer formed of SiGe from a dummy isolation layer (402) and an intermediate isolation layer (415) formed of SiBCN, SiCN, SiOC, SiOCN, SiN, etc.

[0108] Referring to FIG. 5g, the second gate-etched structure (490) can be formed in the space obtained by removing the right portion of the second gate structure (450) that includes a portion in the non-overlapping region.

[0109] To form a second gate-etched structure (490), the right portion of the second gate structure (450B) on the right side of the second channel structure (422) can be etched from the upper surface of the second gate structure (450B) to the upper surface of the dummy separation layer (402) through dry etching, for example, reactive ion etching (RIE). Subsequently, an insulating material or dielectric material, such as silicon nitride (e.g., Si3N4), can be formed in the space provided by the removal of the right portion of the second gate structure (450B) through planarization, for example, CMP, after, for example, PVD, CVD, PECVD, etc., so that the upper surface of the second gate-etched structure (490) can be horizontally coplanar or aligned with the upper surface of the second gate structure (450B). The second gate-etch structure (490) may be formed such that the lower surface of the second gate-etch structure (490) is at a level below the lower surface of the lowest second channel layer (422).

[0110] After the formation of the second gate-etch structure (490), at least a portion of the second gate structure, including the second one-function metal layer and / or the second gate electrode, may remain between the second channel structure and the second gate-etch structure (490) in the D2 direction.

[0111] Since the second gate-etched structure (490) is formed by removing the right portion of the second gate structure (450B), the capacitance generated between the second gate structure (450B) and the source / drain regions (413, 423) is reduced, thereby enhancing device performance.

[0112] Referring to FIG. 5h, the front isolation layer (416) can be formed to surround the first channel stack and the second channel structure (422) of the intermediate semiconductor device (40'), and the back-end process can be performed to form front contact plugs including gate contact plugs (418), via structures and front metal lines (419).

[0113] The formation of the front isolation layer (416) can be performed, for example, through PVD, CVD, PECVD, etc. of a low-k dielectric material such as silicon oxide (e.g., SiO2), followed by planarization, for example, CMP, but is not limited thereto.

[0114] The back-end process may include dry etching or wet etching of the front isolation layer (416) and may include forming front contact plugs including gate contact plugs (418), via structures and front metal lines (419) through, for example, PVD, CVD, PECVD, etc. of a metal or metal alloy.

[0115] Referring to FIG. 5i, the substrate (401') can be partially or wholly removed for a subsequent back process.

[0116] The substrate (401') can be thinned, for example, by a back thinning operation in which the substrate (401') is mechanically polished to expose a placeholder structure formed to secure space for a back contact plug (404) (Fig. 4b) as described with reference to Fig. 5d, and then the remaining portion of the substrate (401') surrounding the placeholder structure can be removed by dry etching or wet etching.

[0117] In this step, the substrate removal operation and subsequent back process can be performed by flipping the intermediate semiconductor device (40') obtained in the previous step upside down.

[0118] Referring to FIG. 5j, the first dummy gate structure (450A'), the first sacrifice layers (411), and the dummy separation layer (402) can be removed and replaced by the first gate structure (450A), and thus the first channel layers (412) are surrounded by the first gate structure (450A).

[0119] The first dummy gate structure (450A') and the first sacrifice layers (411) may be removed, for example, by dry or wet etching, but are not limited thereto, thereby releasing the first channel layers (412) into the first channel structure (412). Additionally, the dummy isolation layer (402) may be removed using etch selectivity for the intermediate isolation layer (415). Furthermore, the space provided by the removal of the first dummy gate structure (450A') and the first sacrifice layers (411) may be filled with a metal or metal alloy to form the first gate structure (450A), for example, through ALD, PEALD, CVD, PVD, etc., or a combination thereof, but is not limited thereto. That is, the first gate structure (450A) and the second gate structure (450B) may form the gate structure (450) of the intermediate semiconductor device (40').

[0120] The metal or metal alloy forming the first gate electrode of the first gate structure (450A) may be the same or different from the second gate electrode forming the second gate structure (450B). However, even if the two gate electrodes of the two gate structures (450A and 450B) are formed of the same metal or metal alloy, a connection surface, interface, or junction may be formed between the two gate electrodes because the two gate structures (450A and 450B) are formed at different stages and at different times.

[0121] Referring to FIG. 5k, the first gate-etch structure (480) can be formed in the space obtained by removing the left portion of the first gate structure (450A) and the left portion of the first channel structure (412).

[0122] To form the first gate-etched structure (480), the left portion of the first gate structure (450A) may be etched from the bottom surface of the first gate structure (450A) to the level of the bottom surface of the intermediate isolation layer (415) or the level above the top surface of the upper first channel layer (412) through dry etching, for example, reactive ion etching (RIE). Subsequently, an insulating material or dielectric material, such as silicon nitride (e.g., Si3N4), may be formed in the space removed by the removal of the left portion of the first gate structure (450A) through planarization, for example, CMP, after, for example, PVD, CVD, PECVD, etc., so that the bottom surface of the first gate-etched structure (480) may be in the same plane as or aligned horizontally with the bottom surface of the first gate structure (450A).

[0123] In this step, the left portion of the first gate structure (450A) may be removed so that the left portion of the first channel layers (412) may also be removed, and the first gate-etch structure (480) may be formed in the space provided by the removal of the left portion of the first gate structure (450A) so that the first gate-etch structure (480) contacts each left side of the first channel layers (412) in the D2 direction and is connected to the first channel layers (412). That is, the right portion of the first gate-etch structure (480) may be vertically overlapped by the intermediate isolation layer (415) and the second channel layers (422), and additionally, the first gate-etch structure (480) may contact the first source / drain regions (413) in the D1 direction and be connected to the first source / drain regions (413).

[0124] Since the first gate-etch structure (480) is formed in the manner described above, the effective channel width (Weff) of the first FET to be formed at the first level for the stacked semiconductor device can be reduced. Additionally, the size of the gate structure (450) can be reduced by the gate-etch structures (480 and 490). Therefore, the power consumption of the stacked semiconductor device to be manufactured from the intermediate semiconductor device (40') can be reduced, and thus a low-power semiconductor device can be achieved. Furthermore, similar to the second gate-etch structure (490), the first gate-etch structure (480) can improve device performance by reducing the channel resistance or diffusion resistance between the gate structure (450) and the source / drain regions (413).

[0125] It is understood that when the first gate-etch structure (480) is formed in the space obtained by removing the right portion of the first gate structure (450A) and the right portion of the first channel structure (412), the first gate-etch structure (480) of the intermediate semiconductor device (40') illustrated in FIG. 5k may take the form of the first gate-etch structure (380) of the stacked semiconductor device (30) as illustrated in FIG. 3c.

[0126] Referring to FIG. 5L, the rear isolation layer (401) can be formed in the space provided by the removal of the substrate (401'), and the rear contact plug and rear metal lines (409) can be formed on the rear isolation layer (401).

[0127] The back isolation layer (401) may be formed in the space of the removed substrate (401') by the deposition of a low-k material such as silicon oxide (e.g., SiO2) using, for example, CVD, PVD, PECVD, etc., or a combination thereof, but is not limited thereto.

[0128] Additionally, with reference to FIG. 5d and FIG. 5l, the placeholder structure described above may be removed, and the rear contact plug (404) ( FIG. 4b) may be formed in the space provided by the removal of the placeholder structure from the rear isolation layer (401), and additionally, rear metal lines (409) may be formed to connect the first source / drain regions (413) and / or the second source / drain regions (423) to the voltage sources of other circuit elements through the via structures and the rear contact plug (404).

[0129] In the embodiments described above, a method for manufacturing a stacked semiconductor device (40) illustrated in FIGS. 4a through 4d and an additional method for manufacturing a stacked semiconductor device (30) illustrated in FIGS. 3a through 3d are described with reference to FIGS. 5a through 5l. However, a stacked semiconductor device (20) illustrated in FIGS. 2a through 2d may be manufactured through a similar method, excluding some steps. For example, a method for manufacturing a stacked semiconductor device (20) may not require the formation of two different dummy gate structures (450A' and 450B') having a dummy separation layer (402) between the two different dummy gate structures (450A' and 450B') as described with reference to FIG. 5c. Instead, this method may include the formation of a single dummy gate structure surrounding the first channel stack and the second channel stack in a step corresponding to FIG. 5c, and the formation of a single gate structure (250) replacing the single dummy gate structure in a step corresponding to FIG. 5f. Additionally, the gate-etched structure (280) of the stacked semiconductor device (20) may be formed in a front process step corresponding to the step of FIG. 5g. That is, the method for manufacturing the stacked semiconductor device (20) may be simplified and have more process margin than the methods for the stacked semiconductor devices (30 and 40).

[0130] FIGS. 6a and 6b are flowcharts for manufacturing a stacked semiconductor device including gate-etched structures according to one or more embodiments.

[0131] The stacked semiconductor device to be formed through the flowcharts of FIGS. 6a and 6b may be identical or similar to the stacked semiconductor device (40) manufactured through the steps described above with reference to FIGS. 5a to 5l, and thus, redundant descriptions thereof may be omitted from the specification.

[0132] In step S10, an intermediate semiconductor device formed of a plurality of vertically stacked semiconductor layers is provided on a substrate and patterned to form a first channel stack and a second channel stack on the substrate, and the second channel structure may have a width smaller than that of the first channel stack in the D2 direction so that the right portion of the first channel stack is not vertically overlapped by the second channel stack (Figs. 5a and 5b).

[0133] Both the first channel stack and the second channel stack can be formed by a plurality of SiGe sacrificial layers and a plurality of Si channel layers alternately stacked on a substrate. A lower sacrificial layer can be formed between the substrate and the first channel structure, and an intermediate sacrificial layer can be formed between the first channel stack and the second channel stack. The lower sacrificial layer and the intermediate sacrificial layer can be formed of SiGe having a higher Ge concentration than the sacrificial layers included in the first channel stack and the second channel stack.

[0134] In step S20, the first dummy gate structure and the second dummy gate structure, having a dummy isolation layer between the first dummy gate structure and the second dummy gate structure, can be formed to surround the first channel stack and the second channel stack, respectively, and later the lower sacrifice layer and the intermediate sacrifice layer can be replaced with the BDI layer and the intermediate isolation layer, respectively (Fig. 5c).

[0135] The dummy separation layer can be used to enable the separation of the first gate structure and the second gate structure, which replace the first dummy gate structure and the second dummy gate structure respectively in a subsequent step, and thus facilitates the separation of the first gate-etch structure and the second gate-etch structure by removing parts of the first gate structure and the second gate structure respectively.

[0136] In step S30, first source / drain regions connected through first channel layers in the first channel stack and second source / drain regions connected through second channel layers in the second channel stack may be formed (Figs. 5d and 5e).

[0137] The first source / drain regions can be epitaxially grown from the first channel layers mainly in the D1 direction, and the second source / drain regions can be epitaxially grown from the second channel layers mainly in the D1 direction. That is, the second source / drain regions can have a smaller width than the corresponding first source / drain regions in the D2 direction, and the right portions of the first source / drain regions may not be vertically overlapped by the second source / drain regions.

[0138] In step S40, the second dummy gate structure and the second sacrifice layer in the second channel stack can be removed with respect to the dummy separation layer and the intermediate isolation layer to release the second channel layers into the second channel structure, and the space provided by the removal of the second dummy gate structure and the second sacrifice layer can be filled with a metal or metal alloy to form a second gate structure surrounding the second channel structure (Fig. 5f).

[0139] In step S50, the right portion of the second gate structure may be removed from the side of the second channel structure, which includes a non-overlapping region where the second channel structure does not overlap vertically with the first channel stack, and the space provided by the removal of the right portion of the second gate structure may be filled with an insulating material or a dielectric material to form a second gate-etched structure (Fig. 5g).

[0140] The second gate-etch structure and the upper surfaces of the second gate structure may be horizontally aligned with each other on the same plane, and the second gate-etch structure may be formed such that the lower surface of the second gate-etch structure is at a level below the lower surface of the lowest second channel layer or contacts the upper surface of the dummy separation layer. Additionally, the second gate-etch structure may be formed such that the width of the second gate structure is equal to the width of the second gate structure in the D1 direction, and a portion of the second gate structure is formed between the second gate-etch structure and the second channel structure in the D2 direction.

[0141] In step S60, the first dummy gate structure, the first sacrifice layers, and the dummy isolation layer may be removed with respect to the first gate structure and the intermediate isolation layer to release the first channel layers into the first channel structure, and the space provided by the removal of the first dummy gate structure, the first sacrifice layers, and the dummy isolation layer may be filled with a metal or metal alloy to form a first gate structure surrounding the first channel structure (Figs. 5h to 5j).

[0142] In step S70, the left portion of the first gate structure and the left portion of the first channel structure that is surrounded by the left portion of the first gate structure and vertically overlapped by the second channel structure can be removed, and the space provided by the removal of the left portion of the first gate structure and the left portion of the first channel structure can be filled with an insulating material or a dielectric material to form a first gate-etch structure (Fig. 5k).

[0143] The first gate-etch structure may be formed such that its upper surface contacts the lower surface of the intermediate isolation layer or is at a level above the upper surface of the topmost first channel layer. Additionally, the first gate-etch structure may be formed to be connected to the left side of the first channel structure by contacting the left side of the first channel structure in the D2 direction, for example, the left sides of the first channel layers. That is, the first gate-etch structure may be connected to the first source / drain regions by contacting the first source / drain regions in the D1 direction. Furthermore, the right portion of the first gate-etch structure may be vertically superimposed by the second channel structure.

[0144] FIG. 7 is a schematic block diagram illustrating an electronic device comprising one or more stacked semiconductor devices comprising one or more gate-etched structures according to one or more embodiments. These stacked semiconductor devices may each include one or more stacked semiconductor devices (20, 30, and 40) illustrated in FIG. 2a to 2d, FIG. 3a to 3d, and FIG. 4a to 4d.

[0145] Referring to FIG. 7, a system-on-chip (SoC) (1000) may be an integrated circuit in which components of a computing system or other electronic systems are integrated. As an example of the SoC (1000), an application processor (AP) may include at least one processor and components for various functions. The SoC (1000) may include a core (1011) (e.g., a processor), a digital signal processor (DSP) (1012), a graphic processing unit (GPU) (1013), an embedded memory (1014), a communication interface (1015), and a memory interface (1016). Components of the SoC (1000) may communicate with each other via a bus (1007).

[0146] The core (1011) can process instructions and control the operation of components included in the SoC (1000). For example, the core (1011) can process a series of instructions to execute an operating system and execute applications on the operating system. The DSP (1012) can process digital signals (e.g., digital signals provided from the communication interface (1015)) to generate useful data. The GPU (1013) can generate data for an image output by a display device from image data provided from the embedded memory (1014) or the memory interface (1016), or can encode the image data.

[0147] The embedded memory (1014) can store data necessary for the core (1011), DSP (1012), and GPU (1013) to operate. The communication interface (1015) can provide an interface for a communication network or one-to-one communication. The memory interface (1016) can provide an interface for external memory of the SoC (1000), such as dynamic random access memory (DRAM), flash memory, etc.

[0148] At least one of the core (1011), DSP (1012), GPU (1013), and / or embedded memory (1014) may each include one or more stacked semiconductor devices (20, 30, and 40) as illustrated in FIGS. 2a to 2d, FIGS. 3a to 3d, and FIGS. 4a to 4d.

[0149] The foregoing is a description of exemplary embodiments and is not to be construed as limiting the present disclosure. Although some exemplary embodiments have been described, a person skilled in the art will readily understand that many modifications can be made to the embodiments described above without substantially departing from the present disclosure.

Claims

Claim 1 A semiconductor device comprising: a first channel structure; a first source / drain region on the first channel structure, wherein the first source / drain region and the first channel structure are connected in a first direction; a gate structure on the first channel structure; and a first gate-etch structure having an insulating material on the first channel structure, wherein the first gate-etch structure is connected to the first channel structure in a second direction intersecting the first direction, and the first gate-etch structure does not extend beyond the length of the first channel structure in the first direction along the side of the first source / drain region extending in the first direction. Claim 2 In claim 1, the first gate-etching structure is a semiconductor device in contact with the first source / drain region so as to be connected to the first source / drain region in the first direction. Claim 3 A semiconductor device according to claim 1, wherein the length of the first gate-etch structure is the same as the length of the gate structure in the first direction. Claim 4 A semiconductor device according to claim 1, further comprising: a second channel structure on the first channel structure in a third direction intersecting the first direction and the second direction; and a second source / drain region on the second channel structure, wherein the gate structure is on the second channel structure and the first gate-etch structure is in contact with the gate structure so as to be connected to the gate structure in the second direction. Claim 5 In claim 4, the portion of the gate structure is a semiconductor device located between the second channel structure and the first gate-etch structure in the second direction. Claim 6 In claim 5, the portion of the gate structure is a semiconductor device that is not between the first channel structure and the first gate-etch structure in the second direction. Claim 7 A semiconductor device according to claim 1, further comprising: a second channel structure on the first channel structure in a third direction intersecting the first direction and the second direction; a second source / drain region on the second channel structure; and a second gate-etch structure comprising an insulating material that contacts the gate structure to be connected to the gate structure in the second direction, wherein the second gate-etch structure and the first gate-etch structure are not connected. Claim 8 In claim 7, the portion of the gate structure is a semiconductor device located between the second channel structure and the second gate-etch structure in the second direction. Claim 9 In claim 8, the portion of the gate structure is a semiconductor device that is not between the first channel structure and the first gate-etch structure in the second direction. Claim 10 In claim 7, the second gate-etching structure is a semiconductor device that is not connected to the second channel structure in the second direction. Claim 11 In claim 7, the interface or junction is a semiconductor device formed between a first portion of the gate structure surrounding the first channel structure in the third direction and a second portion of the gate structure surrounding the second channel structure. Claim 12 In claim 7, the second gate-etch structure is a semiconductor device that overlaps the first gate-etch structure in the third direction. Claim 13 In claim 7, the second gate-etch structure is a semiconductor device that does not overlap with the first gate-etch structure in the third direction. Claim 14 A semiconductor device comprising: a first channel structure; a first source / drain region on the first channel structure, wherein the first source / drain region and the first channel structure are connected in a first direction; a first gate structure on the first channel structure; and a first gate-etch structure having an insulating material on the first channel structure, wherein the first gate-etch structure is connected to the first channel structure in a second direction intersecting the first direction, and the length of the first gate-etch structure is equal to the length of the first gate structure in the first direction. Claim 15 In claim 14, the semiconductor device wherein the length of the first gate-etch structure is the same as the length of the first channel structure in the first direction. Claim 16 A semiconductor device according to claim 14, wherein the two sides of the first gate-etch structure opposite to the first direction are coplanar or aligned with the two sides of the first channel structure opposite to the first direction. Claim 17 A semiconductor device comprising: a first gate structure and a second gate structure adjacent to each other in a first direction, wherein the first gate structure and the second gate structure extend in a second direction intersecting the first direction; a source / drain region between the first gate structure and the second gate structure; and a gate-etch structure having an insulating material, which is positioned above the first gate structure among the first gate structure and the second gate structure. Claim 18 In claim 17, the first gate structure is a semiconductor device having a width smaller than that of the second gate structure in the second direction. Claim 19 In claim 17, a semiconductor device further comprising a channel structure, wherein the gate-etching structure contacts the side of the channel structure so as to be connected to the side of the channel structure in the second direction. Claim 20 In claim 17, the gate-etching structure is a semiconductor device in contact with the source / drain region so as to be connected to the source / drain region in the first direction.

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