Semiconductor package

Abstract

A semiconductor package comprises: a first semiconductor chip having a first substrate having a first surface and a second surface opposite to the first surface, first through electrodes penetrating the first substrate, and recesses formed at a predetermined depth from the second surface of the first substrate and exposing one end portion of the first through electrodes through a bottom surface; a second semiconductor chip having a second substrate having a third surface facing the first semiconductor chip and a fourth surface opposite to the third surface, and second connection pads provided on the third surface, which are stacked on the second surface of the first substrate; and conductive connection members each accommodated within the recesses of the first substrate and including a solder layer bonded between the one end portion of the first through electrode and the second connection pad, and a resin layer surrounding the solder layer and filling the recesses.

Description

Technology Field

[0001] The present invention relates to a semiconductor package and a method for manufacturing a semiconductor package, and more specifically, to a semiconductor package comprising a plurality of stacked chips and a method for manufacturing the same. Background Technology

[0002] To manufacture a multi-chip package in which semiconductor chips are stacked, the semiconductor chips can be stacked using solder bumps via a thermal compression bonding process. At this time, a non-conductive film may be utilized to ensure stable bonding of the solder bumps for connection between the chips. However, there are problems such as short circuit defects occurring at the bonding surface of the solder bumps or the non-conductive film overflowing from the outside of the stacked semiconductor chips, which degrades the reliability of the final product and limits the number of stacked semiconductor chips. Additionally, there is a problem in that the height of the stacked semiconductor chips increases due to the non-conductive film. The problem to be solved

[0003] One objective of the present invention is to provide a semiconductor package that minimizes the spacing between stacked chips and has improved bonding reliability. means of solving the problem

[0004] A semiconductor package according to exemplary embodiments for achieving one objective of the present invention comprises: a first substrate having a first surface and a second surface opposite to the first surface, first through electrodes penetrating the first substrate, and recesses formed at a predetermined depth from the second surface of the first substrate and exposing one end portion of the first through electrodes through a bottom surface; a second semiconductor chip having a second substrate having a third surface facing the first semiconductor chip and a fourth surface opposite to the third surface, and second connection pads provided on the third surface, and a second semiconductor chip stacked on the second surface of the first substrate; and conductive connection members each accommodated within the recesses of the first substrate and comprising a solder layer bonded between the one end portion of the first through electrode and the second connection pad, and a resin layer surrounding the solder layer and filling the recesses.

[0005] A semiconductor package according to exemplary embodiments for achieving one objective of the present invention comprises first to fourth semiconductor chips that are sequentially stacked and electrically connected to one another by conductive connection members. Each of the first to third semiconductor chips comprises a substrate having a through electrode formed thereon, and a recess formed at a predetermined depth from the rear surface of the substrate and having one end of the through electrode exposed through the bottom surface, wherein the conductive connection members are each provided within the recesses, and each of the conductive connection members comprises a solder layer bonded to the one end of the through electrode and a resin layer surrounding the solder layer and filling the recess. Effects of the invention

[0006] According to exemplary embodiments, a semiconductor package may include a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip via conductive connection members. At least a portion of the second connection pad of the second semiconductor chip may be inserted into a recess having a predetermined depth from a second surface of the first substrate of the first semiconductor chip. A solder layer of the conductive connection member is bonded to one end of a first through electrode penetrating the first substrate and to the second connection pad of the second semiconductor chip, and a resin layer may surround the solder layer and fill the recess. The resin layer may cover the outer surface of the second connection pad inserted into the recess. The resin layer may cover the entire outer surface of the second connection pad. Thus, bonding reliability can be improved by preventing short circuit defects from occurring at the bonding surface of the solder layer.

[0007] In addition, the second semiconductor chip may come into contact with the back surface of the first semiconductor chip, that is, the second surface of the first substrate. Therefore, when bonding the second semiconductor chip onto the first semiconductor chip, there may not be a gap between the first semiconductor chip and the second semiconductor chip. Since the first semiconductor chip and the second semiconductor chip come into contact with each other without an adhesive film such as a non-conductive film (NCF), the reliability of the final product is improved, and even if the number of stacked semiconductor chips increases, the height caused by the non-conductive film can be prevented. Brief explanation of the drawing

[0008] FIG. 1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. Figure 2 is an enlarged cross-sectional view showing part A of Figure 1. FIG. 3 is a plan view showing a conductive connection member disposed within a recess formed on the rear surface of the first semiconductor chip of FIG. 1. FIGS. 4 to 15 are drawings illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIG. 16 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. Figure 17 is an enlarged cross-sectional view showing part G of Figure 16. FIG. 18 is an enlarged cross-sectional view showing part H of FIG. 16. FIGS. 19 to 22 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. Specific details for implementing the invention

[0009] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings.

[0010] FIG. 1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIG. 2 is an enlarged cross-sectional view showing portion A of FIG. 1. FIG. 3 is a plan view showing a conductive connection member disposed within a recess formed on the rear surface of the first semiconductor chip of FIG. 1. FIG. 1 includes a cross-section cut along the BB' line of FIG. 3.

[0011] Referring to FIGS. 1 to 3, the semiconductor package (10) may include a first semiconductor chip (20), a second semiconductor chip (40) stacked on the first semiconductor chip (20), and a conductive connection member (32) for electrical connection between the first semiconductor chip (20) and the second semiconductor chip (40). Additionally, the semiconductor package (10) may further include a molding member (50) covering the second semiconductor chip (40) on the first semiconductor chip (20), and an external connection member (60) on the first connection pad (23) of the first semiconductor chip (20).

[0012] Additionally, the semiconductor package (10) may be a Multi-Chip Package (MCP) containing different types of semiconductor chips. The semiconductor package (10) may be a System In Package (SIP) having a single independent function by stacking or arranging multiple semiconductor chips within a single package. The semiconductor package (10) may be a package with a 3D chip structure.

[0013] A semiconductor package (10) may include a first semiconductor chip (20) as a sequentially stacked logic chip and a second semiconductor chip (40) as a memory chip. The first semiconductor chip (20) may be a logic chip including a logic circuit. The logic chip may be a controller that controls memory elements of the second semiconductor chip. The first semiconductor chip may be a processor chip such as an ASIC or AP (Application Processor) as a host such as a CPU, GPU, or SOC. The second semiconductor chip may include DRAM, SRAM, etc.

[0014] In this embodiment, the semiconductor package as a multi-chip package is exemplified as comprising two stacked first and second semiconductor chips (20, 40). However, it is not limited thereto, and for example, the semiconductor package (10) may comprise four, eight, twelve, or sixteen stacked semiconductor chips.

[0015] In exemplary embodiments, the first semiconductor chip (20) as a lower semiconductor chip may include a first substrate (21), a first front insulating film (22), a plurality of first connection pads (23), and a plurality of first through electrodes (24). Additionally, the first semiconductor chip (20) may further include conductive bumps (60) as external connection members provided on each of the first connection pads (23). The first semiconductor chip (20) may be mounted on a package substrate or an interposer via the conductive bumps (60).

[0016] The first substrate (21) may have a first surface (212) and a second surface (214) opposite to each other. The first surface may be an active surface, and the second surface may be an inactive surface. Circuit patterns and cells may be formed on the first surface (212) of the first substrate (21). For example, the first substrate (21) may be a single-crystal silicon substrate. The circuit patterns may include transistors, capacitors, diodes, etc. The circuit patterns may constitute circuit elements. Accordingly, the first semiconductor chip (20) may be a semiconductor device having a plurality of circuit elements formed therein.

[0017] The first front insulating film (22) may be provided on the first surface (212) of the first substrate (21), i.e., the active surface. The first front insulating film (22) may include a plurality of insulating films (222, 224) and wirings (223) within the insulating films. Additionally, the outermost insulating layer of the first front insulating film (22) may be provided with first connection pads (23).

[0018] The first front insulating film (22) may include a first metal wiring layer (222) and a first passivation film (224) sequentially stacked on the first surface (212) of the first substrate (21). The first metal wiring layer (222) may include a metal wiring structure having a plurality of wirings (223) vertically stacked on buffer films and insulating films. A first connection pad (23) may be formed on the uppermost wiring among the plurality of wirings (223). For example, the wirings may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof. The first passivation film (224) is formed on the first metal wiring layer (222) and may expose at least a portion of the first connection pad (23). The first passivation film (224) may include a plurality of stacked insulating films. For example, the first passivation film (224) may comprise silicon oxide, silicon nitride, or silicon carbonitride. The first passivation film (224) may have a single film or a multilayer film structure. The first passivation film (224) may be provided with a first connection pad (23). The first connection pad (23) may be exposed through the outer surface of the first passivation film (224).

[0019] A first through-silicon via (TSV) (24) may be provided to vertically penetrate the first substrate (21) from the first surface (212) of the first substrate (20) to the second surface (214). The first end of the first through-electrode (24) may come into contact with the wiring of the first front insulating film. However, it is not limited thereto, and, for example, the first through-electrode (24) may be provided to penetrate the first front insulating film and come into direct contact with the first connection pad (23).

[0020] In exemplary embodiments, the second semiconductor chip (40) may include a second substrate (41), a second front insulating film (42), and a plurality of second connection pads (43). The second semiconductor chip (40) may be mounted on the first semiconductor chip (20) via conductive connection members (32) each provided on the second connection pads (43).

[0021] The second substrate (41) may have a first surface (412) and a second surface (414) that are opposite to each other. The first surface may be an active surface, and the second surface may be an inactive surface. Circuit elements may be formed on the first surface (412) of the second substrate (41). The circuit elements may include a plurality of memory elements. Examples of the memory elements include volatile semiconductor memory elements and non-volatile semiconductor memory elements. An interlayer insulating film covering the circuit elements may be formed on the first surface (412) of the second substrate (41).

[0022] The second front insulating film (42) may include a second metal wiring layer (422) and a second passivation film (424) sequentially laminated on the first surface (412) of the second substrate (41). The second metal wiring layer (422) may include a plurality of insulating layers and upper wirings (423) within the insulating layers. The outermost insulating layer of the second front insulating film (42) may be provided with second connection pads (43).

[0023] A second passivation film (424) is formed on the second metal wiring layer (422) and may expose at least a portion of the second connection pad (43). The second passivation film (424) may include a plurality of stacked insulating films. For example, the second passivation film (424) may include silicon oxide, silicon nitride, or silicon carbonitride. The second passivation film (424) may have a single film or a multilayer film structure. The second connection pad (43) may be provided in the second passivation film (424). The second connection pad (43) may be exposed through the outer surface of the second passivation film (424).

[0024] The first through electrodes (24) may be arranged in an array form within the first substrate (21). The via arrangement of the first through electrodes (24) may correspond to the pad arrangement of the second connection pads (43) of the second semiconductor chip (40). For example, the first semiconductor chip may have a thickness range of 50 μm to 120 μm, and the second semiconductor chip may have a thickness range of 40 μm to 700 μm.

[0025] It will be understood that the size and thickness of the first and second semiconductor chips, the number, size, arrangement, etc. of the first and second front insulating films and the wirings are provided as examples and that the present invention is not limited thereto.

[0026] As illustrated in FIGS. 2 and 3, a second surface (214) of the first substrate (21) may be provided with recesses (R) that expose portions of the first through electrodes (24). A second end opposite to the first end of the first through electrode (24) may be exposed from the bottom surface of the recess (R).

[0027] For example, the first through electrode (24) may have a first diameter (D1). The first diameter (D1) may be within the range of 2 μm to 10 μm. The recess (R) may have a second diameter (D2) larger than the first diameter (D1). The second diameter (D2) may be within the range of 8 μm to 32 μm. The recess (R) may have a depth (L) from the second surface (214) of the first substrate (21). The depth (L) of the recess (R) may be within the range of 15 μm to 100 μm.

[0028] The diameter (D3) of the second connection pad (43) of the second semiconductor chip (40) may be larger than the first diameter (D1) of the first through electrode (24) and smaller than the second diameter (D2) of the recess (R). The diameter (D3) of the second connection pad (43) may be within the range of 6 μm to 30 μm. Accordingly, as described below, at least a portion of the second connection pad (43) may be inserted into the recess (R).

[0029] In exemplary embodiments, the second semiconductor chip (40) may be mounted on the first semiconductor chip (20) via conductive connection members (32). The first surface (412) of the second substrate (41) of the second semiconductor chip (40) may be positioned to face the first semiconductor chip (20). The second surface (414) of the second substrate (41) may be positioned on the first semiconductor chip (20) to face upward. The first through-electrode (24) of the first semiconductor chip (20) and the second connection pad (43) of the second semiconductor chip (40) may be bonded by the conductive connection member (32).

[0030] Conductive connection members (32) may each be disposed within the recesses (R). The conductive connection member (32) may include a solder layer (322) and a resin layer (324) surrounding the solder layer (322). The solder layer (322) may be bonded to the second end of the first through electrode (24) exposed on the bottom surface of the recess (R) and to the second connection pad (43) of the second semiconductor chip (40). The second connection pad (43) may be electrically connected to the first through electrode (24) by the solder layer (322). The resin layer (324) may fill the recess (R) while surrounding the solder layer (322) and the second connection pad (43) bonded to the solder layer (322). The resin layer (324) may cover the outer surface of the second connection pad (43) inserted into the recess (R). The resin layer (324) can cover the entire outer surface of the second connection pad (43). For example, the solder layer (322) may include tin (Sn), tin / lead (Sn / Pb), tin / silver (Sn / Ag), tin / copper (Sn / Cu), tin / indium (Sn / In), tin / silver / copper (Sn / Ag / Cu), etc., and the resin layer (324) may include a resin such as epoxy.

[0031] At least a portion of the second connection pad (43) is inserted into the recess (R), and the second front insulating film (42) of the second semiconductor chip (40) can come into contact with the second surface (214) of the first substrate (21). The front surface of the second semiconductor chip (40) can come into contact with the rear surface of the first semiconductor chip (20), that is, the second surface (214) of the first substrate (21). Therefore, when bonding the second semiconductor chip (40) onto the first semiconductor chip (20), there may not be a gap between the first semiconductor chip (20) and the second semiconductor chip (40). Additionally, the first semiconductor chip (20) and the second semiconductor chip (40) can come into contact with each other without an adhesive film such as a non-conductive film (NCF).

[0032] In exemplary embodiments, the sealing member (50) may cover the second semiconductor chip (40) on the first semiconductor chip (20). The sealing member (50) may cover the side of the second semiconductor chip (40). The upper surface of the second semiconductor chip (40), i.e., the second surface (414) of the second substrate (41), may be exposed by the sealing member (50). For example, the sealing member (50) may include a thermosetting resin, etc. The second surface (414) of the second substrate (41) and the upper surface of the sealing member (50) may be located on the same plane.

[0033] Although not illustrated in the drawing, the first semiconductor chip (20) may be mounted on a package substrate via conductive bumps (60). Additionally, an underfill member may be interposed between the first semiconductor chip (20) and the package substrate. For example, the underfill member may include an epoxy material to reinforce the gap between the first semiconductor chip (20) and the package substrate.

[0034] External connection pads are provided on the lower surface of the package substrate, and external connection members may be disposed on the external connection pads. For example, the external connection member may be a solder ball. The semiconductor package (10) may be mounted on a module substrate (not shown) via the solder balls to form a memory module.

[0035] As described above, the semiconductor package (10) may include a first semiconductor chip (20) and a second semiconductor chip (40) stacked on the first semiconductor chip (20) via conductive connection members (32). The first semiconductor chip (20) may include a first substrate (21) having a first through electrode (24) formed thereon. A recess (R) having a predetermined depth (L) may be provided from a second surface (214) of the first substrate (21). One end of the first through electrode (24) may be exposed through the bottom surface of the recess (R). Conductive connection members (32) are each provided within the recesses (R), and each of the conductive connection members (32) may include a solder layer (322) and a resin layer (324). The solder layer (322) is bonded to the first end of the first through electrode (24) and the second connection pad (43) of the second semiconductor chip (40), and the resin layer (324) can surround the solder layer (322) and fill the recess (R).

[0036] At least a portion of the second connection pad (43) of the second semiconductor chip (40) may be inserted into the recess (R). The resin layer (324) may cover the outer surface of the second connection pad (43) inserted into the recess (R). The resin layer (324) may cover the entire outer surface of the second connection pad (43). Thus, the bonding reliability can be improved by preventing short circuit defects from occurring at the bonding surface of the solder layer (322).

[0037] Additionally, the second semiconductor chip (40) can come into contact with the back surface of the first semiconductor chip (20), that is, the second surface (214) of the first substrate (21). Therefore, when bonding the second semiconductor chip (40) onto the first semiconductor chip (20), there may be no gap between the first semiconductor chip (20) and the second semiconductor chip (40). Since the first semiconductor chip (20) and the second semiconductor chip (40) come into contact with each other without an adhesive film such as a non-conductive film (NCF), the reliability of the final product is improved, and even if the number of stacked semiconductor chips increases, the height caused by the non-conductive film can be prevented.

[0038] Below, a method for manufacturing the semiconductor package of FIG. 1 will be described.

[0039] FIGS. 4 through 15 are drawings illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIGS. 4 through 6, FIG. 8, FIG. 10, FIG. 12, and FIG. 15 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIG. 7 is a plan view of FIG. 6. FIG. 6 is a cross-sectional view cut along the CC' line of FIG. 7. FIG. 9 is an enlarged cross-sectional view showing section D of FIG. 8. FIG. 11 is an enlarged cross-sectional view showing section E of FIG. 10. FIG. 13 is an enlarged cross-sectional view showing section F of FIG. 12. FIG. 14 is a graph showing the temperature change over time in the solder reflow process performed in FIG. 12 and FIG. 13.

[0040] Referring to FIGS. 4 to 7, first, recesses (R2) can be formed on the second surface (214) of the first wafer (W1) to expose one end portion of each of the through electrodes (24).

[0041] As illustrated in FIG. 4, a first wafer (W1) may be provided comprising a first substrate (21), a first front insulating film (22), a plurality of first connection pads (23), and a plurality of first through electrodes (24). The first front insulating film (22) may be provided on a first surface (212) of the first substrate (21), i.e., an active surface. The first connection pad (23) may be provided on the outermost insulating layer of the first front insulating film (22). The first connection pad (23) may be provided as a bump-under metal (UBM) pad on which a conductive bump, such as a solder bump, is disposed. For example, the first connection pad (23) may comprise copper (Cu).

[0042] The first substrate (21) may include a die region (DA) in which circuit patterns and cells are formed, and a scribe region (SA) surrounding the die region (DA). As described below, the first substrate (210) may be cut along the scribe region (SA) separating a plurality of die regions (DA) of the first wafer (W2) to be individualized into first semiconductor chips.

[0043] The circuit patterns provided on the active surface of the first substrate (21) may include transistors, diodes, etc. The circuit patterns may constitute circuit elements.

[0044] A first front insulating film (22) may be formed on the active surface of the first substrate (21). The first front insulating film (22) may include a plurality of insulating films and wiring within the insulating films. The wiring may include metal wiring and contacts formed within each of the insulating films. At least a portion of the metal wiring provided on the outermost insulating film may serve as a landing pad on which a first connection pad (23) is placed. The first connection pad (23) may be provided on the front surface of the first wafer (W1) (hereinafter referred to as the first surface (212) of the first substrate (21) for convenience of explanation).

[0045] As illustrated in FIG. 4, the first through electrode (24) may be provided to penetrate a portion of the first substrate (21). The first through electrode (24) may extend a predetermined depth in a vertical direction from the first surface (212) of the first substrate (211). Thus, the first end of the first through electrode (24) may be exposed from the first surface (212) of the first substrate (21), and the second end of the first through electrode (24) may not be exposed from the second surface (214) of the first substrate (21). The first end of the first through electrode (24) may be electrically connected to the first connection pad (23) through the wiring of the first front insulating film.

[0046] As shown in FIG. 5, the second surface (214) of the first substrate (21) can be partially removed so that the second end of the first through electrode (24) is exposed.

[0047] Specifically, the back surface of the first substrate (21), i.e., the second surface (214), can be polished using a substrate support system (WSS). After attaching the first wafer (W1) onto the carrier substrate using an adhesive film, the second surface (214) of the first substrate (21) can be removed so that the second end of the first through electrode (24) is exposed.

[0048] The second surface (214) of the first substrate (21) can be partially removed by a grinding process such as chemical mechanical polishing (CMP). Accordingly, the thickness of the first substrate (21) can be reduced to a desired thickness. For example, the first substrate (21) may have a thickness range of about 30 µm to 150 µm. The second end of the first through electrode (24) may be exposed from the second surface (214) of the substrate (210).

[0049] Alternatively, the second surface (214) of the first substrate (21) can be removed so that the second end of the first through electrode (24) is not exposed. In this case, the third end of the first through electrode (24) can be buried to a predetermined depth (e.g., 3 μm to 5 μm) from the second surface (214) of the first substrate (21).

[0050] As illustrated in FIGS. 6 and 7, recesses (R) can be formed on the second surface (214) of the first substrate (21). The second ends of the first through electrodes (24) can be exposed from the bottom surfaces of the recesses (R), respectively.

[0051] For example, a plasma etching process can be performed on the back surface of the first wafer (W1) to form recesses (R). Specifically, after forming a photoresist pattern having openings to expose recess regions on the second surface (214) of the first substrate (211), the first wafer (W1) can be loaded into a plasma processing device, and then a process gas can be supplied onto the first wafer (W1). The process gas may include argon (Ar) gas, hydrogen (H2) gas, nitrogen (N2) gas, etc. The plasma processing device may include an induced coupled plasma (ICP) chamber, a capacitively coupled plasma (CCP) chamber, etc. When high-frequency power having a predetermined frequency is applied to the upper electrode, the electromagnetic field induced by the upper electrode is applied to the process gas injected into the chamber, thereby generating plasma. The above plasma etching process can form recesses (R) so that the second ends of the first through electrodes (24) are exposed.

[0052] Alternatively, recesses (R) can be formed by performing a laser processing process on the back surface of the first wafer (W1). For example, the recesses (R) can be formed by a laser drilling process. The laser in the laser drilling process may include a CO2 laser, a YAG laser, an excimer laser, a UV laser, etc.

[0053] For example, the first through electrode (24) may have a first diameter (D1). The first diameter (D1) may be within the range of 2 μm to 10 μm. The recess (R) may have a second diameter (D2) larger than the first diameter (D1). The second diameter (D2) may be within the range of 8 μm to 32 μm. The recess (R) may have a depth (L) from the second surface (214) of the first substrate (21). The depth (L) of the recess (R) may be within the range of 15 μm to 100 μm.

[0054] In exemplary embodiments, an insulating film may be formed on the second surface (214) of the first substrate (21) to expose the first through electrode (24). The insulating film may be formed on the bottom surface and sidewall of the recess (R) along the profile of the recess (R). For example, the insulating film may include oxides, nitrides, etc. These may be used alone or in combination. For the simplification of the process, the process of forming the insulating film may be omitted.

[0055] Referring to FIGS. 8 and 9, a solder resin layer (30) can be formed on the second end of the first through electrode (24) within the recess (R) of the first substrate (21).

[0056] In exemplary embodiments, the solder resin layer (30) may be printed on the second end of the first through electrode (24) in the recess (R) by a screen printing process. The solder resin layer (30) may comprise solder powder (302) and a resin (304) surrounding them. For example, the solder resin layer (30) may comprise an epoxy solder paste. The epoxy solder paste may consist of a mixture of an epoxy formulation and solder powder. The epoxy formulation may serve as a substitute for the flux in the solder paste.

[0057] Referring to FIGS. 10 to 14, a second semiconductor chip (40) can be stacked on the first substrate (21) of the first wafer (W1).

[0058] In exemplary embodiments, the second semiconductor chip (40) may include a second substrate (41), a second front insulating film (42), and a plurality of second connection pads (43). The second front insulating film (42) may be provided on the first surface (412) of the second substrate (41), i.e., the active surface. The second front insulating film (42) may include a plurality of insulating films (422, 424) and wirings (423) within the insulating films. A second connection pad (43) may be provided on the outermost insulating film of the second front insulating film (42).

[0059] The second front insulating film (42) may include a second metal wiring layer (422) and a second passivation film (424). The second metal wiring layer (422) may include a plurality of wirings (423) inside. For example, the second metal wiring layer (422) may include a metal wiring structure having a plurality of wirings (423) vertically stacked in buffer films and insulating films. The second connection pad (43) may be formed on the uppermost wiring among the plurality of wirings (423). For example, the wirings may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

[0060] The second passivation film (424) is formed on the second metal wiring layer (422) and may expose at least a portion of the second connection pad (43). The second passivation film (424) may include a plurality of stacked insulating films. For example, the second passivation film (424) may be stacked sequentially and may include an oxide film and a nitride film.

[0061] As illustrated in FIGS. 10 and 11, the second semiconductor chip (40) can be attached to the first wafer (W1) through solder resin layers (30). The second connection pads (43) of the second semiconductor chip (40) can each be attached to the solder resin layers (30) within the recesses (R). The diameter (D3) of the second connection pad (43) of the second semiconductor chip (40) may be larger than the first diameter (D1) of the first through electrode (24) and smaller than the second diameter (D2) of the recess (R). The diameter (D3) of the second connection pad (43) may be within the range of 6 μm to 30 μm. Accordingly, at least a portion of the second connection pad (43) may be inserted into the recess (R) by a reflow process described later.

[0062] As illustrated in FIGS. 12 to 14, a second semiconductor chip (40) can be bonded onto a first wafer (W1) by performing a reflow process. The first through-electrode (24) of the first wafer (W1) and the second connection pad (43) of the second semiconductor chip (40) can be bonded by a conductive connection member (32).

[0063] In exemplary embodiments, the individual solder powders in the epoxy solder paste are changed into a liquid state by the reflow process and then combined with adjacent powders to lower the surface energy, thereby forming a solder layer (322). The solder layer (322) is bonded to the second end of the first through electrode (24) exposed on the bottom surface of the recess (R) and the second connection pad (43) of the second semiconductor chip (40). At this time, the epoxy in the epoxy solder paste has a rapidly lowered viscosity and, due to the difference in interfacial energy, can form a resin layer (324) that fills the recess (R) while surrounding the solder layer (322) and the second connection pad (43) bonded to the solder layer (322).

[0064] As illustrated in FIG. 14, the reflow process can be described by dividing the behavior of the solder powder and epoxy according to time and temperature into four stages. In the first stage reduction reaction section (I), the epoxy can reduce the oxide on the surface of the solder powder and the oxide on the second connection pad (43) to expose a clean metal surface. In the second stage section (II), the solder powder is heated above the solder powder melting temperature (T1), and the solder powder from which oxide has been removed changes into a liquid state to form a single liquid structure to minimize surface tension between adjacent liquid metals. At this time, the viscosity of the epoxy present in the epoxy solder paste decreases rapidly, and it flows out to the outer edge of the joint due to the difference in interfacial energy. The liquid solder comes into contact with the second end of the first through electrode (24) and the second connection pad (43) of the second semiconductor chip (40), and some of the epoxy pushed outward fills the recess (R), while some of the epoxy travels up along the outer surface of the second connection pad (43) and surrounds the second connection pad (43). In the third stage (III), curing of the epoxy can occur at an epoxy curing initiation temperature (T2) above the melting temperature of the solder powder. Subsequently, in the fourth stage (IV), the epoxy is completely cured to form a conductive connection member (32).

[0065] A conductive connection member (32) is formed within a recess (R) and may include a solder layer (322) between the second end of the first through electrode (24) and the second connection pad (43) of the second semiconductor chip (40), and a resin layer (324) that surrounds the solder layer (322) and the second connection pad (43) and fills the recess (R). The resin layer (324) may cover the outer surface of the second connection pad (43) inserted into the recess (R). The resin layer (324) may cover the entire outer surface of the second connection pad (43).

[0066] When bonding the second semiconductor chip (40) onto the first wafer (W1) by the above reflow process, there may not be a gap between the first wafer (W1) and the second semiconductor chip (40). By the above reflow process, at least a portion of the second connection pad (43) is inserted into the recess (R), and the second front insulating film (42) of the second semiconductor chip (40) may come into contact with the second surface (214) of the first substrate (21).

[0067] Referring to FIG. 15, a sealing member (50) covering a second semiconductor chip (40) can be formed on a first wafer (W1).

[0068] In exemplary embodiments, a sealing member (50) may be formed on a first wafer (W1) to cover the upper surfaces of the second semiconductor chips (40) and to fill the spaces between the second semiconductor chips (40). The sealing member (50) may be formed to surround the second semiconductor chips (40). The sealing member (50) may be formed by a dispensing process or a spin coating process. For example, the sealing member (50) may include a thermosetting resin, etc.

[0069] Next, the upper surface of the sealing member (50) can be partially removed to expose the upper surface of the second semiconductor chip (40), i.e., the second surface (414). The upper surface of the sealing member (50) can be partially removed by a grinding process. The upper surface of the sealing member (50) can be removed until parts of the second surface (414) of the second semiconductor chip (40) are exposed. At this time, the second surface (414) of the second semiconductor chip (40) can also be partially removed. After the grinding process, the upper surface of the sealing member (50) may be on the same plane as the second surface (414) of the second semiconductor chip (40).

[0070] Next, conductive bumps (60, see FIG. 1) can be formed on the first connection pads (23) of the first wafer (W1).

[0071] Afterwards, the first wafer (W1) and the sealing member (50) can be cut along the scribe lane area (SA) to form a stacked package (10, see FIG. 1) in which the individualized first semiconductor chip (20) and the second semiconductor chip (40) are stacked on the first semiconductor chip (20).

[0072] FIG. 16 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIG. 17 is an enlarged cross-sectional view showing portion G of FIG. 16. FIG. 18 is an enlarged cross-sectional view showing portion H of FIG. 16. The semiconductor package is substantially the same as the semiconductor package described with reference to FIG. 1 through 3, except for the structure of the stacked semiconductor chips. Accordingly, the same components are indicated by the same reference numerals, and the repeated description of the same components is omitted.

[0073] Referring to FIGS. 16 to 18, the semiconductor package (11) may include stacked semiconductor chips. The semiconductor package (11) may include a first semiconductor chip (20), second to fifth semiconductor chips (40a, 40b, 40c, 40d) sequentially stacked on the first semiconductor chip (20), and first to fourth conductive connection members (32a, 32b, 32c, 32d) for electrical connection between the first to fifth semiconductor chips (20, 40a, 40b, 40c, 40d). Additionally, the semiconductor package (11) may further include a molding member (50) covering the second to fifth semiconductor chips (40a, 40b, 40c, 40d) on the first semiconductor chip (20).

[0074] In the present embodiment, the first to fifth semiconductor chips (20, 40a, 40b, 40c, 40d) may be substantially identical or similar to one another. Accordingly, identical or similar components are indicated by identical or similar reference numerals, and repeated descriptions of identical components may be omitted.

[0075] The first to fifth semiconductor chips (20, 40a, 40b, 40c, 40d) may be stacked on a package substrate such as a printed circuit board (PCB) or an interposer. In the present embodiment, a semiconductor package as a multi-chip package is exemplified as comprising five stacked semiconductor chips (20, 40a, 40b, 40c, 40d). However, it will be understood that it is not limited thereto.

[0076] For example, the semiconductor package (11) may include a High Bandwidth Memory (HBM) device. The High Bandwidth Memory (HBM) package may have a high-bandwidth interface for faster data exchange with a processor chip. The High Bandwidth Memory (HBM) package may have an input / output (TSV I / O) structure including a large number of through-silicon via structures to implement the high-bandwidth interface. A processor chip requiring support for the HBM package may be an application-specific integrated circuit (ASIC) chip including a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor, a microcontroller, an application processor (AP), a digital signal processing core, and an interface for signal exchange.

[0077] A semiconductor package (11) may include a first semiconductor chip (20) as a buffer die and second to fifth semiconductor chips (40a, 40b, 40c, 40d) as memory dies that are sequentially stacked. The first to fifth semiconductor chips (20, 40a, 40b, 40c, 40d) may be electrically connected by through electrodes such as through-silicon vias (TSVs). The memory die may include a memory element, and the buffer die may include a controller that controls the memory element.

[0078] In exemplary embodiments, the semiconductor chip (20) may include a first substrate (21), a first front insulating film (22), a plurality of first connection pads (23), and a plurality of first through electrodes (24). Additionally, the first semiconductor chip (20) may further include conductive bumps (60) as external connection members, each provided on the first connection pads (23).

[0079] The first substrate (21) may have a first surface (212) and a second surface (214) opposite to each other. The first surface may be an active surface, and the second surface may be an inactive surface. A first front insulating film (22) may be provided on the first surface (212), i.e., the active surface, of the first substrate (21). Additionally, first connection pads (23) may be provided on the outermost insulating layer of the first front insulating film (22).

[0080] The second semiconductor chip (40a) may include a second substrate (41a), a second front insulating film (42a), a plurality of second connection pads (43a), and a plurality of second through electrodes (44a). The second semiconductor chip (40a) may be mounted on the first semiconductor chip (20) via first conductive connection members (32a) each provided on the second connection pads (43a).

[0081] As illustrated in FIG. 17, the first semiconductor chip (20) may include first recesses (R1) formed at a predetermined depth (L) from the second surface (214) of the first substrate (21). One end of the first through electrode (24) may be exposed from the bottom surface of the first recess (R1). First conductive connection members (32a) may each be disposed within the first recesses (R1). The first conductive connection member (32a) may include a solder layer (322a) and a resin layer (324a) surrounding the solder layer (322a). The solder layer (322a) may be bonded to the exposed end of the first through electrode (24) exposed on the bottom surface of the first recess (R1) and to the second connection pad (43a) of the second semiconductor chip (40a). The second connection pad (43a) can be electrically connected to the first through electrode (24) by the solder layer (322a). The resin layer (324a) can fill the first recess (R1) while surrounding the solder layer (322a) and the second connection pad (43a) bonded to the solder layer (322a). The resin layer (324a) can cover the outer surface of the second connection pad (43a) inserted into the first recess (R1). The resin layer (324a) can cover the entire outer surface of the second connection pad (43a).

[0082] In exemplary embodiments, the third semiconductor chip (40b) may include a third substrate (41b), a third front insulating film (42b), a plurality of third connection pads (43b), and a plurality of third through electrodes (44b). The third semiconductor chip (40b) may be mounted on the second semiconductor chip (40a) via second conductive connection members (32b) each provided on the third connection pads (43b).

[0083] The fourth semiconductor chip (40c) may include a fourth substrate (41c), a fourth front insulating film (42c), a plurality of fourth connection pads (43c), and a plurality of fourth through electrodes (44c). The fourth semiconductor chip (40c) may be mounted on the third semiconductor chip (40b) via third conductive connection members (32c) each provided on the fourth connection pads (43c).

[0084] The fifth semiconductor chip (40d) may include a fifth substrate (41d), a fifth front insulating film (42d), and a plurality of fifth connection pads (43d). The fifth semiconductor chip (40d) may be mounted on the fourth semiconductor chip (40c) via fourth conductive connection members (32d) each provided on the fifth connection pads (43d).

[0085] As illustrated in FIG. 18, the second semiconductor chip (40a) may include second recesses (R2) formed at a predetermined depth from the second surface (414a) of the second substrate (41a). One end of the second through electrode (44a) may be exposed from the bottom surface of the second recess (R2). Second conductive connection members (32b) may each be disposed within the second recesses (R2). The second conductive connection member (32b) may include a solder layer (322b) and a resin layer (324b) surrounding the solder layer (322b). The solder layer (322b) may be bonded to the exposed end of the second through electrode (44a) exposed on the bottom surface of the second recess (R2) and to the third connection pad (43b) of the third semiconductor chip (40b). The third connection pad (43b) can be electrically connected to the second through electrode (44a) by the solder layer (322b). The resin layer (324b) can fill the second recess (R2) while surrounding the solder layer (322b) and the third connection pad (43b) bonded to the solder layer (322b). The resin layer (324b) can cover the outer surface of the third connection pad (43b) inserted into the second recess (R2). The resin layer (324b) can cover the entire outer surface of the third connection pad (43b).

[0086] Similarly, the third semiconductor chip (40b) may include third recesses (R3) formed at a predetermined depth from the second surface (414b) of the third substrate (41b). One end of the third through electrode (44b) may be exposed from the bottom surface of the third recess (R3). Third conductive connection members (32c) may each be disposed within the third recesses (R3). The third conductive connection member (32c) may include a solder layer (322c) and a resin layer (324c) surrounding the solder layer (322c). The solder layer (322c) may be bonded to the exposed end of the third through electrode (44b) exposed from the bottom surface of the third recess (R3) and to the third connection pad (43b) of the third semiconductor chip (40b). The third connection pad (43b) can be electrically connected to the third through electrode (44b) by the solder layer (322c). The resin layer (324c) can fill the third recess (R3) while surrounding the solder layer (322c) and the fourth connection pad (43c) bonded to the solder layer (322c). The resin layer (324c) can cover the outer surface of the fourth connection pad (43c) inserted into the third recess (R3). The resin layer (324c) can cover the entire outer surface of the fourth connection pad (43c).

[0087] Similarly, the fourth semiconductor chip (40c) may include fourth recesses formed to a predetermined depth from the second surface of the fourth substrate (41c). One end of the fourth through electrode (44c) may be exposed from the bottom surface of the fourth recess. Fourth conductive connection members (32d) may each be disposed within the fourth recesses. The fourth conductive connection member (32d) may include a solder layer and a resin layer surrounding the solder layer. The solder layer may be bonded to the exposed end of the fourth through electrode (44c) exposed on the bottom surface of the fourth recess and to the fourth connection pad (43c) of the fourth semiconductor chip (40c). The fourth connection pad (43c) may be electrically connected to the fourth through electrode (44c) by the solder layer. The resin layer may fill the fourth recess while surrounding the solder layer and the fifth connection pad (43d) bonded to the solder layer. The resin layer can cover the outer surface of the fifth connection pad (43d) inserted into the fourth recess. The resin layer can cover the entire outer surface of the fifth connection pad (43d).

[0088] In exemplary embodiments, the second semiconductor chip (40a) may be in contact with the back surface of the first semiconductor chip (20), that is, the second surface (214) of the first substrate (21). There may be no gap between the first semiconductor chip (20) and the second semiconductor chip (40a). The third semiconductor chip (40b) may be in contact with the back surface of the second semiconductor chip (40a), that is, the second surface (414a) of the second substrate (41a). There may be no gap between the second semiconductor chip (40a) and the third semiconductor chip (40b). The fourth semiconductor chip (40c) may be in contact with the back surface of the third semiconductor chip (40b), that is, the second surface (414b) of the third substrate (41b). There may be no gap between the third semiconductor chip (40b) and the fourth semiconductor chip (40c). The fifth semiconductor chip (40d) can be in contact with the back surface of the fourth semiconductor chip (40c), that is, the second surface of the fourth substrate (41c). There may be no gap between the fourth semiconductor chip (40c) and the fifth semiconductor chip (40d). Since the first to fifth semiconductor chips are in contact with each other without an adhesive film such as a non-conductive film (NCF), the reliability of the final product is improved, and even if the number of stacked semiconductor chips increases, the height caused by the non-conductive film can be prevented.

[0089] Below, a method for manufacturing the semiconductor package of FIG. 16 will be described.

[0090] FIGS. 19 to 22 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments.

[0091] Referring to FIG. 19, first recesses (R1) can be formed by performing processes identical or similar to those described with reference to FIG. 4 to 7 to each expose one end of a through electrode (24) on the second surface (214) of the first wafer (W1).

[0092] In exemplary embodiments, first, conductive bumps (60) as external connection members can be formed on the front surface of a first wafer (W1), and an adhesive film (F1) covering the conductive bumps (60) can be formed on the front surface of the first wafer (W1). Subsequently, the first wafer (W1) can be attached to a first carrier substrate (C1) using the adhesive film (F1).

[0093] Next, the second surface (214) of the first substrate (21) can be partially removed so that one end of the first through electrode (24) is exposed. First recesses (R1) can be formed on the second surface (214) of the first substrate (21). The ends of the first through electrodes (24) can be exposed from the bottom surfaces of the first recesses (R1), respectively.

[0094] Referring to FIG. 20, processes identical or similar to those described with reference to FIG. 8 to FIG. 11 can be performed to form a first solder resin layer (30a) on one end of a first through electrode (24) within a first recess (R1) of a first substrate (21), and a second semiconductor chip (40a) can be attached to a first wafer (W1) through the solder resin layers (30). At this time, second recesses (R2) that expose one end of the second through electrodes (44a) can be formed on the back surface of the second semiconductor chip (40a).

[0095] Similarly, a second solder resin layer (30b) can be formed on the end portion of the second through electrode (44a) within the second recess (R2) of the second semiconductor chip (40a), and the third semiconductor chip (40b) can be attached to the second semiconductor chip (40b) through the second solder resin layers (30b). At this time, third recesses (R3) that expose the end portions of the third through electrodes (44b) can be formed on the rear surface of the third semiconductor chip (40b).

[0096] Similarly, a third solder resin layer (30c) can be formed on the end portion of the third through electrode (44b) within the third recess (R3) of the third semiconductor chip (40b), and the fourth semiconductor chip (40c) can be attached to the third semiconductor chip (40b) through the third solder resin layers (30c). At this time, fourth recesses (R4) that expose the end portions of the fourth through electrodes (44c) can be formed on the rear surface of the fourth semiconductor chip (40c).

[0097] Similarly, a fourth solder resin layer (30d) can be formed on one end of the fourth through electrode (44c) within the fourth recess (R4) of the fourth semiconductor chip (40c), and the fifth semiconductor chip (40d) can be attached to the fourth semiconductor chip (40c) through the fourth solder resin layers (30d).

[0098] Each of the first to fourth solder resin layers (30a, 30b, 30c, 30d) may comprise solder powder and a resin surrounding them. For example, each of the first to fourth solder resin layers (30a, 30b, 30c, 30d) may comprise an epoxy solder paste. The epoxy solder paste may be composed of a mixture of an epoxy formulation and solder powder. The epoxy formulation may serve as a substitute for the flux in the solder paste.

[0099] Referring to FIG. 21, the second semiconductor chip (40a) can be bonded onto the first wafer (W1) by performing processes identical or similar to those described with reference to FIG. 12 to 14. By a reflow process, the third semiconductor chip (40b) can be bonded onto the second semiconductor chip (40a), the fourth semiconductor chip (40c) can be bonded onto the third semiconductor chip (40b), and the fifth semiconductor chip (40d) can be bonded onto the fourth semiconductor chip (40c).

[0100] In exemplary embodiments, the individual solder powders in the epoxy solder paste may be converted into a liquid state by the reflow process, then combined with adjacent powders to lower surface energy, and subsequently form a solder layer. The solder layer is bonded to one end of the through electrode exposed on the bottom surface of each of the first to fourth recesses and to the connection pad of the stacked semiconductor chip. At this time, the epoxy in the epoxy solder paste may rapidly decrease in viscosity and, due to the difference in interfacial energy, form a resin layer that fills the recess while surrounding the solder layer and the connection pad bonded to the solder layer.

[0101] The first to fourth conductive connection members (32a, 32b, 32c, 32d) are each formed within the first to fourth recesses and may include a solder layer between the one end of the through electrode and the connection pad of the stacked semiconductor chip, and a resin layer that surrounds the solder layer and the connection pad and fills the recess. The resin layer may cover the outer surface of the connection pad inserted into the recess. The resin layer may cover the entire outer surface of the connection pad (43).

[0102] When bonding the second semiconductor chip (40) onto the first wafer (W1) by the above reflow process, there may not be a gap between the first wafer (W1) and the second semiconductor chip (40). The second semiconductor chip (40a) may come into contact with the back surface of the first semiconductor chip (20), that is, the second surface (214) of the first substrate (21). There may not be a gap between the first semiconductor chip (20) and the second semiconductor chip (40a). The third semiconductor chip (40b) may come into contact with the back surface of the second semiconductor chip (40a), that is, the second surface (414a) of the second substrate (41a). There may not be a gap between the second semiconductor chip (40a) and the third semiconductor chip (40b). The fourth semiconductor chip (40c) may come into contact with the back surface of the third semiconductor chip (40b), that is, the second surface (414b) of the third substrate (41b). There may not be a gap between the third semiconductor chip (40b) and the fourth semiconductor chip (40c). The fifth semiconductor chip (40d) may come into contact with the back surface of the fourth semiconductor chip (40c), that is, the second surface of the fourth substrate (41c). There may not be a gap between the fourth semiconductor chip (40c) and the fifth semiconductor chip (40d). Since the first to fifth semiconductor chips come into contact with each other without an adhesive film such as a non-conductive film (NCF), the reliability of the final product is improved, and even if the number of stacked semiconductor chips increases, the height caused by the non-conductive film can be prevented.

[0103] Referring to FIG. 22, a sealing member (50) covering second, third, fourth, and fifth semiconductor chips (40a, 40b, 40c, 40d) can be formed on a first wafer (W1) by performing processes identical or similar to those described with reference to FIG. 15.

[0104] Subsequently, the first wafer (W1) and the sealing member (50) can be cut along the scribe lane area (SA) to form a stacked package (11, see FIG. 16) comprising a first semiconductor chip (20) that has been individualized and second, third, fourth, and fourth semiconductor chips (40a, 40b, 40c, 40d) that are sequentially stacked on the first semiconductor chip (20).

[0105] The aforementioned semiconductor package may include semiconductor devices such as logic devices or memory devices. The semiconductor package may include logic devices such as, for example, a central processing unit (CPU, MPU), an application processor (AP), volatile memory devices such as, for example, an SRAM device, a DRAM device, and non-volatile memory devices such as, for example, a flash memory device, a PRAM device, an MRAM device, an RRAM device, and so on.

[0106] Although the present invention has been described above with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as described in the following claims. Explanation of the symbols

[0107] 10, 11: Semiconductor package 20: The first semiconductor chip 21: First substrate 22: First front insulating film 23: 1st Connection Pad 24: First penetrating electrode 30: Solder resin layer 302: Solder powder 304: Suzy 32, 32a, 32b, 32c, 32d: Conductive connection members 322, 322a, 322b, 322c: Solder layer 324, 324a, 324b, 324c: Resin layer 40, 40a: Second semiconductor chip 40b: Third semiconductor chip 40c: 4th semiconductor chip 40d: The 5th semiconductor chip 41, 41a: Second substrate 41b: Third substrate 41c: 4th substrate 41d: 5th substrate 42, 42a: Second front insulating film 42b: Third front insulating film 42c: 4th front insulating film 42d: 5th front insulating film 43, 43a: Second connection pad 43b: Third connection pad 43c: 4th connection pad 43d: 4th connection pad 44, 44a: Second penetrating electrode 44b: Third penetrating electrode 44c: 4th penetrating electrode 50: Molding member 60: Absence of external connection

Claims

Claim 1 A semiconductor package comprising: a first substrate having a first surface and a second surface opposite to the first surface, first penetrating electrodes penetrating the first substrate, and recesses formed at a predetermined depth from the second surface of the first substrate and exposing one end portion of the first penetrating electrodes through a bottom surface; a second semiconductor chip having a second substrate having a third surface facing the first semiconductor chip and a fourth surface opposite to the third surface, and second connection pads provided on the third surface, and a second semiconductor chip having conductive connection members each accommodated within the recesses of the first substrate, and including a solder layer bonded between the one end portion of the first penetrating electrode and the second connection pad, and a resin layer surrounding the solder layer and filling the recesses. Claim 2 A semiconductor package according to claim 1, wherein at least a portion of the second connection pad is inserted into the recess. Claim 3 In claim 1, the resin layer covers the entire outer surface of the second connection pad in a semiconductor package. Claim 4 A semiconductor package according to claim 1, wherein the first through electrode has a first diameter, and the recess has a second diameter larger than the first diameter. Claim 5 In claim 4, the second diameter of the recess is within the range of 8㎛ to 32㎛ for the semiconductor package. Claim 6 In claim 1, the second connection pad is a semiconductor package having a third diameter that is larger than the first diameter and smaller than the second diameter. Claim 7 In claim 1, the second semiconductor chip is a semiconductor package in contact with the second surface of the first substrate of the first semiconductor chip. Claim 8 A semiconductor package according to claim 1, further comprising a molding member covering the second semiconductor chip on the first semiconductor chip. Claim 9 A semiconductor package comprising first to fourth semiconductor chips that are sequentially stacked and electrically connected to one another by conductive connection members, wherein each of the first to third semiconductor chips comprises a substrate having a through electrode formed therein, and a recess formed at a predetermined depth from the rear surface of the substrate and exposing one end of the through electrode through the bottom surface, wherein each of the conductive connection members is provided within the recesses, and each of the conductive connection members comprises a solder layer bonded to the one end of the through electrode and a resin layer surrounding the solder layer and filling the recess. Claim 10 In claim 9, each of the second to fourth semiconductor chips comprises a front insulating film provided on the front surface of the substrate and a connection terminal provided on the front insulating film, and the connection terminal is a semiconductor package bonded to the solder layer of the conductive connection member.

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