Semiconductor device and method for fabricating the same

Abstract

A semiconductor device including source / drain contacts and a method for manufacturing the same are provided. The semiconductor device comprises a substrate, a first active pattern extending in a first direction on the substrate, a first gate structure extending in a second direction intersecting the first direction on the first active pattern, a second gate structure extending in a second direction and spaced apart from the first gate structure in the first direction on the first active pattern, a first epitaxial pattern connected to the first active pattern between the first gate structure and the second gate structure, an insulating pattern covering at least a portion of the upper surface of the first epitaxial pattern, and a dummy contact on the upper surface of the insulating pattern spaced apart from the first epitaxial pattern by the insulating pattern.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. More specifically, the present invention relates to a semiconductor device comprising a source / drain contact and a method for manufacturing the same. Background Technology

[0002] As one of the scaling techniques to increase the density of integrated circuit devices, a multi-gate transistor has been proposed in which a silicon body in the shape of a fin or nanowire is formed on a substrate and a gate is formed on the surface of the silicon body.

[0003] Since these multi-gate transistors utilize a three-dimensional channel, they are easy to scale. In addition, current control capability can be improved without increasing the gate length of the multi-gate transistor. Furthermore, the short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage, can be effectively suppressed. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a semiconductor device with improved quality and performance.

[0005] Another technical problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor device capable of manufacturing a semiconductor device with improved quality and performance.

[0006] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A semiconductor device according to some embodiments for achieving the above technical problem comprises a substrate, a first active pattern extending in a first direction on the substrate, a first gate structure extending in a second direction intersecting the first direction on the first active pattern, a second gate structure extending in a second direction spaced apart from the first gate structure in the first direction on the first active pattern, a first epitaxial pattern connected to the first active pattern between the first gate structure and the second gate structure, an insulating pattern covering at least a portion of the upper surface of the first epitaxial pattern, and a dummy contact spaced apart from the first epitaxial pattern by the insulating pattern on the upper surface of the insulating pattern.

[0008] A semiconductor device according to some embodiments for achieving the above technical problem comprises a substrate, an active pattern on the substrate, a gate structure intersecting the active pattern on the substrate, a first epitaxial pattern connected to the active pattern on one side of the gate structure, an insulating pattern covering at least a portion of the upper surface of the first epitaxial pattern, an interlayer insulating film covering the first epitaxial pattern and the insulating pattern on the side of the gate structure, and a dummy contact on the upper surface of the insulating pattern penetrating the interlayer insulating film and contacting the insulating pattern, wherein the insulating pattern and the interlayer insulating film comprise different insulating materials.

[0009] A semiconductor device according to some embodiments for achieving the above technical problem comprises a substrate including a first surface and a second surface opposite to each other, an active pattern including a plurality of bridge patterns stacked spaced apart from each other on the first surface, a gate structure penetrated by the plurality of bridge patterns on the active pattern, a first epitaxial pattern connected to the plurality of bridge patterns on one side of the gate structure, a second epitaxial pattern connected to the plurality of bridge patterns on the other side of the gate structure, an insulating pattern covering at least a portion of the upper surface of the first epitaxial pattern, a dummy contact spaced apart from the first epitaxial pattern by the insulating pattern on the upper surface of the insulating pattern, a source / drain contact connected to the second epitaxial pattern on the upper surface of the second epitaxial pattern, a front wiring structure electrically connected to the source / drain contact on the dummy contact and the source / drain contact, and a rear wiring structure on the second surface.

[0010] A method for manufacturing a semiconductor device according to some embodiments for achieving the above other technical objectives comprises forming an active pattern extending in a first direction on a substrate, forming a first gate structure and a second gate structure respectively extending in a second direction that is spaced apart from each other in the first direction and intersects the first direction on the active pattern, forming an epitaxial pattern connected to the active pattern between the first gate structure and the second gate structure, forming an insulating pattern covering at least a portion of the upper surface of the epitaxial pattern, and forming a dummy contact on the upper surface of the insulating pattern that is spaced apart from the epitaxial pattern by the insulating pattern.

[0011] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0012] FIG. 1 is an exemplary circuit diagram for explaining a semiconductor device according to some embodiments. FIG. 2 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. Figure 3 is a cross-sectional view taken along AA of Figure 2. Figure 4 is a cross-sectional view taken along BB of Figure 2. Figure 5 is a cross-sectional view taken along CC of Figure 2. Figure 6 is a cross-sectional view taken along DD of Figure 2. FIGS. 7 to 10 are various exemplary cross-sectional views for illustrating semiconductor devices according to some embodiments. FIG. 11 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 12 is an exemplary circuit diagram for explaining a semiconductor device according to some embodiments. FIG. 13 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 14 is a cross-sectional view taken along EE of FIG. 13. FIG. 15 is a cross-sectional view taken along the FF of FIG. 13. FIG. 16 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIGS. 17 to 28 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. FIGS. 29 and FIGS. 30 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. Specific details for implementing the invention

[0013] In this specification, "identical" means not only completely identical but also includes minute differences that may occur due to process margins, etc.

[0014] In this specification, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used to facilitate the description of the relationship between one element or component and another element or component as illustrated in the drawings. Spatially relative terms should be understood as terms that include different orientations of the element during use or operation in addition to the orientations illustrated in the drawings. For example, if the element illustrated in the drawings is flipped, the element described as "below" or "beneath" of another element may be placed "above" of the other element. Accordingly, the exemplary term "below" may include both the lower and upper directions. The element may also be oriented in other directions, and accordingly, spatially relative terms may be interpreted according to the orientation.

[0015] Although terms such as "first," "second," etc., are used to describe various elements or components, it goes without saying that these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Therefore, it goes without saying that the first element or component mentioned below may also be the second element or component within the technical scope of the present invention.

[0016] Hereinafter, a semiconductor device according to exemplary embodiments is described with reference to FIGS. 1 to 16. The embodiments disclosed with respect to FIGS. 1 to 11 are described primarily as an inverter as a semiconductor device, and the embodiments disclosed with respect to FIGS. 12 to 16 are described primarily as a NAND gate as a semiconductor device, but these are merely exemplary. A person skilled in the art to which the present invention pertains will understand that the technical concept of the present invention can be applied to various other logic devices such as AND gates, OR gates, NOR gates, XOR gates, or various other semiconductor devices such as SRAM (static random access memory) devices.

[0017] FIG. 1 is an exemplary circuit diagram for illustrating a semiconductor device according to some embodiments. FIG. 2 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 3 is a cross-sectional view taken along AA of FIG. 2. FIG. 4 is a cross-sectional view taken along BB of FIG. 2. FIG. 5 is a cross-sectional view taken along CC of FIG. 2. FIG. 6 is a cross-sectional view taken along DD of FIG. 2.

[0018] Referring to FIG. 1, a semiconductor device according to some embodiments may be provided as an inverter circuit.

[0019] For example, a semiconductor device according to some embodiments has a first power node (V SS ) and the second power node (V DD It may include a first transistor (TR11) and a second transistor (TR12) connected in series between ). The first transistor (TR11) may be an NFET, and the second transistor (TR12) may be a PFET. The source of the first transistor (TR11) is a first power node (V SS It can be connected to ), and the source of the second transistor (TR12) is the second power node (VDD It can be connected to the inverter's input signal (V in ) can be input to the gate of the first transistor (TR11) and the gate of the second transistor (TR12). The output signal of the inverter (V out ) can be output from a node where the drain of the first transistor (TR11) and the drain of the second transistor (TR12) are connected.

[0020] Referring to FIGS. 1 through 6, a semiconductor device according to some embodiments comprises a substrate (102), first and second active patterns (AP1, AP2), first and second gate structures (GS1, GS2), first and second source / drain regions (SD1, SD2), a first interlayer insulating film (180), an insulating pattern (170), a second interlayer insulating film (185), a first source / drain contact (FC1), first and second dummy contacts (DC1, DC2), a third interlayer insulating film (190), a front wiring structure (FW), first to fourth rear source / drain contacts (BC1~BC4) and a rear wiring structure (BW).

[0021] The substrate (102) may be bulk silicon or SOI (silicon-on-insulator). Alternatively, the substrate (102) may be a silicon substrate, or may include other materials, for example, silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate (102) may be a base substrate on which an epitaxial layer is formed.

[0022] In some embodiments, the substrate (102) may be an insulating substrate comprising an insulating material. For example, the substrate (102) may comprise at least one of silicon oxide, silicon oxynitride, silicon carbonitride, or a combination thereof, but is not limited thereto. For example, the substrate (102) may comprise a silicon oxide film.

[0023] The substrate (102) may include a first surface (102a) and a second surface (102b) that are opposite to each other. In the following description, the first surface (102a) of the substrate (102) may also be referred to as the front side of the substrate (102), and the second surface (102b) of the substrate (102) may also be referred to as the back side of the substrate (102).

[0024] The first and second active patterns (AP1, AP2) may be formed on the first surface (102a) of the substrate (102). The first and second active patterns (AP1, AP2) may each be extended in a first direction (X) parallel to the upper surface of the substrate (102). The first and second active patterns (AP1, AP2) may be spaced apart from each other in a second direction (Y) that is parallel to the upper surface of the substrate (102) and intersects the first direction (X).

[0025] The first and second active patterns (AP1, AP2) may each include silicon (Si) or germanium (Ge), which are elemental semiconductor materials. Alternatively, the first and second active patterns (AP1, AP2) may each include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be, for example, a binary compound, a ternary compound containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound in which a group IV element is doped. The group III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of the group III elements aluminum (Al), gallium (Ga), and indium (In) with at least one of the group V elements phosphorus (P), arsenic (As), and antimonium (Sb).

[0026] In some embodiments, the first and second active patterns (AP1, AP2) may be provided as channel regions of different conductivity types. In the following description, the first active pattern (AP1) is exemplified as being a channel region of an NFET and the second active pattern (AP2) is exemplified as being a channel region of a PFET. However, this is merely illustrative, and it is obvious that the first active pattern (AP1) may be a channel region of a PFET and the second active pattern (AP2) may be a channel region of an NFET.

[0027] In some embodiments, each of the first and second active patterns (AP1, AP2) may include a plurality of bridge patterns (111 to 113). The plurality of bridge patterns (111 to 113) may be spaced apart from each other in a third direction (Z) intersecting the upper surface of the substrate (102) (e.g., the first surface (102a)) and may be stacked in sequence. The bridge patterns (111 to 113) include an MBCFET comprising a multi-bridge channel. ® It can be used as a channel area. The number of bridge patterns (111–113) included in each of the first and second active patterns (AP1, AP2) is merely exemplary and is not limited to what is illustrated.

[0028] In some embodiments, each of the first and second active patterns (AP1, AP2) may further include a pin pattern (110) between the substrate (102) and the bridge patterns (111–113). The pin pattern (110) may protrude from the upper surface of the substrate (102) and extend in a first direction (X). The bridge patterns (111–113) may be spaced apart from the pin pattern (110) in a third direction (Z).

[0029] The first active pattern (AP1) can be provided as the channel region of the first transistor (TR11) of FIG. 1. The second active pattern (AP2) can be provided as the channel region of the second transistor (TR12) of FIG. 1.

[0030] The first and second gate structures (GS1, GS2) may be formed on the first and second active patterns (AP1, AP2). The first and second gate structures (GS1, GS2) may each be extended in the second direction (Y). The first and second gate structures (GS1, GS2) may be spaced apart from each other in the first direction (X). Each of the first and second gate structures (GS1, GS2) may intersect with the first active pattern (AP1) and the second active pattern (AP2). For example, each of the bridge patterns (111–113) may extend in the first direction (X) and penetrate the first and second gate structures (GS1, GS2).

[0031] Each of the first and second gate structures (GS1, GS2) may include a gate dielectric film (120), a gate electrode (130), a gate spacer (140), and a gate capping film (150).

[0032] A gate dielectric film (120) may be interposed between each of the first and second active patterns (AP1, AP2) and the gate electrode (130). The gate dielectric film (120) may comprise at least one of a dielectric material, for example, silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. The high dielectric constant material is, for example, hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), lanthanum aluminum oxide (LaAlO3), yttrium oxide (Y2O3), hafnium oxynitride (HfO2). x N y ), zirconium oxynitride (ZrO x N y ), lanthanum oxynitride (La2O x N y ), aluminum oxynitride (Al2O x N y ), titanium oxynitride (TiO₂ x Ny ), strontium titanium oxynitride (SrTiO2) x N y ), Lanthanum aluminum oxynitride (LaAlO x N y ), yttrium oxynitride (Y2O x It may include at least one of Ny) and combinations thereof, but is not limited thereto.

[0033] In some embodiments, the gate dielectric film (120) may include an interface film (121) and a high dielectric film (122) that are sequentially stacked on the first and second active patterns (AP1, AP2).

[0034] The interface film (121) may surround the perimeter of each bridge pattern (111–113). For example, the interface film (121) may extend conformally along the perimeter of each bridge pattern (111–113). The interface film (121) may also extend along the surface of the pin pattern (110). In some embodiments, the interface film (121) may include an oxide film formed by oxidizing the surface of each bridge pattern (111–113) and / or the pin pattern (110). For example, when the bridge patterns (111–113) are each silicon (Si) patterns, the interface film (121) may include a silicon oxide film.

[0035] A high dielectric film (122) may be formed on an interface film (121). The high dielectric film (122) may surround the perimeter of the interface film (121). In some embodiments, a portion of the high dielectric film (122) may be interposed between the gate electrode (130) and the gate spacer (140). For example, the high dielectric film (122) may extend conformally along the perimeter of the interface film (121) and the profile of the inner surface of the gate spacer (140). Additionally, the high dielectric film (122) may extend further along the first surface (102a) of the substrate (102). The high dielectric film (122) may comprise the high dielectric constant material having a dielectric constant greater than that of silicon oxide.

[0036] The gate electrode (130) can be extended in the second direction (Y) to intersect with the first active pattern (AP1) and the second active pattern (AP2). Each of the bridge patterns (111 to 113) can be extended in the second direction (Y) to penetrate the gate electrode (130). The gate electrode (130) may include at least one of a conductive material, for example, TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, Al, and combinations thereof, but is not limited thereto. The gate electrode (130) may be formed by a replacement process, but is not limited thereto.

[0037] Although the gate electrode (130) is illustrated as being a single film, this is merely exemplary, and it is obvious that it may be a multi-film formed by stacking multiple conductive films. For example, the gate electrode (130) may include a work function controlling film that controls the work function and a filling conductive film that fills the space formed by the work function controlling film. The work function controlling film may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. The filling conductive film may include, for example, W or Al.

[0038] The gate spacer (140) may extend along the side of the gate electrode (130). Each bridge pattern (111–113) may extend in a second direction (Y) and penetrate the gate spacer (140). The gate spacer (140) may comprise at least one insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonate, and combinations thereof, but is not limited thereto.

[0039] The gate capping film (150) may extend along the upper surface of the gate electrode (130). The gate capping film (150) may comprise at least one insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonate, and combinations thereof, but is not limited thereto.

[0040] In some embodiments, each of the first and second gate structures (GS1, GS2) may further include an internal spacer (145). The internal spacer (145) may be formed on the side of the gate electrode (130) between the bridge patterns (111 to 113). The internal spacer (145) may also be formed on the side of the gate electrode (130) between the pin pattern (110) and the bridge patterns (111 to 113). The internal spacer (145) may include at least one insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonide, and combinations thereof, but is not limited thereto.

[0041] The gate electrode (130) of the first gate structure (GS1) can be provided as the gate of the first transistor (TR11) of FIG. 1 and the gate of the second transistor (TR12) of FIG. 1.

[0042] First source / drain regions (SD1) may be formed within a first active pattern (AP1) on the side of the first and second gate structures (GS1, GS2). Bridge patterns (111–113) of the first active pattern (AP1) may be connected to the first source / drain regions (SD1) by penetrating the gate electrode (130) and the gate spacer (140). The first source / drain regions (SD1) may be separated from the gate electrode (130) by a gate dielectric film (120), a gate spacer (140), and / or an internal spacer (145).

[0043] The second source / drain regions (SD2) may be formed within the second active pattern (AP2) on the side of the first and second gate structures (GS1, GS2). Bridge patterns (111–113) of the second active pattern (AP2) may be connected to the second source / drain regions (SD2) by penetrating the gate electrode (130) and the gate spacer (140). The second source / drain regions (SD2) may be separated from the gate electrode (130) by the gate dielectric film (120), the gate spacer (140), and / or the internal spacer (145).

[0044] In some embodiments, the first and second source / drain regions (SD1, SD2) may each comprise an epitaxial layer doped with impurities. For example, the first source / drain regions (SD1) may comprise an epitaxial pattern grown from a first active pattern (AP1) by an epitaxial growth method. For example, the second source / drain regions (SD2) may comprise an epitaxial pattern grown from a second active pattern (AP2) by an epitaxial growth method.

[0045] When the first active pattern (AP1) is the channel region of the NFET, the first source / drain regions (SD1) may contain N-type impurities (e.g., P, Sb, or As) or impurities to prevent the diffusion of N-type impurities.

[0046] When the second active pattern (AP2) is the channel region of the PFET, the second source / drain regions (SD2) may contain P-type impurities (e.g., B, In, Ga, or Al) or impurities to prevent the diffusion of P-type impurities.

[0047] The first interlayer insulating film (180) may be formed on the first and second gate structures (GS1, GS2) and the first and second source / drain regions (SD1, SD2). The first interlayer insulating film (180) may fill the space on the outer surface of the first and second gate structures (GS1, GS2). The first interlayer insulating film (180) may cover the first and second source / drain regions (SD1, SD2).

[0048] The first interlayer insulating film (180) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbide, and a low dielectric constant material having a dielectric constant smaller than that of silicon oxide, but is not limited thereto. The above low dielectric constant material may include, for example, at least one of FOX (Flowable Oxide), TOSZ (Torene SilaZene), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped Silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material, or a combination thereof, but is not limited thereto.

[0049] An insulating pattern (170) may be formed within the first interlayer insulating film (180). The insulating pattern (170) may be formed on the first source / drain regions (SD1) and / or the second source / drain regions (SD2). The insulating pattern (170) may cover at least a portion of the upper surface of the first source / drain regions (SD1) and / or at least a portion of the upper surface of the second source / drain regions (SD2). For example, as shown in FIG. 3, the first source / drain regions (SD1) may include a first epitaxial pattern (161) between the first gate structure (GS1) and the second gate structure (GS2). The insulating pattern (170) may cover at least a portion of the upper surface of the first epitaxial pattern (161).

[0050] The insulating pattern (170) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbide, and combinations thereof, but is not limited thereto. The insulating pattern (170) may include an insulating material different from the first interlayer insulating film (180). The first interlayer insulating film (180) and the insulating pattern (170) may have different etching selectivity ratios. For example, when the first interlayer insulating film (180) includes a silicon oxide film, the insulating pattern (170) may include a silicon nitride film.

[0051] In some embodiments, the width of the insulating pattern (170) may decrease toward the first surface (102a) of the substrate (102). This may be due to the characteristics of the etching process performed on the first interlayer insulating film (180) to form the insulating pattern (170).

[0052] In some embodiments, the upper surface of the insulating pattern (170) may be lower than the upper surface of the gate electrode (130). For example, with respect to the first surface (102a) of the substrate (102), the height of the upper surface of the insulating pattern (170) may be formed lower than the height of the upper surface of the gate electrode (130). Accordingly, the lower surface of the first dummy contact (DC1) may be formed lower than the upper surface of the gate electrode (130).

[0053] The second interlayer insulating film (185) may be formed within the first interlayer insulating film (180). The second interlayer insulating film (185) may be formed on the insulating pattern (170). The second interlayer insulating film (185) may cover the upper surface of the insulating pattern (170). For example, the second interlayer insulating film (185) may fill the space on the upper surface of the insulating pattern (170).

[0054] The second interlayer insulating film (185) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbide, and the low dielectric constant material having a dielectric constant smaller than that of silicon oxide, but is not limited thereto. The second interlayer insulating film (185) may include an insulating material different from that of the insulating pattern (170). The insulating pattern (170) and the second interlayer insulating film (185) may have different etching selectivity ratios. For example, if the insulating pattern (170) includes a silicon nitride film, the second interlayer insulating film (185) may include a silicon oxide film. The second interlayer insulating film (185) may include the same insulating material as the first interlayer insulating film (180), or it may include an insulating material different from that of the first interlayer insulating film (180).

[0055] Only the existence of a boundary between the first interlayer insulating film (180) and the second interlayer insulating film (185) is illustrated, but this is merely illustrative. In some cases, the boundary between the first interlayer insulating film (180) and the second interlayer insulating film (185) may not exist.

[0056] A first dummy contact (DC1) may be interposed between a first gate structure (GS1) and a second gate structure (GS2). The first dummy contact (DC1) may be formed on an insulating pattern (170). The insulating pattern (170) may be interposed between at least some of the first source / drain regions (SD1) and the first dummy contact (DC1). For example, as shown in FIG. 3, the first dummy contact (DC1) may penetrate the second interlayer insulating film (185) and come into contact with the upper surface of the insulating pattern (170). Accordingly, the first dummy contact (DC1) may be separated from the first epitaxial pattern (161) by the insulating pattern (170) and may be electrically isolated from the first epitaxial pattern (161).

[0057] In some embodiments, the first dummy contact (DC1) may overlap the insulation pattern (170) entirely in the third direction (Z). For example, as shown in FIG. 3, the width (W1a) of the insulation pattern (170) in the first direction (X) may be greater than or equal to the width (W2a) of the first dummy contact (DC1) in the first direction (X). Or, for example, as shown in FIG. 6, the width (W1b) of the insulation pattern (170) in the second direction (Y) may be greater than or equal to the width (W2b) of the first dummy contact (DC1) in the second direction (Y).

[0058] A first dummy contact (DC1) may be placed on one side of a second gate structure (GS2), and a second dummy contact (DC2) may be placed on the other side of a second gate structure (GS2). That is, the second gate structure (GS2) may be interposed between the first dummy contact (DC1) and the second dummy contact (DC2). The second dummy contact (DC2) may be formed on an insulating pattern (170). The insulating pattern (170) may be interposed between the second source / drain regions (SD2) and the second dummy contact (DC2). Since the second dummy contact (DC2) may be similar to the first dummy contact (DC1) except that it is placed on the second source / drain regions (SD2), a detailed description is omitted below.

[0059] A first source / drain contact (FC1) may be disposed on one side of a first gate structure (GS1), and a first dummy contact (DC1) may be disposed on the other side of the first gate structure (GS1). That is, the first gate structure (GS1) may be interposed between the first source / drain contact (FC1) and the first dummy contact (DC1). The first source / drain contact (FC1) may be formed on at least some of the first source / drain regions (SD1). The first source / drain contact (FC1) may be connected to at least some of the first source / drain regions (SD1). For example, as shown in FIG. 3, the first source / drain regions (SD1) may include a second epitaxial pattern (162) on one side of the first gate structure (GS1). The first gate structure (GS1) may intersect with the first active pattern (AP1) between the first epitaxial pattern (161) and the second epitaxial pattern (162). The first source / drain contact (FC1) may penetrate the first interlayer insulating film (180) and contact the upper surface of the second epitaxial pattern (162). Accordingly, the first source / drain contact (FC1) may be electrically connected to the second epitaxial pattern (162).

[0060] The first source / drain contact (FC1) can connect the first source / drain regions (SD1) and the second source / drain regions (SD2). For example, the first source / drain contact (FC1) can be extended in the second direction (Y) to contact both the first source / drain regions (SD1) and the second source / drain regions (SD2).

[0061] In some embodiments, as shown in FIG. 2, the width (Wa) of the first source / drain contact (FC1) in the first direction (X) and the width (Wb) of the first dummy contact (DC1) in the first direction (X) may be the same.

[0062] In some embodiments, as illustrated in FIG. 3, the upper surface of the first source / drain contact (FC1) and the upper surface of the first dummy contact (DC1) may be placed in a co-plane. Although only the upper surface of the first source / drain contact (FC1) and the upper surface of the first dummy contact (DC1) are shown to be placed in a co-plane with the upper surface of the first interlayer insulating film (180) and / or the upper surface of the gate capping film (150), this is merely exemplary. In some embodiments, unlike illustrated, the upper surface of the first source / drain contact (FC1) and the upper surface of the first dummy contact (DC1) may be formed higher than the upper surface of the first interlayer insulating film (180) and / or the upper surface of the gate capping film (150).

[0063] The first dummy contact (DC1), the second dummy contact (DC2), and the first source / drain contact (FC1) are each shown as having a single film, but this is merely exemplary. For example, the first dummy contact (DC1), the second dummy contact (DC2), and the first source / drain contact (FC1) may each include a barrier conductive film and a filling conductive film that fills the space formed by the barrier conductive film. The barrier conductive film may include at least one of a metal or metal nitride to prevent the diffusion of a metal element contained in the filling conductive film, such as titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), alloys thereof, and nitrides thereof, but is not limited thereto. The above-mentioned filling conductive film may include at least one of a metal, for example, aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru) and alloys thereof, but is not limited thereto.

[0064] The first dummy contact (DC1), the second dummy contact (DC2), and the first source / drain contact (FC1) may be formed at the same level. In this specification, "same level" means formed by the same manufacturing process. For example, the first dummy contact (DC1), the second dummy contact (DC2), and the first source / drain contact (FC1) may have the same material composition.

[0065] The third interlayer insulating film (190) may be formed on the first interlayer insulating film (180), the second interlayer insulating film (185), the first dummy contact (DC1), the second dummy contact (DC2), and the first source / drain contact (FC1). The third interlayer insulating film (190) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbide, and the low dielectric constant material having a dielectric constant smaller than that of silicon oxide, but is not limited thereto.

[0066] A front wiring structure (FW) may be formed on a third interlayer insulating film (190). The front wiring structure (FW) may include a front interlayer insulating film (200) and front wiring patterns (211, 212) within the front interlayer insulating film (200). The shape, number, arrangement, and number of layers of the front interlayer insulating film (200) and the front wiring patterns (211, 212) are merely exemplary and are not limited to those illustrated. Although not specifically illustrated, the front wiring patterns (211, 212) may each include a barrier conductive film and a filling conductive film.

[0067] In some embodiments, the front wiring patterns (211, 212) may each include a first front wiring pattern (211) and a second front wiring pattern (212) that extend in a first direction (X). The first front wiring pattern (211) and the second front wiring pattern (212) may be spaced apart from each other in a second direction (Y).

[0068] The first front wiring pattern (211) can be connected to the first gate structure (GS1). For example, as shown in FIG. 4, a first gate contact (CB1) can be formed that penetrates the third interlayer insulating film (190) and the gate capping film (150) and contacts the gate electrode (130) of the first gate structure (GS1). The first front wiring pattern (211) can be electrically connected to the first gate structure (GS1) through the first gate contact (CB1).

[0069] The first front wiring pattern (211) is the input signal (V) of the inverter. in It can be connected to ). For example, the region of the first gate structure (GS1) intersecting the first active pattern (AP1) can be provided as the gate of the first transistor (TR11) of FIG. 1, and the region of the first gate structure (GS1) intersecting the second active pattern (AP2) can be provided as the gate of the second transistor (TR12) of FIG. 1.

[0070] The second front wiring pattern (212) can be connected to the first source / drain contact (FC1). For example, as shown in FIG. 5, a first via pattern (VA1) can be formed to connect the first source / drain contact (FC1) and the second front wiring pattern (212) by penetrating the third interlayer insulating film (190). The second front wiring pattern (212) can be electrically connected to the first source / drain contact (FC1) through the first via pattern (VA1).

[0071] The second front wiring pattern (212) is the output signal (V) of the inverter. out It can be connected to ). For example, the first source / drain contact (FC1) can be provided as the drain of the first transistor (TR11) of FIG. 1 and the drain of the second transistor (TR12) of FIG. 1.

[0072] In some embodiments, the front wiring structure (FW) may not be electrically connected to the first dummy contact (DC1) and / or the second dummy contact (DC2). For example, the first dummy contact (DC1) and / or the second dummy contact (DC2) may each be electrically floating.

[0073] The first to fourth rear source / drain contacts (BC1 to BC4) may each be formed below the first source / drain regions (SD1) and / or the second source / drain regions (SD2). The first to fourth rear source / drain contacts (BC1 to BC4) may each be connected to the first source / drain regions (SD1) and / or the second source / drain regions (SD2).

[0074] For example, as illustrated in FIG. 3, the first rear source / drain contact (BC1) can penetrate the substrate (102) and contact the lower surface of the first epitaxial pattern (161). Accordingly, the first rear source / drain contact (BC1) can be electrically connected to the first epitaxial pattern (161). In some embodiments, the first rear source / drain contact (BC1) can overlap with the first dummy contact (DC1) in a third direction (Z).

[0075] For example, as illustrated in FIG. 3, the first source / drain regions (SD1) may include a third epitaxial pattern (163) on the other side of the second gate structure (GS2). The second gate structure (GS2) may intersect with a first active pattern (AP1) between the first epitaxial pattern (161) and the third epitaxial pattern (163). A third rear source / drain contact (BC3) may penetrate the substrate (102) and contact the lower surface of the third epitaxial pattern (163). Accordingly, the third rear source / drain contact (BC3) may be electrically connected to the third epitaxial pattern (163).

[0076] Except for being connected to the second source / drain regions (SD2), the second rear source / drain contact (BC2) and the fourth rear source / drain contact (BC4) may be similar to the first rear source / drain contact (BC1) and the third rear source / drain contact (BC3), respectively, so a detailed description is omitted below.

[0077] A rear wiring structure (BW) may be formed on a second surface (102b) of a substrate (102). The rear wiring structure (BW) may include a rear wiring inter-insulating film (300) and rear wiring patterns (311, 312) within the rear wiring inter-insulating film (300). The shape, number, arrangement, and number of layers of the rear wiring inter-insulating film (300) and the rear wiring patterns (311, 312) are merely exemplary and are not limited to those illustrated. Although not specifically illustrated, the rear wiring patterns (311, 312) may each include a barrier conductive film and a filling conductive film.

[0078] In some embodiments, the rear wiring patterns (311, 312) may each include a first rear wiring pattern (311) and a second rear wiring pattern (312) that extend in a first direction (X). The first rear wiring pattern (311) and the second rear wiring pattern (312) may be spaced apart from each other in a second direction (Y).

[0079] The first rear wiring pattern (311) may be connected to the first source / drain regions (SD1) through the first rear source / drain contact (BC1) and / or the third rear source / drain contact (BC3). For example, the first rear wiring pattern (311) may be electrically connected to the first epitaxial pattern (161) through the first rear source / drain contact (BC1). For example, the first rear wiring pattern (311) may be electrically connected to the third epitaxial pattern (163) through the third rear source / drain contact (BC3).

[0080] The first rear wiring pattern (311) is the first power node (V SS It can be connected to ). For example, the first rear source / drain contact (BC1) can be provided as the source of the first transistor (TR11) of FIG. 1.

[0081] The second rear wiring pattern (312) may be connected to the second source / drain regions (SD2) through the second rear source / drain contact (BC2) and / or the fourth rear source / drain contact (BC4). Except for being connected to the second rear source / drain contact (BC2) and / or the fourth rear source / drain contact (BC4), the second rear wiring pattern (312) may be similar to the first rear wiring pattern (311), so a detailed description is omitted below.

[0082] The second rear wiring pattern (312) is the second power node (V DD It can be connected to ). For example, the second rear source / drain contact (BC2) can be provided as the source of the second transistor (TR12) of FIG. 1.

[0083] Depending on the design of the semiconductor device, a source / drain region that is not connected to a wiring structure may be provided. For example, as described above using FIGS. 1 to 6, in the case of a first epitaxial pattern (161) interposed between a first gate structure (GS1) and a second gate structure (GS2), it may not be electrically connected to another node through a front wiring structure (FW) as a so-called shared source / drain. Accordingly, a dummy source / drain contact connected to the shared source / drain may be omitted at least partially, which may contribute to reducing the parasitic capacitance of the semiconductor device. However, the indiscriminate omission of the dummy source / drain contact may cause defects or flaws caused by non-uniformity of pattern density. Furthermore, these defects or flaws are further exacerbated in semiconductor devices including BackSide Power Delivery Networks (BSPDNs) with a high omission rate of the aforementioned dummy source / drain contacts.

[0084] In contrast, a semiconductor device according to some embodiments may use an insulating pattern (170) to prevent defects or flaws caused by non-uniformity of the pattern density. For example, as described above, a first dummy contact (DC1) may be separated from the first epitaxial pattern (161) by the insulating pattern (170) even though it exists on the first epitaxial pattern (161) provided as the shared source / drain. Accordingly, the pattern density by the first source / drain contact (FC1) and the first dummy contact (DC1) is maintained, while parasitic capacitance increase by the first dummy contact (DC1) can be effectively prevented. Through this, a semiconductor device with improved quality and performance can be provided.

[0085] FIGS. 7 to 10 are various exemplary cross-sectional views for illustrating semiconductor devices according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 6 are briefly described or omitted.

[0086] Referring to FIG. 7, in a semiconductor device according to some embodiments, the upper surface of the insulating pattern (170) includes an upwardly concave surface (170U).

[0087] The first dummy contact (DC1) can penetrate the second interlayer insulating film (185) and come into contact with the concave surface (170U) of the insulating pattern (170). In some embodiments, the second interlayer insulating film (185) can come into contact with the concave surface (170U) of the insulating pattern (170). This may be due to the characteristics of the recess process for forming the insulating pattern (170).

[0088] Referring to FIG. 8, in a semiconductor device according to some embodiments, the lower surface of the first dummy contact (DC1) is lower than the upper surface of the insulation pattern (170).

[0089] For example, with respect to the first surface (102a) of the substrate (102), the height of the lower surface of the first dummy contact (DC1) may be formed lower than the height of the upper surface of the insulating pattern (170). Alternatively, for example, the lower portion of the first dummy contact (DC1) may be embedded within the insulating pattern (170). This may be due to the characteristics of the etching process performed on the insulating pattern (170) to form the first dummy contact (DC1).

[0090] Referring to FIG. 9, in a semiconductor device according to some embodiments, the upper surface of the insulating pattern (170) is higher than the upper surface of the gate electrode (130).

[0091] For example, with respect to the first surface (102a) of the substrate (102), the height of the upper surface of the insulating pattern (170) can be formed higher than the height of the upper surface of the gate electrode (130). Accordingly, the lower surface of the first dummy contact (DC1) can be formed higher than the upper surface of the gate electrode (130). In this case, the parasitic capacitance between the first dummy contact (DC1) and the gate electrode (130) can be further reduced.

[0092] Referring to FIG. 10, in a semiconductor device according to some embodiments, a portion of the insulating pattern (170) is interposed between the first interlayer insulating film (180) and the first dummy contact (DC1).

[0093] For example, the insulating pattern (170) may extend along the upper surface of the first epitaxial pattern (161) and the side of the first interlayer insulating film (180). In some embodiments, the side of the first dummy contact (DC1) may be in contact with the insulating pattern (170). In some embodiments, unlike illustrated, a second interlayer insulating film (185) may be interposed between the side of the first dummy contact (DC1) and the insulating pattern (170).

[0094] FIG. 11 is an exemplary layout diagram for explaining a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 10 are briefly described or omitted.

[0095] Referring to FIG. 11, a semiconductor device according to some embodiments further includes a third dummy contact (DC3) and a fourth dummy contact (DC4).

[0096] A first dummy contact (DC1) may be placed on one side of a second gate structure (GS2), and a third dummy contact (DC3) may be placed on the other side of a second gate structure (GS2). The third dummy contact (DC3) and the second dummy contact (DC2) may be arranged along a second direction (Y). The third dummy contact (DC3) may be spaced apart from the first source / drain regions (SD1) by an insulating pattern (170). In some embodiments, the third dummy contact (DC3) may overlap with the third rear source / drain contact (BC3) in the third direction (Z). Except for the placement of the third dummy contact (DC3), the third dummy contact (DC3) may be similar to the first dummy contact (DC1), so a detailed description is omitted below.

[0097] A fourth dummy contact (DC4) may be placed on one side of the second gate structure (GS2), and a second dummy contact (DC2) may be placed on the other side of the second gate structure (GS2). The first dummy contact (DC1) and the fourth dummy contact (DC4) may be arranged along the second direction (Y). The fourth dummy contact (DC4) may be spaced apart from the second source / drain regions (SD2) by an insulating pattern (170). In some embodiments, the fourth dummy contact (DC4) may overlap with the second back source / drain contact (BC2) in the third direction (Z). Except for the placement of the fourth dummy contact (DC4), the fourth dummy contact (DC4) may be similar to the first dummy contact (DC1), so a detailed description is omitted below.

[0098] FIG. 12 is an exemplary circuit diagram for explaining a semiconductor device according to some embodiments. FIG. 13 is an exemplary layout diagram for explaining a semiconductor device according to some embodiments. FIG. 14 is a cross-sectional view taken along EE in FIG. 13. FIG. 15 is a cross-sectional view taken along FF in FIG. 13. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 11 are briefly explained or omitted.

[0099] Referring to FIG. 12, a semiconductor device according to some embodiments may be provided as a NAND gate circuit.

[0100] For example, a semiconductor device according to some embodiments has a first power node (V SS ) and the second power node (V DD It may include a third transistor (TR21), a fourth transistor (TR22), a fifth transistor (TR23), and a sixth transistor (TR24) connected between ). The third transistor (TR21) and the fourth transistor (TR22) may be NFETs, and the fifth transistor (TR23) and the sixth transistor (TR24) may be PFETs. The third transistor (TR21) and the fourth transistor (TR22) are connected to the first power node (V SS ) and the output signal of the NAND gate (V out ) can be connected in series between. The fifth transistor (TR23) and the sixth transistor (TR24) are connected to the second power node (V DD ) and the output signal of the NAND gate (V out It can be connected in parallel between ).

[0101] The source of the third transistor (TR21) is the first power node (V SS It can be connected to ). The source of the 5th transistor (TR23) and the source of the 6th transistor (TR24) can be connected to the 2nd power node (V DD It can be connected to ). The first input signal (V) of the NAND gate. in1) can be input to the gate of the third transistor (TR21) and the gate of the fifth transistor (TR23). The second input signal (V) of the NAND gate in2 ) can be input to the gate of the fourth transistor (TR22) and the gate of the sixth transistor (TR24). The output signal (V) of the NAND gate out ) can be output from the node where the drain of the fourth transistor (TR22), the drain of the fifth transistor (TR23), and the drain of the sixth transistor (TR24) are connected.

[0102] Referring to FIGS. 12 to 14, a semiconductor device according to some embodiments comprises a substrate (102), first and second active patterns (AP1, AP2), first and second gate structures (GS1, GS2), first and second source / drain regions (SD1, SD2), a first interlayer insulating film (180), an insulating pattern (170), a second interlayer insulating film (185), first and second source / drain contacts (FC1, FC2), a first dummy contact (DC1), a third interlayer insulating film (190), a front wiring structure (FW), second and third back source / drain contacts (BC2, BC3) and a back wiring structure (BW).

[0103] The first active pattern (AP1) may be provided as the channel region of the third transistor (TR21) of FIG. 12 and the channel region of the fourth transistor (TR22) of FIG. 12. The second active pattern (AP2) may be provided as the channel region of the fifth transistor (TR23) of FIG. 12 and the channel region of the sixth transistor (TR24) of FIG. 12.

[0104] The gate electrode (130) of the first gate structure (GS1) can be provided as the gate of the fourth transistor (TR22) of FIG. 12 and the gate of the sixth transistor (TR24) of FIG. 12. The gate electrode (130) of the second gate structure (GS2) can be provided as the gate of the third transistor (TR21) of FIG. 12 and the gate of the fifth transistor (TR23) of FIG. 12.

[0105] A first dummy contact (DC1) may be disposed on one side of a second gate structure (GS2), and a second source / drain contact (FC2) may be disposed on the other side of a second gate structure (GS2). That is, the second gate structure (GS2) may be interposed between the first dummy contact (DC1) and the second source / drain contact (FC2). The second source / drain contact (FC2) may be formed on the second source / drain regions (SD2). The second source / drain contact (FC2) may be connected to the second source / drain regions (SD2). Except for being connected to the second source / drain regions (SD2), the second source / drain contact (FC2) may be similar to the first source / drain contact (FC1), so a detailed description is omitted below.

[0106] In some embodiments, the front wiring patterns (211, 212, 213) may each include a first front wiring pattern (211), a second front wiring pattern (212), and a third front wiring pattern (213) that extend in a first direction (X). The first front wiring pattern (211), the second front wiring pattern (212), and the third front wiring pattern (213) may be spaced apart from each other in a second direction (Y).

[0107] The third front wiring pattern (213) can be connected to the second gate structure (GS2). For example, a second gate contact (CB2) can be formed that penetrates the third interlayer insulating film (190) and the gate capping film (150) and contacts the gate electrode (130) of the second gate structure (GS2). The third front wiring pattern (213) can be electrically connected to the second gate structure (GS2) through the second gate contact (CB2).

[0108] The third front wiring pattern (213) is the first input signal (V) of the NAND gate. in1 It can be connected to ). For example, the area of ​​the second gate structure (GS2) intersecting the first active pattern (AP1) can be provided as the gate of the third transistor (TR21) of FIG. 12, and the area of ​​the second gate structure (GS2) intersecting the second active pattern (AP2) can be provided as the gate of the fifth transistor (TR23) of FIG. 12.

[0109] The first front wiring pattern (211) can be connected to the first gate structure (GS1). For example, a first gate contact (CB1) can be formed that penetrates the third interlayer insulating film (190) and the gate capping film (150) and contacts the gate electrode (130) of the first gate structure (GS1). The first front wiring pattern (211) can be electrically connected to the first gate structure (GS1) through the first gate contact (CB1).

[0110] The first front wiring pattern (211) is the second input signal (V) of the NAND gate. in2 It can be connected to ). For example, the area of ​​the first gate structure (GS1) intersecting the first active pattern (AP1) can be provided as the gate of the fourth transistor (TR22) of FIG. 12, and the area of ​​the first gate structure (GS1) intersecting the second active pattern (AP2) can be provided as the gate of the sixth transistor (TR24) of FIG. 12.

[0111] The second front wiring pattern (212) can be connected to the first source / drain contact (FC1) and the second source / drain contact (FC2). For example, a first via pattern (VA1) connecting the first source / drain contact (FC1) and the second front wiring pattern (212) can be formed by penetrating the third interlayer insulating film (190). Additionally, for example, a second via pattern (VA2) connecting the second source / drain contact (FC2) and the second front wiring pattern (212) can be formed by penetrating the third interlayer insulating film (190). The second front wiring pattern (212) can electrically connect the first source / drain contact (FC1) and the second source / drain contact (FC2) through the first via pattern (VA1) and the second via pattern (VA2).

[0112] The second front wiring pattern (212) is the output signal (V) of the NAND gate. out It can be connected to ). For example, the first source / drain contact (FC1) can be provided as the drain of the fourth transistor (TR22) of FIG. 12 and the drain of the sixth transistor (TR24) of FIG. 12. Also, for example, the second source / drain contact (FC2) can be provided as the drain of the fifth transistor (TR23) of FIG. 12.

[0113] The first rear wiring pattern (311) can be connected to the first source / drain regions (SD1) through the third rear source / drain contact (BC3). For example, the first rear wiring pattern (311) can be electrically connected to the third epitaxial pattern (163) through the third rear source / drain contact (BC3).

[0114] The first rear wiring pattern (311) is the first power node (V SS It can be connected to ). For example, the third rear source / drain contact (BC3) can be provided as the source of the third transistor (TR21) of FIG. 12.

[0115] The second rear wiring pattern (312) can be connected to the second source / drain regions (SD2) through the second rear source / drain contact (BC2). Except for being connected to the second rear source / drain contact (BC2), the second rear wiring pattern (312) may be similar to the first rear wiring pattern (311), so a detailed description is omitted below.

[0116] The second rear wiring pattern (312) is the second power node (V DD It can be connected to ). For example, the second rear source / drain contact (BC2) can be provided as the source of the fifth transistor (TR23) of FIG. 12 and the source of the sixth transistor (TR24) of FIG. 12.

[0117] FIG. 16 is an exemplary layout diagram for explaining a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 15 are briefly described or omitted.

[0118] Referring to FIG. 16, a semiconductor device according to some embodiments further includes a third dummy contact (DC3) and a fourth dummy contact (DC4).

[0119] A first dummy contact (DC1) may be placed on one side of a second gate structure (GS2), and a third dummy contact (DC3) may be placed on the other side of a second gate structure (GS2). The third dummy contact (DC3) and the second source / drain contact (FC2) may be arranged along a second direction (Y). The third dummy contact (DC3) may be spaced apart from the first source / drain regions (SD1) by an insulating pattern (170). In some embodiments, the third dummy contact (DC3) may overlap with the third rear source / drain contact (BC3) in the third direction (Z). Except for the placement of the third dummy contact (DC3), the third dummy contact (DC3) may be similar to the first dummy contact (DC1), so a detailed description is omitted below.

[0120] A fourth dummy contact (DC4) may be placed on one side of the second gate structure (GS2), and a second source / drain contact (FC2) may be placed on the other side of the second gate structure (GS2). The first dummy contact (DC1) and the fourth dummy contact (DC4) may be arranged along the second direction (Y). The fourth dummy contact (DC4) may be spaced apart from the second source / drain regions (SD2) by an insulating pattern (170). In some embodiments, the fourth dummy contact (DC4) may overlap with the second rear source / drain contact (BC2) in the third direction (Z). Except for the placement of the fourth dummy contact (DC4), the fourth dummy contact (DC4) may be similar to the first dummy contact (DC1), so a detailed description is omitted below.

[0121] Hereinafter, a method for manufacturing a semiconductor device according to exemplary embodiments is described with reference to FIGS. 1 to 30.

[0122] FIGS. 17 to 28 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 16 are briefly explained or omitted.

[0123] Referring to FIG. 17, first and second active patterns (AP1, AP2), first and second gate structures (GS1, GS2), first and second source / drain regions (SD1, SD2), and a first interlayer insulating film (180) are formed on a base substrate (100). In the following description, the first active pattern (AP1) and the first source / drain regions (SD1) are described primarily, but those skilled in the art will understand that the second active pattern (AP2) and the second source / drain regions (SD2) may be similar.

[0124] The first and second active patterns (AP1, AP2) can each be extended in the first direction (X). The first and second active patterns (AP1, AP2) can be spaced apart from each other in the second direction (Y).

[0125] The first and second gate structures (GS1, GS2) may each be extended in the second direction (Y). The first and second gate structures (GS1, GS2) may be spaced apart from each other in the first direction (X). Each of the first and second gate structures (GS1, GS2) may intersect with the first active pattern (AP1) and the second active pattern (AP2).

[0126] The first source / drain regions (SD1) may be formed within a first active pattern (AP1) on the side of the first and second gate structures (GS1, GS2). The second source / drain regions (SD2) may be formed within a second active pattern (AP2) on the side of the first and second gate structures (GS1, GS2).

[0127] The first interlayer insulating film (180) can fill the space on the outer surface of the first and second gate structures (GS1, GS2). The first interlayer insulating film (180) can cover the first and second source / drain regions (SD1, SD2).

[0128] Referring to FIG. 18, a preliminary hole (H1) is formed within the first interlayer insulating film (180).

[0129] The preliminary hole (H1) may overlap with at least a portion of the first source / drain regions (SD1) in the third direction (Z). In some embodiments, the preliminary hole (H1) may expose at least a portion of the upper surface of the first source / drain regions (SD1). In some embodiments, unlike illustrated, the preliminary hole (H1) may not expose the first source / drain regions (SD1).

[0130] Referring to FIG. 19, a preliminary insulating film (170L) is formed within the preliminary hole (H1).

[0131] The preliminary insulating film (170L) may fill at least a portion of the preliminary hole (H1). The preliminary insulating film (170L) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbide, and combinations thereof, but is not limited thereto. The preliminary insulating film (170L) may include an insulating material different from that of the first interlayer insulating film (180). The first interlayer insulating film (180) and the preliminary insulating film (170L) may have different etching selectivity ratios. For example, if the first interlayer insulating film (180) includes a silicon oxide film, the preliminary insulating film (170L) may include a silicon nitride film.

[0132] Referring to FIG. 20, a recess process is performed on the preliminary insulating film (170L).

[0133] As the above recess process is performed, an insulating pattern (170) that fills a portion of the preliminary hole (H1) may be formed. In some embodiments, the upper surface of the insulating pattern (170) may be formed lower than the upper surface of the gate electrode (130). In some embodiments, unlike what is illustrated, the upper surface of the insulating pattern (170) may be formed higher than the upper surface of the gate electrode (130).

[0134] Referring to FIG. 21, a second interlayer insulating film (185) is formed on the insulating pattern (170).

[0135] The second interlayer insulating film (185) can fill the area of ​​the remaining reserve hole (H1) after the insulating pattern (170) is filled. The second interlayer insulating film (185) may include the same insulating material as the first interlayer insulating film (180), or it may include an insulating material different from the first interlayer insulating film (180).

[0136] Referring to FIG. 22, a source / drain contact hole (H2a) and a dummy contact hole (H2b) are formed.

[0137] Source / drain contact holes (H2a) and dummy contact holes (H2b) can be formed simultaneously by the same etching process. In the etching process, an insulating pattern (170) can be provided as an etch stop layer. Accordingly, the source / drain contact holes (H2a) can penetrate the first interlayer insulating film (180) to expose at least a portion of the first source / drain regions (SD1). Additionally, the dummy contact holes (H2b) can penetrate the second interlayer insulating film (185) to expose at least a portion of the upper surface of the insulating pattern (170).

[0138] In some embodiments, the width of the source / drain contact hole (H2a) in the first direction (X) and the width of the dummy contact hole (H2b) in the first direction (X) may be the same.

[0139] Referring to FIG. 23, a first source / drain contact (FC1) and a first dummy contact (DC1) are formed.

[0140] The first source / drain contact (FC1) can fill the source / drain contact hole (H2a). Through this, the first source / drain contact (FC1) connected to the first source / drain regions (SD1) can be formed.

[0141] The first dummy contact (DC1) can fill the dummy contact hole (H2b). By doing so, the first dummy contact (DC1) can be formed, which is spaced apart from the first source / drain regions (SD1) by the insulation pattern (170).

[0142] The first source / drain contact (FC1) and the first dummy contact (DC1) can be formed simultaneously by the same deposition process. Accordingly, the first source / drain contact (FC1) and the first dummy contact (DC1) can have the same material configuration.

[0143] Referring to FIG. 24, a third interlayer insulating film (190) and a front wiring structure (FW) are formed.

[0144] The third interlayer insulating film (190) can cover the first interlayer insulating film (180), the second interlayer insulating film (185), the first source / drain contact (FC1), and the first dummy contact (DC1). A front wiring structure (FW) can be formed on the third interlayer insulating film (190).

[0145] Referring to FIG. 25, a front wiring structure (FW) is attached to a carrier substrate (400).

[0146] For example, a carrier substrate (400) may be attached to the result of FIG. 24. After the carrier substrate (400) is attached, the result of FIG. 24 may be inverted.

[0147] Referring to FIG. 26, a thinning process is performed on the base substrate (100).

[0148] The above thinning process may include, for example, a back grinding process on the back surface of the base substrate (100), but is not limited thereto.

[0149] Referring to FIG. 27, a substrate (102) is formed.

[0150] For example, a substrate (102) including an insulating material that replaces the area where the base substrate (100) has been removed may be formed.

[0151] Referring to FIG. 28, first to fourth rear source / drain contacts (BC1 to BC4) are formed.

[0152] The first to fourth rear source / drain contacts (BC1 to BC4) can each penetrate the substrate (102) and be connected to the first source / drain regions (SD1) and / or the second source / drain regions (SD2).

[0153] Next, referring to FIG. 3, a rear wiring structure (BW) is formed on the second surface (102b) of the substrate (102). Through this, the semiconductor device described above can be manufactured using FIG. 1 to FIG. 6.

[0154] FIGS. 29 and FIGS. 30 are intermediate step drawings for explaining a method for manufacturing a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 28 are briefly explained or omitted. For reference, FIG. 29 is an intermediate step drawing for explaining steps after FIG. 18.

[0155] Referring to FIG. 29, a preliminary insulating film (170L) and a second interlayer insulating film (185) are formed within the preliminary hole (H1).

[0156] The preliminary insulating layer (170L) can be conformally extended along the profile of the preliminary hole (H1). A second interlayer insulating layer (185) can be formed on the preliminary insulating layer (170L). The second interlayer insulating layer (185) can fill the area of ​​the preliminary hole (H1) remaining after the preliminary insulating layer (170L) is filled.

[0157] Referring to FIG. 30, a planarization process is performed on the preliminary insulating film (170L) and the second interlayer insulating film (185).

[0158] The planarization process may include, for example, a Chemical Mechanical Polishing (CMP) process, but is not limited thereto. As the planarization process is performed, an insulating pattern (170) and a second interlayer insulating film (185) that fills the preliminary hole (H1) may be formed.

[0159] Next, the steps described above can be performed using FIGS. 22 to 28 and FIG. 3. Through this, the semiconductor device described above can be manufactured using FIG. 10.

[0160] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0161] 102: Substrate 102a: 1st side 102b: 2nd side 110: Pin pattern 111~113: Bridge Patterns 120: Gate dielectric 121: Interface 122: High-grade membrane 130: Gate electrode 140: Gate Spacer 145: Internal spacer 150: Gate capping membrane 161: First Epitaxial Pattern 162: Second Epitaxial Pattern 163: Third Epitaxial Pattern 170: Insulation pattern 180: First interlayer insulating film 185: Second interlayer insulating film 190: Third interlayer insulating film 200: Insulation film between front wiring 211: 1st Front Wiring Pattern 212: Second front wiring pattern 300: Insulation film between rear wiring 311: 1st rear wiring pattern 312: Second rear wiring pattern AP1: First active pattern AP2: Second active pattern BC1: 1st rear source / drain contact BC2: Second rear source / drain contact BC3: Third rear source / drain contact BC4: 4th rear source / drain contact DC1: 1st Dummy Contact DC2: The Second Dummy Contact FC1: 1st Source / Drain Contact FC2: Second Source / Drain Contact GS1: First gate structure GS2: Second Gate Structure SD1: 1st Source / Drain Area SD2: Second Source / Drain Area

Claims

Claim 1 A semiconductor device comprising: a substrate; a first active pattern extending in a first direction on the substrate; a first gate structure extending in a second direction intersecting the first direction on the first active pattern; a second gate structure extending in the second direction and spaced apart from the first gate structure in the first direction on the first active pattern; a first epitaxial pattern connected to the first active pattern between the first gate structure and the second gate structure; an insulating pattern covering at least a portion of the upper surface of the first epitaxial pattern; and a dummy contact spaced apart from the first epitaxial pattern by the insulating pattern on the upper surface of the insulating pattern. Claim 2 A semiconductor device according to claim 1, wherein, in the first direction, the width of the insulating pattern is greater than or equal to the width of the dummy contact. Claim 3 A semiconductor device according to claim 1, wherein in the second direction, the width of the insulating pattern is greater than or equal to the width of the dummy contact. Claim 4 A semiconductor device according to claim 1, further comprising a rear source / drain contact on the lower surface of the first epitaxial pattern that penetrates the substrate and is connected to the first epitaxial pattern. Claim 5 A semiconductor device according to claim 1, wherein the first gate structure is interposed between the first epitaxial pattern and the second epitaxial pattern connected to the first active pattern; and further comprising a source / drain contact connected to the second epitaxial pattern on the upper surface of the second epitaxial pattern. Claim 6 A semiconductor device according to claim 1, wherein the second gate structure is interposed between the first epitaxial pattern and the second epitaxial pattern and the second epitaxial pattern is connected to the first active pattern; and further comprising a rear source / drain contact on the lower surface of the second epitaxial pattern that penetrates the substrate and is connected to the second epitaxial pattern. Claim 7 A semiconductor device according to claim 1, further comprising an interlayer insulating film covering the upper surface of the insulating pattern, wherein the dummy contact penetrates the interlayer insulating film and contacts the insulating pattern, and the insulating pattern and the interlayer insulating film comprise different insulating materials. Claim 8 A semiconductor device according to claim 1, wherein the first active pattern comprises a plurality of bridge patterns spaced apart from each other in a third direction intersecting the upper surface of the substrate. Claim 9 A semiconductor device comprising: a substrate; an active pattern on the substrate; a gate structure on the substrate intersecting the active pattern; a first epitaxial pattern connected to the active pattern on one side of the gate structure; an insulating pattern covering at least a portion of the upper surface of the first epitaxial pattern; an interlayer insulating film covering the first epitaxial pattern and the insulating pattern on a side of the gate structure; and a dummy contact on the upper surface of the insulating pattern penetrating the interlayer insulating film and contacting the insulating pattern, wherein the insulating pattern and the interlayer insulating film comprise different insulating materials. Claim 10 A semiconductor device comprising: a substrate including a first surface and a second surface opposite to each other; an active pattern including a plurality of bridge patterns stacked spaced apart from each other on the first surface; a gate structure penetrated by the plurality of bridge patterns on the active pattern; a first epitaxial pattern connected to the plurality of bridge patterns on one side of the gate structure; a second epitaxial pattern connected to the plurality of bridge patterns on the other side of the gate structure; an insulating pattern covering at least a portion of the upper surface of the first epitaxial pattern; a dummy contact spaced apart from the first epitaxial pattern by the insulating pattern on the upper surface of the insulating pattern; a source / drain contact connected to the second epitaxial pattern on the upper surface of the second epitaxial pattern; a front wiring structure electrically connected to the source / drain contact on the dummy contact and the source / drain contact; and a rear wiring structure on the second surface.

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