Semiconductor Package

Abstract

The technical concept of the present invention provides a semiconductor package comprising: a rewiring structure; a semiconductor substrate located on the rewiring structure and including an active surface and an inactive surface opposite thereto; a wiring structure located on the active surface of the semiconductor substrate; and a plurality of dummy pads; a first end in contact with the plurality of dummy pads of the semiconductor chip, and a second end opposite to the first end, spaced apart from the semiconductor chip and the rewiring structure; wherein the plurality of dummy pads of the semiconductor chip further include a side dummy pad located on the side of the semiconductor substrate, and the plurality of dummy wires include a side dummy wire in which the first end contacts the side dummy pad of the semiconductor chip.

Description

Technology Field

[0001] The technical concept of the present invention relates to a semiconductor package, specifically to a semiconductor package including a wire. Background Technology

[0002] As the storage capacity of semiconductor chips increases, there is a demand for semiconductor packages containing these chips to become thinner and lighter. Furthermore, there is a growing trend of research aimed at incorporating semiconductor chips with various functions within the package and driving them at high speeds. In line with this trend, the need for miniaturization and multifunctionality of semiconductor chips used in electronic components is increasing. Additionally, in the packaging field, research is actively underway on methods to dissipate heat from within the semiconductor package while miniaturizing the size based on small semiconductor chips. The problem to be solved

[0003] The technical problem that the technical concept of the present invention aims to solve is to provide a semiconductor package that efficiently dissipates heat generated from a semiconductor chip to the outside.

[0004] However, the problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] To solve the above problem, the technical concept of the present invention provides a semiconductor package comprising: a rewiring structure; a semiconductor substrate located on the rewiring structure and including an active surface and an inactive surface opposite thereto; a wiring structure located on the active surface of the semiconductor substrate; and a plurality of dummy pads; a first end in contact with the plurality of dummy pads of the semiconductor chip, and a second end opposite to the first end, spaced apart from the semiconductor chip and the rewiring structure; wherein the plurality of dummy pads of the semiconductor chip further include a side dummy pad located on the side of the semiconductor substrate, and the plurality of dummy wires include a side dummy wire in which the first end contacts the side dummy pad of the semiconductor chip.

[0006] To solve the above problem, the technical concept of the present invention is a lower redistribution structure;

[0007] A semiconductor package is provided comprising: a lower semiconductor substrate having an active surface and an inactive surface opposite thereto, located on the lower redistribution structure; a lower wiring structure located on the active surface of the lower semiconductor substrate; and a plurality of lower dummy pads; a plurality of lower dummy wires, the first end of which is in contact with the plurality of lower dummy pads of the lower semiconductor chip, and the second end opposite to the first end of which is spaced apart from the lower redistribution structure and the lower semiconductor chip; a lower molding layer located on the lower redistribution structure and in contact with the lower semiconductor chip and the plurality of lower dummy wires; a plurality of lower through-vias located on the lower redistribution structure and extending from the lower surface to the upper surface of the molding layer; and an upper redistribution structure located on the lower molding layer and electrically connected to the plurality of lower through-vias.

[0008] To solve the above problem, the technical concept of the present invention comprises: a lower redistribution structure; a lower semiconductor substrate located on the lower redistribution structure and including an active surface and an inactive surface opposite thereto, a lower wiring structure located on the active surface of the lower semiconductor substrate, and a lower semiconductor chip including a plurality of lower dummy pads; a plurality of lower dummy wires, the first end of which contacts the plurality of lower dummy pads of the lower semiconductor chip, and the second end opposite to the first end of which is spaced apart from the lower redistribution structure and the lower semiconductor chip; a lower molding layer located on the lower redistribution structure and contacting the lower semiconductor chip and the plurality of lower dummy wires; a plurality of lower through-vias located on the lower redistribution structure and extending from the lower surface to the upper surface of the molding layer; an upper redistribution structure located on the lower molding layer and electrically connected to the plurality of lower through-vias; an upper semiconductor chip located on the upper redistribution structure and including an active surface and an inactive surface opposite thereto, an upper wiring structure located on the active surface of the upper semiconductor substrate, and a plurality of upper dummy pads. A semiconductor package is provided comprising: a first stage in contact with the plurality of upper dummy pads, and a second stage opposite to the first stage, a plurality of upper dummy wires spaced apart from the upper rewiring structure and the upper semiconductor chip. Effects of the invention

[0009] In the technical concept of the present invention, a semiconductor package provides a heat path for releasing heat generated in a semiconductor chip to the outside of the semiconductor chip, thereby enabling efficient release of heat generated in the semiconductor chip to the outside of the semiconductor package. Brief explanation of the drawing

[0010] FIG. 1 is a plan view schematically showing a semiconductor package according to exemplary embodiments. FIG. 2 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments. FIG. 3 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments. FIG. 4 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments. FIG. 5 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments. FIG. 6 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments. FIG. 7 is a plan view schematically showing a semiconductor package according to exemplary embodiments. FIG. 8 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments. FIG. 9 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments. FIG. 10 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments. FIG. 11 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments. FIGS. 12a to 12j are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. Specific details for implementing the invention

[0011] Exemplary embodiments of the present invention are provided to more fully explain the invention to those skilled in the art to which the concept of the invention pertains, and the following embodiments may be modified in various different forms, and the scope of the invention is not limited to the following embodiments. Rather, these embodiments are provided to make the disclosure more faithful and complete and to fully convey the spirit of the invention to those skilled in the art.

[0012] Additionally, expressions such as upper, upper, lower, lower, up and down, front and back, left, right, etc. in this specification describe the relative positions between each component based on the respective drawings, and may be expressed differently or omitted if the direction of the object changes.

[0013] FIG. 1 is a plan view schematically illustrating a semiconductor package (1000) according to exemplary embodiments. FIG. 2 is a cross-sectional view schematically illustrating a semiconductor package (1000) according to exemplary embodiments. FIG. 3 is a cross-sectional view schematically illustrating a semiconductor package (1000) according to exemplary embodiments. Specifically, FIG. 1 shows a lower molding layer (ML) transparently to disclose a plurality of lower dummy wires (DW).

[0014] Referring to FIGS. 1 to 3, the semiconductor package (1000) may include a lower rewiring structure (100), a lower semiconductor chip (200), a lower molding layer (ML), and a plurality of lower dummy wires (DW).

[0015] In the present specification, the lower redistribution structure (100) is referred to as the redistribution structure, the lower semiconductor chip (200) is referred to as the semiconductor chip, the lower molding layer (ML) is referred to as the molding layer, and the plurality of lower dummy wires (DW) may be referred to as the plurality of dummy wires.

[0016] In this specification, unless specifically defined otherwise, a direction parallel to the upper surface of the lower redistribution structure (100) is defined as the first horizontal direction (X direction), a direction perpendicular to the upper surface of the lower redistribution structure (100) is defined as the vertical direction (Z direction), and a direction perpendicular to the first horizontal direction (X direction) and the vertical direction (Z direction) is defined as the second horizontal direction (Y direction). A horizontal direction is defined as a combined direction of the first horizontal direction (Y direction) and the second horizontal direction (X direction).

[0017] The lower redistribution structure (100) may be a redistribution layer (RDL) that extends the input / output terminals of the lower semiconductor chip (200) to an outer region of the lower semiconductor chip (200). However, it is not limited thereto, and the lower redistribution structure (100) may be a printed circuit board (PCB) or an interposer.

[0018] The lower redistribution structure (100) may include a lower redistribution pattern (110) including lower redistribution vias (112) and lower redistribution lines (111), and lower redistribution insulating layers (120) surrounding the lower redistribution pattern (110).

[0019] The number and arrangement of the lower redistribution insulating layers (120), lower redistribution vias (112), and lower redistribution lines (111) forming the lower redistribution structure (100) are not limited to those shown in the drawings and may be varied in the embodiments.

[0020] The lower redistribution insulating layers (120) may be made of an insulating material, for example, a photoimaginable dielectric (PID) resin. In this case, the lower redistribution insulating layers (120) may further include an inorganic filler. The lower redistribution insulating layers (120) may be made of the same or different materials.

[0021] A lower redistribution pattern (110) including lower redistribution vias (112) and lower redistribution lines (111) can serve to extend the input / output terminals of a lower semiconductor chip (200) to the outside. The lower redistribution line (111) is disposed on at least one of the upper and lower surfaces of the lower redistribution insulating layers (120) and can extend in a horizontal direction. The lower redistribution vias (112) penetrate the lower redistribution insulating layers (120) and extend in a vertical direction (Z direction), and can be connected to the lower redistribution line (111).

[0022] The lower redistribution via (112) may be completely filled with a conductive material, or the conductive material may have a shape formed along the wall of the via. The lower redistribution pattern (110) may include a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

[0023] The lower redistribution structure (100) may include an external connection pad (CP1). The external connection pad (CP1) is located on the lower surface of the lower redistribution structure (100) and may be exposed to the outside. The external connection pad (CP1) may be electrically connected to the lower redistribution pattern (110) of the lower redistribution structure (100).

[0024] External connection terminals (CT1) may be attached to an external connection pad (CP1) of a lower redistribution structure (100). The external connection terminals (CT1) may connect the semiconductor package (1000) to a main board of a separate electronic device on which the semiconductor package (1000) is mounted. The external connection terminals (CT1) may include at least one of a conductive material, such as solder, tin (Sn), silver (Ag), copper (Cu), and aluminum (Al). The shape of the external connection terminals (CT1) may be changed to various shapes, such as land, bump, pillar, or pin, in addition to a ball shape.

[0025] The lower semiconductor chip (200) may include a lower semiconductor substrate (210), a lower wiring structure (220), and a plurality of lower dummy pads (DP).

[0026] The lower semiconductor substrate (210) may include an active surface (210_A) and an inactive surface opposite thereto. The lower semiconductor chip (200) may be placed on the lower redistribution structure (100) such that the active surface (210_A) of the lower semiconductor substrate (210) faces the lower redistribution structure (100). For example, the lower semiconductor chip (200) may be placed on the lower redistribution structure (100) in a face-down manner.

[0027] The lower semiconductor substrate (210) may include a semiconductor material such as silicon (Si) or germanium (Ge), for example. Alternatively, the lower semiconductor substrate (210) may include a compound semiconductor material such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). The lower semiconductor substrate (210) may include an impurity-doped well which is a conductive region. The lower semiconductor substrate (210) may have various device isolation structures such as a shallow trench isolation (STI) structure.

[0028] Various types of individual devices may be formed on the active surface (210_A) of the lower semiconductor substrate (210). The plurality of individual devices may be electrically connected to the lower wiring pattern (221) of the lower wiring structure (220). Additionally, each of the plurality of individual devices may be electrically separated from neighboring individual devices by an insulating film.

[0029] In some embodiments, the lower semiconductor chip (200) may include a logic element. For example, the lower semiconductor chip (200) may be a central processing unit chip, a graphics processing unit chip, or an application processor (AP). In other embodiments, when the semiconductor package (1000) includes a plurality of lower semiconductor chips (200), one of the plurality of lower semiconductor chips (200) may be a central processing unit chip, a graphics processing unit chip, or an application processor chip, and the other may be a memory semiconductor chip including a memory element.

[0030] For example, the memory device may be a non-volatile memory device such as Flash Memory, PRAM (Phase-change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory). In some embodiments, the memory device may be a volatile memory device such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory).

[0031] The lower wiring structure (220) may be located on the active surface (210_A) of the lower semiconductor substrate (210). For example, the lower wiring structure (220) may be a back end of line (BEOL) structure. The inactive surface of the lower semiconductor substrate (210) may be referred to as the back-side of the lower semiconductor chip (200), and the surface of the upper and lower surfaces of the lower wiring structure (220) that is spaced apart from the active surface (210_A) of the lower semiconductor substrate (210) may be referred to as the front-side of the lower semiconductor chip (200).

[0032] The lower wiring structure (220) may include a lower wiring pattern (221) and a lower wiring insulation layer (222) surrounding the lower wiring pattern (221). The lower wiring pattern (221) may include lower wiring lines (221_L) extending in a horizontal direction and lower wiring vias (221_V) extending in a vertical direction (Z direction) from the lower wiring lines (221_L). The lower wiring pattern (221) may be electrically connected to a plurality of individual elements of the lower semiconductor substrate (210).

[0033] In some embodiments, the lower wiring structure (220) may have a multilayer wiring structure including lower wiring lines (221_L) and lower wiring vias (221_V) located at different vertical levels. In this specification, a vertical level may refer to a distance from the lower surface of the lower wiring structure (100).

[0034] The lower wiring structure (220) may include a lower front pad (CP2). The lower front pad (CP2) is located on the lower surface of the lower wiring structure (220) and may be exposed to the outside. The lower front pad (CP2) may be electrically connected to the lower wiring pattern (221). For example, the lower front pad (CP2) may be located below the lowest of the lower wiring lines (221_L).

[0035] In some embodiments, lower connection terminals (CT2) may be attached to the lower front pad (CP2) of the lower wiring structure (220). Each of the lower connection terminals (CT2) may be located between the lower redistribution structure (100) and the lower front pad (CP2). The lower connection terminals (CT2) may electrically connect the lower semiconductor chip (200) and the lower redistribution structure (100).

[0036] A plurality of lower dummy pads (DP) are located on the outer surface of the lower semiconductor chip (200) and may be exposed to the outside of the lower semiconductor chip (200). A plurality of lower dummy pads (DP) may not be electrically connected to a plurality of individual elements on the active surface (210_A) of the lower semiconductor substrate (210) of the lower semiconductor chip (200). A plurality of lower dummy pads (DP) may not be electrically connected to a lower wiring pattern (221) of the lower wiring structure (220) of the lower semiconductor chip (200).

[0037] A plurality of lower dummy pads (DP) may be located on the outer surface of the lower semiconductor chip (200) adjacent to a point where a relatively large amount of heat is generated in the lower semiconductor chip (200). For example, the plurality of lower dummy pads (DP) may be pads for forming a plurality of lower dummy wires (DW). For example, the semiconductor package (1000) may form a plurality of lower dummy pads (DP) and a plurality of lower dummy wires (DW) at a location where a relatively large amount of heat is generated in the lower semiconductor chip (200), thereby efficiently discharging the heat generated in the lower semiconductor chip (200) to the outside of the semiconductor package (1000).

[0038] A plurality of lower dummy pads (DP) may include a side lower dummy pad (DP_S) located on the side of the lower semiconductor substrate (210) of the lower semiconductor chip (200). For example, the side lower dummy pad (DP_S) may be located on the side of the lower semiconductor substrate (210) and may be spaced apart from the active surface (210_A) of the lower semiconductor substrate (210).

[0039] A plurality of lower dummy wires (DW) may be attached to a lower semiconductor chip (200). For example, the first end of each of the plurality of lower dummy wires (DW) may be in contact with one of the plurality of lower dummy pads (DP) of the lower semiconductor chip (200), and the second end of each of the plurality of lower dummy wires (DW) may be spaced apart from the lower semiconductor chip (200) and the lower redistribution structure (100). The second end of the lower dummy wire (DW) may be a single end opposite to the first end of the lower dummy wire (DW).

[0040] For example, a plurality of lower dummy wires (DW) may not be electrically connected to the lower semiconductor chip (200) and the lower redistribution structure (100). In some embodiments, a plurality of lower dummy wires (DW) may be located inside the lower molding layer (ML).

[0041] For example, a plurality of lower dummy wires (DW) may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Preferably, a plurality of lower dummy wires (DW) may include copper.

[0042] The lower molding layer (ML) is located on the lower redistribution structure (100) and contacts the side of the lower semiconductor chip (200), and the lower molding layer (ML) may contact the outer surface of a plurality of lower dummy wires (DW). The lower molding layer (ML) can protect the lower semiconductor chip (200) from external impact.

[0043] For example, the upper surface of the lower molding layer (ML) may be co-surfaced with the upper surface of the lower semiconductor chip (200). For example, the upper surface of the lower semiconductor chip (200) may be exposed to the outside of the semiconductor package (1000). For example, the upper surface of the lower semiconductor chip (200) may be exposed to the outside so that heat generated from the lower semiconductor chip (200) can be efficiently released to the outside.

[0044] The lower molding layer (ML) may be composed of epoxy-based materials, thermosetting materials, thermoplastic materials, etc. For example, the lower molding layer (ML) may include ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), EMC (Epoxy Molding Compound), etc.

[0045] In some embodiments, the heat transfer coefficient of a plurality of lower dummy wires (DW) may be greater than the heat transfer coefficient of a lower molding layer (ML). For example, the plurality of lower dummy wires (DW) may have a heat transfer coefficient greater than that of the lower molding layer (ML), so that heat emitted from the lower semiconductor chip (200) can be transferred faster than that of the lower molding layer (ML).

[0046] A plurality of lower dummy wires (DW) may further include side lower dummy wires (DW_S). A first stage of the side lower dummy wire (DW_S) may be in contact with a side lower dummy pad (DP_S) of the lower semiconductor chip (200). The side lower dummy wire (DW_S) may include an exposed side lower dummy wire (DW_S1) and a buried side lower dummy wire (DW_S2).

[0047] Referring to FIG. 2, the exposed side lower dummy wire (DW_S1) may have a first end in contact with the side lower dummy pad (DP_S) of the lower semiconductor chip (200), and a second end in a co-surface with the outer surface of the lower molding layer (ML). For example, the second end of the exposed side lower dummy wire (DW_S1) may be in a co-surface with the side or top surface of the lower molding layer (ML). The second end of the exposed side lower dummy wire (DW_S1) may be exposed to the outside of the semiconductor package (1000).

[0048] The exposed side lower dummy wire (DW_S1) may be exposed to the outside of the lower molding layer (ML). The exposed side lower dummy wire (DW_S1) may provide a path to release heat to the outside of the semiconductor package (1000) that is not released from the lower semiconductor chip (200) to the outside of the semiconductor package (1000) due to the relatively low heat transfer coefficient of the lower molding layer (ML).

[0049] In some embodiments, the exposed side lower dummy wire (DW_S1) may include a first exposed side lower dummy wire (DW_S1a) and a second exposed side lower dummy wire (DW_S1b). The second end of the first exposed side lower dummy wire (DW_S1a) may be co-plane with the side of the lower molding layer (ML), and the second end of the second exposed side lower dummy wire (DW_S1b) may be co-plane with the upper surface of the lower molding layer (ML). In some embodiments, the first exposed side lower dummy wire (DW_S1a) may be extended in a parabolic shape.

[0050] For example, the first exposed side lower dummy wire (DW_S1a) may extend from the lower semiconductor chip (200) to the side of the lower molding layer (ML), and the second exposed side lower dummy wire (DW_S1b) may extend from the lower semiconductor chip (200) to the upper surface of the lower molding layer (ML).

[0051] For example, the vertical level of the second stage of the first exposed side lower dummy wire (DW_S1a) may be lower than the vertical level of the side lower dummy pad (DP_S). The vertical level of the second stage of the second exposed side lower dummy wire (DW_S1b) may be higher than the vertical level of the side lower dummy pad (DP_S).

[0052] Referring to FIG. 3, the buried side lower dummy wire (DW_S2) may have a first end in contact with the side lower dummy pad (DP_S) of the lower semiconductor chip (200), and a second end located inside the lower molding layer (ML). For example, the buried side lower dummy wire (DW_S2) may not be exposed to the outside of the semiconductor package (1000).

[0053] The buried side lower dummy wire (DW_S2) can be extended from the lower semiconductor chip (200) to a first portion of the lower molding layer (ML) that is relatively far from the lower semiconductor chip (200). The buried side lower dummy wire (DW_S2) can transfer heat generated from the lower semiconductor chip (200) to the first portion relatively quickly. Accordingly, the temperature of the lower molding layer (ML) can be raised evenly, thereby increasing the heat dissipation efficiency of the semiconductor package (1000).

[0054] FIG. 4 is a cross-sectional view schematically showing a semiconductor package (1000a) according to exemplary embodiments.

[0055] Most of the components constituting the semiconductor package (1000a) described below and the materials forming said components are substantially the same or similar as those described above in FIG. 2. Therefore, for the convenience of explanation, the explanation will focus on the differences between the semiconductor package (1000a) of FIG. 4 and the semiconductor package (1000) of FIG. 2 described above.

[0056] Referring to FIG. 4, the semiconductor package (1000a) may include a lower redistribution structure (100), a lower semiconductor chip (200), a plurality of lower dummy wires (DW), and a lower molding layer (ML).

[0057] The lower semiconductor chip (200) may include a plurality of lower dummy pads (DP). The plurality of lower dummy pads (DP) may include a side lower dummy pad (DP_S) located on the side of the lower semiconductor substrate (210) of the lower semiconductor chip (200) and a back-side lower dummy pad (DP_B) located on the inactive surface of the lower semiconductor substrate (210) of the lower semiconductor chip (200).

[0058] The lower molding layer (ML) is located on the lower redistribution structure (100) and can come into contact with the lower semiconductor chip (200) and a plurality of lower dummy wires (DW). The lower molding layer (ML) can cover the upper surface of the lower semiconductor chip (200). For example, the vertical level of the upper surface of the lower molding layer (ML) may be higher than the vertical level of the upper surface of the lower semiconductor chip (200).

[0059] Each of the plurality of lower dummy wires (DW) may have a first end in contact with one of the plurality of lower dummy pads (DP) of the lower semiconductor chip (200), and a second end spaced apart from the lower semiconductor chip (200) and the lower rewiring structure (100). The plurality of lower dummy wires (DW) may include a side lower dummy wire (DW_S) and a back-side lower dummy wire (DW_B). The side lower dummy wire (DW_S) may be substantially the same as described above with reference to FIGS. 1 to 3.

[0060] The rear lower dummy wire (DW_B) can contact the rear lower dummy pad (DP_B) of the lower semiconductor chip (200) at the first stage. The rear lower dummy wire (DW_B) may include an exposed rear lower dummy wire (DW_B1) and a buried rear lower dummy wire (DW_B2).

[0061] The exposed rear lower dummy wire (DW_B1) may have a first end in contact with the rear lower dummy pad (DP_B) of the lower semiconductor chip (200), and a second end in a co-surface with the outer surface of the lower molding layer (ML). For example, the second end of the exposed rear lower dummy wire (DW_B1) may be in a co-surface with the side or top surface of the lower molding layer (ML). The second end of the exposed rear lower dummy wire (DW_B1) may be exposed to the outside of the semiconductor package (1000).

[0062] The exposed rear lower dummy wire (DW_B1) may be exposed to the outside of the lower molding layer (ML). The exposed rear lower dummy wire (DW_B1) may provide a path to release heat to the outside of the semiconductor package (1000) that is not released from the lower semiconductor chip (200) to the outside of the semiconductor package (1000) due to the relatively low heat transfer coefficient of the lower molding layer (ML).

[0063] In some embodiments, the exposed rear lower dummy wire (DW_B1) may include a first exposed rear lower dummy wire (DW_B1a) and a second exposed rear lower dummy wire (DW_B1b). The second end of the first exposed rear lower dummy wire (DW_B1a) may be co-plane with the side of the lower molding layer (ML), and the second end of the second exposed rear lower dummy wire (DW_B1b) may be co-plane with the top surface of the lower molding layer (ML). In some embodiments, the first exposed rear lower dummy wire (DW_B1a) may be extended in a parabolic shape.

[0064] For example, the first exposed rear lower dummy wire (DW_B1a) may extend from the lower semiconductor chip (200) to the side of the lower molding layer (ML), and the second exposed rear lower dummy wire (DW_B1b) may extend from the lower semiconductor chip (200) to the upper surface of the lower molding layer (ML).

[0065] For example, the vertical level of the second stage of the first exposed rear lower dummy wire (DW_B1a) may be lower than the vertical level of the rear lower dummy pad (DP_B). The vertical level of the second stage of the second exposed rear lower dummy wire (DW_B1b) may be higher than the vertical level of the rear lower dummy pad (DP_B).

[0066] The buried rear lower dummy wire (DW_B2) may have a first end in contact with the rear lower dummy pad (DP_B) of the lower semiconductor chip (200), and a second end located inside the lower molding layer (ML). For example, the buried rear lower dummy wire (DW_B2) may not be exposed to the outside of the semiconductor package (1000).

[0067] The buried rear lower dummy wire (DW_B2) can be extended from the lower semiconductor chip (200) to a first portion of the lower molding layer (ML) that is relatively far from the lower semiconductor chip (200). The buried rear lower dummy wire (DW_B2) can transfer heat generated from the lower semiconductor chip (200) to the first portion relatively quickly. Accordingly, the temperature of the lower molding layer (ML) can be raised evenly, thereby increasing the heat dissipation efficiency of the semiconductor package (1000).

[0068] FIG. 5 is a cross-sectional view schematically showing a semiconductor package (1000b) according to exemplary embodiments.

[0069] Most of the components constituting the semiconductor package (1000b) described below and the materials forming said components are substantially the same or similar as those described above in FIG. 2. Therefore, for the convenience of explanation, the explanation will focus on the differences between the semiconductor package (1000b) of FIG. 5 and the semiconductor package (1000) of FIG. 2 described above.

[0070] Referring to FIG. 5, the semiconductor package (1000b) may include a lower redistribution structure (100b), a lower semiconductor chip (200), a plurality of lower dummy wires (DW), a plurality of lower connection wires (CW), and a lower molding layer (ML).

[0071] The lower redistribution structure (100b) may include a lower chip connection pad (CP_U) and an external connection pad (CP1). The lower chip connection pad (CP_U) may be located on the upper surface of the lower redistribution structure (100b), and the external connection pad (CP1) may be located on the lower surface of the lower redistribution structure (100b). For example, the lower redistribution structure (100b) may include internal wiring (CL) that electrically connects the lower chip connection pad (CP_U) and the external connection pad (CP1).

[0072] The lower semiconductor chip (200) may be placed on the lower redistribution structure (100b) such that the inactive surface of the lower semiconductor substrate (210) faces the lower redistribution structure (100b). For example, the lower semiconductor chip (200) may be placed on the lower redistribution structure (100b) in a face-up manner. For example, the lower semiconductor chip (200) may be placed on the lower redistribution structure (100b) such that the lower wiring structure (220) faces upward in the vertical direction (Z direction). For example, the lower semiconductor chip (200) may be placed in an area of ​​the upper surface of the lower redistribution structure (100b) that does not overlap with the lower chip connection pad (CP_U).

[0073] A plurality of lower dummy pads (DP) of the lower semiconductor chip (200) may include a side lower dummy pad (DP_S) and a front lower dummy pad (DP_F). The front lower dummy pad (DP_F) may be located on the front of the lower semiconductor chip (200). For example, the front lower dummy pad (DP_F) may be located on one side of the lower wiring structure (220) of the lower semiconductor chip (200).

[0074] A plurality of lower connection wires (CW) can electrically connect the lower semiconductor chip (200) and the lower redistribution structure (100b). For example, the first end of each of the plurality of lower connection wires (CW) may be in contact with the lower front pad (CP2) of the lower wiring structure (220) of the lower semiconductor chip (200), and the second end of each of the plurality of lower connection wires (CW) may be in contact with the lower chip connection pad (CP_U) of the lower redistribution structure (100b).

[0075] For example, a plurality of lower connecting wires (CW) may comprise copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Preferably, a plurality of lower connecting wires (CW) may comprise gold. In some embodiments, the constituent material of the plurality of lower connecting wires (CW) and the constituent material of the plurality of lower dummy wires (DW) may be different.

[0076] A plurality of lower dummy wires (DW) may include a side lower dummy wire (DW_S) and a front-side lower dummy wire (DW_F). A first end of the front-side lower dummy wire (DW_F) may contact the front-side lower dummy pad (DP_F) of the lower semiconductor chip (200). The front-side lower dummy wire (DW_F) may include an exposed front-side lower dummy wire (DW_F1) and a buried front-side lower dummy wire (DW_F2).

[0077] The exposed front lower dummy wire (DW_F1) may have a first end in contact with the front lower dummy pad (DP_F) of the lower semiconductor chip (200), and a second end in a co-surface with the outer surface of the lower molding layer (ML). For example, the second end of the exposed front lower dummy wire (DW_F1) may be in a co-surface with the side or top surface of the lower molding layer (ML). The second end of the exposed front lower dummy wire (DW_F1) may be exposed to the outside of the semiconductor package (1000).

[0078] The exposed front lower dummy wire (DW_F1) may be exposed to the outside of the lower molding layer (ML). The exposed front lower dummy wire (DW_F1) may provide a path to release heat to the outside of the semiconductor package (1000) that is not released from the lower semiconductor chip (200) to the outside of the semiconductor package (1000) due to the relatively low heat transfer coefficient of the lower molding layer (ML).

[0079] In some embodiments, the exposed front lower dummy wire (DW_F1) may include a first exposed front lower dummy wire (DW_F1a) and a second exposed front lower dummy wire (DW_F1b). The second end of the first exposed front lower dummy wire (DW_F1a) may be co-plane with the side of the lower molding layer (ML), and the second end of the second exposed front lower dummy wire (DW_F1b) may be co-plane with the top surface of the lower molding layer (ML). In some embodiments, the first exposed front lower dummy wire (DW_F1a) may be extended in a parabolic shape.

[0080] For example, the first exposed front lower dummy wire (DW_F1a) may extend from the lower semiconductor chip (200) to the side of the lower molding layer (ML), and the second exposed front lower dummy wire (DW_F1b) may extend from the lower semiconductor chip (200) to the upper surface of the lower molding layer (ML).

[0081] For example, the vertical level of the second stage of the first exposed front lower dummy wire (DW_F1a) may be lower than the vertical level of the front lower dummy pad (DP_F). The vertical level of the second stage of the second exposed front lower dummy wire (DW_F1b) may be higher than the vertical level of the front lower dummy pad (DP_F).

[0082] The buried front lower dummy wire (DW_F2) may have its first end in contact with the front lower dummy pad (DP_F) of the lower semiconductor chip (200), and its second end located inside the lower molding layer (ML). For example, the buried front lower dummy wire (DW_F2) may not be exposed to the outside of the semiconductor package (1000).

[0083] The buried front lower dummy wire (DW_F2) can be extended from the lower semiconductor chip (200) to a first portion of the lower molding layer (ML) that is relatively far from the lower semiconductor chip (200). The buried front lower dummy wire (DW_F2) can transfer heat generated from the lower semiconductor chip (200) to the first portion relatively quickly. Accordingly, the temperature of the lower molding layer (ML) can be raised evenly, thereby increasing the heat dissipation efficiency of the semiconductor package (1000).

[0084] The lower molding layer (ML) is located on the lower redistribution structure (100) and can come into contact with the lower semiconductor chip (200) and a plurality of lower dummy wires (DW). The lower molding layer (ML) can cover the upper surface of the lower semiconductor chip (200). For example, the vertical level of the upper surface of the lower molding layer (ML) may be higher than the vertical level of the upper surface of the lower semiconductor chip (200).

[0085] FIG. 6 is a cross-sectional view schematically showing a semiconductor package (1000c) according to exemplary embodiments.

[0086] Most of the components constituting the semiconductor package (1000c) described below and the materials forming said components are substantially the same or similar as those described above in FIG. 2. Therefore, for the convenience of explanation, the explanation will focus on the differences between the semiconductor package (1000c) of FIG. 6 and the semiconductor package (1000) of FIG. 2 described above.

[0087] Referring to FIG. 6, the semiconductor package (1000c) may include a lower rewiring structure (100), a lower semiconductor chip (200), a plurality of lower dummy wires (DW), and a lower molding layer (ML).

[0088] The lower semiconductor chip (200) can be mounted on the upper surface of the lower redistribution structure (100). For example, the lower wiring structure (220) of the lower semiconductor chip (200) can come into contact with the lower redistribution structure (100). For example, the lower semiconductor chip (200) can be electrically connected to the lower redistribution structure (100) without lower connection terminals (CT2, see FIG. 2).

[0089] In some embodiments, the semiconductor package (1000c) may be manufactured in a chip-first manner. For example, after mounting a lower semiconductor chip (200) on a carrier substrate such that the inactive surface of the lower semiconductor substrate (210) faces the carrier substrate, a lower redistribution structure (100) may be formed on the lower wiring structure (220) of the lower semiconductor chip (200).

[0090] In some embodiments, the lower redistribution via (112) of the lower redistribution pattern (110) of the lower redistribution structure (100) may have a horizontal width that increases as it moves away from the lower semiconductor chip (200).

[0091] FIG. 7 is a plan view schematically illustrating a semiconductor package (1000d) according to exemplary embodiments. FIG. 8 is a cross-sectional view schematically illustrating a semiconductor package (1000d) according to exemplary embodiments. Specifically, FIG. 7 transparently shows a lower molding layer (ML) and an upper redistribution structure (300) to disclose a plurality of lower dummy wires (DW).

[0092] Most of the components constituting the semiconductor package (1000d) described below and the materials forming said components are substantially the same or similar as those described above in FIG. 4. Therefore, for the convenience of explanation, the explanation will focus on the differences between the semiconductor package (1000d) of FIG. 7 and FIG. 8 and the semiconductor package (1000a) of FIG. 4 described above.

[0093] Referring to FIGS. 7 and 8, the semiconductor package (1000d) may include a lower rewiring structure (100), a lower semiconductor chip (200), a lower molding layer (ML), a plurality of lower through-vias (EV), a plurality of lower dummy wires (DW), and an upper rewiring structure (300).

[0094] A plurality of lower through-vias (EV) are located on the lower redistribution structure (100) and can penetrate the lower molding layer (ML). For example, a plurality of lower through-vias (EV) can extend from the upper surface to the lower surface of the lower molding layer (ML).

[0095] For example, a plurality of lower through-vias (EV) can electrically connect a lower redistribution structure (100) and an upper redistribution structure (300). For example, the lower surface of each of the plurality of lower through-vias (EV) may be in contact with the lower redistribution pattern (110) of the lower redistribution structure (100), and the upper surface of each of the plurality of lower through-vias (EV) may be in contact with the upper redistribution pattern (310) of the upper redistribution structure (300).

[0096] In some embodiments, a plurality of lower dummy wires (DW) may be spaced apart from a plurality of lower through-vias (EV). For example, a lower molding layer (ML) may be positioned between the plurality of lower dummy wires (DW) and the plurality of lower through-vias (EV) so that the plurality of lower dummy wires (DW) and the plurality of lower through-vias (EV) may be insulated from each other.

[0097] For example, a plurality of lower through-vias (EVs) may include a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

[0098] The upper redistribution structure (300) may be positioned on a lower molding layer (ML) and a plurality of lower through vias (EV). The upper redistribution structure (300) may include an upper redistribution pattern (310) comprising upper redistribution vias (312) and upper redistribution lines (311), and upper redistribution insulating layers (320) surrounding the upper redistribution pattern (310).

[0099] The number and arrangement of the upper redistribution insulating layers (320), upper redistribution vias (312), and upper redistribution lines (311) forming the upper redistribution structure (300) are not limited to those shown in the drawings and may be varied in the embodiments.

[0100] The upper redistribution insulating layers (320) may be made of an insulating material, for example, a photoimaginable dielectric (PID) resin. In this case, the upper redistribution insulating layers (320) may further include an inorganic filler. The upper redistribution insulating layers (320) may be made of the same or different materials.

[0101] The upper redistribution line (311) is positioned on at least one of the upper and lower surfaces of the upper redistribution insulation layers (320) and can extend in a horizontal direction. The upper redistribution via (312) penetrates the upper redistribution insulation layers (320) and extends in a vertical direction (Z direction) and can be connected to the upper redistribution line (311).

[0102] The upper redistribution via (312) may be completely filled with a conductive material, or the conductive material may have a shape formed along the wall of the via. The upper redistribution pattern (310) may include a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

[0103] For example, the width of the upper redistribution structure (300), the width of the lower molding layer (ML), and the width of the lower redistribution structure (100) may be the same. For example, the sides of the upper redistribution structure (300), the lower molding layer (ML), and the lower redistribution structure (100) may be aligned in the vertical direction (Z direction).

[0104] In some embodiments, some of the plurality of lower dummy wires (DW) may come into contact with the upper redistribution structure (300). For example, the exposed side lower dummy wire (DW_S1) and the exposed rear lower dummy wire (DW_B1) of the plurality of lower dummy wires (DW) may come into contact with the upper redistribution insulation layers (320) of the upper redistribution structure (300).

[0105] FIG. 9 is a cross-sectional view schematically showing a semiconductor package (1000e) according to exemplary embodiments.

[0106] Most of the components constituting the semiconductor package (1000e) described below and the materials forming said components are substantially the same or similar as those described in FIG. 8 above. Therefore, for the convenience of explanation, the explanation will focus on the differences between the semiconductor package (1000e) of FIG. 9 and the semiconductor package (1000d) of FIG. 8 described above.

[0107] For example, the semiconductor package (1000e) of FIG. 9 may be an exemplary embodiment in which an upper semiconductor chip (400) is mounted in a flipping manner on the semiconductor package (1000d) of FIG. 8. For example, the semiconductor package (1000e) of FIG. 9 may be a package in which the lower semiconductor chip (200) of FIG. 1, a plurality of lower dummy wires (DW), and a lower molding layer (ML) are formed on the semiconductor package (1000d) of FIG. 8.

[0108] Referring to FIG. 9, the semiconductor package (1000e) may include a lower rewiring structure (100), a lower semiconductor chip (200), a lower molding layer (ML), a plurality of lower through-vias (EV), a plurality of lower dummy wires (DW), an upper rewiring structure (300), an upper semiconductor chip (400), an upper molding layer (ML'), and a plurality of upper dummy wires (DW').

[0109] The upper semiconductor chip (400) may include an upper semiconductor substrate (410), an upper wiring structure (420), and a plurality of upper dummy pads (DP').

[0110] The upper semiconductor substrate (410) may include an active surface (210_A) and an inactive surface opposite thereto. The upper semiconductor chip (400) may be placed on the upper redistribution structure (300) such that the active surface (410_A) of the upper semiconductor substrate (410) faces the upper redistribution structure (300). For example, the upper semiconductor chip (400) may be placed on the upper redistribution structure (300) in a face-down manner.

[0111] The upper semiconductor substrate (410) may include a semiconductor material such as silicon (Si) or germanium (Ge), for example. Alternatively, the upper semiconductor substrate (410) may include a compound semiconductor material such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). The upper semiconductor substrate (410) may include an impurity-doped well which is a conductive region. The upper semiconductor substrate (410) may have various device isolation structures such as a shallow trench isolation (STI) structure.

[0112] Various types of individual devices may be formed on the active surface (410_A) of the upper semiconductor substrate (410). The plurality of individual devices may be electrically connected to the upper wiring pattern (421) of the upper wiring structure (420). Additionally, each of the plurality of individual devices may be electrically separated from neighboring individual devices by an insulating film.

[0113] In some embodiments, the upper semiconductor chip (400) may include a logic element. For example, the upper semiconductor chip (400) may be a central processing unit chip, a graphics processing unit chip, or an application processor (AP). In other embodiments, when the semiconductor package (1000) includes a plurality of upper semiconductor chips (400), one of the plurality of upper semiconductor chips (400) may be a central processing unit chip, a graphics processing unit chip, or an application processor chip, and the other may be a memory semiconductor chip including a memory element.

[0114] In some embodiments, the lower semiconductor chip (200) and the upper semiconductor chip (400) may be different types of semiconductor chips.

[0115] The upper wiring structure (420) may be located on the active surface (410_A) of the upper semiconductor substrate (410). For example, the upper wiring structure (420) may be a back end of line (BEOL) structure. The inactive surface of the upper semiconductor substrate (410) may be referred to as the back-side of the upper semiconductor chip (400), and the surface of the upper wiring structure (420) that is spaced apart from the active surface (210_A) of the upper semiconductor substrate (410) may be referred to as the front-side of the upper semiconductor chip (400).

[0116] The upper wiring structure (420) may include an upper wiring pattern (421) and a lower wiring insulation layer (422) surrounding the upper wiring pattern (421). The upper wiring pattern (421) may include upper wiring lines (421_L) extending in a horizontal direction and upper wiring vias (421_V) extending in a vertical direction (Z direction) from the upper wiring lines (421_L). The upper wiring pattern (421) may be electrically connected to a plurality of individual elements of the upper semiconductor substrate (410).

[0117] In some embodiments, the upper wiring structure (420) may have a multilayer wiring structure including upper wiring lines (421_L) and upper wiring vias (421_V) located at different vertical levels.

[0118] The upper wiring structure (420) may include an upper front pad (CP4). The upper front pad (CP4) is located on the lower surface of the upper wiring structure (420) and may be exposed to the outside. The upper front pad (CP4) may be electrically connected to the upper wiring pattern (421). For example, the upper front pad (CP4) may be located below the lowest of the upper wiring lines (421_L).

[0119] In some embodiments, upper connection terminals (CT4) may be attached to the upper front pad (CP4) of the upper wiring structure (420). Each of the upper connection terminals (CT4) may be located between the upper rewiring structure (300) and the upper front pad (CP4). The upper connection terminals (CT4) may electrically connect the upper semiconductor chip (400) and the upper rewiring structure (300).

[0120] A plurality of upper dummy pads (DP') are located on the outer surface of the upper semiconductor chip (400) and may be exposed to the outside of the upper semiconductor chip (400). A plurality of upper dummy pads (DP') may not be electrically connected to a plurality of individual elements of the active surface (410_A) of the upper semiconductor substrate (410) of the upper semiconductor chip (400). A plurality of upper dummy pads (DP') may not be electrically connected to an upper wiring pattern (421) of an upper wiring structure (420) of the upper semiconductor chip (400).

[0121] A plurality of upper dummy pads (DP') may be located on the outer surface of the upper semiconductor chip (400) adjacent to a point where heat is generated relatively high on the upper semiconductor chip (400). For example, the plurality of upper dummy pads (DP') may be pads for forming a plurality of upper dummy wires (DW').

[0122] For example, the semiconductor package (1000) can form an upper dummy pad (DP') and an upper dummy wire (DW) at a location where a relatively large amount of heat is generated in the upper semiconductor chip (400), thereby efficiently discharging the heat generated in the upper semiconductor chip (400) to the outside of the semiconductor package (1000).

[0123] A plurality of upper dummy pads (DP') may include a side upper dummy pad (DP'_S) located on the side of the upper semiconductor substrate (410) of the upper semiconductor chip (400). For example, the side upper dummy pad (DP'_S) may be located on the side of the upper semiconductor substrate (410) and may be spaced apart from the active surface (410_A) of the upper semiconductor substrate (410).

[0124] However, this is not limited thereto, and a plurality of upper dummy pads (DP') of the upper semiconductor chip (400) may be substantially identical to a plurality of lower dummy pads (DP) of the lower semiconductor chip (200) described above in FIGS. 2 to 4.

[0125] A plurality of upper dummy wires (DW') may be attached to an upper semiconductor chip (400). For example, the first end of each of the plurality of upper dummy wires (DW') may be in contact with one of the plurality of upper dummy pads (DP') of the upper semiconductor chip (400), and the second end of each of the plurality of upper dummy wires (DW') may be spaced apart from the upper semiconductor chip (400) and the upper rewiring structure (300). The second end of the upper dummy wire (DW') may be a single end opposite to the first end of the upper dummy wire (DW').

[0126] For example, a plurality of upper dummy wires (DW') may not be electrically connected to the upper semiconductor chip (400) and the upper redistribution structure (300). In some embodiments, a plurality of upper dummy wires (DW') may be located inside the upper molding layer (ML').

[0127] In some embodiments, a plurality of upper dummy wires (DW') may include side upper dummy wires (DW'_S). A first end of the side upper dummy wire (DW'_S) may be in contact with a side upper dummy pad (DP'_S) of the upper semiconductor chip (400).

[0128] However, this is not limited thereto, and a plurality of upper dummy wires (DW') may be substantially identical to the plurality of lower dummy wires (DW) described above in FIGS. 2 to 4.

[0129] For example, a plurality of upper dummy wires (DW') may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Preferably, a plurality of upper dummy wires (DW') may include copper.

[0130] The upper molding layer (ML') is located on the upper redistribution structure (300) and contacts the side of the upper semiconductor chip (400), and the upper molding layer (ML') may contact the outer surface of a plurality of upper dummy wires (DW'). The upper molding layer (ML') can protect the upper semiconductor chip (400) from external impact.

[0131] In some embodiments, the upper surface of the upper molding layer (ML') may be co-surfaced with the upper surface of the upper semiconductor chip (400). However, it is not limited thereto, and the upper molding layer (ML') may cover the upper surface of the upper semiconductor chip (400) in the same way as the lower molding layer (ML).

[0132] The upper molding layer (ML') may be made of epoxy-based materials, thermosetting materials, thermoplastic materials, etc. For example, the upper molding layer (ML') may include ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), EMC (Epoxy Molding Compound), etc.

[0133] FIG. 10 is a cross-sectional view schematically showing a semiconductor package (1000f) according to exemplary embodiments.

[0134] Most of the components constituting the semiconductor package (1000f) described below and the materials forming said components are substantially the same or similar as those described in FIG. 9 above. Therefore, for the convenience of explanation, the explanation will focus on the differences between the semiconductor package (1000f) of FIG. 10 and the semiconductor package (1000e) of FIG. 9 described above.

[0135] For example, the semiconductor package (1000f) of FIG. 10 may be an exemplary embodiment in which an upper semiconductor chip (400) is mounted on the semiconductor package (1000d) of FIG. 8 by a wire bonding method. For example, the semiconductor package (1000f) of FIG. 10 may be a package formed on the semiconductor package (1000d) of FIG. 8, the lower semiconductor chip (200) of FIG. 5, a plurality of lower connection wires (CW), a plurality of lower dummy wires (DW), and a lower molding layer (ML).

[0136] Referring to FIG. 10, a semiconductor package (1000f) may include a lower rewiring structure (100), a lower semiconductor chip (200), a lower molding layer (ML), a plurality of lower through-vias (EV), a plurality of lower dummy wires (DW), an upper rewiring structure (300), an upper semiconductor chip (400), an upper molding layer (ML'), a plurality of upper connection wires (CW'), and a plurality of upper dummy wires (DW').

[0137] The upper semiconductor chip (400) can be placed on the upper redistribution structure (300) such that the inactive surface of the upper semiconductor substrate (410) faces the upper redistribution structure (300). For example, the upper semiconductor chip (400) can be placed on the upper redistribution structure (300) in a face-up manner. For example, the upper semiconductor chip (400) can be placed on the upper redistribution structure (300) such that the lower wiring structure (220) faces upward in the vertical direction (Z direction).

[0138] For example, the upper redistribution structure (300) may further include an upper chip connection pad (CP3) that is located on the upper surface of the upper redistribution structure (300) and exposed to the outside. For example, the side and bottom surfaces of the upper chip connection pad (CP3) may be covered by upper redistribution insulating layers (320). For example, the upper chip connection pad (CP3) may be electrically connected to the upper redistribution pattern (310). For example, the upper chip connection pad (CP3) may not overlap with the upper semiconductor chip (400) in a vertical direction (Z direction).

[0139] A plurality of upper dummy pads (DP') of the upper semiconductor chip (400) may include a side lower dummy pad (DP'_S) and a front lower dummy pad (DP'_F). The front lower dummy pad (DP'_F) may be located on the front of the upper semiconductor chip (400). For example, the front lower dummy pad (DP'_F) may be located on one side of the upper wiring structure (420) of the upper semiconductor chip (400).

[0140] A plurality of upper connection wires (CW') can electrically connect an upper semiconductor chip (400) and a lower redistribution structure (100b). For example, the first end of each of the plurality of upper connection wires (CW') may be in contact with the lower front pad (CP2) of the upper wiring structure (420) of the upper semiconductor chip (400), and the second end of each of the plurality of upper connection wires (CW') may be in contact with the upper chip connection pad (CP3) of the lower redistribution structure (100b).

[0141] For example, a plurality of upper connecting wires (CW') may comprise copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Preferably, a plurality of upper connecting wires (CW') may comprise gold. In some embodiments, the constituent material of the plurality of upper connecting wires (CW') and the constituent material of the plurality of upper dummy wires (DW') may be different.

[0142] A plurality of upper dummy wires (DW') may include a side upper dummy wire (DW'_S) in which a first end contacts a side dummy pad (DP'_S) of the upper semiconductor chip (400), and a front-side upper dummy wire (DW'_F) in which a first end contacts a front dummy pad (DP'_F) of the upper semiconductor chip (400).

[0143] The first end of the side upper dummy wire (DW'_S) may come into contact with the side dummy pad (DP'_S) of the upper semiconductor chip (400). The side upper dummy wire (DW'_S) may include an exposed side upper dummy wire (DW'_S1) that is exposed outside the semiconductor package (1000f) and a buried side upper dummy wire (DW'_S2) that is not exposed outside the semiconductor package (1000f).

[0144] The exposed side upper dummy wire (DW'_S1) may have its first end in contact with the side upper dummy pad (DP'_S) of the upper semiconductor chip (400) and its second end in a co-surface with the outer surface of the upper molding layer (ML'). The buried side upper dummy wire (DW'_S2) may have its first end in contact with the side upper dummy pad (DP'_S) of the upper semiconductor chip (400) and its second end located inside the upper molding layer (ML').

[0145] In some embodiments, the exposed side upper dummy wire (DW'_S1) may include a first exposed side upper dummy wire (DW'_S1a) in which the second end forms a co-plane with the side of the upper molding layer (ML'), and a second exposed side upper dummy wire (DW'_S1b) in which the second end forms a co-plane with the upper surface of the upper molding layer (ML').

[0146] The first end of the front upper dummy wire (DW'_F) may come into contact with the front dummy pad (DP'_F) of the upper semiconductor chip (400). The front upper dummy wire (DW'_F) may include an exposed front upper dummy wire (DW'_F1) that is exposed outside the semiconductor package (1000f) and a buried front upper dummy wire (DW'_F2) that is not exposed outside the semiconductor package (1000f).

[0147] The exposed front upper dummy wire (DW'_F1) may have its first end in contact with the front upper dummy pad (DP'_F) of the upper semiconductor chip (400), and its second end may form a co-surface with the outer surface of the upper molding layer (ML'). The buried front upper dummy wire (DW'_F2) may have its first end in contact with the front upper dummy pad (DP'_F) of the upper semiconductor chip (400), and its second end may be located inside the upper molding layer (ML').

[0148] In some embodiments, the exposed front upper dummy wire (DW'_F1) may include a first exposed front upper dummy wire (DW'_F1a) in which the second end forms a co-plane with the side of the upper molding layer (ML'), and a second exposed front upper dummy wire (DW'_F1b) in which the second end forms a co-plane with the upper surface of the upper molding layer (ML').

[0149] FIG. 11 is a cross-sectional view schematically showing a semiconductor package (1000g) according to exemplary embodiments.

[0150] Most of the components constituting the semiconductor package (1000g) described below and the materials forming said components are substantially the same or similar as those described in FIG. 9 above. Therefore, for the convenience of explanation, the explanation will focus on the differences between the semiconductor package (1000g) of FIG. 11 and the semiconductor package (1000g) of FIG. 9 described above.

[0151] For example, the semiconductor package (1000g) of FIG. 11 may be an exemplary embodiment in which a package substrate (500) having an upper semiconductor chip (400) mounted thereon is mounted on the semiconductor package (1000d) of FIG. 8. For example, the semiconductor package (1000g) of FIG. 11 may be a package in which the semiconductor package (1000) of FIG. 1 is mounted on the semiconductor package (1000d) of FIG. 8.

[0152] Referring to FIG. 11, a semiconductor package (1000g) may include a lower rewiring structure (100), a lower semiconductor chip (200), a lower molding layer (ML), a plurality of lower through-vias (EV), a plurality of lower dummy wires (DW), an upper rewiring structure (300), a package substrate (500), an upper semiconductor chip (400), an upper molding layer (ML'), and a plurality of upper dummy wires (DW').

[0153] The package substrate (500) may be positioned on the upper redistribution structure (300). An upper semiconductor chip (400) may be mounted on the package substrate (500). For example, the package substrate (500) may electrically connect the upper semiconductor chip (400) and the upper redistribution structure (300).

[0154] A package substrate (500) may include a base insulating layer (510), upper surface connection pads (CP5_U) located on the upper surface of the base insulating layer (510), and lower surface connection pads (CP5_L) located on the lower surface of the base insulating layer (510). The upper surface connection pads (CP5_U) of the package substrate (500) and the lower surface connection pads (CP5_L) of the package substrate (500) may be electrically connected through internal wiring (CL5) located inside the base insulating layer (510).

[0155] In some embodiments, the pitch between the upper surface connecting pads (CP5_U) and the pitch between the lower surface connecting pads (CP5_L) may be different from each other. For example, the pitch between the upper surface connecting pads (CP5_U) may be smaller than the pitch between the lower surface connecting pads (CP5_L).

[0156] In some embodiments, the size of each of the upper surface connection pads (CP5_U) and each of the lower surface connection pads (CP5_L) may be different. For example, the size of each of the upper surface connection pads (CP5_U) may be smaller than the size of each of the lower surface connection pads (CP5_L).

[0157] In some embodiments, substrate connection terminals (CT5) may be located between the lower connection pads (CP5_L) of the package substrate (500) and the upper redistribution pattern (310) of the upper redistribution structure (300). Through the substrate connection terminals (CT5), the package substrate (500) and the upper redistribution structure (300) may be electrically connected.

[0158] In some embodiments, upper connection terminals (CT4) may be located between the upper surface connection pads (CP5_U) of the package substrate (500) and the upper front pad (CP4) of the upper semiconductor chip (400). For example, the package substrate (500) and the upper semiconductor chip (400) may be electrically connected through the upper connection terminals (CT4). However, this is not limited thereto, and the package substrate (500) and the upper semiconductor chip may be electrically connected through a plurality of connection wires.

[0159] The upper semiconductor chip (400) and the plurality of upper dummy wires (DW') may be substantially the same as the upper semiconductor chip (400) and the plurality of upper dummy wires (DW;) described above.

[0160] The upper molding layer (ML') is located on the package substrate (500) and can wrap the upper semiconductor chip (400) and a plurality of upper dummy wires (DW'). For example, the width of the package substrate (500) and the width of the upper molding layer (ML') may be the same. The width of the package substrate (500) may be smaller than the width of the upper redistribution structure (300).

[0161] FIGS. 12a to 12j are cross-sectional views illustrating a method for manufacturing a semiconductor package (1000e) according to exemplary embodiments. Specifically, FIGS. 12a to 12j are cross-sectional views schematically illustrating the process of manufacturing the semiconductor package (1000e) of FIG. 9.

[0162] Referring to FIGS. 12a and 12b, a lower redistribution structure (100) can be formed on a carrier substrate (CR), and then a lower semiconductor chip (200) and a plurality of lower through-vias (EV) can be formed on the lower redistribution structure (100).

[0163] For example, FIGS. 12a and FIGS. 12b illustrate a chip-last process in which a lower redistribution structure (100) is first formed on a carrier substrate (CR), but the manufacturing order of the lower redistribution structure (100) and the lower semiconductor chip is not limited thereto.

[0164] For example, in FIG. 12b, the lower semiconductor chip (200) is shown with the active surface (210_A) of the lower semiconductor substrate (210) facing the lower redistribution structure (100) and mounted on the lower redistribution structure (100) in a flip-chip manner, but is not limited thereto, and the lower semiconductor chip (200) may be mounted on the lower redistribution structure (100) in a wire bonding manner with the inactive surface of the lower semiconductor substrate (210) facing the lower redistribution structure (100).

[0165] In some embodiments, the lower redistribution structure (100) may be manufactured with a large surface area capable of mounting multiple lower semiconductor chips (200). For example, after mounting the lower semiconductor chips (200) on the lower redistribution structure (100), a dicing process may be performed. However, for convenience of explanation, the description will be based on the size of the diced lower redistribution structure (100) later.

[0166] The lower semiconductor chip (200) is electrically connected to the lower redistribution structure (100), and a plurality of lower through-vias (EV) can be electrically connected to the lower redistribution structure (100).

[0167] In some embodiments, the lower semiconductor chip (200) may include a plurality of lower dummy pads (DP). The plurality of lower dummy pads (DP) may be located on the side or inactive surface of the lower semiconductor substrate (210) of the lower semiconductor chip (200). For example, the plurality of lower dummy pads (DP) may include a side lower dummy pad (DP_S) and a rear lower dummy pad (DP_B).

[0168] For example, when a lower semiconductor chip (200) is attached to a lower rewiring structure (100) by wire bonding, a plurality of lower dummy pads (DP) of the lower semiconductor chip (200) may include a side lower dummy pad (DP_S) and a front lower dummy pad (DP_F, see FIG. 5).

[0169] Referring to FIG. 12c and FIG. 12d, a plurality of lower dummy wires (DW) can be formed in contact with a plurality of lower dummy pads (DP) of a lower semiconductor chip (200). Subsequently, a lower molding layer (ML) can be formed on a lower redistribution structure (100) to cover the lower semiconductor chip (200) and the plurality of lower dummy wires (DW).

[0170] In some embodiments, the first stage may be in contact with a plurality of lower dummy pads (DP), and the second stage may be formed with each of a plurality of lower dummy wires (DW) so as to be suspended in the air without contacting a plurality of lower through-vias (EV), a lower semiconductor chip (200), and a lower redistribution structure (100).

[0171] In some embodiments, each of the lower dummy wires (DW) may be formed such that the first stage contacts a plurality of lower dummy pads (DP), and the second stage contacts a dummy pad located outside the semiconductor package (1000e) among the pads of the large-area lower redistribution structure (100). For example, the dummy pad located outside the semiconductor package (1000e) may be a dummy pad located outside the planned cutting line of the lower redistribution structure (100).

[0172] In some embodiments, a plurality of lower dummy wires (DW) may be formed so as not to come into contact with a plurality of lower through vias (EV). In some embodiments, a portion of the plurality of lower dummy wires (DW) may have a vertical level higher than the vertical level of the upper surface of the plurality of lower through vias (EV).

[0173] The lower molding layer (ML) can completely enclose the lower semiconductor chip (200) and a plurality of lower dummy wires (DW). For example, the plurality of lower dummy wires (DW) and the lower semiconductor chip (200) may be embedded inside the lower molding layer (ML) and not exposed to the outside.

[0174] Referring to FIG. 12e, the upper portion of the lower molding layer (ML) can be partially removed so that the upper surface of a plurality of lower through-vias (EV) is exposed. In some embodiments, the lower molding layer (ML) can be partially removed through a chemical mechanical polishing (CMP) process.

[0175] In some embodiments, during the process of removing the lower molding layer (ML), a portion of a plurality of lower dummy wires (DW) may be removed together. For example, the plurality of lower dummy wires (DW) from which a portion is removed during the process of removing the lower molding layer (ML) may become an exposed rear lower dummy wire (DW_B) or an exposed side lower dummy wire (DW_S). For example, the second end of the plurality of lower dummy wires (DW) from which a portion is removed during the process of removing the lower molding layer (ML) may form a co-plane with the upper surface of the lower molding layer (ML).

[0176] Referring to FIG. 12f, an upper redistribution structure (300) can be formed on a lower molding layer (ML) and a plurality of lower through vias (EV). For example, the upper redistribution structure (300) can also be formed over a large area, similar to the lower redistribution structure (100). However, for convenience of explanation, the description will be based on the size of the diced upper redistribution structure (300).

[0177] The upper redistribution structure (300) can be electrically connected to a plurality of lower through vias (EV). The upper redistribution structure (300) can come into contact with a dummy wire whose second end is in a co-plane with the upper surface of the lower molding layer (ML) among a plurality of lower dummy wires (DW). For example, a dummy wire whose second end is in a co-plane with the upper surface of the lower molding layer (ML) can come into contact with the upper redistribution insulating layers (320) of the upper redistribution structure (300).

[0178] Referring to FIG. 12g, an upper semiconductor chip (400) can be mounted on an upper redistribution structure (300). In FIG. 12g, the upper semiconductor chip (400) is mounted on the upper redistribution structure (300) in a flip-chip manner, but the upper semiconductor chip (400) can be mounted on the upper redistribution structure (300) in a wire bonding manner.

[0179] The upper semiconductor chip (400) may include a plurality of upper dummy pads (DP') that are not electrically connected to a plurality of individual elements formed on the active surface of the upper semiconductor substrate (410) of the upper semiconductor chip (400).

[0180] Referring to FIG. 12h, a plurality of upper dummy wires (DW') can be attached to an upper semiconductor chip (400). A plurality of upper dummy wires (DW') can be formed on a plurality of upper dummy pads (DP') of the upper semiconductor chip (400). For example, the first end of each of the plurality of upper dummy wires (DW') may be in contact with a plurality of upper dummy pads (DP'), and the second end of each of the plurality of upper dummy wires (DW') may be in contact with a dummy pad that is floating in the air or located outside the semiconductor package (1000e) among the pads of a large-area upper redistribution structure (300).

[0181] Referring to FIG. 12i, an upper molding layer (ML') can be formed on an upper redistribution structure (300) to enclose an upper semiconductor chip (400) and a plurality of upper dummy wires. Then, the upper part of the upper molding layer (ML') can be removed so that the upper surface of the upper semiconductor chip (400) is exposed to the outside.

[0182] Subsequently, a dicing process can be performed to cut the upper molding layer (ML'), the upper redistribution structure (300), the lower molding layer (ML), and the lower redistribution structure (100) along a planned cutting line. The sides of the upper molding layer (ML'), the sides of the upper redistribution structure (300), the sides of the lower molding layer (ML), and the sides of the lower redistribution structure (100) can be aligned in a vertical direction (Z direction).

[0183] In some embodiments, during the dicing process, a portion of a plurality of lower dummy wires (DW) and a portion of a plurality of upper dummy wires (DW') may be cut together. The second end of the plurality of lower dummy wires (DW) cut during the dicing process may have a lower molding layer (ML) in a side and a co-plane. The second end of the plurality of upper dummy wires (DW') cut during the dicing process may have an upper molding layer (ML') in a side and a co-plane.

[0184] Referring to FIG. 12j, in the lower redistribution structure (100), the carrier substrate (CR) can be removed and external connection terminals (CT1) can be attached to the external connection pad (CP1) of the lower redistribution structure (100). The external connection terminals (CT1) may include at least one of a conductive material, such as solder, tin (Sn), silver (Ag), copper (Cu), and aluminum (Al).

[0185] In some embodiments, the process of attaching external connection terminals (CT1) to the lower redistribution structure (100) may be performed before mounting the lower semiconductor chip (200) on the lower redistribution structure (100).

[0186] Up to this point, the present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0187] 1000: Semiconductor package 100: Lower redistribution structure 200: Lower semiconductor chip DW: Lower dummy wire DW_S: Side lower dummy wire DW_B: Rear lower dummy wire DW_F: Front bottom dummy wire DP: Lower dummy pad DP_S: Side lower dummy pad DP_B: Rear lower dummy pad DP_F: Front lower dummy pad EV: Penetrating via ML: Molding layer 300: Upper redistribution structure 400: Upper semiconductor chip DW': Upper dummy wire DW'_S: Side upper dummy wire DW'_F: Front upper dummy wire DP': Upper dummy pad DP'_S: Side upper dummy pad DP'_F: Front upper dummy pad ML': Upper molding layer

Claims

Claim 1 A semiconductor package comprising: a rewiring structure; a semiconductor substrate located on the rewiring structure and including an active surface and an inactive surface opposite thereto, a wiring structure located on the active surface of the semiconductor substrate, and a plurality of dummy pads; a first end in contact with the plurality of dummy pads of the semiconductor chip, and a second end opposite to the first end, spaced apart from the semiconductor chip and the rewiring structure; wherein the plurality of dummy pads of the semiconductor chip further include a side dummy pad located on the side of the semiconductor substrate, and the plurality of dummy wires include a side dummy wire in which the first end contacts the side dummy pad of the semiconductor chip. Claim 2 A semiconductor package according to claim 1, further comprising a molding layer positioned on the redistribution structure and in contact with the side surface of the semiconductor chip and the outer surface of each of the plurality of dummy wires, wherein the upper surface of the molding layer and the upper surface of the semiconductor chip form a co-plane. Claim 3 A semiconductor package according to claim 2, wherein the side dummy wire comprises an exposed side dummy wire in which the first end contacts the side dummy pad of the semiconductor chip and the second end forms a co-plane with the outer surface of the molding layer. Claim 4 A semiconductor package according to claim 2, wherein the side dummy wire comprises a buried side dummy wire in which the first end contacts the side dummy pad of the semiconductor chip and the second end is located inside the molding layer. Claim 5 A semiconductor package according to claim 1, wherein the semiconductor chip is positioned on the redistribution structure such that the inactive surface of the semiconductor substrate faces the redistribution structure, and the wiring structure of the semiconductor chip includes a front pad electrically connected to a plurality of individual elements of the active surface of the semiconductor substrate, and further includes a plurality of connection wires in which a first end contacts the front pad of the wiring structure of the semiconductor chip and a second end opposite to the first end contacts the redistribution structure, and the plurality of dummy pads of the semiconductor chip further include a front dummy pad located on the wiring structure, and the plurality of dummy wires further include a front dummy wire in which the first end contacts the front dummy pad of the semiconductor chip. Claim 6 A semiconductor package according to claim 1, wherein the semiconductor chip is positioned on the redistribution structure such that the active surface of the semiconductor substrate faces the redistribution structure, the plurality of dummy pads of the semiconductor chip further include a rear dummy pad positioned on the inactive surface of the semiconductor substrate, and the plurality of dummy wires further include a rear dummy wire in which the first end contacts the rear dummy pad of the semiconductor chip. Claim 7 A semiconductor package according to claim 1, wherein the semiconductor chip further comprises a plurality of individual elements located on the active surface of the semiconductor substrate and electrically connected to the wiring structure, and the plurality of dummy pads of the semiconductor chip are not electrically connected to the plurality of individual elements on the active surface of the semiconductor substrate of the semiconductor chip. Claim 8 A semiconductor package comprising: a lower redistribution structure; a lower semiconductor substrate located on the lower redistribution structure and including an active surface and an inactive surface opposite thereto, a lower wiring structure located on the active surface of the lower semiconductor substrate, and a plurality of lower dummy pads; a plurality of lower dummy wires, the first end of which contacts the plurality of lower dummy pads of the lower semiconductor chip and the second end opposite to the first end of which is spaced apart from the lower redistribution structure and the lower semiconductor chip; a lower molding layer located on the lower redistribution structure and contacting the lower semiconductor chip and the plurality of lower dummy wires; a plurality of lower through-vias located on the lower redistribution structure and extending from the lower surface to the upper surface of the molding layer; and an upper redistribution structure located on the lower molding layer and electrically connected to the plurality of lower through-vias. Claim 9 In claim 8, the plurality of lower dummy wires are spaced apart from the plurality of lower through-vias in a semiconductor package. Claim 10 A lower redistribution structure; a lower semiconductor substrate located on the lower redistribution structure and comprising an active surface and an inactive surface opposite thereto, a lower wiring structure located on the active surface of the lower semiconductor substrate, and a plurality of lower dummy pads; a plurality of lower dummy wires, the first end of which contacts the plurality of lower dummy pads of the lower semiconductor chip, and the second end opposite to the first end of which is spaced apart from the lower redistribution structure and the lower semiconductor chip; a lower molding layer located on the lower redistribution structure and contacting the lower semiconductor chip and the plurality of lower dummy wires; a plurality of lower through-vias located on the lower redistribution structure and extending from the lower surface to the upper surface of the molding layer; an upper redistribution structure located on the lower molding layer and electrically connected to the plurality of lower through-vias; an upper semiconductor chip located on the upper redistribution structure and comprising an upper semiconductor substrate including an active surface and an inactive surface opposite thereto, an upper wiring structure located on the active surface of the upper semiconductor substrate, and a plurality of upper dummy pads. A semiconductor package comprising: a first stage in contact with the plurality of upper dummy pads, and a second stage opposite to the first stage, a plurality of upper dummy wires spaced apart from the upper redistribution structure and the upper semiconductor chip.

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