Semiconductor package including a plurality of semiconductor chips

Abstract

A semiconductor package according to embodiments of the present disclosure may include: a package substrate; a first semiconductor chip and a support member disposed on the package substrate; a first stack comprising second, third, fourth, and fifth semiconductor chips stacked on the first semiconductor chip and the support member; a second stack comprising sixth, seventh, eighth, and ninth semiconductor chips stacked on the package substrate; and a mold layer covering the first semiconductor chip, the support member, and the first and second stacks. The second, third, fourth, and fifth semiconductor chips may be stacked in a stepped manner so that the chip pads of the second, third, fourth, and fifth semiconductor chips are exposed. The seventh semiconductor chip may be offset relative to the sixth semiconductor chip so that the chip pad of the sixth semiconductor chip is exposed. The eighth semiconductor chip may be overlapped in a vertical direction with respect to the chip pad of the seventh semiconductor chip, and the ninth semiconductor chip may be overlapped in a vertical direction with respect to the chip pad of the eighth semiconductor chip.

Description

Technology Field

[0001] The embodiments of the present disclosure relate to a semiconductor package comprising a plurality of semiconductor chips. Background Technology

[0002] Electronic products are becoming increasingly smaller in size while requiring high-capacity data processing. Consequently, there is a growing need to increase the integration density of semiconductor devices used in these products. Due to the limitations of integration technology, it is difficult to satisfy the required functions with a single semiconductor chip alone; therefore, semiconductor packages are being manufactured using multiple chips.

[0003] Even if a semiconductor package includes multiple semiconductor chips, it is required to be made to a specified size or smaller, depending on the requirements of the application in which it is mounted. Recently, System-in-Package (SIP) packages in which memory and a memory controller are integrated into a single package have been proposed. The problem to be solved

[0004] Embodiments of the present disclosure may provide a semiconductor package comprising a plurality of semiconductor chips.

[0005] The problems of the embodiments of the present disclosure are not limited to those mentioned in this specification, and other problems not mentioned will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] Embodiments of the present disclosure may provide a semiconductor package comprising: a package substrate; a first semiconductor chip and a support member disposed on the package substrate; a first stack comprising second, third, fourth, and fifth semiconductor chips stacked on the first semiconductor chip and the support member; a second stack comprising sixth, seventh, eighth, and ninth semiconductor chips stacked on the package substrate; and a mold layer covering the first semiconductor chip, the support member, and the first and second stacks; wherein the second, third, fourth, and fifth semiconductor chips are stacked in a stepped manner so as to expose the chip pads of the second, third, fourth, and fifth semiconductor chips, the seventh semiconductor chip is offset relative to the sixth semiconductor chip so as to expose the chip pad of the sixth semiconductor chip, the eighth semiconductor chip is overlapped in a vertical direction with respect to the chip pad of the seventh semiconductor chip, and the ninth semiconductor chip is overlapped in a vertical direction with respect to the chip pad of the eighth semiconductor chip.

[0007] Embodiments of the present disclosure include: a package substrate; a controller chip and a support member disposed on the package substrate; a first stack comprising first, second, third, and fourth memory chips stacked on the controller chip and the support member; a second stack comprising fifth, sixth, seventh, and eighth memory chips stacked on the package substrate; a first bonding wire connecting a first upper surface substrate pad of the package substrate and a chip pad of the first memory chip; a second bonding wire connecting a chip pad of the first memory chip and a chip pad of the second memory chip; a third bonding wire connecting a chip pad of the second memory chip and a chip pad of the third memory chip; a fourth bonding wire connecting a chip pad of the third memory chip and a chip pad of the fourth memory chip; a fifth bonding wire connecting a second upper surface substrate pad of the package substrate and a chip pad of the fifth memory chip; and a sixth bonding wire connecting a chip pad of the fifth memory chip and a chip pad of the sixth memory chip. A semiconductor package may be provided comprising: a seventh bonding wire connecting the second upper surface substrate pad and the chip pad of the seventh memory chip; an eighth bonding wire connecting the second upper surface substrate pad and the chip pad of the eighth memory chip; a controller chip, a support member, the first and second stacks, and a mold layer covering the first to eighth bonding wires; wherein the first, second, third, and fourth memory chips are stacked in a stepped manner so that the chip pads of the first, second, third, and fourth memory chips are exposed, the sixth memory chip is offset relative to the fifth semiconductor chip so that the chip pad of the fifth memory chip is exposed, and the side of the seventh memory chip and the side of the eighth memory chip are vertically aligned with the side of the fifth semiconductor chip. Effects of the invention

[0008] According to embodiments of the present disclosure, a semiconductor package comprising a plurality of semiconductor chips can be provided.

[0009] The effects of the embodiments of the present disclosure are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description in the claims. Brief explanation of the drawing

[0010] The content of this disclosure will be more fully understood from the detailed description and accompanying drawings provided below, which are provided solely for illustrative purposes and are not intended to limit the content of this disclosure. FIG. 1 is a drawing showing a semiconductor package according to one embodiment of the present disclosure. FIG. 2 is an enlarged view of the package substrate, first semiconductor chip, support pattern, first stack, and first bonding wire of FIG. 1. FIG. 3 is an enlarged view of the package substrate, the second stack, and the second, third, and fourth bonding wires of FIG. 1. Figure 4 is an enlarged view of part A of Figure 1. FIG. 5 is a schematic plan view of a semiconductor package according to one embodiment of the present disclosure. Specific details for implementing the invention

[0011] Embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed herein. Embodiments or examples according to the concepts of the present disclosure may be carried out in various forms, and the scope of the present disclosure is not limited to the embodiments or examples described herein.

[0012] Identical hatching shown across the drawings indicates corresponding or identical areas in the drawings and does not indicate materials associated with said areas.

[0013] Where one element is described as being "connected" or "combined" to another element, the elements may be directly connected or directly combined, or connected or combined through an intermediate element between them. Where two elements are described as being "directly connected" or "directly combined," one element is directly connected or directly combined to the other without an intermediate element between them.

[0014] When one element is described as being placed "above" or "below" another element, the elements may come into direct contact with each other, or an intermediate element may be placed between the elements.

[0015] Terms such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "front," "rear," "side," "column," "row," and other terms denoting relative spatial relationships or directions are used solely for the purpose of facilitating description or reference of the drawings and are not limited thereto. Other spatial relationships or directions not shown in the drawings or described in the specification are also possible within the scope of this specification.

[0016] Terms such as "first" and "second" are used to distinguish different elements and do not imply the size, order, priority, quantity, or importance of the elements. For example, in some embodiments, the first element may be named the second element, and in other embodiments, the second element may be named the first element.

[0017] Where an element included in the embodiments is described in a singular form in this specification, the element may be interpreted as including a plurality of elements that perform the same or similar functions.

[0018] FIG. 1 is a drawing showing a semiconductor package according to one embodiment of the present disclosure, FIG. 2 is an enlarged drawing showing the package substrate, first semiconductor chip, support pattern, first stack, and first bonding wire of FIG. 1, FIG. 3 is an enlarged drawing showing the package substrate, second stack, and second, third, and fourth bonding wires of FIG. 1, and FIG. 4 is an enlarged view of part A of FIG. 1.

[0019] Referring to FIG. 1, a semiconductor package (100) according to one embodiment of the present disclosure includes a package substrate (10), a first semiconductor chip (21A), a support member (50), a first stack (ST1) and a second stack (ST2). In addition, the semiconductor package (100) includes first to eighth bonding wires (61 to 68), a mold layer (70), and an external connection terminal (80).

[0020] The package substrate (10) may include a circuit and / or wiring structure for electrically connecting the first semiconductor chip (21A), the first stack (ST1), and the second stack (ST2) to an external connection terminal (80). The package substrate (10) may be any one of a printed circuit board (PCB), an interposer, and a redistribution layer.

[0021] Upper surface substrate pads (11, 12, 13) for connection with a first semiconductor chip (21A), a first stack (ST1), and a second stack (ST2) may be disposed on the upper surface (10T) of the package substrate (10), and lower surface substrate pads (14) for connection with an external connection terminal (80) may be disposed on the lower surface (10B) of the package substrate (10). The upper surface substrate pads (11, 12, 13) and the lower surface substrate pad (14) may be part of the circuit and / or wiring structure of the package substrate (10).

[0022] The upper surface substrate pads (11, 12, 13) include a first upper surface substrate pad (11) connected to a first semiconductor chip (21A), a second upper surface substrate pad (12) connected to a first stack (ST1), and a third upper surface substrate pad (13) connected to a second stack (ST2).

[0023] Referring to FIGS. 1 and 2, a first semiconductor chip (21A) is placed on a package substrate (10). As illustrated in FIG. 1, the first semiconductor chip (21A) is placed offset to one side with respect to the center of the package substrate (10) in a first direction (FD).

[0024] A connection electrode (40) is disposed between the first semiconductor chip (21A) and the package substrate (10). The first semiconductor chip (21A) has a first chip pad (22A) on its lower surface (21AB). The first chip pad (22A) is electrically connected to a first integrated circuit inside the first semiconductor chip (21A). The connection electrode (40) is disposed below the first chip pad (22A) and is connected to the first chip pad (22A) and the first upper surface substrate pad (11) of the package substrate (10). The connection electrode (40) electrically connects the first chip pad (22A) and the first upper surface substrate pad (11). The connection electrode (40) may be a bump, a solder ball, or a combination thereof, but is not limited thereto.

[0025] The first semiconductor chip (21A) may be a controller chip for controlling semiconductor chips (21B, 21C, 21D, 21E) included in the first stack (ST1) and semiconductor chips (21F, 21G, 21H, 21I) included in the second stack (ST2). If the semiconductor chips (21B, 21C, 21D, 21E, 21F, 21G, 21H, 21I) included in the first and second stacks (ST1, ST2) are memory chips, the first semiconductor chip (21A) may be a memory controller chip.

[0026] A first adhesive member (31A) is attached to the lower surface (50B) of a support member (50), and the support member (50) is fixed to the upper surface (10T) of a package substrate (10) by the first adhesive member (31A). The support member (50) may be a dummy chip, but is not limited thereto.

[0027] The sum of the thickness of the support member (50) and the thickness of the first adhesive member (31A) may be substantially the same as the sum of the thickness of the first semiconductor chip (21A) and the height of the connection electrode (40). Accordingly, in the vertical direction (TD), the upper surface (21AT) of the first semiconductor chip (21A) and the upper surface (50T) of the support member (50) may be located at substantially the same level.

[0028] The first semiconductor chip (21A) is positioned between the support member (50) and the second stack (ST2). As illustrated in FIG. 1, the second stack (ST2) is positioned to the left of the first semiconductor chip (21A) in the first direction (FD), and the support member (50) is positioned to the right of the first semiconductor chip (21A) in the first direction (FD). The first semiconductor chip (21A) is positioned closer to the second stack (ST2) than to the support member (50).

[0029] The first stack (ST1) is placed on the first semiconductor chip (21A) and the support member (50), and the second stack (ST2) is placed on the package substrate (10).

[0030] The first stack (ST1) includes second, third, fourth, and fifth semiconductor chips (21B, 21C, 21D, 21E) and second, third, fourth, and fifth adhesive members (31B, 31C, 31D, 31E). The second stack (ST2) includes sixth, seventh, eighth, and ninth semiconductor chips (21F, 21G, 21H, 21I) and sixth, seventh, eighth, and ninth adhesive members (31F, 31G, 31H, 31I).

[0031] The second to ninth semiconductor chips (21B to 21I) may be of the same type. The second to ninth semiconductor chips (21B to 21I) may be memory chips. The memory may include volatile memory and non-volatile memory. Volatile memory may include DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), and non-volatile memory may include NAND, NOR, PRAM (Phase Change Random Access Memory), and MRAM (Magneto-Resistive Random Access Memory).

[0032] Each of the 6th to 9th semiconductor chips (21F to 21I) may be substantially identical to a structure obtained by flipping one of the 2nd to 5th semiconductor chips (21B to 21E) 180 degrees around an axis extending in the vertical direction (TD). The 2nd to 9th semiconductor chips (21B to 21I) may have the same size in the horizontal direction and the same thickness in the vertical direction (TD).

[0033] The second semiconductor chip (21B) is placed on the first semiconductor chip (21A) and the support member (50). The second semiconductor chip (21B) has a second chip pad (22B) on its upper surface (21BT). The second chip pad (22B) is electrically connected to a second integrated circuit inside the second semiconductor chip (21B). The second chip pad (22B) is placed on the other edge area of ​​the second semiconductor chip (21B), such as the right edge area, opposite to the one edge area of ​​the second semiconductor chip (21B) adjacent to the second stack (ST2).

[0034] A second adhesive member (31B) is attached to the lower surface (21BB) of the second semiconductor chip (21B), and the second semiconductor chip (21B) is fixed on the first semiconductor chip (21A) and the support member (50) by the second adhesive member (31B). The second adhesive member (31B) is positioned between the first semiconductor chip (21A) and the second semiconductor chip (21B), and between the support member (50) and the second semiconductor chip (21B), thereby attaching the first semiconductor chip (21A) and the second semiconductor chip (21B), and attaching the support member (50) and the second semiconductor chip (21B).

[0035] A third semiconductor chip (21C) is placed on the second semiconductor chip (21B). The third semiconductor chip (21C) has a third chip pad (22C) on its upper surface (21CT). The third chip pad (22C) is electrically connected to a third integrated circuit inside the third semiconductor chip (21C). The third chip pad (22C) is placed on the other edge area of ​​the third semiconductor chip (21C), such as the right edge area, opposite to the one edge area of ​​the third semiconductor chip (21C) adjacent to the second stack (ST2).

[0036] A third adhesive member (31C) is attached to the lower surface (21CB) of the third semiconductor chip (21C), and the third semiconductor chip (21C) is fixed onto the second semiconductor chip (21B) by the third adhesive member (31C). The third adhesive member (31C) is positioned between the second semiconductor chip (21B) and the third semiconductor chip (21C) to attach the second semiconductor chip (21B) and the third semiconductor chip (21C).

[0037] The fourth semiconductor chip (21D) is placed on the third semiconductor chip (21C). The fourth semiconductor chip (21D) has a fourth chip pad (22D) on its upper surface (21DT). The fourth chip pad (22D) is electrically connected to the fourth integrated circuit inside the fourth semiconductor chip (21D). The fourth chip pad (22D) is placed on the other edge area of ​​the fourth semiconductor chip (21D), such as the right edge area, opposite to the one edge area of ​​the fourth semiconductor chip (21D) adjacent to the second stack (ST2).

[0038] A fourth adhesive member (31D) is attached to the lower surface (21DB) of the fourth semiconductor chip (21D), and the fourth semiconductor chip (21D) is fixed onto the third semiconductor chip (21C) by the fourth adhesive member (31D). The fourth adhesive member (31D) is positioned between the third semiconductor chip (21C) and the fourth semiconductor chip (21D) to attach the third semiconductor chip (21C) and the fourth semiconductor chip (21D).

[0039] The fifth semiconductor chip (21E) is placed on the fourth semiconductor chip (21D). The fifth semiconductor chip (21E) has a fifth chip pad (22E) on its upper surface (21E). The fifth chip pad (22E) is electrically connected to the fifth integrated circuit inside the fifth semiconductor chip (21E). The fifth chip pad (22E) is placed on the other edge area of ​​the fifth semiconductor chip (21E), such as the right edge area, opposite to the one edge area of ​​the fifth semiconductor chip (21E) adjacent to the second stack (ST2).

[0040] A fifth adhesive member (31E) is attached to the lower surface (21EB) of the fifth semiconductor chip (21E), and the fifth semiconductor chip (21E) is fixed onto the fourth semiconductor chip (21D) by the fifth adhesive member (31E). The fifth adhesive member (31E) is positioned between the fourth semiconductor chip (21D) and the fifth semiconductor chip (21E) to attach the fourth semiconductor chip (21D) and the fifth semiconductor chip (21E).

[0041] The second, third, fourth, and fifth semiconductor chips (21B, 21C, 21D, 21E) are stacked in a stepped shape so that the second, third, fourth, and fifth chip pads (22B, 22C, 22D, 22E) are exposed. The third semiconductor chip (21C) is offset to the left relative to the second semiconductor chip (21B) so that the second chip pad (22B) is exposed, the fourth semiconductor chip (21D) is offset to the left relative to the third semiconductor chip (21C) so that the third chip pad (22C) is exposed, and the fifth semiconductor chip (21E) is offset to the left relative to the fourth semiconductor chip (21D) so that the fourth chip pad (22D) is exposed. The second, third, fourth, and fifth semiconductor chips (21B, 21C, 21D, 21E) are stacked in a stepped shape rising to the left, that is, in a stepped shape toward the second stack (ST2).

[0042] Referring to FIGS. 1 and 3, a sixth semiconductor chip (21F) is placed on a package substrate (10). The sixth semiconductor chip (21F) has a sixth chip pad (22F) on its upper surface (21FT). The sixth chip pad (22F) is electrically connected to a sixth integrated circuit inside the sixth semiconductor chip (21F). The sixth chip pad (22F) is placed on the other edge area of ​​the sixth semiconductor chip (21F), such as the left edge area, opposite to the one edge area of ​​the sixth semiconductor chip (21F) adjacent to the first semiconductor chip (21A).

[0043] A sixth adhesive member (31F) is attached to the lower surface (21FB) of the sixth semiconductor chip (21F), and the sixth semiconductor chip (21F) is fixed on the package substrate (10) by the sixth adhesive member (31F). The sixth adhesive member (31F) is positioned between the package substrate (10) and the sixth semiconductor chip (21F) to attach the package substrate (10) and the sixth semiconductor chip (21F).

[0044] The seventh semiconductor chip (21G) is placed on the sixth semiconductor chip (21F). The seventh semiconductor chip (21G) has a seventh chip pad (22G) on its upper surface (21GT). The seventh chip pad (22G) is electrically connected to the seventh integrated circuit inside the seventh semiconductor chip (21G). The seventh chip pad (22G) is placed on the other edge area of ​​the seventh semiconductor chip (21G), such as the left edge area, opposite to the one edge area of ​​the seventh semiconductor chip (21G) adjacent to the first semiconductor chip (21A).

[0045] A seventh adhesive member (31G) is attached to the lower surface (21GB) of the seventh semiconductor chip (21G), and the seventh semiconductor chip (21G) is attached to the sixth semiconductor chip (21F) by the seventh adhesive member (31G). The seventh adhesive member (31G) is positioned between the sixth semiconductor chip (21F) and the seventh semiconductor chip (21G) to attach the sixth semiconductor chip (21F) and the seventh semiconductor chip (21G).

[0046] The eighth semiconductor chip (21H) is placed on the seventh semiconductor chip (21G). The eighth semiconductor chip (21H) has an eighth chip pad (22H) on its upper surface (21HT). The eighth chip pad (22H) is electrically connected to the eighth integrated circuit inside the eighth semiconductor chip (21H). The eighth chip pad (22H) is placed on the other edge area of ​​the eighth semiconductor chip (21H), such as the left edge area, opposite to the one edge area of ​​the eighth semiconductor chip (21H) adjacent to the first stack (ST1).

[0047] An eighth adhesive member (31H) is attached to the lower surface (1HB) of the eighth semiconductor chip (21H), and the eighth semiconductor chip (21H) is fixed onto the seventh semiconductor chip (21G) by the eighth adhesive member (31H). The eighth adhesive member (31H) is positioned between the seventh semiconductor chip (21G) and the eighth semiconductor chip (21H) to attach the seventh semiconductor chip (21G) and the eighth semiconductor chip (21H). The eighth adhesive member (31H) may be an adhesive layer such as a PWBL (Penetrate Wafer Backside Lamination) tape or a P-spacer.

[0048] The ninth semiconductor chip (21I) is placed on the eighth semiconductor chip (21H). The ninth semiconductor chip (21I) has a ninth chip pad (22I) on its upper surface (21IT). The ninth chip pad (22I) is electrically connected to the ninth integrated circuit inside the ninth semiconductor chip (21I). The ninth chip pad (22I) is placed on the other edge area of ​​the ninth semiconductor chip (21I), such as the left edge area, opposite to the one edge area of ​​the ninth semiconductor chip (21I) adjacent to the first stack (ST1).

[0049] A ninth adhesive member (31I) is attached to the lower surface (21IB) of the ninth semiconductor chip (21I), and the ninth semiconductor chip (21I) is fixed onto the eighth semiconductor chip (21H) by the ninth adhesive member (31I). The ninth adhesive member (31I) is positioned between the eighth semiconductor chip (21H) and the ninth semiconductor chip (21I) to attach the eighth semiconductor chip (21H) and the ninth semiconductor chip (21I). The ninth adhesive member (31I) may be an adhesive layer such as PWBL tape or a P-spacer.

[0050] The 6th and 7th semiconductor chips (21F, 21G) are stacked in a stepped shape so that the 6th chip pad (22F) is exposed. The 7th semiconductor chip (21G) is offset to the right relative to the 6th semiconductor chip (21F) so that the 6th chip pad (22F) is exposed. The 6th and 7th semiconductor chips (21F, 21G) are stacked in a stepped shape rising to the right, that is, in a stepped shape toward the 1st semiconductor chip (21A).

[0051] The eighth semiconductor chip (21H) is stacked on the seventh semiconductor chip (21G). The eighth semiconductor chip (21H) is offset to the left relative to the seventh semiconductor chip (21G). The eighth semiconductor chip (21H) overlaps the seventh chip pad (22G) in a vertical direction (TD). The eighth adhesive member (31H) is placed on the seventh chip pad (22G) and covers the seventh chip pad (22G). The side (21HS) of the eighth semiconductor chip (21H) is aligned in a vertical direction (TD) with the side (21FS) of the sixth semiconductor chip (21F).

[0052] The ninth semiconductor chip (21I) is stacked on the eighth semiconductor chip (21H). The ninth semiconductor chip (21I) overlaps the eighth chip pad (22H) in a vertical direction (TD). The ninth adhesive member (31I) is placed on the eighth chip pad (22H) and covers the eighth chip pad (22H). The side (21IS) of the ninth semiconductor chip (21I) is aligned in a vertical direction (TD) with the side (21HS) of the eighth semiconductor chip (21H). The side (21IS) of the ninth semiconductor chip (21I) is aligned in a vertical direction (TD) with the side (21FS) of the sixth semiconductor chip (21F).

[0053] The first bonding wire (61) connects the second substrate pad (12) and the second chip pad (22B). The second bonding wire (62) connects the second chip pad (22B) and the third chip pad (22C). The third bonding wire (63) connects the third chip pad (22C) and the fourth chip pad (22D). The fourth bonding wire (64) connects the fourth chip pad (22D) and the fifth chip pad (22E). The fifth bonding wire (65) connects the third substrate pad (13) and the sixth chip pad (22F). The sixth bonding wire (66) connects the sixth chip pad (22F) and the seventh chip pad (22G). At least a portion of the peak of the sixth bonding wire (66) positioned above the upper surface (21GT) of the seventh semiconductor chip (21G) is impregnated into the eighth adhesive member (31H).

[0054] The seventh bonding wire (67) connects the third substrate pad (13) and the eighth chip pad (22H). At least a portion of the peak of the seventh bonding wire (67), which is positioned above the upper surface (21HT) of the eighth semiconductor chip (21H), is impregnated into the ninth adhesive member (31I). The eighth bonding wire (68) connects the third substrate pad (13) and the ninth chip pad (22I).

[0055] The mold layer (70) is formed to cover the first semiconductor chip (21A), the support member (50), the first stack (ST1), the second stack (ST2), and the first to eighth bonding wires (61 to 68). The mold layer (70) can cover the first semiconductor chip (21A), the support member (50), the first stack (ST1), the second stack (ST2), and the first to eighth bonding wires (61 to 68) to protect the first semiconductor chip (21A), the support member (50), the first stack (ST1), the second stack (ST2), and the first to eighth bonding wires (61 to 64) from the external environment. The mold layer (70) includes an insulating layer. The insulating layer may include an epoxy molding compound (EMC). The epoxy molding compound may include a resin and a filler.

[0056] An external connection terminal (80) is connected to a lower substrate pad (14). The external connection terminal (80) has a ball shape. As another example, the external connection terminal (80) may have various shapes, such as a pillar shape, a combination of a ball shape and a pillar shape. The external connection terminal (80) may include various conductive materials, such as solder material, metal material, or a combination thereof.

[0057] Referring to FIG. 4, the second adhesive member (31B) has a thickness of d1. The thicknesses of the third to seventh adhesive members (31C to 31G) may be equal to the thickness (d1) of the second adhesive member (31B). The eighth adhesive member (31H) and the ninth adhesive member (31I) have greater thicknesses than the second to seventh adhesive members (31B to 31G). The eighth adhesive member (31H) has a thickness of d2, and the ninth adhesive member (31I) has a thickness of d3, and d2 and d3 are greater than d1.

[0058] The upper surface (21FT) of the sixth semiconductor chip (21F) is positioned closer to the upper surface (10T) of the package substrate (10) than the upper surface (21AT) of the first semiconductor chip (21A). The upper surface (21AT) of the first semiconductor chip (21A) is positioned at a height h1 from the upper surface (10T) of the package substrate (10), and the upper surface (21FT) of the sixth semiconductor chip (21F) is positioned at a height h2 from the upper surface (10T) of the package substrate (10), where h2 is smaller than h1.

[0059] The distance between the upper surface (10T) of the package substrate (10) and the upper surface (21FT) of the sixth semiconductor chip (21F) is substantially equal to the sum of the thickness of the sixth adhesive member (31F) and the thickness of the sixth semiconductor chip (21F). The distance between the upper surface (10T) of the package substrate (10) and the upper surface (21AT) of the first semiconductor chip (21A) is substantially equal to the sum of the height of the connection electrode (40) and the thickness of the first semiconductor chip (21A). The sum of the thickness of the sixth adhesive member (31F) and the thickness of the sixth semiconductor chip (21F) is smaller than the sum of the height of the connection electrode (40) and the thickness of the first semiconductor chip (21A).

[0060] The upper surface (21GT) of the seventh semiconductor chip (21G) is positioned further from the upper surface (10T) of the package substrate (10) than the upper surface (21AT) of the first semiconductor chip (21A). The upper surface (21GT) of the seventh semiconductor chip (21G) is positioned at a height h3 from the upper surface (10T) of the package substrate (10), where h3 is greater than h1.

[0061] The distance between the upper surface (10T) of the package substrate (10) and the upper surface (21GT) of the seventh semiconductor chip (21G) is substantially equal to the sum of the thickness of the sixth adhesive member (31F), the thickness of the sixth semiconductor chip (21F), the thickness of the seventh adhesive member (31G), and the thickness of the seventh semiconductor chip (21G). The sum of the thickness of the sixth adhesive member (31F), the thickness of the sixth semiconductor chip (21F), the thickness of the seventh adhesive member (31G), and the thickness of the seventh semiconductor chip (21G) is greater than the sum of the height of the connection electrode (40) and the thickness of the first semiconductor chip (21A).

[0062] The upper surface (21GT) of the seventh semiconductor chip (21G) is positioned closer to the upper surface (10T) of the package substrate (10) than the upper surface (21BT) of the second semiconductor chip (21B). The upper surface (21GT) of the seventh semiconductor chip (21G) is positioned at a height h3 from the upper surface (10T) of the package substrate (10), and the upper surface (21BT) of the second semiconductor chip (21B) is positioned at a height h4 from the upper surface (10T) of the package substrate (10), and h3 is smaller than h4.

[0063] The distance between the upper surface (10T) of the package substrate (10) and the upper surface (21CT) of the second semiconductor chip (21C) is substantially equal to the sum of the height of the connection electrode (40), the thickness of the first semiconductor chip (21A), the thickness of the second adhesive member (31B), and the thickness of the second semiconductor chip (21B).

[0064] The sum of the thickness of the 6th adhesive member (31F), the thickness of the 6th semiconductor chip (21F), the thickness of the 7th adhesive member (31G), and the thickness of the 7th semiconductor chip (21G) is smaller than the sum of the height of the connection electrode (40), the thickness of the 1st semiconductor chip (21A), the thickness of the 2nd adhesive member (31B), and the thickness of the 2nd semiconductor chip (21B).

[0065] A portion of the seventh semiconductor chip (21G) overlaps with a portion of the fifth semiconductor chip (21E) in the vertical direction (TD). As illustrated in FIG. 4, the seventh semiconductor chip (21G) overlaps with the fifth semiconductor chip (21E) in the vertical direction (TD) by a width of Wa.

[0066] FIG. 5 is a schematic plan view of a semiconductor package according to one embodiment of the present disclosure.

[0067] Referring to FIG. 5, the first stack (ST1) has a width of W1 in the first direction (FD). The second stack (ST2) has a width of W2 in the first direction (FD) that is smaller than W1.

[0068] As described with reference to FIGS. 1 to 3, the second to fifth semiconductor chips (21B to 21E) included in the first stack (ST1) are stacked in a stepped shape, whereas among the sixth to ninth semiconductor chips (21F to 21I) included in the second stack (ST2), only the sixth and seventh semiconductor chips (21F, 21G) are stacked in a stepped shape and the eighth and ninth semiconductor chips (21H, 21I) are stacked vertically, so the width (W2) of the first direction (FD) of the second stack (ST2) has a smaller size than the width (W1) of the first direction (FD) of the first stack (ST1).

[0069] As illustrated in FIG. 5, when the length of the second direction (SD) of the first stack (ST1) and the length of the second direction (SD) of the second stack (ST2) are substantially the same, the planar area of ​​the second stack (ST2) has a smaller size than the planar area of ​​the first stack (ST1).

[0070] The first stack (ST1) and the second stack (ST2) overlap each other by a width of Wa. Since the first stack (ST1) and the second stack (ST2) overlap by a width of Wa, the width (Wt) of the first direction (FD) of the area occupied by the first stack (ST1) and the second stack (ST2) is smaller than the sum of W1 and W2 by Wa. That is, Wt has a value of W1 + W2 - Wa.

[0071] According to the present disclosure, the second to fifth semiconductor chips (21B to 21E) of the first stack (ST1) disposed on the first semiconductor chip (21A) and the support pattern (50) are stacked in a stepped shape so that the second to fifth chip pads (22B to 22E) are exposed, and thus the second to fifth adhesive members (31B to 31E) attached to the lower part of the second to fifth semiconductor chips (21B to 21E) are formed with a thin thickness, thereby reducing the height of the semiconductor package. The eighth and ninth semiconductor chips (21H, 21I) of the second stack (ST2) disposed on the package substrate (10) are stacked vertically so that the planar area of ​​the second stack (ST2) has a smaller size than the planar area of ​​the first stack (ST1), so the planar area of ​​the semiconductor package can be reduced compared to the case where the semiconductor chips of the second stack are stacked in the same shape as the semiconductor chips of the first stack.

[0072] The foregoing description is merely an illustrative explanation of the technical concept of the present disclosure, and those skilled in the art to which the present disclosure pertains may make various modifications and variations within the scope of the essential characteristics of the present disclosure. Furthermore, the embodiments disclosed in the present disclosure are intended to explain, not limit, the technical concept of the present disclosure, and thus the scope of the technical concept of the present disclosure is not limited by these embodiments.

Claims

Claim 1 A semiconductor package comprising: a package substrate; a first semiconductor chip and a support member disposed on the package substrate; a first stack including second, third, fourth, and fifth semiconductor chips stacked on the first semiconductor chip and the support member; a second stack including sixth, seventh, eighth, and ninth semiconductor chips stacked on the package substrate; and a mold layer covering the first semiconductor chip, the support member, and the first and second stacks; wherein the second, third, fourth, and fifth semiconductor chips are stacked in a stepped manner so that the chip pads of the second, third, fourth, and fifth semiconductor chips are exposed, the seventh semiconductor chip is offset relative to the sixth semiconductor chip so that the chip pad of the sixth semiconductor chip is exposed, the eighth semiconductor chip is overlapped in a vertical direction with respect to the chip pad of the seventh semiconductor chip, and the ninth semiconductor chip is overlapped in a vertical direction with respect to the chip pad of the eighth semiconductor chip. Claim 2 In claim 1, the second, third, fourth, and fifth semiconductor chips are stacked in a stepped shape toward the second stack, and the seventh semiconductor chip is a semiconductor package offset relative to the sixth semiconductor chip in a direction toward the first semiconductor chip. Claim 3 A semiconductor package according to claim 1, comprising: a first bonding wire connecting the package substrate and the chip pad of the second semiconductor chip; a second bonding wire connecting the chip pad of the second semiconductor chip and the chip pad of the third semiconductor chip; a third bonding wire connecting the chip pad of the third semiconductor chip and the chip pad of the fourth semiconductor chip; a fourth bonding wire connecting the chip pad of the fourth semiconductor chip and the chip pad of the fifth semiconductor chip; a fifth bonding wire connecting the package substrate and the chip pad of the sixth semiconductor chip; a sixth bonding wire connecting the chip pad of the sixth semiconductor chip and the chip pad of the seventh semiconductor chip; a seventh bonding wire connecting the package substrate and the chip pad of the eighth semiconductor chip; and an eighth bonding wire connecting the package substrate and the chip pad of the ninth semiconductor chip. Claim 4 A semiconductor package according to claim 3, further comprising: a first adhesive member disposed on the lower surface of the second semiconductor chip and attached to the first semiconductor chip and the support member; a second adhesive member disposed on the lower surface of the third semiconductor chip and attached to the second semiconductor chip; a third adhesive member disposed on the lower surface of the fourth semiconductor chip and attached to the third semiconductor chip; a fourth adhesive member disposed on the lower surface of the fifth semiconductor chip and attached to the fourth semiconductor chip; a fifth adhesive member disposed on the lower surface of the sixth semiconductor chip and attached to the package substrate; a sixth adhesive member disposed on the lower surface of the seventh semiconductor chip and attached to the sixth semiconductor chip; a seventh adhesive member disposed on the lower surface of the eighth semiconductor chip and attached to the seventh semiconductor chip; and an eighth adhesive member disposed on the lower surface of the ninth semiconductor chip and attached to the eighth semiconductor chip. Claim 5 A semiconductor package according to claim 4, wherein at least a portion of the peak portion of the sixth bonding wire disposed above the upper surface of the seventh semiconductor chip is impregnated into the seventh adhesive member, and at least a portion of the peak portion of the seventh bonding wire disposed above the upper surface of the eighth semiconductor chip is impregnated into the eighth adhesive member. Claim 6 In claim 4, the semiconductor package having a thickness greater than that of the first, second, third, fourth, fifth, and sixth adhesive members. Claim 7 A semiconductor package according to claim 1, wherein the side of the 8th semiconductor chip and the side of the 9th semiconductor chip are aligned with each other in a vertical direction. Claim 8 A semiconductor package according to claim 1, wherein the side of the 8th semiconductor chip and the side of the 9th semiconductor chip are aligned vertically with the side of the 6th semiconductor chip. Claim 9 A semiconductor package according to claim 1, wherein the upper surface of the sixth semiconductor chip is positioned closer to the upper surface of the package substrate than the upper surface of the first semiconductor chip, and the upper surface of the seventh semiconductor chip is positioned further from the upper surface of the package substrate than the upper surface of the first semiconductor chip. Claim 10 In claim 1, the upper surface of the seventh semiconductor chip is positioned closer to the upper surface of the package substrate than the upper surface of the second semiconductor chip. Claim 11 A semiconductor package according to claim 1, wherein the first semiconductor chip includes a controller chip, and the second to ninth semiconductor chips include a memory chip. Claim 12 In claim 1, the first semiconductor chip is a semiconductor package positioned closer to the second stack than to the support member. Claim 13 In claim 1, the semiconductor package further comprises a connection electrode disposed on the lower surface of the first semiconductor chip, wherein the first semiconductor chip is connected to the package substrate through the connection electrode. Claim 14 A package substrate; a controller chip and a support member disposed on the package substrate; a first stack comprising first, second, third, and fourth memory chips stacked on the controller chip and the support member; a second stack comprising fifth, sixth, seventh, and eighth memory chips stacked on the package substrate; a first bonding wire connecting a first upper surface substrate pad of the package substrate and a chip pad of the first memory chip; and a second bonding wire connecting a chip pad of the first memory chip and a chip pad of the second memory chip. A third bonding wire connecting the chip pad of the second memory chip and the chip pad of the third memory chip; a fourth bonding wire connecting the chip pad of the third memory chip and the chip pad of the fourth memory chip; a fifth bonding wire connecting the second upper surface substrate pad of the package substrate and the chip pad of the fifth memory chip; a sixth bonding wire connecting the chip pad of the fifth memory chip and the chip pad of the sixth memory chip; a seventh bonding wire connecting the second upper surface substrate pad and the chip pad of the seventh memory chip; an eighth bonding wire connecting the second upper surface substrate pad and the chip pad of the eighth memory chip; the controller chip, the support member, the first and second stacks, and a mold layer covering the first to eighth bonding wires; A semiconductor package comprising, wherein the first, second, third, and fourth memory chips are stacked in a stepped manner so that the chip pads of the first, second, third, and fourth memory chips are exposed, the sixth memory chip is offset relative to the fifth semiconductor chip so that the chip pads of the fifth memory chip are exposed, and the side of the seventh memory chip and the side of the eighth memory chip are vertically aligned with the side of the fifth semiconductor chip. Claim 15 In claim 14, the chip pad of the 6th memory chip is vertically overlapped with the 7th memory chip, and the chip pad of the 7th memory chip is vertically overlapped with the 8th memory chip in a semiconductor package. Claim 16 A semiconductor package according to claim 14, further comprising: a first adhesive member disposed between the controller chip and the first memory chip and between the support pattern and the first memory chip; a second adhesive member disposed between the first memory chip and the second memory chip; a third adhesive member disposed between the second memory chip and the third memory chip; a fourth adhesive member disposed between the third memory chip and the fourth memory chip; a fifth adhesive member disposed between the package substrate and the fifth memory chip; a sixth adhesive member disposed between the fifth memory chip and the sixth memory chip; a seventh adhesive member disposed between the sixth memory chip and the seventh memory chip; and an eighth adhesive member disposed between the seventh memory chip and the eighth memory chip. Claim 17 In claim 16, the semiconductor package having a thickness greater than that of the first, second, third, fourth, fifth, and sixth adhesive members. Claim 18 A semiconductor package according to claim 16, wherein at least a portion of the peak portion of the sixth bonding wire disposed on the upper surface of the sixth memory chip is impregnated into the seventh adhesive member, and at least a portion of the peak portion of the seventh bonding wire disposed on the upper surface of the seventh memory chip is impregnated into the eighth adhesive member. Claim 19 In claim 14, the first, second, third, and fourth memory chips are stacked in a stepped shape toward the second stack, and the sixth memory chip is offset relative to the fifth memory chip in a direction toward the controller chip. Claim 20 A semiconductor package according to claim 14, wherein a portion of the sixth memory chip and a portion of the fourth memory chip overlap each other in a vertical direction. Claim 21 A semiconductor package according to claim 14, wherein the first stack and the second stack are adjacent in a first direction, and the width of the second stack in the first direction is smaller than the width of the first stack in the first direction from a planar perspective.

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