Display device, method of manufacturing the same, and electronic device including the same

Abstract

A display device comprises a substrate including a first subpixel area, a second subpixel area, and a third subpixel area; a first pixel electrode disposed in the first subpixel area on the substrate; a second pixel electrode disposed in the second subpixel area on the substrate; a third pixel electrode disposed in the third subpixel area on the substrate; a first insulating pattern, a first conductive pattern, a second insulating pattern, and a second conductive pattern sequentially stacked on the third pixel electrode, and a first thickness compensation pattern overlapping with the third subpixel area; a first anode connection pattern disposed on the third pixel electrode, covering the side of the first thickness compensation pattern, and contacting the third pixel electrode, the first conductive pattern, and the second conductive pattern; a first light-emitting layer disposed on the first pixel electrode and emitting a first light; a second light-emitting layer disposed on the second pixel electrode and emitting a second light having a color different from the first light; and a third light-emitting layer disposed on the third pixel electrode and emitting a third light having a color different from the first light and the second light.

Description

Technology Field

[0001] The present invention relates to a display device. More specifically, the present invention relates to a display device, a method for manufacturing the display device, and an electronic device including the display device. Background Technology

[0002] As information technology develops, the importance of display devices, which serve as a medium of connection between users and information, is being highlighted. For example, the use of display devices such as liquid crystal display devices (LCDs), organic light emitting diode (OLED) displays, plasma display panels (PDPs), and quantum dot displays is increasing.

[0003] A display device includes a light-emitting element, wherein the light-emitting element includes a pixel electrode, a common electrode, and a light-emitting layer disposed between the pixel electrode and the common electrode. To improve the light efficiency of the light-emitting element, functional layers (e.g., a hole transport layer, an electron transport layer, etc.) may be further disposed on the upper and / or lower portions of the light-emitting layer.

[0004] Meanwhile, in the case of a full-color display device, it is necessary to increase the intensity of light of different wavelengths for each subpixel of a different color (e.g., red, green, and blue subpixels). To this end, the resonance thickness of the light can be controlled for each subpixel. The problem to be solved

[0005] One objective of the present invention is to provide a display device with improved light efficiency and device reliability.

[0006] Another objective of the present invention is to provide a method for manufacturing the above-mentioned display device.

[0007] Another objective of the present invention is to provide an electronic device including the above-mentioned display device.

[0008] However, the objectives of the present invention are not limited to such objectives and may be extended in various ways without departing from the spirit and scope of the invention. means of solving the problem

[0009] To achieve one objective of the present invention as described above, a display device according to one embodiment of the present invention comprises: a substrate including a first sub-pixel area, a second sub-pixel area, and a third sub-pixel area; a first pixel electrode disposed in the first sub-pixel area on the substrate; a second pixel electrode disposed in the second sub-pixel area on the substrate; a third pixel electrode disposed in the third sub-pixel area on the substrate; a first insulating pattern, a first conductive pattern, a second insulating pattern, and a second conductive pattern sequentially stacked on the third pixel electrode, and a first thickness compensation pattern overlapping with the third sub-pixel area; a first anode connection pattern disposed on the third pixel electrode, covering the side of the first thickness compensation pattern, and contacting the third pixel electrode, the first conductive pattern, and the second conductive pattern; a first light-emitting layer disposed on the first pixel electrode and emitting a first light; a second light-emitting layer disposed on the second pixel electrode and emitting a second light having a color different from the first light; and a second light-emitting layer disposed on the third pixel electrode and emitting the first light and the second It may include a third light-emitting layer that emits a third light having a color different from light.

[0010] In one embodiment, the thickness of the first insulating pattern and the thickness of the second insulating pattern may be greater than the thickness of the first conductive pattern and the thickness of the second conductive pattern.

[0011] In one embodiment, the first insulating pattern and the second insulating pattern each comprise silicon oxide, and the first conductive pattern and the second conductive pattern each may comprise a transparent conductive oxide.

[0012] In one embodiment, the first anode connection pattern may completely surround the first thickness compensation pattern on a plane.

[0013] In one embodiment, the first anode connection pattern may be in contact with the edge of the third pixel electrode and spaced apart from the central part of the third pixel electrode on a plane.

[0014] In one embodiment, the side of the first conductive pattern may protrude further in a direction away from the center of the first thickness compensation pattern than the side of the first insulating pattern. The side of the second conductive pattern may protrude further in a direction away from the center of the first thickness compensation pattern than the side of the second insulating pattern.

[0015] In one embodiment, the first anode connection pattern may be in contact with the lower surface of the first conductive pattern and the lower surface of the second conductive pattern.

[0016] In one embodiment, the display device may further include a third insulating pattern and a third conductive pattern sequentially stacked on the second pixel electrode, a second thickness compensation pattern overlapping with the second subpixel area, and a second anode connection pattern disposed on the second pixel electrode, covering the side of the second thickness compensation pattern and contacting the second pixel electrode and the third conductive pattern.

[0017] In one embodiment, the first insulating pattern and the third insulating pattern may include the same material, and the first conductive pattern and the third conductive pattern may include the same material.

[0018] In one embodiment, the second anode connection pattern may be spaced apart from the upper surface of the second thickness compensation pattern.

[0019] In one embodiment, the second thickness compensation pattern may further include a residual insulation pattern disposed on the third conductivity pattern and overlapping with the edge of the third conductivity pattern, and a residual conductivity pattern disposed on the residual insulation pattern.

[0020] In one embodiment, the second anode connection pattern may overlap with all of the residual insulation pattern and all of the residual conductivity pattern on a plane.

[0021] In one embodiment, the first light-emitting layer may overlap with the first sub-pixel area, the second light-emitting layer may overlap with the first to third sub-pixel areas, and the third light-emitting layer may overlap with the third sub-pixel area.

[0022] To achieve another objective of the present invention as described above, a method for manufacturing a display device according to one embodiment of the present invention comprises the steps of: forming a first pixel electrode overlapping with the first subpixel area, a second pixel electrode overlapping with the second subpixel area, and a third pixel electrode overlapping with the third subpixel area on a substrate comprising a first subpixel area, a second subpixel area, and a third subpixel area; forming a first pre-insulating layer covering the first to third pixel electrodes on the substrate; sequentially forming a first pre-conductive layer, a second pre-insulating layer, and a second pre-conductive layer on the first pre-insulating layer; etching the first pre-insulating layer, the first pre-conductive layer, the second pre-insulating layer, and the second pre-conductive layer through a first etching process to form a first thickness compensation pattern including a first insulating pattern, a first conductive pattern, a second insulating pattern, and a second conductive pattern sequentially stacked on the third pixel electrode, overlapping with the third subpixel area; covering the side of the first thickness compensation pattern, and the third pixel electrode, the first conductive pattern, and the The method may include the steps of forming an anode connection pattern in contact with a second challenge pattern, forming a first light-emitting layer that emits a first light on the first pixel electrode, forming a second light-emitting layer that emits a second light having a color different from the first light on the second pixel electrode, and forming a third light-emitting layer that emits a third light having a color different from the first light and the second light on the third pixel electrode.

[0023] In one embodiment, the thickness of the first pre-insulating layer and the thickness of the second pre-insulating layer may be greater than the thickness of the first pre-conductive layer and the thickness of the second pre-conductive layer.

[0024] In one embodiment, the method for manufacturing the display device may further include, after the step of forming the first thickness compensation pattern, the step of removing a portion of the side of the first insulating pattern and a portion of the side of the second insulating pattern through an additional etching process.

[0025] In one embodiment, the step of etching the first pre-insulating layer, the first pre-conducting layer, the second pre-insulating layer, and the second pre-conducting layer through the first etching process may include the step of forming a third insulating pattern, a third conductive pattern, a fourth insulating pattern, and a fourth conductive pattern that overlap with the second sub-pixel region and are sequentially stacked on the second pixel electrode.

[0026] In one embodiment, the method for manufacturing the display device may further include the step of removing the fourth insulating pattern and the fourth conductive pattern through a second etching process.

[0027] In one embodiment, the second etching process is an anisotropic etching process, and a portion of the fourth insulating pattern and a portion of the fourth conductive pattern may remain after the second etching process.

[0028] To achieve another objective of the present invention as described above, an electronic device according to one embodiment of the present invention may include a display device comprising first to third light-emitting layers and a processor that transmits an image data signal and an input control signal to the display device. The above display device comprises a substrate including a first subpixel area, a second subpixel area, and a third subpixel area; a first pixel electrode disposed in the first subpixel area on the substrate; a second pixel electrode disposed in the second subpixel area on the substrate; a third pixel electrode disposed in the third subpixel area on the substrate; a first insulating pattern, a first conductive pattern, a second insulating pattern, and a second conductive pattern sequentially stacked on the third pixel electrode, a first thickness compensation pattern overlapping with the third subpixel area; an anode connection pattern disposed on the third pixel electrode, covering the side of the first thickness compensation pattern, and in contact with the third pixel electrode, the first conductive pattern, and the second conductive pattern; a first light-emitting layer disposed on the first pixel electrode and emitting a first light; a second light-emitting layer disposed on the second pixel electrode and emitting a second light having a color different from the first light; and a third light disposed on the third pixel electrode and emitting a color different from the first light and the second light. It may include a third light-emitting layer. Effects of the invention

[0029] A display device according to one embodiment of the present invention may include first to third pixel electrodes, a first thickness compensation pattern including a first insulating pattern, a first conductive pattern, a second insulating pattern, and a second conductive pattern sequentially stacked on the third pixel electrode, and a first anode connection pattern covering the side of the first thickness compensation pattern.

[0030] Each of the first insulating pattern and the second insulating pattern may include a material having a low absorption coefficient. Accordingly, the reduction of light efficiency by the thickness compensation pattern for controlling the resonance thickness of light can be prevented.

[0031] The first anode connection pattern can come into contact with the third pixel electrode, the first conductive pattern, and the second conductive pattern. Accordingly, the first anode connection pattern can electrically connect the third pixel electrode, the first conductive pattern, and the second conductive pattern. That is, even if a disconnection occurs between the first conductive pattern and the second conductive pattern during the process of patterning the first thickness compensation pattern, the first anode connection pattern can electrically connect the third pixel electrode, the first conductive pattern, and the second conductive pattern. Accordingly, the reliability of the light-emitting device can be improved.

[0032] However, the effects of the present invention are not limited to the effects described above, and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0033] FIG. 1 is a plan view showing a display device according to one embodiment of the present invention. Figure 2 is a cross-sectional view taken along line II' of Figure 1. Figure 3 is an enlarged cross-sectional view of area A of Figure 2. Figure 4 is an enlarged cross-sectional view of area B of Figure 2. FIG. 5 is a cross-sectional view schematically showing a light-emitting element included in the display device of FIG. 2. FIG. 6 is a cross-sectional view showing a display device according to one embodiment of the present invention. Figure 7 is an enlarged cross-sectional view of region C of Figure 6. FIG. 8 is a cross-sectional view showing a display device according to one embodiment of the present invention. Figure 9 is an enlarged cross-sectional view of region D of Figure 8. FIG. 10 is a cross-sectional view showing a display device according to one embodiment of the present invention. Figure 11 is an enlarged cross-sectional view of region E of Figure 10. FIG. 12 is a cross-sectional view showing a display device according to one embodiment of the present invention. FIGS. 13 to 21 are cross-sectional views illustrating a method for manufacturing a display device according to an embodiment of the present invention. FIG. 22 is a block diagram of an electronic device according to one embodiment of the present invention. FIG. 23 is a schematic diagram of an electronic device according to various embodiments. Specific details for implementing the invention

[0034] Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are given the same reference numerals, and redundant descriptions of identical components are omitted. The present invention may be implemented in various different forms and is not limited to the embodiments described herein.

[0035] FIG. 1 is a plan view showing a display device according to one embodiment of the present invention.

[0036] In this specification, a plane may be defined as a first direction (DR1) and a second direction (DR2) that intersects the first direction (DR1). For example, the first direction (DR1) and the second direction (DR2) may be perpendicular to each other. The normal direction of the plane, i.e., the thickness direction of the display device (DD), may be a third direction (DR3). In other words, the third direction (DR3) may be perpendicular to the first direction (DR1) and the second direction (DR2), respectively. In this specification, the plan view is a view from the third direction (DR3).

[0037] Referring to FIG. 1, a display device (DD) according to one embodiment of the present invention may include a display area (DA) and a non-display area (NDA).

[0038] The display area (DA) can be defined as an area that displays an image by generating light or controlling the transmittance of light provided from an external light source. The non-display area (NDA) can be defined as an area that does not display an image. The non-display area (NDA) may surround at least a portion of the display area (DA) on a plane. For example, the non-display area (NDA) may completely surround the display area (DA) on a plane.

[0039] The display area (DA) may include a plurality of pixel areas (PXA). A pixel may be placed in each of the pixel areas (PXA). The pixel may generate light according to a driving signal.

[0040] Each of the pixel regions (PXA) may include a first sub-pixel region (SPA1), a second sub-pixel region (SPA2), and a third sub-pixel region (SPA3). Each of the first to third sub-pixel regions (SPA1, SPA2, SPA3) may be a region where light emitted from a light-emitting element is emitted to the outside of the display device (DD).

[0041] The first to third subpixel regions (SPA1, SPA2, SPA3) may emit light of different colors. The first subpixel region (SPA1) may emit first light, the second subpixel region (SPA2) may emit second light, and the third subpixel region (SPA3) may emit third light. In one embodiment, the first light may be red light, the second light may be green light, and the third light may be blue light. However, the present invention is not limited thereto. For example, each of the pixel regions (PXA) may be combined to emit yellow, cyan, and magenta light.

[0042] Each of the first to third subpixel regions (SPA1, SPA2, SPA3) may have a planar shape among a triangle, a square, a circle, a track shape, an ellipse, etc. In one embodiment, each of the first to third subpixel regions (SPA1, SPA2, SPA3) may have a rectangular planar shape. However, the present invention is not limited thereto.

[0043] In one embodiment, the first to third subpixel regions (SPA1, SPA2, SPA3) may have the same area (or size) as each other. However, the present invention is not limited thereto. For example, the first subpixel region (SPA1) and the second subpixel region (SPA2) may have the same area as each other, and the third subpixel region (SPA3) may have a larger area than the first subpixel region (SPA1) and the second subpixel region (SPA2).

[0044] The first to third subpixel regions (SPA1, SPA2, SPA3) may be repeatedly arranged along the row direction and column direction on a plane. For example, the first to third subpixel regions (SPA1, SPA2, SPA3) may be repeatedly arranged along the first direction (DR1) and the second direction (DR2).

[0045] FIG. 2 is a cross-sectional view taken along line II' of FIG. 1. FIG. 3 is an enlarged cross-sectional view of region A of FIG. 2. FIG. 4 is an enlarged cross-sectional view of region B of FIG. 2. FIG. 5 is a cross-sectional view schematically showing a light-emitting element included in the display device of FIG. 2.

[0046] Referring to FIGS. 2 to 5, the display device (DD) may include a substrate (SUB), a buffer layer (BUF), first to third transistors (TR1, TR2, TR3), a gate insulating layer (GI), an interlayer insulating layer (ILD), a via insulating layer (VIA), a pixel defining film (PDL), first to third light-emitting elements (LD1, LD2, LD3), and an encapsulation layer (TFE).

[0047] The first transistor (TR1) may include a first active pattern (ACT1), a first gate electrode (GE1), a first source electrode (SE1), and a first drain electrode (DE1). The second transistor (TR2) may include a second active pattern (ACT2), a second gate electrode (GE2), a second source electrode (SE2), and a second drain electrode (DE2). The third transistor (TR3) may include a third active pattern (ACT3), a third gate electrode (GE3), a third source electrode (SE3), and a third drain electrode (DE3).

[0048] The first light-emitting element (LD1) may include a first pixel electrode (PE1), an organic layer (OL), and a common electrode (CE). The second light-emitting element (LD2) may include a second pixel electrode (PE2), an organic layer (OL), and a common electrode (CE). The third light-emitting element (LD3) may include a third pixel electrode (PE3), a thickness compensation pattern (TCP), an anode connection pattern (ACP), an organic layer (OL), and a common electrode (CE).

[0049] The substrate (SUB) may include a transparent or opaque material. The substrate (SUB) may be made of a transparent resin substrate. Examples of the transparent resin substrate include a polyimide substrate. In this case, the polyimide substrate may include a first organic layer, a first barrier layer, a second organic layer, etc. Optionally, the substrate (SUB) may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz (F-doped quartz) substrate, a sodalime glass substrate, a non-alkali glass substrate, etc. These may be used alone or in combination with each other.

[0050] A buffer layer (BUF) can be disposed on a substrate (SUB). The buffer layer (BUF) can prevent metal atoms or impurities from the substrate (SUB) from diffusing into an upper structure. Additionally, the buffer layer (BUF) can improve the flatness of the surface of the substrate (SUB) if the surface of the substrate (SUB) is non-uniform. The buffer layer (BUF) may include an inorganic insulating material. Examples of the inorganic insulating material that can be used as the buffer layer (BUF) include silicon oxide (SiO₂). x ), silicon nitride (SiN x ), silicon oxynitride (SiO₂ x N y There may be ) etc. These can be used alone or in combination with each other. In one embodiment, the buffer layer (BUF) may be omitted.

[0051] The first to third active patterns (ACT1, ACT2, ACT3) may be disposed on a buffer layer (BUF). The first to third active patterns (ACT1, ACT2, ACT3) may include the same material. Each of the first to third active patterns (ACT1, ACT2, ACT3) may include a silicon semiconductor material, an oxide semiconductor material, an organic semiconductor material, etc. The first active pattern (ACT1) may include a first source region, a first drain region, and a first channel region located between the first source region and the first drain region. The second active pattern (ACT2) may include a second source region, a second drain region, and a second channel region located between the second source region and the second drain region. The third active pattern (ACT3) may include a third source region, a third drain region, and a third channel region located between the third source region and the third drain region.

[0052] A gate insulating layer (GI) may be disposed on a buffer layer (BUF). The gate insulating layer (GI) may cover first to third active patterns (ACT1, ACT2, ACT3). The gate insulating layer (GI) may comprise an inorganic insulating material. Examples of the inorganic insulating material that can be used as the gate insulating layer (GI) include silicon oxide (SiO₂). x ), silicon nitride (SiN x ), silicon oxynitride (SiO₂ x N y There may be ) etc. These can be used individually or in combination with each other.

[0053] The first to third gate electrodes (GE1, GE2, GE3) may be disposed on a gate insulating layer (GI). The first gate electrode (GE1) may overlap with the first channel region of the first active pattern (ACT1), the second gate electrode (GE2) may overlap with the second channel region of the second active pattern (ACT2), and the third gate electrode (GE3) may overlap with the third channel region of the third active pattern (ACT3). The first to third gate electrodes (GE1, GE2, GE3) may include the same material. Each of the first to third gate electrodes (GE1, GE2, GE3) may include a conductive material such as a metal, an alloy, a conductive metal nitride, a conductive metal oxide, or a transparent conductive oxide. Examples of the above conductive materials may include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These may be used alone or in combination with each other.

[0054] An interlayer insulating layer (ILD) may be disposed on a gate insulating layer (GI). The interlayer insulating layer (ILD) may cover first to third gate electrodes (GE1, GE2, GE3). The interlayer insulating layer (ILD) may comprise an inorganic insulating material. Examples of the inorganic insulating material that can be used as the interlayer insulating layer (ILD) include silicon oxide (SiO₂). x ), silicon nitride (SiN x ), silicon oxynitride (SiO₂ x N y There may be ) etc. These can be used individually or in combination with each other.

[0055] The first to third source electrodes (SE1, SE2, SE3) and the first to third drain electrodes (DE1, DE2, DE3) may be disposed on the interlayer insulating layer (ILD). The first source electrode (SE1) may be connected to the first source region of the first active pattern (ACT1) through a contact hole penetrating the gate insulating layer (GI) and the interlayer insulating layer (ILD). The first drain electrode (DE1) may be connected to the first drain region of the first active pattern (ACT1) through a contact hole penetrating the gate insulating layer (GI) and the interlayer insulating layer (ILD). The second source electrode (SE2) may be connected to the second source region of the second active pattern (ACT2) through a contact hole penetrating the gate insulating layer (GI) and the interlayer insulating layer (ILD). The second drain electrode (DE2) can be connected to the second drain region of the second active pattern (ACT2) through a contact hole penetrating the gate insulating layer (GI) and the interlayer insulating layer (ILD). The third source electrode (SE3) can be connected to the third source region of the third active pattern (ACT3) through a contact hole penetrating the gate insulating layer (GI) and the interlayer insulating layer (ILD). The third drain electrode (DE3) can be connected to the third drain region of the third active pattern (ACT3) through a contact hole penetrating the gate insulating layer (GI) and the interlayer insulating layer (ILD).

[0056] The first to third source electrodes (SE1, SE2, SE3) and the first to third drain electrodes (DE1, DE2, DE3) may each comprise the same material. Each of the first to third source electrodes (SE1, SE2, SE3) and the first to third drain electrodes (DE1, DE2, DE3) may comprise a conductive material such as a metal, an alloy, a conductive metal nitride, a conductive metal oxide, or a transparent conductive oxide. These may be used alone or in combination with each other.

[0057] Accordingly, a first transistor (TR1) comprising a first active pattern (ACT1), a first gate electrode (GE1), a first source electrode (SE1), and a first drain electrode (DE1) may be disposed on a substrate (SUB). Additionally, a second transistor (TR2) comprising a second active pattern (ACT2), a second gate electrode (GE2), a second source electrode (SE2), and a second drain electrode (DE2) may be disposed on a substrate (SUB). Furthermore, a third transistor (TR3) comprising a third active pattern (ACT3), a third gate electrode (GE3), a third source electrode (SE3), and a third drain electrode (DE3) may be disposed on a substrate (SUB).

[0058] A via insulating layer (VIA) may be disposed on an interlayer insulating layer (ILD). The via insulating layer (VIA) may cover first to third source electrodes (SE1, SE2, SE3) and first to third drain electrodes (DE1, DE2, DE3). The via insulating layer (VIA) may comprise an organic insulating material. Examples of the organic insulating material that can be used as the via insulating layer (VIA) include polyacryl-based resin, polyimide-based resin, polyamide-based resin, siloxane-based resin, acrylic-based resin, epoxy-based resin, etc. These may be used alone or in combination with each other.

[0059] The first to third pixel electrodes (PE1, PE2, PE3) may be placed on a via insulating layer (VIA). The first pixel electrode (PE1) may overlap with the first sub-pixel area (SPA1), the second pixel electrode (PE2) may overlap with the second sub-pixel area (SPA2), and the third pixel electrode (PE3) may overlap with the third sub-pixel area (SPA3).

[0060] Each of the first to third pixel electrodes (PE1, PE2, PE3) may have a single-layer structure or a multi-layer structure. In one embodiment, each of the first to third pixel electrodes (PE1, PE2, PE3) may have a multi-layer structure comprising a plurality of conductive layers.

[0061] In one embodiment, as illustrated in FIG. 3, the first pixel electrode (PE1) may include a first conductive layer (CL1), a second conductive layer (CL2), and a third conductive layer (CL3) sequentially stacked on a via insulating layer (VIA). The second pixel electrode (PE2) and the third pixel electrode (PE3) may have substantially the same structure as the first pixel electrode (PE1). That is, each of the second pixel electrode (PE2) and the third pixel electrode (PE3) may have a structure in which three conductive layers are stacked, each containing the same material as the first to third conductive layers (CL1, CL2, CL3).

[0062] Each of the first to third conductive layers (CL1, CL2, CL3) may include a conductive material such as a metal, an alloy, a conductive metal nitride, a conductive metal oxide, or a transparent conductive oxide. In one embodiment, the first conductive layer (CL1) may include a transparent conductive oxide, the second conductive layer (CL2) may include a metal, and the third conductive layer (CL3) may include a transparent conductive oxide. In one embodiment, the first conductive layer (CL1) and the third conductive layer (CL3) may include the same material, but the present invention is not limited thereto.

[0063] For example, the first conductive layer (CL1) may include indium tin oxide (ITO), the second conductive layer (CL2) may include silver (Ag), and the third conductive layer (CL3) may include indium tin oxide (ITO). However, the present invention is not limited thereto.

[0064] In one embodiment, the thickness of the second conductive layer (CL2) (e.g., length in the third direction (DR3)) may be greater than the thickness of the first conductive layer (CL1) and the thickness of the third conductive layer (CL3).

[0065] A thickness compensation pattern (TCP) may be placed on the third pixel electrode (PE3). The thickness compensation pattern (TCP) may overlap with the third sub-pixel region (SPA3). In one embodiment, the thickness compensation pattern (TCP) may be placed on the upper surface of the third pixel electrode (PE3). The resonant thickness of light emitted from a light-emitting element (e.g., the third light-emitting element (LD3)) may be controlled by the thickness compensation pattern (TCP). The thickness compensation pattern (TCP) may include a lower thickness compensation pattern (TCPa) and an upper thickness compensation pattern (TCPb) sequentially stacked on the third pixel electrode (PE3).

[0066] As illustrated in FIG. 4, the lower thickness compensation pattern (TCPa) may include a first insulation pattern (ILP1) and a first conductive pattern (CDP1) disposed on the first insulation pattern (ILP1), and the upper thickness compensation pattern (TCPb) may include a second insulation pattern (ILP2) and a second conductive pattern (CDP2) disposed on the second insulation pattern (ILP2). That is, the thickness compensation pattern (TCP) may include a first insulation pattern (ILP1), a first conductive pattern (CDP1), a second insulation pattern (ILP2), and a second conductive pattern (CDP2) sequentially stacked on the third pixel electrode (PE3).

[0067] Each of the first insulating pattern (ILP1) and the second insulating pattern (ILP2) may include a material having a low absorption coefficient. For example, each of the first insulating pattern (ILP1) and the second insulating pattern (ILP2) may be silicon oxide (SiO₂). x ), silicon nitride (SiN x It may include ) etc. In one embodiment, the first insulating pattern (ILP1) and the second insulating pattern (ILP2) may each include silicon dioxide (SiO2).

[0068] In one embodiment, the first insulation pattern (ILP1) and the second insulation pattern (ILP2) may comprise the same material. However, the present invention is not limited thereto, and the first insulation pattern (ILP1) and the second insulation pattern (ILP2) may comprise different materials.

[0069] Each of the first conductive pattern (CDP1) and the second conductive pattern (CDP2) may include a transparent conductive oxide. For example, each of the first conductive pattern (CDP1) and the second conductive pattern (CDP2) may include indium tin oxide (ITO), indium zinc oxide (IZO), etc. In one embodiment, each of the first conductive pattern (CDP1) and the second conductive pattern (CDP2) may include indium tin oxide (ITO).

[0070] In one embodiment, the first conductive pattern (CDP1) and the second conductive pattern (CDP2) may comprise the same material. However, the present invention is not limited thereto, and the first conductive pattern (CDP1) and the second conductive pattern (CDP2) may comprise different materials.

[0071] In one embodiment, the thickness of the first insulating pattern (ILP1) and the thickness of the second insulating pattern (ILP2) may be greater than the thickness of the first conductive pattern (CDP1) and the thickness of the second conductive pattern (CDP2). For example, the thickness of each of the first insulating pattern (ILP1) and the second insulating pattern (ILP2) is approximately 300 And, the thickness of each of the first conductive pattern (CDP1) and the second conductive pattern (CDP2) is approximately 70 It may be, but the present invention is not limited thereto.

[0072] An anode connection pattern (ACP) may be placed on the third pixel electrode (PE3). Specifically, the anode connection pattern (ACP) may be placed on the upper surface of the third pixel electrode (PE3) and may be in contact with the edge of the third pixel electrode (PE3). In one embodiment, the anode connection pattern (ACP) may be spaced apart from the central portion of the third pixel electrode (PE3) in a plane. That is, the anode connection pattern (ACP) may not overlap with the central portion of the third pixel electrode (PE3) in a plane.

[0073] The anode connection pattern (ACP) can cover the side of the thickness compensation pattern (TCP). In one embodiment, the anode connection pattern (ACP) can completely surround the thickness compensation pattern (TCP) on a plane. The anode connection pattern (ACP) can come into contact with the side of the first insulation pattern (ILP1), the side of the first conductive pattern (CDP1), the side of the second insulation pattern (ILP2), and the side of the second conductive pattern (CDP2). Additionally, the anode connection pattern (ACP) can come into contact with the top surface of the thickness compensation pattern (TCP). Specifically, the anode connection pattern (ACP) can come into contact with the edge of the top surface of the second conductive pattern (CDP2).

[0074] The anode connection pattern (ACP) can be in contact with the third pixel electrode (PE3), the first conductivity pattern (CDP1), and the second conductivity pattern (CDP2). The anode connection pattern (ACP) can electrically connect the third pixel electrode (PE3), the first conductivity pattern (CDP1), and the second conductivity pattern (CDP2).

[0075] The anode connection pattern (ACP) may include a conductive material. For example, the anode connection pattern (ACP) may include a metal. In one embodiment, the anode connection pattern (ACP) may include titanium (Ti), but the present invention is not limited thereto.

[0076] A pixel defining layer (PDL) may be disposed on a via insulating layer (VIA). The pixel defining layer (PDL) may cover the edges of the first pixel electrode (PE1), the edges of the second pixel electrode (PE2), and the edges of the thickness compensation pattern (TCP). Additionally, the pixel defining layer (PDL) may cover an anode connection pattern (ACP). The pixel defining layer (PDL) may expose a portion of the upper surface of each of the first pixel electrode (PE1), the second pixel electrode (PE2), and the thickness compensation pattern (TCP). The pixel defining layer (PDL) may include an organic insulating material and / or an inorganic insulating material. In one embodiment, the pixel defining layer (PDL) may further include a light-blocking material having a black color. For example, the pixel defining layer (PDL) may further include a black pigment, a black dye, carbon black, etc. These may be used alone or in combination with each other.

[0077] The organic layer (OL) may be disposed on the pixel defining film (PDL), the first pixel electrode (PE1), the second pixel electrode (PE2), and the third pixel electrode (PE3). The organic layer (OL) may be disposed on the thickness compensation pattern (TCP) in the third sub-pixel region (SPA3). The organic layer (OL) may be continuously extended across the first sub-pixel region (SPA1), the second sub-pixel region (SPA2), and the third sub-pixel region (SPA3). In this case, as shown in FIG. 5, the first light-emitting layer (EML1) and the third light-emitting layer (EML3) included in the organic layer (OL) may be disposed individually in the first sub-pixel region (SPA1) and the third sub-pixel region (SPA3), respectively.

[0078] The organic layer (OL) may include a hole transport region (HTR), a first light-emitting layer (EML1), a second light-emitting layer (EML2), a third light-emitting layer (EML3), and an electron transport region (ETR). The first light-emitting layer (EML1) may be included in a first light-emitting device (LD1), the second light-emitting layer (EML2) may be included in a second light-emitting device (LD2), and the third light-emitting layer (EML3) may be included in a third light-emitting device (LD3).

[0079] The first light-emitting layer (EML1) can emit a first light, the second light-emitting layer (EML2) can emit a second light, and the third light-emitting layer (EML3) can emit a third light. For example, the first light may be red light, the second light may be green light, and the third light may be blue light. However, the present invention is not limited thereto.

[0080] A thickness compensation pattern (TCP) can be disposed on the upper surface of the third pixel electrode (PE3). The resonant thickness of the light can be controlled by the thickness compensation pattern (TCP). That is, the thickness compensation pattern (TCP) can form the optimal resonant thickness of the light. Here, the resonant thickness of the light can be defined as the thickness at which the resonant shape of the light occurs. The resonant thickness may vary depending on the wavelength of the light. In one embodiment, the thickness compensation pattern (TCP) can form the optimal resonant thickness of the third light emitted by the third light-emitting layer (EML3).

[0081] Meanwhile, the first pixel electrode (PE1) can be defined as the first anode, the second pixel electrode (PE2) can be defined as the second anode, and the third pixel electrode (PE3) and the thickness compensation pattern (TCP) can be defined as the third anode. The thickness of the third anode can be controlled by the thickness compensation pattern (TCP). The thickness of the third anode may be different from the thickness of the first anode and the thickness of the second anode. For example, the thickness of the third anode may be greater than the thickness of the first anode and the thickness of the second anode.

[0082] The hole transport region (HTR) may be disposed on the first to third pixel electrodes (PE1, PE2, PE3) and the thickness compensation pattern (TCP). The hole transport region (HTR) may overlap with the first to third sub-pixel regions (SPA1, SPA2, SPA3). The hole transport region (HTR) may include a hole injection layer (HIL) and a hole transport layer (HTL).

[0083] A first light-emitting layer (EML1) may be disposed on a hole transport layer (HTL). The first light-emitting layer (EML1) may overlap with a first subpixel region (SPA1). The first light-emitting layer (EML1) may include an organic material that emits the first light. In one embodiment, the first light-emitting layer (EML1) may include a first auxiliary layer. The thickness of the first auxiliary layer may be adjusted to reinforce the resonance of the first light emitted from the first light-emitting layer (EML1). For example, the first auxiliary layer may include an amine-based organic compound, but the present invention is not limited thereto.

[0084] The second light-emitting layer (EML2) may be disposed on the first light-emitting layer (EML1). The second light-emitting layer (EML2) may overlap with the first to third sub-pixel regions (SPA1, SPA2, SPA3). That is, the second light-emitting layer (EML2) may be commonly disposed in the display region (DA). The second light-emitting layer (EML2) may include an organic material that emits the second light.

[0085] A third light-emitting layer (EML3) may be disposed on a second light-emitting layer (EML2). The third light-emitting layer (EML3) may overlap with a third subpixel area (SPA3). The third light-emitting layer (EML3) may include an organic material that emits the third light. In one embodiment, the third light-emitting layer (EML3) may include a second auxiliary layer. The thickness of the second auxiliary layer may be adjusted to reinforce the resonance of the third light emitted from the third light-emitting layer (EML3). For example, the second auxiliary layer may include an amine-based organic compound, but the present invention is not limited thereto.

[0086] The electron transport region (ETR) may be disposed on the first light-emitting layer (EML1), the second light-emitting layer (EML2), and the third light-emitting layer (EML3). The electron transport region (ETR) may overlap with the first to third sub-pixel regions (SPA1, SPA2, SPA3). The electron transport region (ETR) may include at least one of an electron injection layer and an electron transport layer.

[0087] A fine metal mask (FMM) may be used twice to form the first to third light-emitting layers (EML1, EML2, EML3). Accordingly, the manufacturing process of the display device (DD) can be simplified compared to when light-emitting layers are formed individually in each of the first to third sub-pixel regions (SPA1, SPA2, SPA3). That is, as the display device (DD) includes a thickness compensation pattern (TCP), the process of forming an organic thickness compensation pattern using a fine metal mask can be omitted.

[0088] As illustrated in FIG. 2, a common electrode (CE) may be disposed on an organic layer (OL). The common electrode (CE) may extend continuously across first to third subpixel regions (SPA1, SPA2, SPA3). The common electrode (CE) may be disposed along the profile of the organic layer (OL) with a substantially uniform thickness. The common electrode (CE) may comprise a conductive material such as a metal, an alloy, a conductive metal nitride, a conductive metal oxide, or a transparent conductive oxide. These may be used alone or in combination with each other. For example, the common electrode (CE) may function as a cathode.

[0089] Accordingly, a first light-emitting element (LD1) comprising a first pixel electrode (PE1), an organic layer (OL), and a common electrode (CE) may be disposed on a via insulating layer (VIA). A second light-emitting element (LD2) comprising a second pixel electrode (PE2), an organic layer (OL), and a common electrode (CE) may be disposed on a via insulating layer (VIA). A third light-emitting element (LD3) comprising a third pixel electrode (PE3), a thickness compensation pattern (TCP), an anode connection pattern (ACP), an organic layer (OL), and a common electrode (CE) may be disposed on a via insulating layer (VIA).

[0090] The encapsulation layer (TFE) may be disposed on the common electrode (CE). The encapsulation layer (TFE) can prevent impurities, moisture, etc. from penetrating into the first to third light-emitting elements (LD1, LD2, LD3) from the outside. The encapsulation layer (TFE) may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the inorganic encapsulation layer may be silicon oxide (SiO₂). x ), silicon nitride (SiN x ), silicon oxynitride (SiO₂ x N y It may include ) etc. These may be used alone or in combination with each other. For example, the organic encapsulation layer may include a cured polymer such as polyacrylate.

[0091] According to the present invention, as the display device (DD) includes a thickness compensation pattern (TCP), the process of forming an organic thickness compensation pattern using a fine metal mask can be omitted, and a high-resolution display device (DD) can be stably manufactured. In other words, the display device (DD) can achieve high resolution (e.g., about 1500 ppi or higher).

[0092] According to the present invention, a thickness compensation pattern (TCP) may include a first insulating pattern (ILP1) and a second insulating pattern (ILP2) having a low absorption coefficient, and a first conductive pattern (CDP1) and a second conductive pattern (CDP2) comprising a transparent conductive oxide. As the thickness compensation pattern (TCP) includes the first insulating pattern (ILP1) and the second insulating pattern (ILP2) having a low absorption coefficient, a reduction in light efficiency by the thickness compensation pattern (TCP) for controlling the resonant thickness of light can be prevented. In other words, compared to the case where the thickness compensation pattern (TCP) includes only a transparent conductive oxide, the thickness compensation pattern (TCP) of the present invention, which includes the first insulating pattern (ILP1) and the second insulating pattern (ILP2), can absorb relatively less light, and accordingly, the light efficiency can be improved.

[0093] According to the present invention, an anode connection pattern (ACP) can come into contact with a pixel electrode (e.g., a third pixel electrode (PE3)) and a conductive pattern (CDP1, CDP2) included in a thickness compensation pattern (TCP). Accordingly, the anode connection pattern (ACP) can electrically connect the pixel electrode, the first conductive pattern (CDP1), and the second conductive pattern (CDP2). That is, even if a disconnection occurs between the first conductive pattern (CDP1) and the second conductive pattern (CDP2) during the process of patterning the thickness compensation pattern (TCP), the anode connection pattern (ACP) in contact with the pixel electrode, the first conductive pattern (CDP1), and the second conductive pattern (CDP2) can electrically connect the pixel electrode, the first conductive pattern (CDP1), and the second conductive pattern (CDP2). Accordingly, the reliability of the light-emitting element (e.g., a third light-emitting element (LD3)) can be improved.

[0094] FIG. 6 is a cross-sectional view showing a display device according to an embodiment of the present invention. FIG. 7 is an enlarged cross-sectional view of region C of FIG. 6.

[0095] Referring to FIGS. 6 and 7, a display device (DD') according to one embodiment of the present invention may include a substrate (SUB), a buffer layer (BUF), first to third transistors (TR1, TR2, TR3), a gate insulating layer (GI), an interlayer insulating layer (ILD), a via insulating layer (VIA), a pixel defining film (PDL), first to third light-emitting elements (LD1, LD2, LD3), and an encapsulation layer (TFE). The third light-emitting element (LD3) may include a third pixel electrode (PE3), a thickness compensation pattern (TCP), an anode connection pattern (ACP), an organic layer (OL), and a common electrode (CE). The thickness compensation pattern (TCP) may include a lower thickness compensation pattern (TCPa') and an upper thickness compensation pattern (TCPb'). The lower thickness compensation pattern (TCPa') may include a first insulation pattern (ILP1') and a first conductivity pattern (CDP1), and the upper thickness compensation pattern (TCPb') may include a second insulation pattern (ILP2') and a second conductivity pattern (CDP2).

[0096] The display device (DD') may be substantially the same as the display device (DD) described above with reference to FIGS. 1 to 5, except that the side of the first conductive pattern (CDP1) protrudes more than the side of the first insulating pattern (ILP1'), and the side of the second conductive pattern (CDP2) protrudes more than the side of the second insulating pattern (ILP2'). Hereinafter, descriptions that overlap with the display device (DD) described above with reference to FIGS. 1 to 5 are omitted or simplified.

[0097] A thickness compensation pattern (TCP) may be placed on a pixel electrode (e.g., a third pixel electrode (PE3)). The thickness compensation pattern (TCP) may overlap with a third sub-pixel area (SPA3). The resonant thickness of light emitted from a light-emitting element (e.g., a third light-emitting element (LD3)) may be controlled by the thickness compensation pattern (TCP). The thickness compensation pattern (TCP) may include a first insulating pattern (ILP1'), a first conductive pattern (CDP1), a second insulating pattern (ILP2'), and a second conductive pattern (CDP2) sequentially stacked on the third pixel electrode (PE3).

[0098] Each of the first insulating pattern (ILP1') and the second insulating pattern (ILP2') may include a material having a low absorption coefficient. For example, each of the first insulating pattern (ILP1') and the second insulating pattern (ILP2') may be silicon oxide (SiO2). x ), silicon nitride (SiN x It may include ) etc.

[0099] Each of the first conductive pattern (CDP1) and the second conductive pattern (CDP2) may include a transparent conductive oxide. For example, each of the first conductive pattern (CDP1) and the second conductive pattern (CDP2) may include indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0100] In one embodiment, as illustrated in FIG. 7, the side of the first conductive pattern (CDP1) may protrude further in a direction away from the center of the thickness compensation pattern (TCP) than the side of the first insulating pattern (ILP1'), and the side of the second conductive pattern (CDP2) may protrude further in a direction away from the center of the thickness compensation pattern (TCP) than the side of the second insulating pattern (ILP2'). In this case, during the process of patterning the thickness compensation pattern (TCP), the first insulating pattern (ILP1') and the second insulating pattern (ILP2') may be further etched. Accordingly, the side of the first insulating pattern (ILP1') and the side of the second insulating pattern (ILP2') may have a recessed structure toward the center of the thickness compensation pattern (TCP).

[0101] The anode connection pattern (ACP) can cover the side of the thickness compensation pattern (TCP). The anode connection pattern (ACP) can contact the side of the first insulation pattern (ILP1'), the side of the first conductive pattern (CDP1), the side of the second insulation pattern (ILP2'), and the side of the second conductive pattern (CDP2). Additionally, the anode connection pattern (ACP) can contact the top surface of the thickness compensation pattern (TCP).

[0102] In one embodiment, the anode connection pattern (ACP) may come into contact with the lower surface of the first conductive pattern (CDP1) and the lower surface of the second conductive pattern (CDP2). That is, as the side of the first insulating pattern (ILP1') has a recessed structure, a portion of the lower surface of the first conductive pattern (CDP1) may not be covered by the first insulating pattern (ILP1'). Additionally, as the side of the second insulating pattern (ILP2') has a recessed structure, a portion of the lower surface of the second conductive pattern (CDP2) may not be covered by the second insulating pattern (ILP2'). In this case, the anode connection pattern (ACP) may come into contact with the portion of the lower surface of the first conductive pattern (CDP1) and the portion of the lower surface of the second conductive pattern (CDP2). Accordingly, the contact area between the anode connection pattern (ACP) and the first conduction pattern (CDP1) and the contact area between the anode connection pattern (ACP) and the second conduction pattern (CDP2) can be relatively increased, and the anode connection pattern (ACP) can make more stable contact with the first conduction pattern (CDP1) and the second conduction pattern (CDP2).

[0103] FIG. 8 is a cross-sectional view showing a display device according to an embodiment of the present invention. FIG. 9 is a cross-sectional view of area D of FIG. 8 enlarged.

[0104] Referring to FIGS. 8 and 9, a display device (DD2) according to one embodiment of the present invention may include a substrate (SUB), a buffer layer (BUF), first to third transistors (TR1, TR2, TR3), a gate insulating layer (GI), an interlayer insulating layer (ILD), a via insulating layer (VIA), a pixel defining film (PDL), first to third light-emitting elements (LD1, LD2, LD3), and an encapsulation layer (TFE). The third light-emitting element (LD3) may include a third pixel electrode (PE3), a first thickness compensation pattern (TCP1), a first anode connection pattern (ACP1), an organic layer (OL), and a common electrode (CE). The second light-emitting element (LD2) may include a second pixel electrode (PE2), a second thickness compensation pattern (TCP2), a second anode connection pattern (ACP2), an organic layer (OL), and a common electrode (CE).

[0105] The display device (DD2) may be substantially the same as the display device (DD) described above with reference to FIGS. 1 to 5, except that it further includes a second thickness compensation pattern (TCP2) disposed on the second pixel electrode (PE2) and overlapping with the second sub-pixel area (SPA2), and a second anode connection pattern (ACP2) covering the second thickness compensation pattern (TCP2). Hereinafter, descriptions that overlap with the display device (DD) described above with reference to FIGS. 1 to 5 are omitted or simplified.

[0106] The first thickness compensation pattern (TCP1) may be placed on the third pixel electrode (PE3). The first thickness compensation pattern (TCP1) may overlap with the third sub-pixel region (SPA3). The resonant thickness of the light emitted from the third light-emitting element (LD3) may be controlled by the first thickness compensation pattern (TCP1). The first thickness compensation pattern (TCP1) may include a first lower thickness compensation pattern (TCPa) and a first upper thickness compensation pattern (TCPb) sequentially stacked on the third pixel electrode (PE3). The first thickness compensation pattern (TCP1) may have a structure substantially identical to the thickness compensation pattern (TCP) of FIG. 4.

[0107] The second thickness compensation pattern (TCP2) may be placed on the second pixel electrode (PE2). The second thickness compensation pattern (TCP2) may overlap with the second sub-pixel area (SPA2). In one embodiment, the second thickness compensation pattern (TCP2) may be placed on the upper surface of the second pixel electrode (PE2). The resonant thickness of the light emitted from the second light-emitting element (LD2) can be controlled by the second thickness compensation pattern (TCP2).

[0108] As illustrated in FIG. 9, the second thickness compensation pattern (TCP2) may include a third insulating pattern (ILP3) and a third conductive pattern (CDP3) sequentially stacked on the second pixel electrode (PE2).

[0109] The third insulating pattern (ILP3) may include a material having a low absorption coefficient. For example, the third insulating pattern (ILP3) may be silicon oxide (SiO₂). x ), silicon nitride (SiN x It may include ) etc. The third insulation pattern (ILP3) and the first insulation pattern (ILP1) of FIG. 4 may include the same material and may be formed through the same process. In one embodiment, the thickness of the third insulation pattern (ILP3) may be the same as the thickness of the first insulation pattern (ILP1) of FIG. 4.

[0110] The third conductive pattern (CDP3) may include a transparent conductive oxide. For example, the third conductive pattern (CDP3) may include indium tin oxide (ITO), indium zinc oxide (IZO), etc. The third conductive pattern (CDP3) and the first conductive pattern (CDP1) of FIG. 4 may include the same material and may be formed through the same process. In one embodiment, the thickness of the third conductive pattern (CDP3) may be the same as the thickness of the first conductive pattern (CDP1) of FIG. 4.

[0111] In one embodiment, the thickness of the third insulating pattern (ILP3) may be greater than the thickness of the third conductive pattern (CDP3). For example, the thickness of the third insulating pattern (ILP3) is about 300 And, the thickness of the third conduction pattern (CDP3) is approximately 70 It may be, but the present invention is not limited thereto.

[0112] The first anode connection pattern (ACP1) can be placed on the third pixel electrode (PE3). The first anode connection pattern (ACP1) can cover the side of the first thickness compensation pattern (TCP1). The first anode connection pattern (ACP1) can electrically connect the third pixel electrode (PE3) and the conductive pattern included in the first thickness compensation pattern (TCP1). Accordingly, the reliability of the third light-emitting element (LD3) can be improved. The first anode connection pattern (ACP1) can have a structure substantially identical to the anode connection pattern (ACP) of FIG. 4.

[0113] In one embodiment, the second anode connection pattern (ACP2) may be placed on the second pixel electrode (PE2). Specifically, the second anode connection pattern (ACP2) may be placed on the upper surface of the second pixel electrode (PE2) and may be in contact with the edge of the second pixel electrode (PE2). The second anode connection pattern (ACP2) may be spaced apart from the central portion of the second pixel electrode (PE2) in a plane. That is, the second anode connection pattern (ACP2) may not overlap with the central portion of the second pixel electrode (PE2) in a plane.

[0114] The second anode connection pattern (ACP2) can cover the side of the second thickness compensation pattern (TCP2). In one embodiment, the second anode connection pattern (ACP2) can completely surround the second thickness compensation pattern (TCP2) on a plane. The second anode connection pattern (ACP2) can come into contact with the side of the third insulation pattern (ILP3) and the side of the third conductive pattern (CDP3).

[0115] In one embodiment, the second anode connection pattern (ACP2) may be spaced apart from the upper surface of the second thickness compensation pattern (TCP2). That is, a spacing space (SPS) may be formed between the second anode connection pattern (ACP2) and the second thickness compensation pattern (TCP2). The spacing space (SPS) may be formed by removing an insulating pattern and a conductive pattern located on the third conductive pattern (CDP3) during the process of patterning the second thickness compensation pattern (TCP2). In one embodiment, the insulating pattern and the conductive pattern located on the third conductive pattern (CDP3) may be removed by an isotropic etching process.

[0116] The second anode connection pattern (ACP2) can come into contact with the second pixel electrode (PE2) and the third conductivity pattern (CDP3). That is, the second anode connection pattern (ACP2) can electrically connect the second pixel electrode (PE2) and the third conductivity pattern (CDP3). Accordingly, the reliability of the second light-emitting element (LD2) can be improved.

[0117] Meanwhile, the first pixel electrode (PE1) can be defined as the first anode, the second pixel electrode (PE2) and the second thickness compensation pattern (TCP2) can be defined as the second anode, and the third pixel electrode (PE3) and the first thickness compensation pattern (TCP1) can be defined as the third anode. The thickness of the second anode and the thickness of the third anode can be controlled by the first thickness compensation pattern (TCP1) and the second thickness compensation pattern (TCP2). The thickness of the first anode, the thickness of the second anode, and the thickness of the third anode may be different from each other. For example, the thickness of the third anode may be greater than the thickness of the second anode, and the thickness of the second anode may be greater than the thickness of the first anode.

[0118] FIG. 10 is a cross-sectional view showing a display device according to an embodiment of the present invention. FIG. 11 is a cross-sectional view of area E of FIG. 10 enlarged.

[0119] Referring to FIGS. 10 and 11, a display device (DD2') according to one embodiment of the present invention may include a substrate (SUB), a buffer layer (BUF), first to third transistors (TR1, TR2, TR3), a gate insulating layer (GI), an interlayer insulating layer (ILD), a via insulating layer (VIA), a pixel defining film (PDL), first to third light-emitting elements (LD1, LD2, LD3), and an encapsulation layer (TFE). The second light-emitting element (LD2) may include a second pixel electrode (PE2), a second thickness compensation pattern (TCP2), a second anode connection pattern (ACP2), an organic layer (OL), and a common electrode (CE). The second thickness compensation pattern (TCP2) may include a second lower thickness compensation pattern (TCP2a) and a residual pattern (RTP), and the second lower thickness compensation pattern (TCP2a) may include a third insulating pattern (ILP3) and a third conductive pattern (CDP3).

[0120] The display device (DD2') may be substantially identical to the display device (DD2) described above with reference to FIGS. 8 and 9, except that the second thickness compensation pattern (TCP2) further includes a residual pattern (RTP). Hereinafter, descriptions that overlap with the display device (DD2) described above with reference to FIGS. 8 and 9 are omitted or simplified.

[0121] The second thickness compensation pattern (TCP2) may be disposed on the second pixel electrode (PE2). The second thickness compensation pattern (TCP2) may overlap with the second sub-pixel region (SPA2). The second thickness compensation pattern (TCP2) may include a second lower thickness compensation pattern (TCP2a) and a residual pattern (RTP). The residual pattern (RTP) may overlap with the edge of the second lower thickness compensation pattern (TCP2a). The residual pattern (RTP) may include a residual insulation pattern (RIP) and a residual conductivity pattern (RCP).

[0122] As illustrated in FIG. 11, the second thickness compensation pattern (TCP2) may include a third insulation pattern (ILP3), a third conductivity pattern (CDP3), a residual insulation pattern (RIP), and a residual conductivity pattern (RCP) sequentially stacked on the second pixel electrode (PE2).

[0123] The residual insulation pattern (RIP) may be placed on the third conductivity pattern (CDP3). Specifically, the residual insulation pattern (RIP) may overlap with the edge of the third conductivity pattern (CDP3). The residual insulation pattern (RIP) and the second insulation pattern (ILP2) of FIG. 4 may contain the same material. In one embodiment, the thickness of the residual insulation pattern (RIP) may be the same as the thickness of the second insulation pattern (ILP2) of FIG. 4.

[0124] The residual conductivity pattern (RCP) may be placed on the residual insulation pattern (RIP). The residual conductivity pattern (RCP) and the second conductivity pattern (CDP2) of FIG. 4 may contain the same material. In one embodiment, the thickness of the residual conductivity pattern (RCP) may be the same as the thickness of the second conductivity pattern (CDP2) of FIG. 4.

[0125] The second anode connection pattern (ACP2) can cover the side of the second thickness compensation pattern (TCP2). The second anode connection pattern (ACP2) can come into contact with the side of the third insulation pattern (ILP3), the side of the third conductivity pattern (CDP3), the side of the residual insulation pattern (RIP), and the side of the residual conductivity pattern (RCP). In one embodiment, the second anode connection pattern (ACP2) can overlap with the entirety of the residual pattern (RTP) in a plane. That is, the second anode connection pattern (ACP2) can overlap with the entirety of the residual insulation pattern (RIP) and the entirety of the residual conductivity pattern (RCP) in a plane.

[0126] A residual pattern (RTP) can be formed by removing an insulating pattern and a conductive pattern located on a third conductive pattern (CDP3) during the process of patterning a second thickness compensation pattern (TCP2). In one embodiment, the insulating pattern and the conductive pattern located on the third conductive pattern (CDP3) can be removed by an anisotropic etching process. Accordingly, a portion of the insulating pattern that overlaps the second anode connection pattern (ACP2) in a plane may remain after the etching process, and a residual insulating pattern (RIP) may be formed. Additionally, a portion of the conductive pattern that overlaps the second anode connection pattern (ACP2) in a plane may remain after the etching process, and a residual conductive pattern (RCP) may be formed.

[0127] FIG. 12 is a cross-sectional view showing a display device according to one embodiment of the present invention.

[0128] Referring to FIG. 12, a display device (DD3) according to one embodiment of the present invention may include a substrate (SUB), a buffer layer (BUF), first to third transistors (TR1, TR2, TR3), a gate insulating layer (GI), an interlayer insulating layer (ILD), a via insulating layer (VIA), a pixel defining film (PDL), first to third light-emitting elements (LD1, LD2, LD3), and an encapsulation layer (TFE). The third light-emitting element (LD3) may include a third pixel electrode (PE3), a first thickness compensation pattern (TCP1), a first anode connection pattern (ACP1), an organic layer (OL), and a common electrode (CE). The second light-emitting element (LD2) may include a second pixel electrode (PE2), a second thickness compensation pattern (TCP2), a second anode connection pattern (ACP2), an organic layer (OL), and a common electrode (CE). The first light-emitting element (LD1) may include a first pixel electrode (PE1), a third thickness compensation pattern (TCP3), a third anode connection pattern (ACP3), an organic layer (OL), and a common electrode (CE).

[0129] The display device (DD3) may be substantially the same as the display device (DD2) described above with reference to FIGS. 8 and 9, except that it further includes a third thickness compensation pattern (TCP3) placed on the first pixel electrode (PE1) and overlapping with the first sub-pixel area (SPA1), and a third anode connection pattern (ACP3) covering the third thickness compensation pattern (TCP3). Hereinafter, descriptions that overlap with the display device (DD2) described above with reference to FIGS. 8 and 9 are omitted or simplified.

[0130] The first thickness compensation pattern (TCP1) can be placed in the third sub-pixel region (SPA3) on the third pixel electrode (PE3). The resonant thickness of the light emitted from the third light-emitting element (LD3) can be controlled by the first thickness compensation pattern (TCP1). The first thickness compensation pattern (TCP1) may have a structure substantially identical to the thickness compensation pattern (TCP) of FIG. 4.

[0131] The second thickness compensation pattern (TCP2) can be placed in the second sub-pixel area (SPA2) on the second pixel electrode (PE2). The resonant thickness of the light emitted from the second light-emitting element (LD2) can be controlled by the second thickness compensation pattern (TCP2). The second thickness compensation pattern (TCP2) may have a structure substantially identical to the second thickness compensation pattern (TCP2) of FIG. 9.

[0132] The third thickness compensation pattern (TCP3) may be placed in the first sub-pixel area (SPA1) on the first pixel electrode (PE1). The resonant thickness of the light emitted from the first light-emitting element (LD1) can be controlled by the third thickness compensation pattern (TCP3). The third thickness compensation pattern (TCP3) may have a structure substantially identical to the second thickness compensation pattern (TCP2) of FIG. 9. That is, the third thickness compensation pattern (TCP3) may have a stacked structure comprising an insulating pattern and a conductive pattern containing the same material as the third insulating pattern (ILP3) and the third conductive pattern (CDP3) of FIG. 9, respectively.

[0133] A first anode connection pattern (ACP1) may be placed on a third pixel electrode (PE3), a second anode connection pattern (ACP2) may be placed on a second pixel electrode (PE2), and a third anode connection pattern (ACP3) may be placed on a first pixel electrode (PE1). The first to third anode connection patterns (ACP1, ACP2, ACP3) may cover the side of the first thickness compensation pattern (TCP1), the side of the second thickness compensation pattern (TCP2), and the side of the third thickness compensation pattern (TCP3), respectively. The first anode connection pattern (ACP1) may electrically connect the third pixel electrode (PE3) and the conductive pattern included in the first thickness compensation pattern (TCP1). The second anode connection pattern (ACP2) may electrically connect the second pixel electrode (PE2) and the conductive pattern included in the second thickness compensation pattern (TCP2). The third anode connection pattern (ACP3) can electrically connect the conductive pattern included in the first pixel electrode (PE1) and the third thickness compensation pattern (TCP3).

[0134] Meanwhile, the first pixel electrode (PE1) and the third thickness compensation pattern (TCP3) may be defined as the first anode, the second pixel electrode (PE2) and the second thickness compensation pattern (TCP2) may be defined as the second anode, and the third pixel electrode (PE3) and the first thickness compensation pattern (TCP1) may be defined as the third anode. The thickness of the first anode, the thickness of the second anode, and the thickness of the third anode can be controlled by the first thickness compensation pattern (TCP1), the second thickness compensation pattern (TCP2), and the third thickness compensation pattern (TCP3). The thickness of the third anode may be different from the thickness of the first anode and the thickness of the second anode. For example, the thickness of the third anode may be greater than the thickness of the first anode and the thickness of the second anode. The thickness of the first anode and the thickness of the second anode may be the same.

[0135] FIGS. 13 to 21 are cross-sectional views illustrating a method for manufacturing a display device according to an embodiment of the present invention. The method for manufacturing a display device described with reference to FIGS. 13 to 21 may be a method for manufacturing the display device (DD2) described above with reference to FIGS. 8 and 9. Hereinafter, descriptions that overlap with the display device (DD2) described above with reference to FIGS. 8 and 9 are omitted or simplified.

[0136] In FIGS. 13 to 21, a method for manufacturing a display device having a configuration substantially identical or similar to the display device (DD2) described above with reference to FIGS. 8 and 9 is described, but a person skilled in the art will understand that any one of the display devices (DD, DD', DD2', DD3) described above with reference to FIGS. 2, 6, 10 and 12 can be manufactured through obvious modifications of processes such as a patterning process.

[0137] Referring to FIG. 13, a first pixel electrode (PE1) overlapping with a first subpixel region (SPA1), a second pixel electrode (PE2) overlapping with a second subpixel region (SPA2), and a third pixel electrode (PE3) overlapping with a third subpixel region (SPA3) may be formed on a substrate (SUB) (S100). For example, the first to third pixel electrodes (PE1, PE2, PE3) may be formed on a via insulating layer (VIA). A description of the method for forming the first to third transistors (TR1, TR2, TR3), a buffer layer (BUF), a gate insulating layer (GI), an interlayer insulating layer (ILD), and a via insulating layer (VIA) is omitted.

[0138] Each of the first to third pixel electrodes (PE1, PE2, PE3) may have a single-layer structure or a multi-layer structure. In one embodiment, each of the first to third pixel electrodes (PE1, PE2, PE3) may have a multi-layer structure comprising a plurality of conductive layers.

[0139] Referring to FIG. 14, a first pre-insulating layer (PIL1) covering first to third pixel electrodes (PE1, PE2, PE3) can be formed on a substrate (SUB) (S200). For example, the first pre-insulating layer (PIL1) can be formed on a via insulating layer (VIA). The first pre-insulating layer (PIL1) can be formed on a display area (DA). That is, the first pre-insulating layer (PIL1) can be formed entirely on the first to third sub-pixel areas (SPA1, SPA2, SPA3). Additionally, a first pre-conducting layer (PCL1), a second pre-insulating layer (PIL2), and a second pre-conducting layer (PCL2) can be sequentially formed on the first pre-insulating layer (PIL1) (S200). The first preliminary conductive layer (PCL1), the second preliminary insulating layer (PIL2), and the second preliminary conductive layer (PCL2) can be formed in the display area (DA). That is, the first preliminary conductive layer (PCL1), the second preliminary insulating layer (PIL2), and the second preliminary conductive layer (PCL2) can be formed entirely in the first to third subpixel areas (SPA1, SPA2, SPA3).

[0140] Each of the first pre-insulating layer (PIL1) and the second pre-insulating layer (PIL2) may include a material having a low absorption coefficient. For example, each of the first pre-insulating layer (PIL1) and the second pre-insulating layer (PIL2) may be silicon oxide (SiO₂). x ), silicon nitride (SiN x It may include ) etc. In one embodiment, the first pre-insulating layer (PIL1) and the second pre-insulating layer (PIL2) may each include silicon dioxide (SiO2).

[0141] Each of the first preliminary conductive layer (PCL1) and the second preliminary conductive layer (PCL2) may include a transparent conductive oxide. For example, each of the first preliminary conductive layer (PCL1) and the second preliminary conductive layer (PCL2) may include indium tin oxide (ITO), indium zinc oxide (IZO), etc. In one embodiment, each of the first preliminary conductive layer (PCL1) and the second preliminary conductive layer (PCL2) may include indium tin oxide (ITO).

[0142] In one embodiment, the thickness of the first pre-insulating layer (PIL1) and the thickness of the second pre-insulating layer (PIL2) may be greater than the thickness of the first pre-conducting layer (PCL1) and the thickness of the second pre-conducting layer (PCL2). For example, the thickness of each of the first pre-insulating layer (PIL1) and the second pre-insulating layer (PIL2) is approximately 300 And, the thickness of each of the first preliminary conductive layer (PCL1) and the second preliminary conductive layer (PCL2) is approximately 70 It may be, but the present invention is not limited thereto.

[0143] Referring to FIGS. 15 and 16, a first thickness compensation pattern (TCP1) can be formed by etching a first pre-insulating layer (PIL1), a first pre-conducting layer (PCL1), a second pre-insulating layer (PIL2), and a second pre-conducting layer (PCL2) through a first etching process (S300).

[0144] As illustrated in FIG. 15, a first photoresist pattern (PR1) can be formed on a second preconductive layer (PCL2). The first photoresist pattern (PR1) can be formed by applying a photosensitive organic film on the second preconductive layer (PCL2) and through an exposure process using a photomask. Specifically, through the exposure process, a portion of the photosensitive organic film that overlaps with the second subpixel region (SPA2) and the third subpixel region (SPA3) may remain to form the first photoresist pattern (PR1). That is, the first photoresist pattern (PR1) can overlap with the second pixel electrode (PE2) and the third pixel electrode (PE3), respectively, on a planar surface. For example, the upper surface of the first photoresist pattern (PR1) may have a convex shape in cross-section.

[0145] As illustrated in FIG. 16, a first pre-insulating layer (PIL1), a first pre-conducting layer (PCL1), a second pre-insulating layer (PIL2), and a second pre-conducting layer (PCL2) can be patterned through a first etching process using a first photoresist pattern (PR1) as a mask. Accordingly, parts of the first pre-insulating layer (PIL1), the first pre-conducting layer (PCL1), the second pre-insulating layer (PIL2), and the second pre-conducting layer (PCL2) that are spaced apart from the first photoresist pattern (PR1) in a plane can be removed. That is, parts of the first pre-insulating layer (PIL1), the first pre-conducting layer (PCL1), the second pre-insulating layer (PIL2), and the second pre-conducting layer (PCL2) that overlap with the first photoresist pattern (PR1) in a plane can remain. In the above first etching process, the first to third pixel electrodes (PE1, PE2, PE3) may not be etched.

[0146] In one embodiment, the first preliminary conductive layer (PCL1) and the second preliminary conductive layer (PCL2) may be patterned through a wet etch process, and the first preliminary insulating layer (PIL1) and the second preliminary insulating layer (PIL2) may be patterned through a dry etch process. However, the present invention is not limited thereto. In one embodiment, the first preliminary insulating layer (PIL1), the first preliminary conductive layer (PCL1), the second preliminary insulating layer (PIL2), and the second preliminary conductive layer (PCL2) may be patterned through a wet etch process.

[0147] A first thickness compensation pattern (TCP1) may be formed by overlapping with a third sub-pixel region (SPA3) through the first etching process and sequentially stacking a first insulating pattern (ILP1), a first conductive pattern (CDP1), a second insulating pattern (ILP2), and a second conductive pattern (CDP2) on a third pixel electrode (PE3). The first insulating pattern (ILP1) and the first conductive pattern (CDP1) may constitute a first lower thickness compensation pattern (TCP1a), and the second insulating pattern (ILP2) and the second conductive pattern (CDP2) may constitute a first upper thickness compensation pattern (TCP1b).

[0148] Through the first etching process above, a third insulating pattern (ILP3), a third conductive pattern (CDP3), a fourth insulating pattern (ILP4), and a fourth conductive pattern (CDP4) can be formed by overlapping with the second sub-pixel region (SPA2) and sequentially stacking on the second pixel electrode (PE2). The third insulating pattern (ILP3) and the third conductive pattern (CDP3) can form a second lower thickness compensation pattern (TCP2a), and the fourth insulating pattern (ILP4) and the fourth conductive pattern (CDP4) can form a second upper thickness compensation pattern (TCP2b).

[0149] That is, the third insulation pattern (ILP3) and the first insulation pattern (ILP1) may contain the same material and may be formed through the same process. The third conductivity pattern (CDP3) and the first conductivity pattern (CDP1) may contain the same material and may be formed through the same process. The fourth insulation pattern (ILP4) and the second insulation pattern (ILP2) may contain the same material and may be formed through the same process. The fourth conductivity pattern (CDP4) and the second conductivity pattern (CDP2) may contain the same material and may be formed through the same process.

[0150] Through the first etching process above, the first pre-insulating layer (PIL1), the first pre-conducting layer (PCL1), the second pre-insulating layer (PIL2), and the second pre-conducting layer (PCL2) that overlap with the first sub-pixel area (SPA1) can be removed.

[0151] After the first pre-insulating layer (PIL1), the first pre-conducting layer (PCL1), the second pre-insulating layer (PIL2), and the second pre-conducting layer (PCL2) are patterned through the first etching process using the first photoresist pattern (PR1) as a mask, the first photoresist pattern (PR1) can be removed.

[0152] In one embodiment, after the first pre-insulating layer (PIL1), the first pre-conducting layer (PCL1), the second pre-insulating layer (PIL2), and the second pre-conducting layer (PCL2) are patterned, a portion of the first to fourth insulating patterns (ILP1, ILP2, ILP3, ILP4) may be removed through an additional etching process. Specifically, a portion of the side of each of the first to fourth insulating patterns (ILP1, ILP2, ILP3, ILP4) may be removed. Accordingly, as described above with reference to FIGS. 6 and 7, the side of the first to fourth insulating patterns (ILP1, ILP2, ILP3, ILP4) may have a recessed structure.

[0153] Referring to FIG. 17, an anode connection pattern (e.g., a first anode connection pattern (ACP1)) can be formed that covers the side of the first thickness compensation pattern (TCP1) and contacts the third pixel electrode (PE3), the first conductive pattern (CDP1), and the second conductive pattern (CDP2) (S400). For example, the first anode connection pattern (ACP1) can be patterned through a wet etching process.

[0154] A first anode connection pattern (ACP1) may be formed on a third pixel electrode (PE3) in a third subpixel area (SPA3). The first anode connection pattern (ACP1) may be in contact with the edge of the third pixel electrode (PE3). In one embodiment, the first anode connection pattern (ACP1) may be spaced apart from the central part of the third pixel electrode (PE3) on a plane.

[0155] The first anode connection pattern (ACP1) can cover the side of the first thickness compensation pattern (TCP1). In one embodiment, the first anode connection pattern (ACP1) can completely surround the first thickness compensation pattern (TCP1) on a plane. The first anode connection pattern (ACP1) can come into contact with the side of the first insulation pattern (ILP1), the side of the first conductive pattern (CDP1), the side of the second insulation pattern (ILP2), and the side of the second conductive pattern (CDP2). Additionally, the first anode connection pattern (ACP1) can come into contact with the upper surface of the second conductive pattern (CDP2). The first anode connection pattern (ACP1) can electrically connect the third pixel electrode (PE3), the first conductive pattern (CDP1), and the second conductive pattern (CDP2).

[0156] A second anode connection pattern (ACP2) may be formed on the second pixel electrode (PE2) in the second subpixel area (SPA2). The second anode connection pattern (ACP2) may be in contact with the edge of the second pixel electrode (PE2). In one embodiment, the second anode connection pattern (ACP2) may be spaced apart from the central part of the second pixel electrode (PE2) on a plane.

[0157] The second anode connection pattern (ACP2) can be in contact with the side of the third insulation pattern (ILP3), the side of the third conductivity pattern (CDP3), the side of the fourth insulation pattern (ILP4), and the side of the fourth conductivity pattern (CDP4). Additionally, the second anode connection pattern (ACP2) can be in contact with the upper surface of the fourth conductivity pattern (CDP4). The second anode connection pattern (ACP2) can electrically connect the second pixel electrode (PE2) and the third conductivity pattern (CDP3).

[0158] Referring to FIGS. 18 and 19, the fourth insulating pattern (ILP4) and the fourth conductive pattern (CDP4) can be removed through a second etching process (S500).

[0159] As illustrated in FIG. 18, a second photoresist pattern (PR2) may be formed on a via insulating layer (VIA). The second photoresist pattern (PR2) may be formed entirely over the first to third sub-pixel regions (SPA1, SPA2, SPA3). The second photoresist pattern (PR2) may cover the first pixel electrode (PE1), the second pixel electrode (PE2), the third pixel electrode (PE3), the first thickness compensation pattern (TCP1), and the first anode connection pattern (ACP1). That is, the second photoresist pattern (PR2) may protect the first to third pixel electrodes (PE1, PE2, PE3), the first thickness compensation pattern (TCP1), and the first anode connection pattern (ACP1) from the etching solution.

[0160] In one embodiment, the second photoresist pattern (PR2) can cover the second anode connection pattern (ACP2) and expose a portion of the upper surface of the fourth conductive pattern (CDP4). That is, the second photoresist pattern (PR2) can protect the second anode connection pattern (ACP2) from the etching solution.

[0161] As shown in FIG. 19, the fourth insulating pattern (ILP4) and the fourth conductive pattern (CDP4) can be removed through a second etching process using the second photoresist pattern (PR2) as a mask.

[0162] In one embodiment, the fourth conductive pattern (CDP4) may be removed through a wet etching process, and the fourth insulating pattern (ILP4) may be removed through a dry etching process. However, the present invention is not limited thereto. In one embodiment, the fourth conductive pattern (CDP4) and the fourth insulating pattern (ILP4) may be removed through a wet etching process.

[0163] Through the above second etching process, the fourth insulation pattern (ILP4) and the fourth conductivity pattern (CDP4) can be removed, and a second thickness compensation pattern (TCP2) including the third insulation pattern (ILP3) and the third conductivity pattern (CDP3) can be formed.

[0164] In one embodiment, the second etching process may be an isotropic etching process. In this case, as shown in FIG. 19, the second anode connection pattern (ACP2) may be spaced apart from the upper surface of the second thickness compensation pattern (TCP2) (specifically, the upper surface of the third conductivity pattern (CDP3)). That is, a space may be formed between the second anode connection pattern (ACP2) and the second thickness compensation pattern (TCP2).

[0165] In one embodiment, the second etching process may be an anisotropic etching process. In this case, as described above with reference to FIGS. 10 and 11, a portion of the fourth insulating pattern (ILP4) and a portion of the fourth conductive pattern (CDP4) that overlap in a plane with the second anode connection pattern (ACP2) may not be removed. In other words, after the second etching process, a portion of the fourth insulating pattern (ILP4) and a portion of the fourth conductive pattern (CDP4) may remain, and a residual pattern (RTP, see FIG. 11) may be formed.

[0166] After the fourth insulating pattern (ILP4) and the fourth conductive pattern (CDP4) are removed through the second etching process using the second photoresist pattern (PR2) as a mask, the second photoresist pattern (PR2) can be removed.

[0167] Referring to FIG. 20, a pixel defining film (PDL) may be formed on a via insulating layer (VIA) (S600). An opening may be formed in the pixel defining film (PDL) to expose the upper surface of each of the first pixel electrode (PE1), the first thickness compensation pattern (TCP1), and the second thickness compensation pattern (TCP2). The pixel defining film (PDL) may cover the first anode connection pattern (ACP1) and the second anode connection pattern (ACP2).

[0168] Referring to FIG. 21, an organic layer (OL) may be formed on a pixel defining film (PDL), a first pixel electrode (PE1), a second pixel electrode (PE2), and a third pixel electrode (PE3) (S700). For example, the organic layer (OL) may be formed on a second thickness compensation pattern (TCP2) in a second sub-pixel area (SPA2) and on a first thickness compensation pattern (TCP1) in a third sub-pixel area (SPA3). The organic layer (OL) may be continuously extended across the first sub-pixel area (SPA1), the second sub-pixel area (SPA2), and the third sub-pixel area (SPA3).

[0169] The organic layer (OL) may include a first light-emitting layer (EML1, see FIG. 5), a second light-emitting layer (EML2, see FIG. 5), and a third light-emitting layer (EML3, see FIG. 5). The first light-emitting layer (EML1) may be formed on a first pixel electrode (PE1), the second light-emitting layer (EML2) may be formed on a second pixel electrode (PE2), and the third light-emitting layer (EML3) may be formed on a third pixel electrode (PE3). In one embodiment, the first light-emitting layer (EML1) may overlap with a first sub-pixel region (SPA1), the second light-emitting layer (EML2) may overlap with first to third sub-pixel regions (SPA1, SPA2, SPA3), and the third light-emitting layer (EML3) may overlap with a third sub-pixel region (SPA3).

[0170] The first light-emitting layer (EML1), the second light-emitting layer (EML2), and the third light-emitting layer (EML3) can emit light having different colors from each other. That is, the first light-emitting layer (EML1) can emit first light, the second light-emitting layer (EML2) can emit second light having a color different from the first light, and the third light-emitting layer (EML3) can emit third light having a color different from the first light and the second light. For example, the first light may be red light, the second light may be green light, and the third light may be blue light. However, the present invention is not limited thereto.

[0171] A common electrode (CE) can be formed on an organic layer (OL). The common electrode (CE) can be continuously extended across first to third subpixel regions (SPA1, SPA2, SPA3). The common electrode (CE) can be formed along the profile of the organic layer (OL) with a substantially uniform thickness.

[0172] The encapsulation layer (TFE) can be formed on the common electrode (CE). The encapsulation layer (TFE) can prevent impurities, moisture, etc. from penetrating into the first to third light-emitting elements (LD1, LD2, LD3) from the outside. The encapsulation layer (TFE) may include at least one inorganic encapsulation layer and at least one organic encapsulation layer.

[0173] FIG. 22 is a block diagram of an electronic device according to one embodiment of the present invention.

[0174] Referring to FIG. 22, an electronic device (10) according to one embodiment of the present invention may include a display module (11), a processor (12), a memory (13), and a power module (14). The display device according to the embodiment may be applied to various electronic devices. An electronic device (10) according to one embodiment includes the display device described above and may further include a module or device having additional functions other than the display device.

[0175] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0176] The memory (13) may store data information necessary for the operation of the processor (12) or the display module (11). When the processor (12) executes an application stored in the memory (13), an image data signal and / or an input control signal are transmitted to the display module (11), and the display module (11) can process the received signal and output image information through a display screen.

[0177] The power module (14) may include a power supply module, such as a power adapter or a battery device, and a power conversion module that converts the power supplied by the power supply module to generate power necessary for the operation of the electronic device (10). That is, the power module (14) can supply power to the display device according to the embodiments described above.

[0178] At least one of each component of the electronic device (10) described above may be included in a display device according to the embodiments described above. Additionally, some of the individual modules functionally included in one module may be included in the display device, while others may be provided separately from the display device. For example, the display device may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (10) other than the display device.

[0179] FIG. 23 is a schematic diagram of an electronic device according to various embodiments.

[0180] Referring to FIG. 23, various electronic devices to which a display device according to the embodiments is applied may include not only image display electronic devices such as a smartphone (10_1a), tablet PC (10_1b), laptop (10_1c), TV (10_1d), and desk monitor (10_1e), but also wearable electronic devices including display modules such as smart glasses (10_2a), head-mounted display (10_2b), and smart watch (10_2c), and automotive electronic devices (10_3) including display modules such as a CID (Center Information Display) and room mirror display placed on the instrument panel, center fascia, and dashboard of a car.

[0181] Although the present invention has been described above with reference to exemplary embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as set forth in the following claims. Industrial applicability

[0182] The present invention can be applied to various display devices capable of being equipped with a display device. For example, the present invention can be applied to various display devices such as display devices for vehicles, ships, and aircraft, portable communication devices, display devices for exhibition or information transmission, medical display devices, etc. Explanation of the symbols

[0183] DD, DD`, DD2, DD2`, DD3: Display device SUB: Substrate SPA1: 1st subpixel area SPA2: Second subpixel area SPA3: Third subpixel area PE1: 1st pixel electrode PE2: Second pixel electrode PE3: Third pixel electrode TCP1: First thickness compensation pattern ILP1, ILP1`: First insulation pattern CDP1: 1st Challenge Pattern ILP2, ILP2': Second insulation pattern CDP2: 2nd Challenge Pattern ACP1: First anode connection pattern ACP2: Second anode connection pattern EML1: First light-emitting layer EML2: Second light-emitting layer EML3: Third light-emitting layer TCP2: Second thickness compensation pattern ILP3: Third insulation pattern CDP3: Third Challenge Pattern RIP: Residual insulation pattern RCP: Remaining Challenge Pattern PIL1: First pre-insulation layer PCL1: 1st Preliminary Challenge Layer PIL2: Second pre-insulation layer PCL2: 2nd Reserve Challenge Layer ILP4: 4th insulation pattern CDP4: 4th Challenge Pattern 10: Electronic devices 12: Processor

Claims

Claim 1 A substrate comprising a first subpixel area, a second subpixel area, and a third subpixel area; a first pixel electrode disposed in the first subpixel area on the substrate; a second pixel electrode disposed in the second subpixel area on the substrate; a third pixel electrode disposed in the third subpixel area on the substrate; a first thickness compensation pattern comprising a first insulating pattern, a first conductive pattern, a second insulating pattern, and a second conductive pattern sequentially stacked on the third pixel electrode and overlapping with the third subpixel area; a first anode connection pattern disposed on the third pixel electrode, covering the side of the first thickness compensation pattern, and contacting the third pixel electrode, the first conductive pattern, and the second conductive pattern; a first light-emitting layer disposed on the first pixel electrode and emitting a first light; a second light-emitting layer disposed on the second pixel electrode and emitting a second light having a color different from the first light; A display device comprising a third light-emitting layer disposed on the third pixel electrode and emitting a third light having a color different from the first light and the second light. Claim 2 A display device according to claim 1, characterized in that the thickness of the first insulating pattern and the thickness of the second insulating pattern are greater than the thickness of the first conductive pattern and the thickness of the second conductive pattern. Claim 3 A display device according to claim 1, wherein each of the first insulating pattern and the second insulating pattern comprises silicon oxide, and each of the first conductive pattern and the second conductive pattern comprises a transparent conductive oxide. Claim 4 A display device according to claim 1, characterized in that the first anode connection pattern completely surrounds the first thickness compensation pattern on a plane. Claim 5 A display device according to claim 1, characterized in that the first anode connection pattern contacts the edge of the third pixel electrode and is spaced apart from the central part of the third pixel electrode on a plane. Claim 6 A display device according to claim 1, characterized in that the side of the first conductive pattern protrudes further in a direction away from the center of the first thickness compensation pattern than the side of the first insulating pattern, and the side of the second conductive pattern protrudes further in a direction away from the center of the first thickness compensation pattern than the side of the second insulating pattern. Claim 7 A display device according to claim 6, wherein the first anode connection pattern is in contact with the lower surface of the first conductive pattern and the lower surface of the second conductive pattern. Claim 8 A display device according to claim 1, further comprising: a second thickness compensation pattern that overlaps with the second subpixel area and includes a third insulating pattern and a third conductive pattern sequentially stacked on the second pixel electrode; and a second anode connection pattern disposed on the second pixel electrode, covering the side of the second thickness compensation pattern and contacting the second pixel electrode and the third conductive pattern. Claim 9 A display device according to claim 8, wherein the first insulating pattern and the third insulating pattern comprise the same material, and the first conductive pattern and the third conductive pattern comprise the same material. Claim 10 A display device according to claim 8, wherein the second anode connection pattern is spaced apart from the upper surface of the second thickness compensation pattern. Claim 11 A display device according to claim 8, wherein the second thickness compensation pattern is disposed on the third conductivity pattern and further comprises a residual insulation pattern overlapping with the edge of the third conductivity pattern and a residual conductivity pattern disposed on the residual insulation pattern. Claim 12 A display device according to claim 11, characterized in that the second anode connection pattern overlaps the entirety of the residual insulation pattern and the entirety of the residual conductivity pattern on a plane. Claim 13 A display device according to claim 1, wherein the first light-emitting layer overlaps with the first sub-pixel area, the second light-emitting layer overlaps with the first to third sub-pixel areas, and the third light-emitting layer overlaps with the third sub-pixel area. Claim 14 A step of forming a first pixel electrode overlapping the first subpixel area, a second pixel electrode overlapping the second subpixel area, and a third pixel electrode overlapping the third subpixel area on a substrate including a first subpixel area, a second subpixel area, and a third subpixel area; a step of forming a first pre-insulating layer covering the first to third pixel electrodes on the substrate; a step of sequentially forming a first pre-conducting layer, a second pre-insulating layer, and a second pre-conducting layer on the first pre-insulating layer; a step of etching the first pre-insulating layer, the first pre-conducting layer, the second pre-insulating layer, and the second pre-conducting layer through a first etching process to form a first thickness compensation pattern including a first insulating pattern, a first conductive pattern, a second insulating pattern, and a second conductive pattern sequentially stacked on the third pixel electrode, overlapping the third subpixel area; a step of forming an anode connection pattern covering the side of the first thickness compensation pattern and contacting the third pixel electrode, the first conductive pattern, and the second conductive pattern; the first pixel A method for manufacturing a display device comprising: a step of forming a first light-emitting layer that emits a first light on an electrode; a step of forming a second light-emitting layer that emits a second light having a color different from the first light on the second pixel electrode; and a step of forming a third light-emitting layer that emits a third light having a color different from the first light and the second light on the third pixel electrode. Claim 15 A method for manufacturing a display device according to claim 14, wherein the thickness of the first pre-insulating layer and the thickness of the second pre-insulating layer are greater than the thickness of the first pre-conductive layer and the thickness of the second pre-conductive layer. Claim 16 A method for manufacturing a display device according to claim 14, further comprising, after the step of forming the first thickness compensation pattern, a step of removing a portion of the side of the first insulating pattern and a portion of the side of the second insulating pattern through an additional etching process. Claim 17 A method for manufacturing a display device according to claim 14, wherein the step of etching the first pre-insulating layer, the first pre-conducting layer, the second pre-insulating layer and the second pre-conducting layer through the first etching process comprises the step of overlapping with the second sub-pixel region and forming a third insulating pattern, a third conductive pattern, a fourth insulating pattern and a fourth conductive pattern sequentially stacked on the second pixel electrode. Claim 18 A method for manufacturing a display device according to claim 17, further comprising the step of removing the fourth insulating pattern and the fourth conductive pattern through a second etching process. Claim 19 A method for manufacturing a display device according to claim 18, wherein the second etching process is an anisotropic etching process, and a portion of the fourth insulating pattern and a portion of the fourth conductive pattern remain after the second etching process. Claim 20 A display device comprising first to third light-emitting layers; and a processor that transmits an image data signal and an input control signal to the display device, wherein the display device comprises A substrate including a first subpixel area, a second subpixel area and a third subpixel area; A first pixel electrode disposed in the first subpixel area on the substrate; A second pixel electrode disposed in the second subpixel area on the substrate; A third pixel electrode disposed in the third sub-pixel area on the substrate; A thickness compensation pattern comprising a first insulating pattern, a first conductive pattern, a second insulating pattern, and a second conductive pattern sequentially stacked on the third pixel electrode, and overlapping with the third sub-pixel area; An anode connection pattern disposed on the third pixel electrode, covering the side of the thickness compensation pattern, and in contact with the third pixel electrode, the first conductive pattern, and the second conductive pattern; The first light-emitting layer disposed on the first pixel electrode and emitting a first light; The second light-emitting layer disposed on the second pixel electrode and emitting second light having a color different from the first light; and An electronic device comprising a third light-emitting layer disposed on the third pixel electrode and emitting a third light having a color different from the first light and the second light.

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