Display device and electronic device

Abstract

The electronic device includes a display panel comprising a first pixel connected to a first data line and a second pixel connected to a second data line, a scan driving circuit that outputs a scan signal, a data driving circuit that outputs a data signal, and a demultiplexer that provides the data signal to the first data line and the second data line, wherein the demultiplexer includes a switching circuit that transmits the data signal to the first data line in response to a first switching signal and transmits the data signal to the second data line in response to a second switching signal, and a bypass circuit that discharges the current of the first data line and the current of the second data line to a bypass voltage line in response to a third switching signal.

Description

Technology Field

[0001] The present invention relates to a display device and an electronic device for displaying images. Background Technology

[0002] Electronic devices such as televisions, mobile phones, tablet computers, navigation systems, and game consoles generate images and provide the generated images to the user through a display screen.

[0003] The electronic device includes a plurality of pixels and driving circuits that control an image to be displayed on the plurality of pixels. Each of the plurality of pixels includes a light-emitting element and transistors that control the light-emitting element. The problem to be solved

[0004] The objective of the present invention is to provide a display device and an electronic device with improved image display quality. means of solving the problem

[0005] According to one feature of the present invention for achieving the above purpose, an electronic device comprises a display panel including a first pixel connected to a first data line and a scan line and a second pixel connected to a second data line and a scan line, a scan driving circuit that outputs a scan signal to the scan line, a data driving circuit that outputs a data signal, and a demultiplexer that provides the data signal to the first data line and the second data line, wherein the demultiplexer comprises a switching circuit that transmits the data signal to the first data line in response to a first switching signal and transmits the data signal to the second data line in response to a second switching signal, and a bypass circuit that electrically connects the first data line and the second data line to a bypass voltage line in response to a third switching signal.

[0006] In one embodiment, the bypass circuit may include a first bypass transistor connected between the first data line and the bypass voltage line and turned on in response to the third switching signal, and a second bypass transistor connected between the second data line and the bypass voltage line and turned on in response to the third switching signal.

[0007] In one embodiment, a ground voltage may be provided to the bypass voltage line.

[0008] In one embodiment, the active level interval of the scan signal and the active level interval of the third switching signal may not overlap.

[0009] In one embodiment, the demultiplexer may be placed on the display panel.

[0010] A display device according to one feature of the present invention comprises a display panel including a plurality of first data lines and a plurality of first pixels connected to a scan line, a plurality of second data lines and a plurality of second pixels connected to the scan line, a scan driving circuit that outputs a scan signal to the scan line, a data driving circuit that outputs a plurality of data signals, and a demultiplexer that provides the plurality of data signals to the plurality of first data lines and the plurality of second data lines, wherein the demultiplexer comprises a switching circuit that transmits the plurality of data signals to the plurality of first data lines in response to a first switching signal and transmits the plurality of data signals to the plurality of second data lines in response to a second switching signal, and a bypass circuit that connects the plurality of first data lines to a bypass voltage line and connects the plurality of second data lines to a bypass voltage line in response to a third switching signal.

[0011] In one embodiment, the bypass circuit may include a plurality of bypass transistors, each of which is connected between a corresponding data line among the plurality of first data lines and the plurality of second data lines and the bypass voltage line, and is turned on in response to the third switching signal.

[0012] In one embodiment, a ground voltage may be provided to the bypass voltage line.

[0013] In one embodiment, the active level interval of the scan signal and the active level interval of the third switching signal may not overlap.

[0014] In one embodiment, the display panel includes an edge region and a center region arranged sequentially in a first direction, the scan driving circuit is arranged adjacent to the edge region, and the size of the bypass transistor corresponding to the center region among the plurality of bypass transistors may be larger than the size of the bypass transistor corresponding to the edge region.

[0015] In one embodiment, the display panel includes a center region and an edge region arranged sequentially in a first direction, the scan driving circuit is arranged adjacent to the edge region, each of the plurality of bypass transistors is arranged sequentially in the first direction, and the size of each of the plurality of bypass transistors can be progressively reduced as it goes toward the first direction.

[0016] In one embodiment, the display panel includes a center area and an edge area arranged sequentially in a first direction, the scan driving circuit is arranged adjacent to the edge area, each of the plurality of bypass transistors is arranged sequentially in the first direction, and the third switching signal can be provided sequentially from the bypass transistor corresponding to the center area to the bypass transistor corresponding to the edge area among the plurality of bypass transistors.

[0017] In one embodiment, the display panel includes a center area and an edge area sequentially arranged in a first direction, and the data driving circuit includes a first driving circuit corresponding to the center area and a second driving circuit corresponding to the edge area, and the first driving circuit can provide the third switching signal to a clock line.

[0018] In one embodiment, each of the plurality of first pixels may include a first transistor having a gate electrode connected between a first node and a second node, a second transistor having a gate electrode receiving the scan signal connected between any one of the plurality of first data lines and the first node, and a third transistor having a gate electrode receiving the scan signal connected between the second node and the gate electrode of the first transistor.

[0019] An electronic device according to one feature of the present invention comprises a processor that outputs an image signal and a control signal, and a display module that displays an image in response to the image signal and the control signal, wherein the display module comprises a display panel including a first pixel connected to a first data line and a scan line and a second pixel connected to a second data line and the scan line, a scan driving circuit that outputs a scan signal to the scan line, a data driving circuit that outputs a data signal, and a demultiplexer that provides the data signal to the first data line and the second data line, wherein the demultiplexer may include a switching circuit that transmits the data signal to the first data line in response to a first switching signal and transmits the data signal to the second data line in response to a second switching signal, and a bypass circuit that electrically connects the first data line and the second data line to a bypass voltage line in response to a third switching signal.

[0020] In one embodiment, the bypass circuit includes a first bypass transistor connected between the first data line and the bypass voltage line and turned on in response to the third switching signal, and a second bypass transistor connected between the second data line and the bypass voltage line and turned on in response to the third switching signal, and a ground voltage may be provided to the bypass voltage line.

[0021] In one embodiment, the display panel includes a display area and a non-display area adjacent to the display area, the first pixel and the second pixel are disposed in the display area, the demultiplexer is disposed in the non-display area, and the demultiplexer may include at least one bypass transistor.

[0022] In one embodiment, the active level interval of the scan signal and the active level interval of the third switching signal may not overlap.

[0023] In one embodiment, the display panel receives a first driving voltage, a second driving voltage, a first initialization voltage, and a second initialization voltage, and the bypass voltage line may be electrically connected to a voltage line that transmits any one of the second driving voltage, the first initialization voltage, and the second initialization voltage.

[0024] In one embodiment, the display panel includes a center area and an edge area sequentially arranged in a first direction, the scan driving circuit is arranged adjacent to the edge area, the data driving circuit includes a first driving circuit corresponding to the center area and a second driving circuit corresponding to the edge area, and the first driving circuit can provide the third switching signal to a clock line. Effects of the invention

[0025] An electronic device having such a configuration can reduce the production cost of a display device by including a demultiplexer for connecting the output lines of a data driving circuit to data lines. Furthermore, the demultiplexer may include a bypass circuit to discharge a portion of the data signal provided to the data lines through the bypass circuit. In particular, the charging current of the data signal provided to pixels located in the center area of ​​the display panel is discharged through the bypass circuit, thereby compensating for the difference in brightness between the center area and the edge area of ​​the display panel. Therefore, the display quality of the image displayed on the electronic device can be improved. Brief explanation of the drawing

[0026] FIG. 1 is a block diagram of an electronic device according to one embodiment. FIG. 2 is a schematic diagram of electronic devices according to various embodiments. Figure 3 is a plan view schematically showing the display module. FIG. 4 is a block diagram of a display module according to one embodiment of the present invention. FIG. 5 is a circuit diagram of a pixel according to one embodiment of the present invention. FIG. 6 shows the circuit configuration of a demultiplexer according to one embodiment of the present invention. FIG. 7a exemplarily shows a voltage corresponding to a data signal provided by the first data line, scan signals provided by the i-th scan lines, and a third switching signal. FIG. 7b exemplarily shows a voltage corresponding to a data signal provided to the m / 2nd data line, scan signals provided to the i-th scan lines, and a third switching signal. FIG. 8a is a diagram illustrating the operation of a pixel placed in an edge region. FIG. 8b is a diagram illustrating the operation of a pixel placed in a central area. Figures 9a and 9b are drawings that exemplarily show images displayed on a display panel. Figure 10 is a plan view schematically showing the display module. FIG. 11a exemplarily shows a voltage corresponding to a data signal provided by a first data line, scan signals provided by i-th scan lines, and a third switching signal. FIG. 11b exemplarily shows a voltage corresponding to a data signal provided to the m / 2nd data line, scan signals provided to the i-th scan lines, and a third switching signal. Specific details for implementing the invention

[0027] In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "combined" with another component, it means that it may be directly placed / connected / combined with the other component, or that a third component may be placed between them.

[0028] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated for the effective illustration of the technical content. "And / or" includes all of one or more combinations that the associated components may define.

[0029] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0030] Additionally, terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0031] Terms such as "include" or "have" are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0033] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0034] FIG. 1 is a block diagram of an electronic device (10) according to one embodiment.

[0035] Referring to FIG. 1, an electronic device (10) according to one embodiment may include a display module (DM), a processor (PP), a memory (MM), and a power module (PM).

[0036] The processor (PP) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0037] The memory (MM) may store data information necessary for the operation of the processor (PP) or the display module (DM). When the processor (PP) executes an application stored in the memory (MM), video data signals and / or input control signals are transmitted to the display module (DM), and the display module (DM) can process the received signals to output video information through a display screen.

[0038] The power module (PM) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power required for the operation of the electronic device (10).

[0040] FIG. 2 is a schematic diagram of electronic devices according to various embodiments.

[0041] Referring to FIG. 2, various electronic devices according to the embodiments may include not only image display electronic devices such as a smartphone (10_1a), tablet PC (10_1b), laptop (10_1c), TV (10_1d), and desk monitor (10_1e), but also wearable electronic devices including display modules such as smart glasses (10_2a), head-mounted display (10_2b), and smart watch (10_2c), and automotive electronic devices (10_3) including display modules such as a CID (Center Information Display) and room mirror display placed on the instrument panel, center fascia, and dashboard of a car.

[0043] Figure 3 is a plan view schematically showing a display module (DM).

[0044] Referring to FIG. 3, the display module (DM) may include a display panel (DP), a main circuit board (MCB), flexible circuit films (D-FCB), driving circuits (DIC) and a driving controller (100). In one embodiment, the display module (DM) may be referred to as a display device.

[0045] A display panel (DP) according to one embodiment of the present invention may be a light-emitting display panel that displays an image.

[0046] The main circuit board (MCB) can be connected to flexible circuit films (D-FCB) and electrically connected to a display panel (DP). The flexible circuit films (D-FCB) are connected to the display panel (DP) to electrically connect the display panel (DP) and the main circuit board (MCB). The main circuit board (MCB) may further include a plurality of elements. Each of the plurality of elements may include a circuit portion for driving the display panel (DP). Driving circuits (DIC) may be mounted on the flexible circuit films (D-FCB).

[0047] In one example of the present invention, flexible circuit films (D-FCB) may include a first flexible circuit film (D-FCB1), a second flexible circuit film (D-FCB2), a third flexible circuit film (D-FCB3), and a fourth flexible circuit film (D-FCB4). Driving circuits (DIC) may include a first driving circuit (DIC1), a second driving circuit (DIC2), a third driving circuit (DIC3), and a fourth driving circuit (DIC4). The first to fourth flexible circuit films (D-FCB1, D-FCB2, D-FCB3, D-FCB4) may be spaced apart in a first direction (DR1). The first to fourth flexible circuit films (D-FCB1, D-FCB2, D-FCB3, D-FCB4) may be connected to a display panel (DP) to electrically connect the display panel (DP) and the main circuit board (MCB). First to fourth driving circuits (DIC1, DIC2, DIC3, DIC4) may each be mounted on the first to fourth flexible circuit films (D-FCB1, D-FCB2, D-FCB3, D-FCB4). However, embodiments of the present invention are not limited thereto. For example, a display panel (DP) may be electrically connected to a main circuit board (MCB) through a single flexible circuit film, and only one driving circuit may be mounted on the single flexible circuit film. Additionally, a display panel (DP) may be electrically connected to a main circuit board (MCB) through two or more flexible circuit films, and driving circuits may each be mounted on the flexible circuit films. Furthermore, the first to fourth driving circuits (DIC1, DIC2, DIC3, DIC4) may be directly mounted on the main circuit board (MCB).

[0048] In the embodiment illustrated in FIG. 3, the display module (DM) is shown to include four driving circuits, namely the first to fourth driving circuits (DIC1, DIC2, DIC3, DIC4), but the present invention is not limited thereto. The display module (DM) may include one or more driving circuits.

[0049] The driving controller (100) may be mounted on a main circuit board (MCB). The driving controller (100) may be electrically connected to the first to fourth driving circuits (DIC1, DIC2, DIC3, DIC4) through the first to fourth flexible circuit films (D-FCB1, D-FCB2, D-FCB3, D-FCB4). Additionally, the driving controller (100) may be electrically connected to a display panel (DP) through the first to fourth flexible circuit films (D-FCB1, D-FCB2, D-FCB3, D-FCB4).

[0051] FIG. 4 is a block diagram of a display module (DM) according to one embodiment of the present invention.

[0052] Referring to FIG. 4, the display module (DM) includes a driving controller (100), a data driving circuit (200), a first scan driving circuit (300), a second scan driving circuit (400), and a display panel (DP).

[0053] The driving controller (100) receives an input video signal (RGB) and a control signal (CTRL). The input video signal (RGB) and the control signal (CTRL) may be provided from the processor (PP) shown in FIG. 1.

[0054] The driving controller (100) generates an output video signal (DS) that converts an input video signal (RGB) into a video type suitable for a display panel (DP). The driving controller (100) outputs a switching signal (SW), a first scan control signal (SCS1), a second scan control signal (SCS2), and a data control signal (DCS).

[0055] A display panel (DP) according to one embodiment of the present invention may be a light-emitting display panel. For example, the display panel (DP) may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of an inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots and quantum rods, etc. Hereinafter, in this embodiment, the display panel (DP) is described as an organic light-emitting display panel.

[0056] The display panel (DP) includes scan lines (GL1-GLn), data lines (DL1-DLm), and pixels (PX). In one embodiment, a first scan driving circuit (300) and a second scan driving circuit (400) may be disposed on the display panel (DP).

[0057] The display panel (DP) includes a display area (DA) and a non-display area (NDA). Pixels (PX) are placed in the display area (DA), and a first scan driving circuit (300) and a second scan driving circuit (400) may be placed in the non-display area (NDA).

[0058] The display area (DA) of the display panel (DP) can be divided into a center area (CA) and edge areas (EA1, EA2). The center area (CA) may be an area relatively far from the first scan driving circuit (300) or the second scan driving circuit (400) compared to the edge areas (EA1, EA2).

[0059] Each of the pixels (PX) can be electrically connected to the data driving circuit (200), the first scan driving circuit (300), and the second scan driving circuit (400), respectively.

[0060] Scan lines (GL1-GLn) (n is a positive integer) extend from the first scan driving circuit (300) in a first direction (DR1) and are arranged spaced apart from each other in a second direction (DR2). Additionally, scan lines (GL1-GLn) may extend from the second scan driving circuit (400) in the opposite direction of the first direction (DR1), i.e., in the second direction (DR2). That is, scan lines (GL1-GLn) may be connected in common to the first scan driving circuit (300) and the second scan driving circuit (400).

[0061] Data lines (DL1-DLm) (m is a positive integer) extend from the demultiplexer (500) in a second direction (DR2) and are arranged spaced apart from each other in a first direction (DR1).

[0062] Each pixel (PX) may be connected to a corresponding scan line among the scan lines (GL1-GLn) and may be connected to a corresponding data line among the data lines (DL1-DLm). Although FIG. 4 is illustrated with each of the plurality of pixels (PX) connected to one scan line, the present invention is not limited thereto. Each pixel (PX) may be electrically connected to two or more scan lines.

[0063] The data driving circuit (200) receives a data control signal (DCS) and an output image signal (DS) from the driving controller (100). The data driving circuit (200) converts the output image signal (DS) into data signals and outputs the data signals to output lines (YL1-YLs) (where s is a positive integer). Each of the data signals may have a voltage level corresponding to the grayscale level of the output image signal (DS). In one embodiment, the number of output lines (YL1-YLs) may be smaller than the number of data lines (DL1-DLm) (i.e., s <m).

[0064] The data driving circuit (200) may be implemented as an integrated circuit (IC) and directly mounted in a predetermined area of ​​the display panel (DP), or mounted on a separate printed circuit board in a chip-on-film (COF) manner and electrically connected to the display panel (DP). In one embodiment, the data driving circuit (200) may include the first to fourth driving circuits (DIC1, DIC2, DIC3, DIC4) shown in FIG. 3.

[0065] The first scan driving circuit (300) receives a first scan control signal (SCS1) from the driving controller (100). The first scan driving circuit (300) can output scan signals to scan lines (GL1-GLn) in response to the first scan control signal (SCS1).

[0066] The second scan driving circuit (400) receives a second scan control signal (SCS2) from the driving controller (100). The second scan driving circuit (400) can output scan signals to the scan lines (GL1-GLn) in response to the second scan control signal (SCS2).

[0067] In one embodiment, the first scan driving circuit (300) and the second scan driving circuit (400) can be formed by the same process as the pixels (PX).

[0068] FIG. 1 illustrates a first scan driving circuit (300) and a second scan driving circuit (400) disposed on a display panel (DP), but the present invention is not limited thereto. In one embodiment, only one of the first scan driving circuit (300) and the second scan driving circuit (400) may be disposed on the display panel (DP).

[0069] The driving controller (100), data driving circuit (200), first scan driving circuit (300), and second scan driving circuit (400) may be driving circuits for providing a data signal corresponding to an input image signal (RGB) to pixels (PX).

[0070] The demultiplexer (500) can electrically connect multiple output lines (YL1-YLs) and data lines (DL1-DLm) in response to a switching signal (SW) provided by the drive controller (100). The specific circuit configuration and operation of the demultiplexer (500) will be described in detail later.

[0071] In one embodiment, the demultiplexer (500) may be placed in the non-display area (NDA) of the display panel (DP).

[0072] FIG. 4 illustrates a demultiplexer (500) positioned on a display panel (DP), but the present invention is not limited thereto. In one embodiment, the demultiplexer (500) may be included within a data driving circuit (200). In one embodiment, the demultiplexer (500) may be provided on a separate driving circuit or circuit board independent of the display panel (DP) and the data driving circuit (200), respectively.

[0074] FIG. 5 is a circuit diagram of a pixel (PX) according to one embodiment of the present invention.

[0075] Referring to FIG. 5, a pixel (PX) includes a pixel circuit (PXC) comprising at least one transistor and at least one capacitor, and a light-emitting element (ED). The pixel (PX) illustrated in FIG. 5 includes first to seventh transistors (T1, T2, T3, T4, T5, T6, T7) and a capacitor (Cst). The pixel (PX) illustrated in FIG. 5 is merely an example, and the circuit configuration of the pixel (PX) can be varied in many ways.

[0076] In this embodiment, each of the first to seventh transistors (T1-T7) is a P-type transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer.

[0077] However, the present invention is not limited thereto. In one embodiment, at least one of the first to seventh transistors (T1-T7) may be an N-type transistor having an oxide semiconductor as the semiconductor layer, and the remainder may be P-type transistors.

[0078] In one embodiment, a pixel (PX) may be electrically connected to one data line (DLj), three scan lines (GILi, GWLi, GBLi), and one light-emitting line (EMLi). Each of the scan lines (GL1-GLn) shown in FIG. 4 may include a plurality of scan lines and at least one light-emitting line. In one embodiment, the i-th scan line (GLi) among the scan lines (GL1-GLn) shown in FIG. 4 may include three scan lines (GILi, GWLi, GBLi) and one light-emitting line (EMLi).

[0079] Scan lines (GILi, GWLi, GBLi) each transmit scan signals (GIi, GWi, GBi), and the light emission line (EMLi) can transmit a light emission control signal (EMi). The data line (DLj) transmits a data signal (Dj). The data signal (Dj) may have a voltage level corresponding to an image signal (RGB) input to a display module (DM, see FIG. 4). The first to fourth driving voltage lines (VL1, VL2, VL3, VL4) can transmit a first driving voltage (ELVDD), a second driving voltage (ELVSS), a first initialization voltage (VINT1), and a second initialization voltage (VINT2).

[0080] The first transistor (T1) is connected between the first node (N1) and the second node (N2) and includes a gate electrode connected to one end of the capacitor (Cst).

[0081] The second transistor (T2) is connected between the data line (DLj) and the first node (N1) and includes a gate electrode connected to the scan line (GWLi). The second transistor (T2) is turned on according to the scan signal (GWi) received through the scan line (GWLi) and can transmit the data signal (Dj) transmitted from the data line (DLj) to the first node (N1), that is, the first electrode of the first transistor (T1).

[0082] The third transistor (T3) is connected between the gate electrode of the first transistor (T1) and the second node (N2) and includes a gate electrode connected to the scan line (GWLi). The third transistor (T3) is turned on according to the scan signal (GWi) received through the scan line (GWLi) to connect the gate electrode of the first transistor (T1) and the second node (N2), that is, the second electrode of the first transistor (T1), to each other, thereby allowing the first transistor (T1) to be diode-connected.

[0083] The fourth transistor (T4) is connected between the gate electrode of the first transistor (T1) and the third driving voltage line (VL3) to which the first initialization voltage (VINT1) is transmitted, and includes a gate electrode connected to the scan line (GILi). The fourth transistor (T4) can be turned on according to the scan signal (GIi) received through the scan line (GILi) to transmit the first initialization voltage (VINT1) to the gate electrode of the first transistor (T1) and perform an initialization operation to initialize the voltage of the gate electrode of the first transistor (T1).

[0084] The fifth transistor (T5) is connected between the first driving voltage line (VL1) and the first node (N1) and includes a gate electrode connected to the light-emitting line (EMLi). The sixth transistor (T6) is connected between the second node (N2) and the light-emitting element (ED) and includes a gate electrode connected to the light-emitting line (EMLi). The fifth transistor (T5) and the sixth transistor (T6) can be turned on simultaneously according to a light-emitting control signal (EMi) received through the light-emitting line (EMLi). As the fifth transistor (T5) and the sixth transistor (T6) are turned on, a current path can be formed from the first driving voltage line (VL1) to the light-emitting element (ED) through the fifth transistor (T5), the first transistor (T1), and the sixth transistor (T6). At this time, the current flowing through the first transistor (T1) can correspond to the charge charged in the capacitor (Cst). Therefore, a current (Id) corresponding to the data signal (Dj) can be transmitted to the light-emitting element (ED). In other words, the data signal (Dj) can be converted into a current (Id) through the pixel (PX) and provided to the light-emitting element (ED).

[0085] The seventh transistor (T7) is connected between the light-emitting element (ED) and the fourth driving voltage line (VL4) and includes a gate electrode connected to the scan line (GBLi). The seventh transistor (T7) is turned on according to a scan signal (GBi) received through the scan line (GBLi) to initialize the anode of the light-emitting element (ED) to a second initialization voltage (VINT2) from the fourth driving voltage line (VL4).

[0086] One end of the capacitor (Cst) is connected to the gate electrode of the first transistor (T1) as described above, and the other end is connected to the first driving voltage line (VL1). The cathode of the light-emitting element (ED) can be connected to the second driving voltage line (VL2) that transmits the second driving voltage (ELVSS).

[0088] FIG. 6 shows the circuit configuration of a demultiplexer (500) according to one embodiment of the present invention.

[0089] Referring to FIG. 6, the demultiplexer (500) includes a switching circuit (510) and a bypass circuit (520). The switching circuit (510) includes first switching transistors (ST1, ST3, ST5, ST7) and second switching transistors (ST2, ST4, ST6, ST8).

[0090] The first switching transistor (ST1) is connected between the output line (YL1) and the data line (DL1). The first switching transistor (ST3) is connected between the output line (YL2) and the data line (DL3). The first switching transistor (ST5) is connected between the output line (YL3) and the data line (DL5). The first switching transistor (ST7) is connected between the output line (YL4) and the data line (DL7).

[0091] The second switching transistor (ST2) is connected between the output line (YL1) and the data line (DL2). The second switching transistor (ST4) is connected between the output line (YL2) and the data line (DL4). The second switching transistor (ST6) is connected between the output line (YL3) and the data line (DL6). The second switching transistor (ST8) is connected between the output line (YL4) and the data line (DL8).

[0092] Each of the first switching transistors (ST1, ST3, ST5, ST7, ST9) is turned on in response to the first switching signal (CLA). When each of the first switching transistors (ST1, ST3, ST5, ST7, ST9) is turned on, the output lines (YL1, YL2, YL3, Y4) can be electrically connected to the odd-numbered data lines (DL1, DL3, DL5, DL7).

[0093] Each of the second switching transistors (ST2, ST4, ST6, ST8) is turned on in response to the second switching signal (CLB). When each of the second switching transistors (ST2, ST4, ST6, ST8) is turned on, the output lines (YL1, YL2, YL3, Y4) can be electrically connected to the even-numbered data lines (DL2, DL4, DL6, DL8).

[0094] The bypass circuit (520) includes bypass transistors (BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8). Each of the bypass transistors (BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8) is connected between the data lines (DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8) and the fifth voltage line (VL5). Each of the bypass transistors (BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8) is turned on in response to a third switching signal (CLC). The third switching signal (CLC) can be transmitted to the gate electrodes of each of the bypass transistors (BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8) through the clock line (CKL).

[0095] When each of the bypass transistors (BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8) is turned on, a portion of the current flowing through the data lines (DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8) may be bypassed to the fifth voltage line (VL5). In one embodiment, a ground voltage (VG) may be provided to the fifth voltage line (VL5), but the invention is not limited thereto. In one embodiment, the ground voltage (VG) may be the same voltage as any one of the second driving voltage (ELVSS), the first initialization voltage (VINT1), and the second initialization voltage (VINT2). In this case, the fifth voltage line (VL5) may be electrically connected to any one of the second driving voltage line (VL2), the third driving voltage line (VL3), and the fourth driving voltage line (VL4).

[0096] In one embodiment, the fifth voltage line (VL5) may be electrically connected to any one of the voltage lines that transmit voltages required for the operation of the display panel (DP), as well as voltages required for the operation of the first scan driving circuit (300) or the second scan driving circuit (400).

[0097] In one embodiment, the fifth voltage line (VL5) may be called a bypass voltage line.

[0098] In one embodiment, the first switching transistors (ST1, ST3, ST5, ST7), the second switching transistors (ST2, ST4, ST6, ST8), and the bypass transistors (BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8) are each P-type transistors. The first switching transistors (ST1, ST3, ST5, ST7), the second switching transistors (ST2, ST4, ST6, ST8), and the bypass transistors (BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8) can each be formed by the same manufacturing process as the first to seventh transistors (T1, T2, T3, T4, T5, T6, T7) of the pixel (PX) shown in FIG. 5.

[0100] FIG. 7a exemplarily shows a voltage (Vdata) corresponding to a data signal (D1) provided as a first data line, scan signals (GIi, GWi) provided as i-th scan lines (GILi, GWLi), and a third switching signal (CLC).

[0101] FIG. 7b exemplarily shows a voltage (Vdata) corresponding to a data signal (Dm / 2) provided to the m / 2th data line, scan signals (GIi, GWi) provided to the i-th scan lines (GILi, GWLi), and a third switching signal (CLC).

[0102] Referring to FIGS. 4, FIGS. 7a and FIGS. 7b, the pixel (PX) receiving the data signal (D1) and scan signals (GIi, GWi) is a pixel (PX) placed in the edge region (EA1) of the display panel (DP). The pixel (PX) receiving the data signal (Dm / 2) and scan signals (GIi, GWi) is a pixel (PX) placed in the center region (CA) of the display panel (DP).

[0103] Referring to FIG. 4 and FIG. 7a, when the scan signal (GIi) transitions to a low level in the first interval (P1), the fourth transistor (T4) is turned on. The first initialization voltage (VINT1) is provided through the fourth transistor (T4) to the gate electrode of the first transistor (T1) and one end of the capacitor (Cst). The voltage at the gate electrode of the first transistor (T1) and one end of the capacitor (Cst) can be initialized to the first initialization voltage (VINT1).

[0104] When the scan signal (GWi) transitions to a low level in the second section (P2), the second transistor (T2) and the third transistor (T3) are turned on. The data signal (Di) received through the data line (DL1) is provided to one end of the capacitor (Cst) through the second transistor (T2), the first transistor (T1), and the third transistor (T3).

[0105] Subsequently, when the light emission signal (EMi) transitions to a low level, the fifth transistor (T5) and the sixth transistor (T6) are turned on. As the fifth transistor (T5) and the sixth transistor (T6) are turned on, a current (Id) corresponding to the data signal (Di) stored in the capacitor (Cst) is supplied to the light-emitting element (ED), and the light-emitting element (ED) emits light.

[0107] FIG. 8a is a diagram illustrating the operation of a pixel (PX) placed in an edge region (EA1).

[0108] FIG. 8b is a diagram illustrating the operation of a pixel (PX) placed in a central region (CA).

[0109] Referring to FIGS. 7a and 8a, the scan signal (GWi) provided to the pixel (PX) located in the edge region (EA1) adjacent to the first scan driving circuit (300) transitions from a low level to a high level at the beginning of the third interval (P3). Therefore, the second to seventh transistors (T2, T3, T4, T5, T6, T7) are all turned off.

[0110] Referring to FIGS. 7b and FIGS. 8b, a scan signal (GWi) provided to a pixel (PX) located in a central region (CA) far from the first scan driving circuit (300) and the second scan driving circuit (400) can be maintained at a low level at the beginning of the third interval (P3) by an RC delay. In this case, the second transistor (T2) and the third transistor (T3) can be kept in a turned-on state for a portion of the time of the third interval (P3).

[0111] Even if the data signals (D1, Dm / 2) provided to the data lines (DL1, DLm / 2) are the same, the voltage (Vdata) delivered to the capacitor (Cst) in the pixel (PX) located in the edge region (EA1) and the voltage (Vdata) delivered to the capacitor (Cst) in the pixel (PX) located in the center region (CA) may be different. This is because the time for providing the data signal (Dm / 2) to the capacitor (Cst) in the pixel (PX) located in the center region (CA) is longer than the time for providing the data signal (D1) to the capacitor (Cst) in the pixel (PX) located in the edge region (EA1).

[0112] In one embodiment, the voltage level of the voltage (Vdata) transferred to the capacitor (Cst) within the pixel (PX) located in the edge region (EA1) may be V1, and the voltage level of the voltage (Vdata) transferred to the capacitor (Cst) within the pixel (PX) located in the center region (CA) may be V2. Thus, when the voltage (Vdata) stored in the capacitor (Cst) within the pixel (PX) located in the center region (CA) and the voltage (Vdata) stored in the capacitor (Cst) within the pixel (PX) located in the edge region (EA1) are different from each other, the luminance of the center region (CA) and the luminance of the edge region (EA1) become different from each other.

[0113] Referring again to FIGS. 6, FIGS. 7a, and FIGS. 7b, the third switching signal (CLC) transitions to a low level at the beginning of the third interval (P3). Each of the bypass transistors (BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8) is turned on in response to the low-level third switching signal (CLC).

[0114] As illustrated in FIG. 7a, the scan signal (GWi) provided to the pixel (PX) placed in the edge region (EA1) transitions from a low level to a high level, and then the third switching signal (CLC) transitions to a low level. Preferably, the active level interval of the scan signal (GWi), i.e., the low level interval, and the active level interval of the third switching signal (CLC), i.e., the low level interval, do not overlap. Therefore, the pixel (PX) placed in the edge region (EA1) is not affected in transmitting the data signal (D1) to the pixel (PX) even if the third switching signal (CLC) transitions to a low level.

[0115] As illustrated in FIG. 7b, when the third switching signal (CLC) transitions to a low level, each of the bypass transistors (BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8) is turned on so that the data lines (DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8) are electrically connected to the fifth voltage line (VL5), i.e., the bypass voltage line. Therefore, a portion of the current flowing through the data lines (DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8) is bypassed to the fifth voltage line (VL5). Even if the scan signal (GWi) provided to the pixel (PX) located in the center area (CA) at the beginning of the third section (P3) is still maintained at a low level, the data signal (Dm / 2) can be discharged to the ground voltage (VG). Therefore, the voltage level of the voltage (Vdata) stored in the capacitor (Cst) within the pixel (PX) located in the center region (CA) can be V1, which is the same as the voltage (Vdata) stored in the capacitor (Cst) of the pixel (PX) located in the edge region (EA1). In one embodiment, the time during which the third switching signal (CLC) is maintained at a low level can be determined according to the characteristics of the display panel (DP).

[0117] FIGS. 9A and FIGS. 9B are drawings that exemplarily show images displayed on a display panel (DP).

[0118] Referring to FIGS. 4, 6, 7b and 9a, when the voltage (Vdata) stored in the capacitor (Cst) within the pixel (PX) placed in the center region (CA) and the voltage (Vdata) stored in the capacitor (Cst) of the pixel (PX) placed in the edge region (EA1) are different from each other, the luminance of the center region (CA) and the luminance of the edge region (EA1) may be different from each other.

[0119] Referring to FIGS. 4, 6, 7b and 9b, when the third switching signal (CLC) transitions to a low level, a portion of the current flowing through the data lines (DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8) is bypassed to the fifth voltage line (VL5). As a result, the voltage (Vdata) stored in the capacitor (Cst) within the pixel (PX) located in the center region (CA) and the voltage (Vdata) stored in the capacitor (Cst) of the pixel (PX) located in the edge region (EA1) become equal to each other, so the brightness of the center region (CA) and the brightness of the edge region (EA1) can be the same.

[0120] In one embodiment, the sizes of the bypass transistors (BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8) shown in FIG. 6 may differ from each other. As the size of the bypass transistors (BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8) increases, the amount of current bypassed to the fifth voltage line (VL5) among the current flowing through the data lines (DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8) may increase.

[0121] In one embodiment, the size of the bypass transistors connected to the data lines placed in the center region (CA) of the display panel (DP) may be larger than the size of the bypass transistors connected to the data lines placed in the edge region (EA1). In this case, the amount of current bypassed from the data lines placed in the center region (CA) to the fifth voltage line (VL5) may be greater than the amount of current bypassed from the data lines placed in the edge region (EA1) to the fifth voltage line (VL5).

[0122] In one embodiment, the size of the bypass transistors may decrease in steps as they move from the center of the display panel (DP) toward the first direction (DR1). In one embodiment, the size of the bypass transistors may decrease in steps as they move from the center of the display panel (DP) toward the second direction (DR2).

[0124] FIG. 10 is a plan view schematically showing a display module (DM).

[0125] The display module (DM) illustrated in FIG. 10 includes configurations similar to those of the display module (DM) illustrated in FIG. 3. Among the components of the display module (DM) illustrated in FIG. 10, the same draw codes are used for components identical to those of the display module (DM) illustrated in FIG. 3, and redundant descriptions are omitted.

[0126] Referring to FIG. 10, the third switching signal (CLC) can be provided through the clock line (CKL) in the direction from the center area (CA) of the display panel (DP) to the edge area (EA1), i.e., the second direction (DR2). Additionally, the third switching signal (CLC) can be provided through the clock line (CKL) in the direction from the center area (CA) of the display panel (DP) to the edge area (EA2), i.e., the first direction (DR1).

[0127] In one embodiment, the second driving circuit (DIC2) and the third driving circuit (DIC3) correspond to the center region (CA), and the first driving circuit (DIC1) and the fourth driving circuit (DIC4) correspond to the edge regions (EA1, EA2).

[0128] In one embodiment, the third switching signal (CLC) is output from the second driving circuit (DIC2) and the third driving circuit (DIC3) corresponding to the center region (CA). However, the present invention is not limited thereto. In one embodiment, the third switching signal (CLC) may be output from either the second driving circuit (DIC2) or the third driving circuit (DIC3).

[0130] FIG. 11a exemplarily shows a voltage (Vdata) corresponding to a data signal (D1) provided as a first data line, scan signals (GIi, GWi) provided as i-th scan lines (GILi, GWLi), and a third switching signal (CLC).

[0131] FIG. 11b exemplarily shows a voltage (Vdata) corresponding to a data signal (Dm / 2) provided to the m / 2th data line, scan signals (GIi, GWi) provided to the i-th scan lines (GILi, GWLi), and a third switching signal (CLC).

[0132] Referring to FIGS. 4, FIGS. 10, FIGS. 11a and FIGS. 11b, the pixel (PX) receiving the data signal (D1) and scan signals (GIi, GWi) is a pixel (PX) placed in the edge region (EA1) of the display panel (DP). The pixel (PX) receiving the data signal (Dm / 2) and scan signals (GIi, GWi) is a pixel (PX) placed in the center region (CA) of the display panel (DP).

[0133] The scan signal (GWi) is transmitted from the edge region (EA1) of the display panel (DP) to the center region (CA), so it is maintained at a low level at the beginning of the third section (P3). At the beginning of the third section (P3), the third switching signal (CLC) transitions to a low level, so that a portion of the current flowing through the data lines (DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8) can be bypassed to the fifth voltage line (VL5).

[0134] The third switching signal (CLC) can be transmitted in the direction from the center area (CA) of the display panel (DP) to the edge area (EA1), that is, in the second direction (DR2). Due to RC delay, the waveform of the third switching signal (CLC) corresponding to the pixel (PX) placed in the edge area (EA1) may be different from the waveform of the third switching signal (CLC) corresponding to the pixel (PX) placed in the center area (CA).

[0135] As a third switching signal (CLC) is output from the second driving circuit (DIC2) and the third driving circuit (DIC3) corresponding to the center region (CA), the amount of current bypassed from the data lines placed in the center region (CA) to the fifth voltage line (VL5) may be greater than the amount of current bypassed from the data lines placed in the edge region (EA1) to the fifth voltage line (VL5).

[0136] As a result, the voltage level of the voltage (Vdata) transferred to the capacitor (Cst) in the pixel (PX) located in the edge region (EA1) and the voltage level of the voltage (Vdata) transferred to the capacitor (Cst) in the pixel (PX) located in the center region (CA) may be V1.

[0137] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the relevant technical field will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as set forth in the claims below. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0138] 10: Electronic devices DM: Display Module DP: Display Panel 100: Drive controller 200: Data driving circuit 300: First scan driving circuit 400: Second scan driving circuit 500: Demultiplexer 510: Switching circuit 520: Bypass circuit PX: Pixel

Claims

Claim 1 A display device comprising: a display panel including a first pixel connected to a first data line and a scan line, and a second pixel connected to a second data line and the scan line; a scan driving circuit that outputs a scan signal to the scan line; a data driving circuit that outputs a data signal; and a demultiplexer that provides the data signal to the first data line and the second data line, wherein the demultiplexer comprises: a switching circuit that transmits the data signal to the first data line in response to a first switching signal and transmits the data signal to the second data line in response to a second switching signal; and a bypass circuit that electrically connects the first data line and the second data line to a bypass voltage line in response to a third switching signal. Claim 2 A display device according to claim 1, wherein the bypass circuit comprises: a first bypass transistor connected between the first data line and the bypass voltage line and turned on in response to the third switching signal; and a second bypass transistor connected between the second data line and the bypass voltage line and turned on in response to the third switching signal. Claim 3 A display device according to claim 1, wherein a ground voltage is provided to the bypass voltage line. Claim 4 A display device according to claim 1, wherein the active level interval of the scan signal and the active level interval of the third switching signal do not overlap. Claim 5 In claim 1, the demultiplexer is a display device disposed on the display panel. Claim 6 A display device comprising: a plurality of first data lines and a plurality of first pixels connected to a scan line, and a plurality of second data lines and a plurality of second pixels connected to the scan line; a scan driving circuit that outputs a scan signal to the scan line; a data driving circuit that outputs a plurality of data signals; and a demultiplexer that provides the plurality of data signals to the plurality of first data lines and the plurality of second data lines, wherein the demultiplexer comprises: a switching circuit that transmits the plurality of data signals to the plurality of first data lines in response to a first switching signal and transmits the plurality of data signals to the plurality of second data lines in response to a second switching signal; and a bypass circuit that connects the plurality of first data lines to a bypass voltage line and connects the plurality of second data lines to a bypass voltage line in response to a third switching signal. Claim 7 In claim 6, the bypass circuit comprises a plurality of bypass transistors, each connected between a corresponding data line among the plurality of first data lines and the plurality of second data lines and the bypass voltage line, and turned on in response to the third switching signal. Claim 8 In claim 6, a display device in which a ground voltage is provided to the bypass voltage line. Claim 9 A display device according to claim 6, wherein the active level interval of the scan signal and the active level interval of the third switching signal do not overlap. Claim 10 In claim 6, the display panel includes an edge region and a center region arranged sequentially in a first direction, the scan driving circuit is arranged adjacent to the edge region, and the size of the bypass transistor corresponding to the center region among the plurality of bypass transistors is larger than the size of the bypass transistor corresponding to the edge region. Claim 11 In claim 6, the display panel includes a center region and an edge region arranged sequentially in a first direction, the scan driving circuit is arranged adjacent to the edge region, each of the plurality of bypass transistors is arranged sequentially in the first direction, and the size of each of the plurality of bypass transistors decreases stepwise as it goes toward the first direction. Claim 12 A display device according to claim 6, wherein the display panel includes a center region and an edge region arranged sequentially in a first direction, the scan driving circuit is arranged adjacent to the edge region, each of the plurality of bypass transistors is arranged sequentially in the first direction, and the third switching signal is provided sequentially from the bypass transistor corresponding to the center region to the bypass transistor corresponding to the edge region among the plurality of bypass transistors. Claim 13 In claim 6, the display panel includes a center area and an edge area sequentially arranged in a first direction, and the data driving circuit includes a first driving circuit corresponding to the center area and a second driving circuit corresponding to the edge area, and the first driving circuit provides the third switching signal to a clock line. Claim 14 In claim 6, each of the plurality of first pixels comprises: a first transistor including a gate electrode connected between a first node and a second node; a second transistor including a gate electrode receiving the scan signal connected between any one of the plurality of first data lines and the first node; and a third transistor including a gate electrode receiving the scan signal connected between the second node and the gate electrode of the first transistor. Claim 15 An electronic device comprising: a processor that outputs a video signal and a control signal; and a display module that displays a video in response to the video signal and the control signal, wherein the display module comprises: a display panel including a first pixel connected to a first data line and a scan line and a second pixel connected to a second data line and the scan line; a scan driving circuit that outputs a scan signal to the scan line; a data driving circuit that outputs a data signal; and a demultiplexer that provides the data signal to the first data line and the second data line, wherein the demultiplexer comprises: a switching circuit that transmits the data signal to the first data line in response to a first switching signal and transmits the data signal to the second data line in response to a second switching signal; and a bypass circuit that electrically connects the first data line and the second data line to a bypass voltage line in response to a third switching signal. Claim 16 An electronic device according to claim 15, wherein the bypass circuit comprises: a first bypass transistor connected between the first data line and the bypass voltage line and turned on in response to the third switching signal; and a second bypass transistor connected between the second data line and the bypass voltage line and turned on in response to the third switching signal, wherein the bypass voltage line is provided with a ground voltage. Claim 17 An electronic device according to claim 15, wherein the display panel comprises a display area and a non-display area adjacent to the display area, the first pixel and the second pixel are disposed in the display area, the demultiplexer is disposed in the non-display area, and the demultiplexer comprises at least one bypass transistor. Claim 18 An electronic device according to claim 15, wherein the active level interval of the scan signal and the active level interval of the third switching signal do not overlap. Claim 19 An electronic device according to claim 15, wherein the display panel receives a first driving voltage, a second driving voltage, a first initialization voltage, and a second initialization voltage, and the bypass voltage line is electrically connected to a voltage line that transmits any one of the second driving voltage, the first initialization voltage, and the second initialization voltage. Claim 20 An electronic device according to claim 15, wherein the display panel includes a center area and an edge area sequentially arranged in a first direction, the scan driving circuit is arranged adjacent to the edge area, the data driving circuit includes a first driving circuit corresponding to the center area and a second driving circuit corresponding to the edge area, and the first driving circuit provides the third switching signal to a clock line.

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