Semiconductor memroy device

Abstract

A semiconductor memory device is provided. A semiconductor memory device comprises: a first cell structure including first local bit lines extending in a vertical direction, first memory cells connected to each of the first local bit lines and arranged in the vertical direction, first local bit line multiplexers each electrically connected to the first local bit lines, and first global bit lines each electrically connected to the first local bit line multiplexers; a second cell structure on the first cell structure including second local bit lines extending in the vertical direction, second memory cells connected to each of the second local bit lines and arranged in the vertical direction, second local bit line multiplexers each electrically connected to the second local bit lines, and second global bit lines electrically connected to the second local bit line multiplexers; bit line contacts penetrating the second cell structure and electrically connecting each of the first global bit lines and each of the second global bit lines; and a peripheral circuit structure including a sense amplifier electrically connected to the bit line contacts on the second cell structure, wherein the first global bit lines and the second global The bit lines share the sense amplifier mentioned above.

Description

Technology Field

[0001] The present invention relates to a semiconductor memory device, and more specifically, to a three-dimensional semiconductor memory device with improved electrical characteristics. Background Technology

[0002] To meet the superior performance and low prices demanded by consumers, it is necessary to increase the integration density of semiconductor devices. Since integration density is a critical factor in determining product prices for semiconductor devices, particularly increased integration density is required.

[0003] In the case of conventional two-dimensional or planar semiconductor devices, the integration density is largely determined by the area occupied by a unit memory cell, and thus is significantly influenced by the level of fine pattern formation technology. However, since ultra-expensive equipment is required for pattern miniaturization, the integration density of two-dimensional semiconductor devices is increasing but remains limited. Accordingly, three-dimensional semiconductor memory devices equipped with memory cells arranged in three dimensions are being proposed. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a semiconductor memory device comprising cell structures that each include local bit line multiplexers and share a sense amplifier.

[0005] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A semiconductor memory device according to some embodiments of the present invention for achieving the above technical problem comprises: a first cell structure including first local bit lines extending in a vertical direction, first memory cells connected to each of the first local bit lines and arranged in the vertical direction, first local bit line multiplexers electrically connected to each of the first local bit lines, and first global bit lines electrically connected to each of the first local bit line multiplexers; a second cell structure including second local bit lines extending in the vertical direction, second memory cells connected to each of the second local bit lines and arranged in the vertical direction, second local bit line multiplexers electrically connected to each of the second local bit lines, and second global bit lines electrically connected to the second local bit line multiplexers; bit line contacts penetrating the second cell structure and electrically connecting each of the first global bit lines and each of the second global bit lines; and a peripheral circuit structure including a sense amplifier electrically connected to the bit line contacts on the second cell structure. The first global bit lines and the second global bit lines share the sense amplifier.

[0007] A semiconductor memory device according to some embodiments of the present invention for achieving the above technical problem comprises: a first local bit line extending in a vertical direction on a first insulating layer; first cell semiconductor patterns arranged in the vertical direction with one end connected to the first local bit line; first data storage elements connected to the other end of the first cell semiconductor patterns; first cell gate electrodes on the first cell semiconductor patterns; a first logic semiconductor pattern spaced vertically apart from the first cell semiconductor patterns; a first logic transistor electrically connected to the first local bit line on the first logic semiconductor pattern; and a first global bit line electrically connected to the first logic transistor. The device comprises: a second local bit line extending in the vertical direction on a second insulating layer; second cell semiconductor patterns arranged in the vertical direction with one end connected to the second local bit line; second data storage elements connected to the other end of the second cell semiconductor patterns; second cell gate electrodes on the second cell semiconductor patterns; a second logic semiconductor pattern spaced vertically apart from the second cell semiconductor patterns; and the second logic semiconductor pattern It includes a second cell structure comprising a second logic transistor electrically connected to the second local bit line and a second global bit line electrically connected to the second logic transistor, a bit line contact penetrating the second cell structure and electrically connecting the first global bit line and the second global bit line, a peripheral circuit board, and a peripheral circuit structure comprising a peripheral circuit transistor electrically connected to the first global bit line and the second global bit line on the peripheral circuit board.

[0008] A semiconductor memory device according to some embodiments of the present invention for achieving the above technical problem comprises: a first cell structure including first local bit lines extending in a vertical direction, first memory cells connected to each of the first local bit lines and arranged in the vertical direction, first global bit lines on the first memory cells, and first local bit line multiplexers electrically connected to the first global bit lines and the first local bit lines, and first global bit line multiplexers electrically connected to the first global bit lines; a second cell structure including second local bit lines extending in the vertical direction, second memory cells connected to each of the second local bit lines and arranged in the vertical direction, second global bit lines on the second memory cells, second local bit line multiplexers electrically connected to the second global bit lines and the second local bit lines, and second global bit line multiplexers electrically connected to the second global bit lines; and on the second cell structure, electrically connected to the first global bit lines and the second global bit lines It includes a peripheral circuit structure that includes a sense amplifier.

[0009] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0010] FIG. 1 is a schematic layout diagram of a semiconductor memory device according to some embodiments. Figure 2 is a cross-sectional view taken along I-I' of Figure 1. Figure 3 is a cross-sectional view taken along II-II' of Figure 1. FIG. 4 is an exemplary cross-sectional view of a semiconductor memory device according to some embodiments. FIG. 5 is an exemplary cross-sectional view of a semiconductor memory device according to some embodiments. Figure 6 is a cross-sectional view taken along I-I' of Figure 5. Figure 7 is an enlarged view of regions A1 and A2 of Figure 6. Figure 8 is a cross-sectional view taken along I-I' of Figure 5. FIGS. 9 and FIGS. 10 are exemplary cross-sectional views of a semiconductor memory device according to some embodiments. FIGS. 11 to 13 are schematic layout diagrams of semiconductor memory devices according to some embodiments. FIGS. 14 to 37 are intermediate step drawings for explaining a method of manufacturing a semiconductor memory device according to some embodiments. Specific details for implementing the invention

[0011] FIG. 1 is a schematic layout diagram of a semiconductor memory device according to some embodiments. FIG. 2 is a cross-sectional view taken along I-I' of FIG. 1. FIG. 3 is a cross-sectional view taken along II-II' of FIG. 1.

[0012] The first direction (DR1) and the second direction (DR2) may be parallel to the front surface of the first insulating layer (140) to be described later and may intersect each other (e.g., perpendicularly). The third direction (DR3) may be perpendicular to the front surface of the first insulating layer (140) and perpendicular to the first direction (DR1) and the second direction (DR2). The third direction (DR3) may be referred to as a vertical direction, the first direction (DR1) may be referred to as a first horizontal direction, and the second direction (DR2) may be referred to as a second horizontal direction. The front surface of the first insulating layer (140) may refer to the surface on which the first memory cells (MC1) to be described later are placed.

[0013] Referring to FIGS. 1 and FIGS. 2, a semiconductor memory device according to some embodiments may include a cell region (1), a word line pad region (WPR), and a bit line pad region (BPR).

[0014] The cell region (1) may include a bit line region (BR), a semiconductor region (SR), a word line region (WR), a capacitor region (CR), and a plate region (PR). A word line region (WR) may be positioned between the bit line region (BR) and the capacitor region (CR). For example, the bit line region (BR), the word line region (WR), and the capacitor region (CR) may be positioned along a first direction (DR1). A plate region (PR) may be positioned on one side of the capacitor region (CR). At least a portion of the semiconductor region (SR) may overlap with the capacitor region (CR). At least a portion of the semiconductor region (SR) may overlap with the word line region (WR).

[0015] A word line pad region (WPR) may be disposed on at least one side of a cell region (1). For example, the cell region (1) may be adjacent to the word line pad region (WPR) in a second direction (DR2). Although the word line pad region (WPR) is depicted as being spaced apart from the word line region (WR), this is done to distinguish the regions, and the word line pad region (WPR) may be connected to the word line region (WR). A single word line pad region (WPR) is depicted, but is not limited thereto, and a semiconductor device according to some embodiments may include a plurality of word line pad regions (WPR). For example, a word line pad region (WPR) may be disposed on each side of the cell region (1) in the second direction (DR2).

[0016] In some embodiments, the semiconductor memory device may include a plurality of bit line regions (BR), a plurality of word line regions (WR), and a plurality of capacitor regions (CR). The bit line regions (BR), word line regions (WR), semiconductor regions (SR), and capacitor regions (CR) may be symmetrical with respect to the plate region (PR). Although a single plate region (PR) is illustrated in FIG. 1, it is not limited thereto, and the semiconductor memory device according to some embodiments may include a plurality of plate regions (PR). On each side of each plate region (PR), a bit line region (BR), a semiconductor region (SR), a word line region (WR), and a capacitor region (CR) may be arranged symmetrically with respect to the plate region (PR). Although the capacitor region (CR) is illustrated as being spaced apart from the plate region (PR), this is done to distinguish between the plurality of capacitor regions (CR) and the plate region (PR), and the plate region (PR) may be connected to each of the capacitor regions (CR) located on both sides of the plate region (PR).

[0017] A semiconductor memory device according to some embodiments includes first and second cell structures (CS1, CS2) and a peripheral circuit structure (PR).

[0018] The first cell structure (CS1) may include a first insulating layer (140), first local bit lines (LBL1), first memory cells (MC1), a first wiring insulating layer (180), first wirings (182), first vias (186), first global bit lines (GBL1), and first logic transistors (LTR1).

[0019] The first local bit lines (LBL1) may be placed in each bit line area (BR). The first local bit lines (LBL1) may be spaced apart in a second direction (DR2) on each bit line area (BR). Each first local bit line (LBL1) may be extended in a third direction (DR3).

[0020] First memory cells (MC1) arranged in a third direction (DR3) may be connected to each first local bit line (LBL1). First memory cells (MC1) arranged in a third direction (DR3) may be connected in common to the first local bit line (LBL1). First memory cells (MC1) may be spaced apart in a first direction (DR1) and a second direction (DR2) within a single layer. First memory cells (MC1) adjacent in the first direction (DR1) may have a symmetrical structure with respect to a vertical portion extending in the third direction (DR3) of the second conductive layer (176b). Unlike illustrated, in some embodiments, first memory cells (MC1) adjacent in the first direction (DR1) having a symmetrical structure with respect to the vertical portion of the second conductive layer (176b) may be spaced apart along the first direction (DR1).

[0021] Each first memory cell (MC1) may include a first cell transistor (CTR1) and a first data storage element (170) connected to each other.

[0022] The first cell transistor (CTR1) may include a first cell semiconductor pattern (SP1), a first cell gate electrode (GE1), and a first cell gate insulating film (GI1).

[0023] First cell semiconductor patterns (SP1) can be stacked spaced apart in a third direction (DR3) on a first insulating layer (140). Each first local bit line (LBL1) can be connected to the first cell semiconductor patterns (SP1) stacked in the third direction (DR3). Each first cell semiconductor pattern (SP1) can be extended in a first direction (DR1). The first cell semiconductor patterns (SP1) stacked in the third direction (DR3) can be arranged in a first direction (DR1) and a second direction (DR2).

[0024] Each first cell semiconductor pattern (SP1) may include a first source / drain region, a second source / drain region, and a channel region between the first source / drain region and the second source / drain region. One end of the first cell semiconductor pattern (SP1) in the first direction (DR1) may be the first source / drain region, and the other end of the first cell semiconductor pattern (SP1) in the first direction (DR1) may be the second source / drain region. The first source / drain region and the second source / drain region may each be regions doped with n-type or p-type impurities. One end of the first cell semiconductor pattern (SP1) in the first direction (DR1) may be connected to a first local bit line (LBL1), and the other end of the first cell semiconductor pattern (SP1) in the first direction (DR1) may be connected to a first data storage element (170).

[0025] The first cell gate electrodes (GE1) can be placed in each word line region (WR). The first cell gate electrodes (GE1) can be stacked spaced apart in a third direction (DR3). Each first cell gate electrode (GE1) can be placed on at least a portion of the outer surface of each first cell semiconductor pattern (SP1). Each first cell gate electrode (GE1) can be extended in a second direction (DR2). The first cell gate electrodes (GE1) can be extended in a second direction (DR2) across the first semiconductor patterns (SP1) within a single layer.

[0026] The first cell gate insulating film (GI1) can be placed between the first cell gate electrode (GE1) and the first cell semiconductor pattern (SP1). The first cell gate electrode (GE1) can be separated from the first cell semiconductor pattern (SP1) by the first cell gate insulating film (GI1).

[0027] The first cell insulating layer (132) may be disposed on the first insulating layer (140). The first cell insulating layer (132) may be disposed between the first cell semiconductor patterns (SP1) and between the first cell gate electrodes (GE1).

[0028] The first data storage elements (170) may be placed in the capacitor region (CR) and the plate region (PR). The first data storage elements (170) may be placed on the first cell semiconductor patterns (SP1) and the first cell insulating layer (132). The first data storage elements (170) and the first local bit line (LBL1) may each be placed at opposite ends of the first cell semiconductor pattern (SP1) in the first direction (DR1).

[0029] The first data storage element (170) and the second data storage element (270) described below may be capacitors or variable resistors, etc. In the following description, the first data storage element (170) and the second data storage element (270) are described as capacitors. The first data storage element (170) may include a first storage electrode (172), a first plate electrode (176), and a first dielectric layer (174) between the first storage electrode (172) and the first plate electrode (176). Each of the first data storage elements (170) may be defined by each of the first storage electrodes (172).

[0030] The first storage electrode (172) may come into contact with the other end of the first cell semiconductor pattern (SP1). For example, the length of the first storage electrode (172) in the second direction (DR2) and the length in the third direction (DR3) may be equal to the length of the first cell semiconductor pattern (SP1) in the second direction (DR2) and the length in the third direction (DR3), respectively.

[0031] The first dielectric layer (174) may cover the remaining surfaces of the first storage electrode (172), excluding the surface in contact with the first cell semiconductor pattern (SP1). The first dielectric layer (174) may extend along the upper and lower surfaces of the first storage electrode (172) and the side facing the first plate electrode (176). The first dielectric layer (174) may extend along the upper surface of the first insulating layer (140) and the side of the first cell insulating layer (132) between the first storage electrode (172) adjacent in the third direction (DR3).

[0032] The first plate electrode (176) may include a first conductive layer (176a) and a second conductive layer (176b). The first conductive layer (176a) may be disposed on the first dielectric layer (174). The first conductive layer (176a) may extend along the first dielectric layer (174). The second conductive layer (176b) may be disposed on the first conductive layer (176a). The second conductive layer (176b) may include a vertical portion perpendicular to the upper surface of the first insulating layer (140) and a horizontal portion parallel to the upper surface of the first insulating layer (140). The horizontal portions of the second conductive layer (176b) may protrude in a first direction (DR1) from the vertical portion of the second conductive layer (176b) and be surrounded by the first dielectric layer (174) and the first conductive layer (176a). The vertical portion of the second conductive layer (176b) can be placed in the plate area (PR).

[0033] The first logic transistors (LTR1) may be placed on the first memory cells (MC1). In some embodiments, the first logic transistors (LTR1) may be formed on the first cell insulating layer (132). The first logic transistor (LTR1) may include a first logic semiconductor pattern (LSP1), a first logic gate electrode (LGE1), a first logic gate insulating film (LGI1), and a first logic gate spacer (LGS1).

[0034] The first logic semiconductor pattern (LSP1) can be placed in each semiconductor region (SR). The first logic semiconductor patterns (SP1) and the first insulation patterns (133) can be placed on the first cell insulation layer (132). The first logic semiconductor patterns (LSP1) can be defined by the first insulation patterns (133). The first logic semiconductor patterns (LSP1) can be spaced apart from each other by the first insulation patterns (133).

[0035] The first logic semiconductor pattern (LSP1) may include the same material as the first cell semiconductor pattern (SP1). In the third direction (DR3), the thickness of the first logic semiconductor pattern (LSP1) may be thicker than the thickness of the first cell semiconductor pattern (SP1).

[0036] A first logic gate electrode (LGE1) may be disposed on a first logic semiconductor pattern (LSP1). A first logic gate insulating film (LGI1) may be disposed between the first logic semiconductor pattern (LSP1) and the first logic gate electrode (LGE1). A first logic gate spacer (LGS1) may be disposed on the sidewalls of the first logic gate electrode (LGE1) and the first logic gate insulating film (LGI1). First and second source / drain regions may be provided within the first logic semiconductor pattern (LSP1) adjacent to both sides of the first logic gate electrode (LGE1).

[0037] The first interlayer insulating layer (134) may be placed on the first logic semiconductor pattern (LSP1) and the first insulating pattern (133). The first interlayer insulating layer (134) may cover the first logic transistor (LTR1).

[0038] The first logic gate contact (166) can penetrate the first interlayer insulating layer (134) and contact the first logic gate electrode (LGE1). The first source / drain contact (168) can contact the first and second source / drain regions, respectively, within the first logic semiconductor pattern (LSP1) on both sides of the first logic gate electrode (LGE1).

[0039] The first local bit line (LBL1) can penetrate the first cell insulating layer (132), the first insulating pattern (133), and the first interlayer insulating layer (134). The first plate electrode (176) and the first dielectric layer (174) can extend into the first insulating pattern (133) and the first interlayer insulating layer (134).

[0040] The first wiring insulation layer (180) may be disposed on the first interlayer insulation layer (134). The first wirings (182) and the first vias (186) may be disposed within the first interlayer insulation layer (134). The first wirings (182) and the first vias (186) may be electrically connected to the first logic gate contact (166) and the first source / drain contact (168). The number, arrangement, and connection relationship of the first wirings (182) and the first vias (186) may be varied.

[0041] The first global bit lines (GBL1) may be disposed within the first wiring insulation layer (180). The first global bit lines (GBL1) may be disposed spaced apart in the second direction (DR2). Each of the first global bit lines (GBL1) may be electrically connected to a plurality of first local bit lines (LBL1). Each of the first global bit lines (GBL1) may extend in the first direction (DR1) and be electrically connected to the first local bit lines (LBL1) spaced apart in the first direction (DR1). Although the first global bit lines (GBL1) are depicted as being on the top layer within the first wiring insulation layer (180), they are not limited thereto, and the first wires (182) and first vias (186) may be disposed above the first global bit lines (GBL1).

[0042] The first local bit lines (LBL1) can be directly connected to the first memory cells (MC1), and the first global bit lines (GBL1) can be connected to the first local bit lines (LBL1) through the first wires (182), the first vias (186), and the first logic transistors (LTR1).

[0043] At least one first logic transistor (LTR1) may be connected between a first global bit line (GBL1) and first local bit lines (LBL1). For example, a first source / drain region of the first logic transistor (LTR1) may be connected to the first local bit line (LBL1) through a first source / drain contact (168), a first via (186), and a first wire (182), and a second source / drain region of the first logic transistor (LTR1) may be connected to the first global bit line (GBL1) through a first source / drain contact (168), a first via (186), and a first wire (182). The first logic transistor (LTR1) may be configured to connect at least one selected of the first local bit lines (LBL1) to the first global bit line (GBL1). The first logic transistor (LTR1) may constitute a first local bit line multiplexer. The first logic transistor (LTR1) can be referred to as the first local bit line multiplexer.

[0044] A second cell structure (CS2) may be placed on a first cell structure (CS1). The second cell structure (CS2) may include a second insulating layer (240), second local bit lines (LBL2), second memory cells (MC2), a second wiring insulating layer (280), second wirings (282), second vias (286), second global bit lines (GBL2), second logic transistors (LTR2), a first bonding insulating film (290), and a first bonding pad (292).

[0045] The second insulating layer (240) may be disposed on the first cell structure (CS1). The second insulating layer (240) may be disposed on the first wiring insulating layer (180). The first insulating layer (140) and the second insulating layer (240) may each comprise silicon oxide, silicon nitride, or silicon oxynitride, or a combination thereof.

[0046] The second local bit lines (LBL2) may be placed in the bit line area (BR). The second local bit lines (LBL2) may be spaced apart in the second direction (DR2) on the bit line area (BR). Each of the second local bit lines (LBL2) may extend in the third direction (DR3). The second local bit lines (LBL2) may overlap with the first local bit lines (LBL1) in the third direction (DR3).

[0047] The first local bit line (LBL1) and the second local bit lines (LBL2) may each include at least one of a conductive material, for example, a doped semiconductor material (doped silicon, doped silicon-germanium, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal (tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.), but are not limited thereto.

[0048] The second memory cells (MC2) arranged in the third direction (DR3) may be connected to each of the second local bit lines (LBL2). The second memory cells (MC2) arranged in the third direction (DR3) may be connected in common to the second local bit line (LBL2). The second memory cells (MC2) may be spaced apart in the first direction (DR1) and the second direction (DR2) within a single layer. The second memory cells (MC2) adjacent in the first direction (DR1) may have a symmetrical structure with respect to the vertical portion of the fourth conductive layer (276b). Unlike what is illustrated, in some embodiments, the second memory cells (MC2) adjacent in the first direction (DR1) having a symmetrical structure with respect to the vertical portion of the fourth conductive layer (276b) may be spaced apart along the first direction (DR1).

[0049] Each second memory cell (MC2) may include a second cell transistor (CTR2) and a second data storage element (270) connected to each other.

[0050] The second cell transistor (CTR2) may include a second cell semiconductor pattern (SP2), a second cell gate electrode (GE2), and a second cell gate insulating film (GI2).

[0051] The second cell semiconductor patterns (SP2) can be stacked spaced apart in a third direction (DR3) on the second insulating layer (240). Each second local bit line (LBL2) can be connected to the second cell semiconductor patterns (SP2) stacked in the third direction (DR3). Each second cell semiconductor pattern (SP2) can be extended in a first direction (DR1). The second cell semiconductor patterns (SP2) stacked in the third direction (DR3) can be arranged in the first direction (DR1) and the second direction (DR2). The second cell semiconductor patterns (SP2) can be overlapped with the first cell semiconductor patterns (SP1) in the third direction (DR3).

[0052] Each of the second cell semiconductor patterns (SP2) may include a first source / drain region, a second source / drain region, and a channel region between the first source / drain region and the second source / drain region. One end of the second cell semiconductor pattern (SP2) in the first direction (DR1) may be the first source / drain region, and the other end of the second cell semiconductor pattern (SP2) in the first direction (DR1) may be the second source / drain region. The first source / drain region and the second source / drain region may each be regions doped with n-type or p-type impurities. One end of the second cell semiconductor pattern (SP2) in the first direction (DR1) may be connected to a second local bit line (LBL2), and the other end of the second cell semiconductor pattern (SP2) in the first direction (DR1) may be connected to a second data storage element (270).

[0053] The first and second cell semiconductor patterns (SP1, SP2) may each include at least one of a single-crystal semiconductor, a polycrystalline semiconductor, an oxide semiconductor, and a two-dimensional material. For example, the single-crystal semiconductor may be single-crystal silicon. For example, the polycrystalline semiconductor may be polysilicon. For example, the oxide semiconductor may be selected from IGZO (InGaZnO), Sn-IGZO, IWO (InWO), IZO (InZnO), ZTO (ZnSnO), ZnO, YZO (yttrium-doped zinc oxide), IGSO (InGaSiO), InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, AlSnInZnO, SiInZnO, AlZnSnO, GaZnSnO, and ZrZnSnO, but is not limited thereto. For example, the above two-dimensional semiconductor may be composed of a transition metal dichalcogenide or a bipolar semiconductor material that utilizes both electrons and holes as driving charges. For example, the above two-dimensional semiconductor material may be selected from MoS2, MoSe2, WS2, NbS2, TaS2, ZrS2, HfS2, TcS2, ReS2, CuS2, GaS2, InS2, SnS2, GeS2, PbS2, WSe2, NbSe2, TaSe2, ZrSe2, HfSe2, TcSe2, ReSe2, CuSe2, GaSe2, InSe2, SnSe2, GeSe2, PbSe2, MoTe2, WTe2, NbTe2, TaTe2, ZrTe2, HfTe2, TcTe2, ReTe2, CuTe2, GaTe2, InTe2, SnTe2, GeTe2, and PbTe2, but is not limited to these.

[0054] In some embodiments, the first cell transistor (CTR1) and the second cell transistor (CTR2) may each be a Gate All Around Transistor. The first cell gate electrode (GE1) may surround the channel region of the first cell semiconductor pattern (SP1), and the second cell gate electrode (GE2) may surround the channel region of the second cell semiconductor pattern (SP2). The first cell gate electrode (GE1) may surround the outer surface of the channel region of the first cell semiconductor pattern (SP1), and the second cell gate electrode (GE2) may surround the outer surface of the channel region. The first cell gate electrode (GE1) may extend in a second direction (DR2) and surround the channel region of each of the first cell semiconductor patterns (SP1) that are spaced apart in the second direction (DR2) at the same height. The second cell gate electrode (GE2) can extend in the second direction (DR2) and surround the channel region of each second cell semiconductor pattern (SP2) spaced apart in the second direction (DR2) at the same height.

[0055] Unlike what is described, in some other embodiments, the first cell transistor (CTR1) and the second cell transistor (CTR2) may each have a double-gate transistor structure. The first cell gate electrode (GE1) may be spaced apart and disposed on opposite side walls (e.g., opposite side walls in the third direction (DR3)) of the channel region of the first cell semiconductor pattern (SP1), and the second cell gate electrode (GE2) may be spaced apart and disposed on opposite side walls (e.g., opposite side walls in the third direction (DR3)) of the channel region of the second cell semiconductor pattern (SP2).

[0056] In some other embodiments, the first cell gate electrode (GE1) may be placed on one sidewall of the first cell semiconductor pattern (SP1), and the second cell gate electrode (GE2) may be placed on one sidewall of the second cell semiconductor pattern (SP2).

[0057] The first cell gate electrode (GE1) and the second cell gate electrode (GE2) may each include at least one of a conductive material, for example, a doped semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound, but are not limited thereto.

[0058] Cell gate contacts can be placed in the word line pad area (WPR). Each cell gate contact can be in contact with each of the first and second cell gate electrodes (GE1, GE2).

[0059] The second cell gate insulating film (GI2) may be disposed between the second cell gate electrode (GE2) and the second cell semiconductor pattern (SP2). The second cell gate electrode (GE2) may be spaced apart from the second cell semiconductor pattern (SP2) by the second cell gate insulating film (GI2). The first cell gate insulating film (GI1) and the second cell gate insulating film (GI2) may each include, for example, at least one of a high dielectric constant insulating film, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0060] The second cell insulating layer (232) may be disposed on the second insulating layer (240). The second cell insulating layer (232) may be disposed between the second cell semiconductor patterns (SP2) and between the second cell gate electrodes (GE2). The first cell insulating layer (132) and the second cell insulating layer (232) may each include at least one insulating material, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, a carbon-containing silicon nitride film, and a carbon-containing silicon oxynitride film. As an example, the first cell insulating layer (132) and the second cell insulating layer (232) may each include a silicon oxide film.

[0061] The second data storage elements (270) may be placed in the capacitor region (CR) and the plate region (PR). The second data storage elements (270) may be placed on the second cell semiconductor patterns (SP2) and the second cell insulating layer (232). The second data storage elements (270) and the second local bit line (LBL2) may each be placed at opposite ends of the second cell semiconductor pattern (SP2) in the first direction (DR1). The second data storage elements (270) may include a second storage electrode (272), a second plate electrode (276), and a second dielectric layer (274) between the second storage electrode (272) and the second plate electrode (276). Each second data storage element (270) may be defined by each second storage electrode (272).

[0062] The second storage electrode (272) may come into contact with the other end of the second cell semiconductor pattern (SP2). For example, the length of the second storage electrode (272) in the second direction (DR2) and the length in the third direction (DR3) may be equal to the length of the second cell semiconductor pattern (SP2) in the second direction (DR2) and the length in the third direction (DR3), respectively.

[0063] The second dielectric layer (274) may cover the remaining surfaces of the second storage electrode (272), excluding the surface in contact with the second cell semiconductor pattern (SP2). The second dielectric layer (274) may extend along the upper and lower surfaces of the second storage electrode (272) and along the side facing the second plate electrode (276). The second dielectric layer (274) may extend along the upper surface of the second insulating layer (240) and along the side of the second cell insulating layer (232) between the second storage electrode (272) adjacent in the third direction (DR3).

[0064] The second plate electrode (276) may include a third conductive layer (276a) and a fourth conductive layer (276b). The third conductive layer (276a) may extend along the second dielectric layer (274). The fourth conductive layer (276b) may be disposed on the third conductive layer (276a). The fourth conductive layer (276b) may include a vertical portion perpendicular to the upper surface of the second insulating layer (240) (e.g., extending in the third direction (DR3)) and a horizontal portion parallel to the upper surface of the second insulating layer (240) (e.g., extending in the first direction (DR1)). The horizontal portions of the fourth conductive layer (276b) may protrude in the first direction (DR1) from the vertical portion of the fourth conductive layer (276b) and be surrounded by the second dielectric layer (274) and the third conductive layer (276a). The vertical portion of the fourth conductive layer (276b) can be placed in the plate area (PR).

[0065] The first storage electrode (172), the second storage electrode (272), the first plate electrode (176), and the second plate electrode (276) may each include a conductive material. The first storage electrode (172), the second storage electrode (272), the first plate electrode (176), and the second plate electrode (276) may each include, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride or tungsten nitride, etc.), a metal (e.g., ruthenium, iridium, titanium, niobium, tungsten, cobalt, molybdenum or tantalum, etc.), and a conductive metal oxide (e.g., iridium oxide or niobium oxide, etc.), but are not limited thereto. For example, the first and third conductive layers (176a, 276a) may each contain the same material as the first and second storage electrodes (172, 272), respectively, and the second and fourth conductive layers (176b, 276b) may contain a material different from the first and third conductive layers (176a, 276a) and the first and second storage electrodes (172, 272). As an example, the first and second storage electrodes (172, 272) and the first and third conductive layers (176a, 276a) may contain titanium nitride, and the second and fourth conductive layers (176b, 276b) may contain doped silicon germanium.

[0066] The first and second dielectric layers (174, 274) may each comprise, for example, a high dielectric constant material (e.g., hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof). In a semiconductor memory device according to some embodiments, the first dielectric layer (174) may comprise a stacked film structure in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked. In a semiconductor memory device according to some embodiments, the first and second dielectric layers (174, 274) may each comprise hafnium (Hf).

[0067] The second logic transistors (LTR2) may be placed on the second memory cells (MC2). In some embodiments, the second logic transistors (LTR2) may be formed on the second cell insulating layer (232). The second logic transistor (LTR2) may include a second logic semiconductor pattern (LSP2), a second logic gate electrode (LGE2), and a second logic gate insulating film (LGI2).

[0068] The second logic semiconductor pattern (LSP2) can be placed in each semiconductor region (SR). The second logic semiconductor patterns (SP2) and the second insulation patterns (233) can be placed on the second cell insulation layer (232). The second logic semiconductor patterns (SP2) can be defined by the second insulation patterns (233). The second logic semiconductor patterns (SP2) can be spaced apart from each other by the second insulation patterns (233). The second logic semiconductor patterns (LSP2) can be overlapped with the first logic semiconductor patterns (LSP1) in a third direction (DR3).

[0069] The second logic semiconductor pattern (LSP2) may include the same material as the second cell semiconductor pattern (SP1). In the third direction (DR3), the thickness of the second logic semiconductor pattern (LSP2) may be thicker than the thickness of the second cell semiconductor pattern (SP2).

[0070] A second logic gate electrode (LGE2) may be disposed on a second logic semiconductor pattern (LSP2). A second logic gate insulating film (LGI2) may be disposed between the second logic semiconductor pattern (LSP2) and the second logic gate electrode (LGE2). A second logic gate spacer (LGS2) may be disposed on the sidewalls of the second logic gate electrode (LGE2) and the second logic gate insulating film (LGI2). First and second source / drain regions may be provided within the second logic semiconductor pattern (LSP2) adjacent to both sides of the second logic gate electrode (LGE2).

[0071] The first and second logic gate electrodes (LGE1, LGE2) may each comprise at least one of a conductive material, for example, a doped semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound, but are not limited thereto. The first and second logic gate insulating films (LGI1, LGI2) may each comprise at least one of, for example, a high dielectric constant insulating film, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first and second logic gate spacers (LGS1, LGS2) may each comprise at least one of, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0072] The second interlayer insulating layer (234) may be placed on the second logic semiconductor pattern (LSP2) and the second insulating pattern (233). The second interlayer insulating layer (234) may cover the second logic transistor (LTR2).

[0073] The second logic gate contact (266) can penetrate the second interlayer insulating layer (234) and contact the second logic gate electrode (LGE2). The second source / drain contact (268) can each contact the source / drain regions within the second logic semiconductor pattern (LSP2) on both sides of the second logic gate electrode (LGE2).

[0074] The second local bit line (LBL2) can penetrate the second cell insulation layer (232), the second insulation pattern (233), and the second interlayer insulation layer (234). The second plate electrode (276) and the second dielectric layer (274) can extend into the second insulation pattern (133) and the second interlayer insulation layer (234).

[0075] The second wiring insulation layer (280) may be disposed on the second cell insulation layer (232). The second wirings (282) and the second vias (286) may be disposed within the second cell insulation layer (232). The second wirings (282) and the second vias (286) may be electrically connected to the second logic gate contact (266) and the second source / drain contact (268). The number, arrangement, and connection relationships of the second wirings (282) and the second vias (286) may be varied.

[0076] The second global bit lines (GBL2) may be disposed within the second wiring insulation layer (280). The second global bit lines (GBL2) may be disposed spaced apart in the second direction (DR2). Each of the second global bit lines (GBL2) may be electrically connected to a plurality of second local bit lines (LBL2). Each of the second global bit lines (GBL2) may extend in the first direction (DR1) and be electrically connected to the second local bit lines (LBL2) spaced apart in the first direction (DR1). Although the second global bit lines (GBL2) are depicted as being on the top layer within the second wiring insulation layer (280), they are not limited thereto, and the second wires (282) and second vias (286) may be disposed above the second global bit lines (GBL2).

[0077] The second local bit lines (LBL2) can be directly connected to the second memory cells (MC2), and the second global bit line (GBL2) can be connected to the second local bit lines (LBL2) through the second wires (282), the second vias (286), and the second logic transistors (LTR2).

[0078] The first and second global bit lines (GBL1, GBL2) may each include a conductive material and, for example, may include at least one of a doped semiconductor material (doped silicon, doped silicon-germanium, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal (tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.), but are not limited thereto.

[0079] At least one second logic transistor (LTR2) may be connected between the second global bit line (GBL2) and the second local bit lines (LBL2). For example, a first source / drain region of the second logic transistor (LTR2) may be connected to the second local bit line (LBL2) through a second source / drain contact (268), a second via (286), and a second wire (282), and a second source / drain region of the second logic transistor (LTR2) may be connected to the second global bit line (GBL2) through a second source / drain contact (268), a second via (286), and a second wire (282). The second logic transistor (LTR2) may be configured to connect at least one selected of the second local bit lines (LBL2) to the second global bit line (GBL2). The second logic transistor (LTR2) may constitute a second local bit line multiplexer. The second logic transistor (LTR2) can be referred to as the second local bit line multiplexer.

[0080] A bit line pad area (BPR) may be positioned on at least one side of the cell area (1). In some embodiments, the bit line pad area (BPR) may be positioned on one side of the cell area (1) toward the first direction (DR1). The cell area (1) and the bit line pad area (BPR) may be adjacent toward the first direction (DR1). A bit line contact (BLC) may be positioned in the bit line pad area (BPR).

[0081] In some embodiments, the bit line contacts (BLC) may be arranged in a zigzag pattern along the second direction (DR2) in the bit line pad area (BPR).

[0082] The bit line contact (BLC) can be extended in a third direction (DR3). The bit line contact (BLC) can be extended in a third direction (DR3) within the second wiring insulation layer (280), the second interlayer insulation layer (234), the second insulation pattern (233), the second cell insulation layer (232), the second insulation layer (240), and the first wiring insulation layer (180). The bit line contact (BLC) can electrically connect the first global bit line (GBL1) and the second global bit line (GBL2).

[0083] The first bonding insulating layer (290) may be disposed on the second wiring insulating layer (280). The first bonding pad (292) may be disposed within the first bonding insulating layer (290). The first bonding pad (292) may be connected to the second via (286). The first bonding pad (292) may be electrically connected to the second wirings (262) and the second vias (286). The first bonding pad (292) may be electrically connected to the second global bit line (GLB2).

[0084] In some embodiments, the first cell structure (CS1) and the second cell structure (CS2) may be bonded to each other by bonding the first insulating layer (140) and the second insulating layer (240). The first insulating layer (140) and the second insulating layer (240) may be in contact. In some embodiments, each bit line contact (BLC) may be in contact with each first global bit line (GLB1) and the second global bit line (GBL2). The first logic transistor (LTR1) and the first global bit line (GBL1) may be between the first memory cells (MC1) and the second cell structure (CS2), and the second logic transistor (LTR2) and the second global bit line (GBL2) may be between the second memory cells (MC2) and the first cell structure (CS1).

[0085] A peripheral circuit structure (PR) may be placed on a second cell structure (CS2). The peripheral circuit structure (PR) may include a substrate (300), peripheral circuit transistors (PTR1, PTR2), a front insulating layer (380), front wiring (382), front vias (286), a second bonding insulating film (390), a second bonding pad (392), a rear insulating layer (320), rear wiring (322), rear vias (326), an external connection pad (340), and a through-via (330).

[0086] The substrate (300) may include a front and a back surface opposite in the third direction (DR3). The substrate (300) may include a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the substrate (300) may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0087] A device isolation pattern (302) may be formed within the substrate (300). The device isolation pattern (302) may be embedded in the front surface of the substrate (300). Peripheral circuit transistors (PTR1, PTR2) may be placed on the front surface of the substrate (300). Peripheral circuit transistors (PTR1, PTR2) may be placed on an active region defined by the device isolation pattern (302).

[0088] The first peripheral circuit transistor (PTR1) can constitute a sense amplifier. The first peripheral circuit transistor (PTR1) may be referred to as a sense amplifier. The first peripheral circuit transistor (PTR1) may be configured to sense and amplify data from the first and second local bit lines (LBL1, LBL2). The second peripheral circuit transistor (PTR2) may be a transistor that constitutes various circuits controlling the first and second memory cells (MC1, MC2). For example, the second peripheral circuit transistor (PTR2) may be a transistor that constitutes a sub-word line driver providing voltage to the first and second cell gate electrodes (GE1, GE2).

[0089] A front insulating layer (380) may be placed on the front surface of a substrate (300). Front wiring (382) and front vias (386) may be placed within the front insulating layer (380). Front vias (386) may connect front wirings (382) of different heights. The number, arrangement, and connection relationships of front wiring (382) and front vias (386) may vary. Front wiring (382) and front vias (386) may be electrically connected to peripheral circuit transistors (PTR1, PTR2). Front vias (386) may include vias connected to the source / drain regions and gate electrodes, respectively, of the peripheral circuit transistors (PTR1, PTR2).

[0090] The second bonding insulating film (390) may be disposed on the front insulating layer (380). The second bonding pad (392) may be disposed within the second bonding insulating film (390). The second bonding pad (392) may be connected to the front via (386). The second bonding pad (392) may be electrically connected to the front wiring (382) and the front vias (386).

[0091] In a semiconductor memory device according to some embodiments, the second cell structure (CS2) and the peripheral circuit structure (PR) may have a chip-to-chip structure. After manufacturing the second cell structure (CS2) and the peripheral circuit structure (PR), the semiconductor memory device may be manufactured by joining them.

[0092] The first bonding pad (292) and the second bonding pad (392) can be bonded to each other. As the first bonding pad (292) and the second bonding pad (392) are bonded, the second cell structure (CS2) and the peripheral circuit structure (PR) can be electrically connected. The first bonding pad (292) and the second bonding pad (392) can each be formed of various other metals such as copper (Cu), aluminum (Al), or tungsten (W). The first bonding insulating film (290) and the second bonding insulating film (390) can be bonded to each other. The first bonding insulating film (290) and the second bonding insulating film (390) can each include an insulating material such as silicon oxide.

[0093] The rear insulating layer (320) may be placed on the rear surface of the substrate (300). Rear wiring (322) and rear vias (326) may be placed within the rear insulating layer (320). The rear vias (326) may connect rear wirings (322) of different heights. The number, arrangement, and connection relationships of the rear wiring (322) and rear vias (326) may be varied.

[0094] A through-via (330) can pass through a rear insulating layer (320), a substrate (300), and a front insulating layer (380) to connect a rear wiring (322) and a front wiring (382). The through-via (330) can come into contact with the rear wiring (322) and the front wiring (382). An insulating spacer (332) can surround the side wall of the through-via (330).

[0095] The external connection pad (340) can be placed on the rear insulating layer (320). The external connection pad (340) can be connected to the rear wiring (322) and rear vias (326).

[0096] In a semiconductor memory device according to some embodiments, a first cell structure (CS1) and a second cell structure (CS2) may share a sense amplifier, that is, a first peripheral transistor (PTR1). A first global bit line (GBL1) and a second global bit line (GBL2) may share a sense amplifier. A plurality of global bit lines (GBL1, GBL2) can be sensed simultaneously with a single sense amplifier.

[0097] Specifically, the first local bit line (LBL1) can be electrically connected to the first peripheral transistor (PTR1) through the first logic transistor (LTR1), the first global bit line (GBL1), and the bit line contact (BLC). The second local bit line (BLB2) can be electrically connected to the first peripheral transistor (PTR1) through the second logic transistor (LTR2) and the second global bit line (GBL2). The first local bit line (LBL1) and the second local bit line (LBL2) can be selected by the first logic transistor (LTR1) and the second logic transistor (LTR2) and connected to a sense amplifier. Accordingly, the size of the semiconductor memory device can be reduced compared to the case where a sense amplifier is provided for each of the first and second cell structures (CS1, CS2). In addition, it may be easy to form a semiconductor memory device including a plurality of cell structures.

[0098] FIG. 4 is an exemplary cross-sectional view of a semiconductor memory device according to some embodiments. FIG. 4 is a cross-sectional view taken along I-I' of FIG. 1.

[0099] In some embodiments of FIGS. 1 and FIGS. 4, the first cell structure (CS1) may further include a third logic transistor (LTR3), and the second cell structure (CS2) may further include a fourth logic transistor (LTR4).

[0100] The third logic transistor (LTR3) and the fourth logic transistor (LTR4) may be placed in the bit line pad area (BPR). For example, the fourth logic transistor (LTR4) may be placed between the adjacent second local bit line (LBL2) and the bit line contact (BLC), and the third logic transistor (LTR3) may be placed below the fourth logic transistor (LTR4) so ​​as to overlap with the fourth logic transistor (LTR4) in the third direction (DR3).

[0101] In some embodiments, the third logic transistor (LTR3) may be formed at the same height as the first logic transistor (LTR1), and the fourth logic transistor (LTR4) may be formed at the same height as the second logic transistor (LTR2).

[0102] A third logic transistor (LTR3) may be formed on the first cell insulating layer (132). The third logic transistor (LTR3) may include a third logic semiconductor pattern (LSP3), a third logic gate electrode (LGE3), a third logic gate insulating film (LGI3), and a third logic gate spacer (LGS3).

[0103] The third logic semiconductor patterns (LSP3) can be defined by the first insulation patterns (133). The third logic semiconductor patterns (LSP3) can be insulated from the first logic semiconductor pattern (LSP1) by the first insulation pattern (133).

[0104] The third logic semiconductor pattern (LSP3) may include the same material as the first cell semiconductor pattern (SP1). In the third direction (DR3), the thickness of the third logic semiconductor pattern (LSP3) may be substantially the same as the thickness of the first logic semiconductor pattern (LSP1) and may be thicker than the thickness of the first cell semiconductor pattern (SP1).

[0105] A third logic gate electrode (LGE3) may be disposed on a third logic semiconductor pattern (LSP3). A third logic gate insulating film (LGI3) may be disposed between the third logic semiconductor pattern (LSP3) and the third logic gate electrode (LGE3). A third logic gate spacer (LGI3) may be disposed on the sidewalls of the third logic gate electrode (LGE3) and the third logic gate insulating film (LGI3). First and second source / drain regions may be provided within the third logic semiconductor pattern (LSP3) adjacent to both sides of the third logic gate electrode (LGE3).

[0106] The first interlayer insulating layer (134) can cover the third logic transistor (LTR3). The first logic gate contact (166) can contact the third logic gate electrode (LGE3), and the first source / drain contact (168) can contact the first and second source / drain regions, respectively, within the third logic semiconductor pattern (LS3P) on both sides of the third logic gate electrode (LGE3).

[0107] At least one third logic transistor (LTR3) may be connected between the first global bit line (GBL1) and the bit line contact (BLC). For example, the first source / drain region of the third logic transistor (LTR3) may be connected to the first global bit line (GBL1) through the first source / drain contact (168), the first via (186), and the first wiring (182), and the second source / drain region of the third logic transistor (LTR3) may be connected to the bit line contact (BLC) through the first wiring (188) located at the same height as the first global bit line (GBL1) among the first source / drain contact (168), the first via (186), and the first wirings (182). The third logic transistor (LTR3) may be configured to connect at least one selected of the first global bit lines (GLB1) to the bit line contact (BLC). The third logic transistor (LTR3) can constitute the first global bit line multiplexer. The third logic transistor (LTR3) can be referred to as the first global bit line multiplexer.

[0108] At least one fourth logic transistor (LTR4) may be connected between the second global bit line (GBL2) and the bit line contact (BLC). For example, the first source / drain region of the fourth logic transistor (LTR4) may be connected to the second global bit line (GBL2) through the second source / drain contact (268), the second via (286), and the second wiring (282), and the second source / drain region of the fourth logic transistor (LTR4) may be connected to the bit line contact (BLC) through the second wiring (288) located at the same height as the second global bit line (GBL2) among the second source / drain contact (268), the second via (286), and the second wirings (282). The fourth logic transistor (LTR4) may be configured to connect at least one selected of the second global bit lines (GLB2) to the bit line contact (BLC). The fourth logic transistor (LTR4) can constitute a second global bit line multiplexer. The fourth logic transistor (LTR4) can be referred to as a second global bit line multiplexer.

[0109] The bit line contact (BLC) can contact the first wiring (188) and the second wiring (288).

[0110] In a semiconductor memory device according to some embodiments, a sense amplifier can sense global bit lines (GBL1, GBL2) of selected cell structures (CS1, CS2) through first and second global bit line multiplexers.

[0111] FIG. 5 is an exemplary cross-sectional view of a semiconductor memory device according to some embodiments. FIG. 6 and FIG. 8 are cross-sectional views taken along I-I' of FIG. 5. FIG. 7 is an enlarged view of regions A1 and A2 of FIG. 6. For convenience of explanation, parts that overlap with those explained using FIG. 1 to 4 are briefly described, and the explanation focuses on the differences.

[0112] Referring to FIGS. 5 through 8, in a semiconductor memory device according to some embodiments, a first cell transistor (CTR1) included in some of the first memory cells (MC1) may be provided as a first logic transistor (LTR1), and a second cell transistor (CTR2) included in some of the second memory cells (MC2) may be provided as a second logic transistor (LTR2). A semiconductor region (SR) may overlap with a word line region (WR).

[0113] The first cell transistor (CTR1) of the first memory cell (MC1) placed at the top of the first memory cells (MC1) may be provided as a first logic transistor (LTR1). The first cell semiconductor pattern (SP1) placed at the top may be provided as a first logic semiconductor pattern (LSP1), and the first cell gate electrode (GE1) and the first cell gate insulating film (GI1) on the first cell semiconductor pattern (SP1) placed at the top may be provided as a first logic gate electrode (LGE1) and a first logic gate insulating film (LGI1), respectively. One end of the first logic semiconductor pattern (LSP1) toward the first direction (DR1) may be connected to a first local bit line (LBL1).

[0114] The second cell transistor (CTR2) of the second memory cell (MC2) placed at the top of the second memory cells (MC2) may be provided as a second logic transistor (LTR2). The second cell semiconductor pattern (SP2) placed at the top may be provided as a second logic semiconductor pattern (LSP2), and the second cell gate electrode (GE2) and the second cell gate insulating film (GI2) on the second cell semiconductor pattern (SP2) placed at the top may be provided as a second logic gate electrode (LGE2) and a second logic gate insulating film (LGI2), respectively. One end of the second logic semiconductor pattern (LSP2) toward the second direction (DR2) may be connected to a second local bit line (LBL2).

[0115] The first source / drain contact (164) can penetrate the first interlayer insulating layer (134) and the first cell insulating layer (132) to contact the second source / drain region of the first logic semiconductor pattern (LSP1). The second source / drain contact (268) can penetrate the second interlayer insulating layer (234) and the second cell insulating layer (232) to contact the second source / drain region of the second logic semiconductor pattern (LSP2). Although not illustrated, logic gate contacts may, for example, be placed in the word line pad region (WPR). Each of the logic gate contacts may contact the respective first and second logic gate electrodes (LGE1, LGE2).

[0116] In some embodiments, the other end of the first and second logic semiconductor patterns (LSP1, LSP2) toward the first direction (DR1) may be connected to the first and second data storage elements (170, 270), respectively. The first and second storage electrodes (172, 272) may each be in contact with the other end of the first and second logic semiconductor patterns (LSP1, LSP2), respectively. One end of the first and second logic semiconductor patterns (LSP1, LSP2) toward the first direction (DR1) may each be in contact with the first and second local bit lines (LBL1, LBL2), respectively.

[0117] Referring to FIG. 7, in some embodiments, an insulating pattern (150) may be interposed between the first and second logic semiconductor patterns (LSP1, LSP2) and the first and second data storage elements (170, 270). The other end of the first and second logic semiconductor patterns (LSP1, LSP2) in the first direction (DR1) may be spaced apart from each of the first and second data storage elements (170, 270). For example, an insulating pattern (150) may be interposed between each of the first and second logic semiconductor patterns (LSP1, LSP2) and each of the first and second storage electrodes (172, 272).

[0118] Referring to FIG. 8, in some embodiments, the first cell structure (CS1) may further include a third logic transistor (LTR3) described using FIG. 4, and the second cell structure (CS2) may further include a fourth logic transistor (LTR4) described using FIG. 4.

[0119] In some embodiments, the third logic transistor (LTR3) may be formed at a different height from the first logic transistor (LTR1), and the fourth logic transistor (LTR4) may be formed at a different height from the second logic transistor (LTR2). For example, the third logic transistor (LTR3) may be formed above the first logic transistor (LTR1) with respect to the front of the first insulating layer (140) on which the first memory cell (MC1) is formed, and the fourth logic transistor (LTR4) may be formed above the second logic transistor (LTR2) with respect to the front of the second insulating layer (240) on which the second memory cell (MC2) is formed.

[0120] FIGS. 9 and 10 are exemplary cross-sectional views of a semiconductor memory device according to some embodiments. For convenience of explanation, parts that overlap with those described using FIGS. 1 to 8 are described briefly, and the differences are described in detail.

[0121] Referring to FIG. 9, a semiconductor memory device according to some embodiments may include a plurality of cell structures (CS1 to CSn, where n is a natural number greater than or equal to 3) stacked in a third direction (DR3). The first cell structure (CS1) may have the same structure as any one of the first cell structures (CS1) described using FIGS. 1 to 8. The second to nth cell structures (CS2 to CSn) may each have the same structure as any one of the second cell structures (CS2) described using FIGS. 1 to 8. The second to nth cell structures (CS2 to CSn) may each include a bit line contact (BLC).

[0122] The first to nth cell structures (CS1 to CSn) may share a first peripheral transistor (PTR1). The global bit lines (GBL1, GBL2) of each of the first to nth cell structures (CS1 to CSn) may be electrically connected to the first peripheral transistor (PTR1) through a bit line contact (BLC).

[0123] Referring to FIG. 10, in a semiconductor memory device according to some embodiments, a first cell structure (CS1) and a second cell structure (CS2) may be a chip-to-chip structure. After manufacturing the first cell structure (CS1) and the second cell structure (CS2), the semiconductor memory device may be manufactured by joining them.

[0124] The first cell structure (CS1) may include a third bonding insulating film (490) and a third bonding pad (492) within the third bonding insulating film (490). The third bonding insulating film (490) may be disposed on the first wiring insulating layer (180). The third bonding pad (492) may be electrically connected to the first wiring (182, 188) and the first via (186).

[0125] The second cell structure (CS2) may include a fourth bonding insulating film (590) and a fourth bonding pad (592) within the fourth bonding insulating film (590). The fourth bonding insulating film (590) may be disposed on the second wiring insulating layer (280). The fourth bonding pad (592) may be electrically connected to the second wiring (282, 288) and the second via (286).

[0126] The third bonding pad (492) and the fourth bonding pad (592) can be bonded to each other. As the third bonding pad (492) and the fourth bonding pad (592) are bonded, the first cell structure (CS1) and the second cell structure (CS2) can be electrically connected. The third bonding pad (492) and the fourth bonding pad (592) can each be formed of various other metals such as copper (Cu), aluminum (Al), or tungsten (W). The third bonding insulating film (490) and the fourth bonding insulating film (590) can be bonded to each other. The third bonding insulating film (490) and the fourth bonding insulating film (590) can each include an insulating material such as silicon oxide.

[0127] The first logic transistors (LTR1) and the first global bit lines (GBL1) may be located between the first memory cells (MC1) and the second cell structure (CS2), and the second logic transistor (LTR2) and the second global bit lines (GBL2) may be located between the second memory cells (MC2) and the peripheral circuit structure (PR).

[0128] The first and second cell structures (CS1, CS2) may each have the same structure as either of the first and second cell structures (CS1, CS2) described using FIGS. 1 to 8.

[0129] FIGS. 11 to 13 are schematic layout diagrams of semiconductor memory devices according to several embodiments. For convenience of explanation, parts that overlap with those explained using FIGS. 1 to 10 are briefly described, and the explanation focuses on the differences.

[0130] Referring to FIG. 11, in a semiconductor memory device according to some embodiments, bit line pad regions (BPR1, BPR2) may be placed on both sides of a cell region (1), respectively.

[0131] For example, a first bit line pad area (BPR1), a cell area (1), and a second bit line pad area (BPR2) may be arranged along a first direction (DR1). A first bit line contact (BLC1) may be arranged in the first bit line pad area (BPR1), and a second bit line contact (BLC2) may be arranged in the second bit line pad area (BPR2). The first and second global bit lines (GBL1, GBL2) adjacent to the second direction (DR2) may be connected to the first bit line contact (BLC1) and the second bit line contact (BLC2), respectively. The first bit line contact (BLC1) and the second bit line contact (BLC2) may be arranged along the second direction (DR2) in the first bit line pad area (BPR1) and the second bit line pad area (BPR2), respectively. For example, each of the first global bit lines (GBL1) adjacent to the second direction (DR2) can be electrically connected to the first and second bit line contacts (BLC1, BLC2), respectively.

[0132] Although the cell region (1) of FIG. 11 is illustrated as an example, it is not limited thereto, and the semiconductor memory device may include the cell region (1) of FIG. 5.

[0133] Referring to FIGS. 12 and 13, a semiconductor memory device according to some embodiments may include first to nth memory blocks (BLK1 to BLKn) (n is a natural number, i is a natural number smaller than n). For example, the first to nth memory blocks (BLK1 to BLKn) may be arranged along a first direction (DR1). Each of the first to nth memory blocks (BLK1 to BLKn) may include a first cell structure (CS1), a second cell structure (CS2), and a peripheral circuit structure (PR) as described using FIGS. 1 to 10.

[0134] In FIGS. 12 and 13, the first to nth memory blocks (BLK1 to BLKn) are illustrated as examples including the cell region (1) of FIG. 1, but are not limited thereto, and the first to nth memory blocks (BLK1 to BLKn) may include the cell region (1) of FIG. 5.

[0135] The first and second global bit lines (GBL1, GBL2) of each of the first to nth memory blocks (BLK1 to BLKn) may be connected to each other. The first and second global bit lines (GBL1, GBL2) may extend in a first direction (DR1) on the first to nth memory blocks (BLK1 to BLKn). A bit line contact (BLC) may be placed in a bit line pad area (BPR). The first global bit line (GBL1) and the second global bit line (GBL2) may be electrically connected by the bit line contact (BLC).

[0136] Referring to FIG. 12, a bit line pad area (BPR) can be placed between adjacent memory blocks among memory blocks (BLK1 to BLKn). Bit line contacts (BLC) can be placed between adjacent memory blocks among memory blocks (BLK1 to BLKn). For example, a bit line pad area (BPR) can be placed between the i-th memory block (BLKi) and the (i+1)-th memory block (BLK(i+1)).

[0137] Referring to FIG. 13, a bit line pad region (BPR) may be placed at at least one end of the first to nth memory blocks (BLK1 to BLKn).

[0138] For example, a bit line pad area (BPR) may be placed on one side toward the first direction (DR1) of the nth memory block (BLKn). The bit line pad area (BPR) may be adjacent to the nth memory block (BLKn) in the first direction (DR1). As another example, the bit line pad area (BPR) may be placed on one side toward the first direction (DR1) of the first memory block (BLK1). The first memory block (BLK1) may be adjacent to the bit line pad area (BPR) in the first direction (DR1). As yet another example, the bit line pad area (BPR) may be placed on each side toward the first direction (DR1) of the first to nth memory blocks (BLK1 to BLKn). That is, the first to nth memory blocks (BLK1 to BLKn) may be placed between two bit line pad areas (BPR). A portion of the bit line contact (BLC) may be placed in a bit line pad area (BPR) adjacent to the nth memory block (BLKn), and the remainder may be placed in a bit line pad area (BPR) adjacent to the first memory block (BLK1).

[0139] FIGS. 14 to 37 are intermediate step drawings for explaining a method for manufacturing a semiconductor memory device according to some embodiments. FIGS. 15, 17, 21, 25, 29, 33, and 37 are cross-sectional views taken along A-A' of FIGS. 14, 16, 20, 24, 28, 32, and 36, respectively. FIGS. 18, 22, 26, 31, and 34 are cross-sectional views taken along B-B' of FIGS. 16, 20, 24, 30, and 32, respectively. FIGS. 19, 23, 27, and 35 are cross-sectional views taken along C-C' of FIGS. 16, 20, 24, and 32, respectively.

[0140] The bit line region (BR), word line region (WR), semiconductor region (SR), capacitor region (CR), plate region (PR), and word line pad region (WPR) shown in FIGS. 14, 16, 20, 24, 28, 30, 32, and 36 may represent, on a plane, regions in which a first local bit line (LBL1), a first cell gate electrode (GE1), a first logic semiconductor pattern (LSP1), a first data storage element (170), a first plate electrode (176), and a first cell gate connection pad (WLP1) are disposed to be formed in the processes described later. In FIGS. 14, 16, 20, 24, 28, 30, 32, and 36, A-A' may correspond to I-I' in FIG. 1. B-B' of the word line area (WR) in FIGS. 14, FIGS. 16, FIGS. 20, FIGS. 24, FIGS. 28, FIGS. 30, FIGS. 32 and FIGS. 36 may correspond to II-II' of FIGS. 1.

[0141] Referring to FIGS. 14 and 15, a mold structure (MS) is formed including a plurality of sacrificial layers (110) and a plurality of semiconductor layers (120) alternately stacked on a substrate (10).

[0142] The substrate (10) may be bulk silicon or SOI (silicon-on-insulator). The substrate (10) may be a silicon substrate, or may include other materials, for example, silicon germanium, gallium arsenide, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate (10) may be a base substrate on which an epitaxial layer is formed, or a ceramic substrate, a quartz substrate, or a glass substrate for a display.

[0143] The sacrificial layer (110) may be formed of a material having etch selectivity with respect to the semiconductor layer (120). The sacrificial layer (110) may be formed of at least one of, for example, silicon germanium, silicon oxide, silicon nitride, and silicon oxynitride. The semiconductor layer (120) may include, for example, silicon, germanium, silicon-germanium, or IGZO (Indium Gallium Zinc Oxide). In one example, the semiconductor layer (120) may include silicon, and the sacrificial layer (110) may include carbon-doped silicon germanium.

[0144] Next, a mold insulating layer (130) is formed on the mold structure (MS). The mold insulating layer (130) may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0145] Referring to FIGS. 14 to 19, the remaining sacrifice layers, excluding the lowest sacrifice layer (110a) among the plurality of sacrifice layers (110), are removed, and the remaining semiconductor layers, excluding the lowest semiconductor layer (120a) among the plurality of semiconductor layers (120), are patterned to form first cell semiconductor patterns (SP1).

[0146] For example, through a selective etching process, the semiconductor layers other than the semiconductor layer (120a) placed at the bottom of the plurality of semiconductor layers (120) can be removed. Accordingly, the upper and lower surfaces of the remaining sacrificial layers, excluding the sacrificial layer (110a) placed at the bottom of the plurality of sacrificial layers (110), can be exposed. Subsequently, through a thinning process, the thickness of the remaining semiconductor layers other than the semiconductor layer (110a) placed at the bottom of the plurality of semiconductor layers (120) can be reduced.

[0147] Next, the remaining layers, excluding the sacrificial layer (110a) placed at the bottom of the plurality of sacrificial layers (110), are removed, and the remaining space is filled with an insulating material to form a first cell insulating layer (132).

[0148] Next, the mold insulating layer (130) may be patterned to form a first insulating pattern. Using the first insulating pattern as an etching mask, semiconductor layers excluding the semiconductor layer (120a) placed at the bottom of the plurality of semiconductor layers (120) may be patterned. Using the first insulating pattern as an etching mask, a first trench may be formed to separate the semiconductor layers excluding the semiconductor layer (120a) placed at the bottom of the plurality of semiconductor layers (120) in a first direction (DR1). At this time, the bottom semiconductor layer (120a) may be used as an etching stop layer. The first trench may extend in a third direction (DR3) and penetrate the semiconductor layers excluding the bottom sacrificial layer (110a) and the bottom semiconductor layer (120a).

[0149] Subsequently, the first insulation pattern is removed, and an insulation layer covering the first interlayer insulation layer (134) can be formed. The insulation layer can be patterned to form a second insulation pattern. Using the second insulation pattern as an etching mask, semiconductor layers excluding the semiconductor layer (120a) located at the bottom of the plurality of semiconductor layers (120) can be patterned. Using the second insulation pattern as an etching mask, a second trench can be formed to separate the semiconductor layers excluding the semiconductor layer (120a) located at the bottom of the plurality of semiconductor layers (120) into a second direction (DR2). At this time, the bottom semiconductor layer (120a) can be used as an etching stop layer. The second trench can be extended in a third direction (DR3) and penetrate the semiconductor layers excluding the bottom sacrificial layer (110a) and the bottom semiconductor layer (120a). Subsequently, the second insulation pattern can be removed.

[0150] Accordingly, a plurality of first cell semiconductor patterns (SP1) can be formed that are spaced apart along the first direction (DR1) and the second direction (DR2) and stacked in the third direction (DR3). Among the semiconductor layers (120) excluding the first bottom semiconductor layer (120a), at least a portion of the remaining portion (120P) after the first cell semiconductor pattern (SP1) is formed can be replaced with a first cell gate connection pad (WLP1) in the subsequent process. The remaining portion (120P) can be located on an extension line along the second direction (DR2) of the plurality of first cell semiconductor patterns (SP1). The remaining portion (110P) can be placed in a word line pad area (WPR).

[0151] Next, a portion of the first cell insulating layer (132) surrounding a plurality of first cell semiconductor patterns (SP1) can be removed through a selective etching process. Subsequently, a first cell gate insulating film (GI1) surrounding each portion of a plurality of first cell semiconductor patterns (SP1) can be formed through a deposition process. The first cell gate insulating film (GI1) can be formed, for example, through an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process.

[0152] Subsequently, a first cell gate electrode (GE1) covering the first cell gate insulating film (GI1) may be formed. For example, a portion of the first interlayer insulating layer (134) may be removed through the selective etching process via a CVD process, and a first cell gate electrode (GE1) that fills the remaining space may be formed. Accordingly, a first cell transistor (CTR1) including the first cell gate electrode (GE1) and the first cell semiconductor pattern (SP1) may be formed.

[0153] The first cell gate electrode (GE1) may have a line shape extending in the second direction (DR2). The first cell gate electrode (GE1) may surround a first cell semiconductor pattern (SP1) disposed along the second direction (DR2). The first cell gate electrode (GE1) may be spaced apart from the first cell gate electrode (GE1) by a first cell gate insulating film (GI1). The first cell gate electrode (GE1) may be disposed in a word line region (WR).

[0154] Referring to FIGS. 20 to 23, a first insulating layer (140) may be formed on a mold structure (MS). A carrier substrate (20) may be attached to the first insulating layer (140). The carrier substrate (20), the mold structure (MS), and the substrate (10) may be inverted vertically. That is, the substrate (10) may be placed at the top and the carrier substrate (20) may be placed at the bottom. Subsequently, the substrate (10) and the bottom sacrificial layer (110a) may be removed.

[0155] Next, the bottom semiconductor layer (120a) may be patterned to form a first logic semiconductor pattern (LSP1). For example, a photoresist pattern may be formed on the bottom semiconductor layer (120a) through an exposure and development process, and an etching process may be performed using the photoresist pattern as an etching mask to form a third trench penetrating the bottom semiconductor layer (120a) in a third direction (DR3). An insulating material may be filled into the third trench to form a first insulating pattern (133). The first insulating pattern (133) may serve as a device isolation mechanism. The first logic semiconductor pattern (LSP1) may be defined by the first insulating pattern (133). The first logic semiconductor pattern (LSP1) may be placed in a semiconductor region (SR).

[0156] Subsequently, a first logic gate electrode (LGE1), a first logic gate insulating film (LGI1), and a first gate spacer (LGS1) may be formed on a first logic semiconductor pattern (LSP1). The first logic gate insulating film (LGI1) may be formed on the first logic semiconductor pattern (LSP1). The first logic gate electrode (LGE1) may be formed on the first logic gate insulating film (LGI1). The first logic gate spacer (LGS1) may be formed on both sides of the first logic gate electrode (LGE1) and on both sides of the first logic gate insulating film (LGI1). Impurities may be doped into the first logic semiconductor pattern (LSP1) on both sides of the first logic gate electrode (LGE1) to form first and second source / drain regions. Accordingly, a first logic gate insulating film (LGI1), a first logic semiconductor pattern (LSP1), a first logic gate electrode (LGE1), a first gate spacer (LGS1), and a first logic transistor (LTR1) including the first and second source / drain regions can be formed.

[0157] Referring to FIGS. 24 to 27, a first interlayer insulating layer (134) covering a first logic gate electrode (LGE1), a first logic semiconductor pattern (LSP1), and a first insulating pattern (133) may be formed. The first interlayer insulating layer (134) may cover the first logic gate electrode (GE1), the first logic gate spacer (LGS1), the first logic semiconductor pattern (LSP1), and the first insulating pattern (133).

[0158] Subsequently, a first logic gate contact (162) and a first source / drain contact (164) can be formed penetrating the first interlayer insulating layer (134). For example, contact holes penetrating the first interlayer insulating layer (134) can be formed, and a metal material can be filled into the internal space of the contact holes to form the first logic gate contact (162) and the first source / drain contact (164). The first logic gate contact (162) can penetrate the first interlayer insulating layer (134) and contact the upper surface of the first logic gate electrode (LGE1). The first source / drain contact (164) can penetrate the first interlayer insulating layer (134) and contact the upper surface of the first logic semiconductor pattern (LSP1) located on both sides of the first logic gate electrode (LGE1). The first source / drain contact (164) can be connected to each of the first and second source / drain regions.

[0159] Subsequently, a fourth trench may be formed penetrating the first interlayer insulating layer (134), the first insulating pattern (133), and the first cell insulating layer (132). The fourth trench may be formed through a process of etching the first interlayer insulating layer (134), the first insulating pattern (133), and the first cell insulating layer (132) in a third direction (DR3), and in the etching process for forming the fourth trench, the first insulating layer (140) may be used as an etching stop layer. By forming the fourth trench, one end of each of the plurality of first cell semiconductor patterns (SP1) may be exposed. For example, one end of each of the plurality of first cell semiconductor patterns (SP1) may be exposed in a first direction (DR1). Impurities may be doped onto the surface of the exposed end of each of the plurality of first cell semiconductor patterns (SP1) in the first direction (DR1).

[0160] Next, a first local bit line (LBL1) can be formed by filling the fourth trench with a conductive material. The first local bit line (LBL1) can come into contact with one end of each of a plurality of first cell semiconductor patterns (SP1). The first local bit line (LBL1) may have a pillar shape extending in a third direction (DR3). A plurality of first cell semiconductor patterns (SP1) stacked in the third direction (DR3) may be connected to a single first local bit line (LBL1).

[0161] The first local bit line (LBL1) may be formed in the bit line area (BR) of FIG. 24. Although the planar shape of the first local bit line (LBL1) is depicted as being rectangular, it is not limited thereto, and the planar shape of the first local bit line (LBL1) may be circular, elliptical, or other polygonal.

[0162] Subsequently, the remaining portions (120P) of the semiconductor layer (120) located on the same layer as each of the plurality of first cell semiconductor patterns (SP1) may be replaced with a conductive material to form a plurality of first cell gate connection pads (WLP1) connected to each of the plurality of first cell gate electrodes (GE1). Each of the plurality of first cell gate connection pads (WLP1) may be connected to each of the plurality of first cell gate electrodes (GE1) in a second direction (DR2). The plurality of first cell gate connection pads (WLP1) may be placed in the word line pad area (WPR) of FIG. 24.

[0163] A plurality of first cell gate connection pads (WLP1) may have a stepped structure. For example, the length of a plurality of first cell gate connection pads (WLP1) in the second direction (DR2) may increase as it is adjacent to the first insulating layer (140).

[0164] Referring to FIGS. 28 and 29, a fifth trench is formed penetrating the first interlayer insulating layer (134), the first insulating pattern (133), and the first cell insulating layer (132), and a plurality of data storage elements (170) can be formed through the fifth trench. The fifth trench can be formed by a process of etching the first interlayer insulating layer (134), the first insulating pattern (133), and the first cell insulating layer (132) in a third direction (DR3). At this time, the first insulating layer (140) can be used as an etching stop layer. The bottom surface of the fifth trench can be defined by the upper surface of the first insulating layer (140). The sidewalls of the fifth trench may be defined by the side of the first interlayer insulating layer (134), the side of the first insulating pattern (133), the side of the first cell insulating layer (132), and the side of each of the plurality of first cell semiconductor patterns (SP1). The plurality of first cell semiconductor patterns (SP1) may be exposed by the fifth trench.

[0165] Subsequently, a plurality of first recesses may be formed by etching a portion of each of the plurality of first cell semiconductor patterns (SP1) exposed through the fifth trench. The first recesses may be formed by etching the first cell semiconductor pattern (SP1) in a first direction (DR1). By forming the first recesses, the other end of the first cell semiconductor pattern (SP1) may be exposed. For example, the other end according to the first direction (DR1) of each of the plurality of first cell semiconductor patterns (SP1) may be exposed. Impurities may be doped onto the surface of the exposed other end of each of the plurality of first cell semiconductor patterns (SP1) through the first recesses.

[0166] Subsequently, a plurality of first electrodes (172) can be formed by filling the plurality of first recesses with a conductive material. Each of the plurality of first electrodes (172) can be in contact with the other end of each of the plurality of first cell semiconductor patterns (SP1). Each of the plurality of first electrodes (172) can be connected to each of the plurality of first cell semiconductor patterns (SP1) in a first direction (DR1).

[0167] Subsequently, a portion of the first cell insulating layer (132) exposed through the fifth trench may be etched to form a plurality of second recesses. Some of the plurality of second recesses may have side walls defined by faces facing the third direction (DR3) of the plurality of first electrodes (172), and a bottom surface defined by the side of the first cell insulating layer (132). Other portions of the plurality of second recesses may have side walls defined by the upper surface of the first electrode (172), the lower surface of the first logic semiconductor pattern (LSP1) and the first insulating pattern (133), and a bottom surface defined by the side of the first cell insulating layer (132). Yet another portion of the plurality of second recesses may have side walls defined by the lower surface of the first electrode (172) and the upper surface of the first insulating layer (140), and a bottom surface defined by the side of the first cell insulating layer (132). Each of the above plurality of second recesses can be formed by etching a first cell insulating layer (132) located between the plurality of first cell semiconductor patterns (SP1), between the uppermost first cell semiconductor pattern (SP1) and the first logic semiconductor pattern (LSP1), and between the lowermost first cell semiconductor pattern (SP1) and the first insulating layer (140) in the first direction (DR1).

[0168] Next, a first dielectric layer (174) and a first conductive layer (176a) can be formed covering the side walls and bottom surfaces of the plurality of second recesses and the side walls and bottom surfaces of the fifth trench. The first dielectric layer (174) may extend along the fifth trench and the plurality of second recesses. The first conductive layer (176a) may be formed along the first dielectric layer (174).

[0169] Subsequently, the remaining space of the plurality of second recesses and the remaining space of the fifth trench may be filled with a conductive material to form a second conductive layer (176b). Accordingly, a first plate electrode (176) comprising a first conductive layer (176a) and a second conductive layer (176b) may be formed. A plurality of data storage elements (170) comprising a plurality of first electrodes (172), a first dielectric layer (174), and a first plate electrode (176) may be formed. The first plate electrode (176) may be placed in a plate region (PR). A plurality of first electrodes (172), a first dielectric layer (174), and a first plate electrode (176) between adjacent first electrodes (172) may be placed in a capacitor region (CR).

[0170] Referring to FIGS. 30 and 31, a plurality of sixth trenches can be formed penetrating the first interlayer insulating layer (134), the first insulating pattern (133), and the first cell insulating layer (132). The plurality of sixth trenches can be formed through a process of etching the first interlayer insulating layer (134), the first insulating pattern (133), and the first cell insulating layer (132) in a third direction (DR3). At this time, the first cell gate connection pad (WLP1) can be used as an etching stop layer.

[0171] Subsequently, a plurality of first cell gate contacts (WLC1) may be formed by filling the plurality of sixth trenches with a conductive material. Each of the plurality of first cell gate contacts (WLC1) may contact the upper surface of each of the plurality of first cell gate connection pads (WLP1). Each of the plurality of first cell gate connection pads (WLP1) may be connected to each of the plurality of first cell gate electrodes (GE1) stacked in the third direction (DR3). The first cell gate contacts (WLC1) may have a pillar shape extending in the third direction (DR3).

[0172] The first cell gate contact (WLC1) may be placed in the word line pad area (WPR). Although the planar shape of the first cell gate contact (WLC1) is depicted as being rectangular, it is not limited thereto, and the planar shape of the first cell gate contact (WLC1) may be circular, elliptical, or other polygonal.

[0173] Referring to FIGS. 32 to 35, a first wiring (182) and a first global bit line (GBL1) may be formed on a first interlayer insulating layer (134). For example, a first wiring insulating layer (180) may be formed on the first interlayer insulating layer (134), and after patterning the first wiring insulating layer (180), a conductive material may be deposited to form a plurality of first wirings (182), a plurality of first vias (186), and a first global bit line (GBL1). The plurality of first wirings (182) may be composed of a plurality of layers, and the plurality of first vias (186) may connect a plurality of first wirings (182) located on different layers. A plurality of first wires (182) and a plurality of first vias (186) can be connected to a first global bit line (GBL1), a first local bit line (LBL1), a first cell gate contact (WLC1), a first plate electrode (176) of a plurality of first data storage elements (170), a first logic gate contact (166), and a first source / drain contact (168).

[0174] The first wiring (182) can connect the first global bit line (GBL1) and the first local transistor (LTR1), and can connect the first local bit line (LBL1) and the first local transistor (LTR1). The first wiring (182) can connect the first global bit line (GBL1) to one of a pair of first source / drain contacts (168) connected to a pair of source / drain regions of the first local transistor (LTR1), and can connect the first local bit line (LBL1) to the other of the said pair of first source / drain contacts (168). That is, the first local transistor (LTR1) can be connected between the first global bit line (GBL1) and the first local bit line (LBL1).

[0175] Referring to FIGS. 36 and 37, a second cell structure (CS2) can be bonded to a first cell structure (CS1).

[0176] For example, by the manufacturing method described above using FIGS. 14 to 35, a second insulating layer (240), second local bit lines (LBL2), second memory cells (MC2), second logic transistors (LTR2), second logic gate contacts (266), second source / drain contacts (268), a second wiring insulating layer (280), and second wirings (282) can be formed on a carrier substrate. That is, a part of a second cell structure (CS2) can be formed on the carrier substrate. The carrier substrate can be removed, and a part of the second cell structure (CS2) can be bonded. The second insulating layer (240) can be in contact with the first wiring insulating layer (180). Accordingly, the second cell structure (CS2) can be bonded to the first cell structure (CS1). Subsequently, a bit line contact (BLC), a first global bit line (GLB2), a second via (286), a second wiring insulation layer (280), a first bonding insulation film (290), and a first bonding pad (292) may be formed. Accordingly, a second cell structure (CS2) may be formed.

[0177] Next, referring to FIGS. 1 and 2, a peripheral circuit structure (PR) can be bonded onto a second cell structure (CS2). The first bonding insulating film (290) and the first bonding pad (292) of the second cell structure (CS2) can be bonded to the second bonding insulating film (390) and the second bonding pad (392) of the peripheral circuit structure (PR), respectively.

[0178] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0179] CS1, CS2: First and second cell structures PR: Peripheral circuit structure LBL1, LBL2: 1st and 2nd local bit lines GBL1, GBL2: 1st and 2nd global bit lines LTR1~LTR4: 1st to 4th logic transistors PTR1, PTR2: 1st and 2nd peripheral circuit transistors BLC: Bit Line Contact

Claims

Claim 1 A first cell structure comprising first local bit lines extending in a vertical direction, first memory cells connected to each of the first local bit lines and arranged in the vertical direction, first local bit line multiplexers each electrically connected to the first local bit lines, and first global bit lines each electrically connected to the first local bit line multiplexers; a second cell structure on the first cell structure comprising second local bit lines extending in the vertical direction, second memory cells connected to each of the second local bit lines and arranged in the vertical direction, second local bit line multiplexers each electrically connected to the second local bit lines, and second global bit lines electrically connected to the second local bit line multiplexers; bit line contacts penetrating the second cell structure and electrically connecting each of the first global bit lines and each of the second global bit lines; A semiconductor memory device comprising a peripheral circuit structure including a sense amplifier electrically connected to the bit line contacts on the second cell structure, wherein the first global bit lines and the second global bit lines share the sense amplifier. Claim 2 A semiconductor memory device according to claim 1, wherein the first cell structure further comprises first global bit line multiplexers electrically connected to the first global bit lines, the second cell structure further comprises second global bit line multiplexers electrically connected to the second global bit lines, and each bit line contact electrically connects each of the first global bit line multiplexers and each of the second global bit line multiplexers. Claim 3 A semiconductor memory device according to claim 1, wherein the first cell structure and the second cell structure comprise a cell region and a bit line pad region adjacent to the cell region in a first horizontal direction, the first global bit lines and the second global bit lines extend in the first horizontal direction in the cell region and the bit line pad region, and the bit line contacts are arranged in a zigzag pattern along the second horizontal direction in the bit line pad region. Claim 4 A first cell structure comprising: a first local bit line extending vertically on a first insulating layer; first cell semiconductor patterns arranged vertically with one end connected to the first local bit line; first data storage elements connected to the other end of the first cell semiconductor patterns; first cell gate electrodes on the first cell semiconductor patterns; a first logic semiconductor pattern spaced vertically from the first cell semiconductor patterns; a first logic transistor electrically connected to the first local bit line on the first logic semiconductor pattern; and a first global bit line electrically connected to the first logic transistor; a second local bit line extending vertically on a second insulating layer; second cell semiconductor patterns arranged vertically with one end connected to the second local bit line; second data storage elements connected to the other end of the second cell semiconductor patterns; second cell gate electrodes on the second cell semiconductor patterns; a second logic semiconductor pattern spaced vertically from the second cell semiconductor patterns; and a second logic semiconductor pattern electrically connected to the second local bit line on the second logic semiconductor pattern. A semiconductor memory device comprising: a transistor; a second cell structure including a second global bit line electrically connected to the second logic transistor; a bit line contact penetrating the second cell structure and electrically connecting the first global bit line and the second global bit line; and a peripheral circuit structure including a peripheral circuit board and a peripheral circuit transistor electrically connected to the first global bit line and the second global bit line on the peripheral circuit board. Claim 5 A semiconductor memory device according to claim 4, wherein the first cell structure further comprises a first cell insulating layer between the first cell semiconductor patterns, the second cell structure further comprises a second cell insulating layer between the second cell semiconductor patterns, the first logic semiconductor pattern is disposed on the first cell insulating layer, and the second logic semiconductor pattern and the second logic transistor are on the second insulating layer. Claim 6 A semiconductor memory device according to claim 5, wherein the first cell structure further comprises a third logic semiconductor pattern on the first cell insulating layer and a third logic transistor on the third logic semiconductor pattern, and the second cell structure further comprises a fourth logic semiconductor pattern on the second insulating layer and a fourth logic transistor on the fourth logic semiconductor pattern, wherein the third logic transistor is electrically connected to the first global bit line and the bit line contact, and the fourth logic transistor is electrically connected to the second global bit line and the bit line contact. Claim 7 A semiconductor memory device according to claim 4, wherein one end of the first logic semiconductor pattern is connected to the first local bit line and the other end of the first logic semiconductor pattern is connected to the first data storage elements, one end of the second logic semiconductor pattern is connected to the second local bit line and the other end of the second logic semiconductor pattern is connected to the first data storage elements. Claim 8 A semiconductor memory device according to claim 4, wherein the first cell structure further comprises a first cell insulating layer between the first cell semiconductor patterns on the first insulating layer, and a first cell insulating layer covering the first global bit line on the first cell insulating layer, and the second cell structure further comprises a second cell insulating layer between the second cell semiconductor patterns on the second insulating layer, a second cell insulating layer covering the second global bit line on the second cell insulating layer, a first bonding insulating layer on the second cell insulating layer, and a first bonding pad in the second cell insulating layer, and the peripheral circuit structure further comprises a second bonding insulating layer and a second bonding pad in the second bonding insulating layer, wherein the first cell insulating layer contacts the second insulating layer, the first bonding insulating layer contacts the second bonding insulating layer, and the first bonding pad contacts the second bonding pad. Claim 9 In claim 4, the first cell structure further comprises a first cell insulating layer between the first cell semiconductor patterns on the first insulating layer, a first cell insulating layer covering the first global bit line on the first cell insulating layer, a first bonding insulating layer on the first cell insulating layer, and a first bonding pad within the first bonding insulating layer; the second cell structure further comprises a second cell insulating layer between the second cell semiconductor patterns on the second insulating layer, and a second cell insulating layer covering the second global bit line on the second cell insulating layer, a second bonding insulating layer on the second cell insulating layer, a second bonding pad within the second cell insulating layer, a third bonding insulating layer on the second insulating layer, and a third bonding pad within the third bonding insulating layer; the peripheral circuit structure further comprises a fourth bonding insulating layer and a fourth bonding pad within the fourth bonding insulating layer; the first bonding insulating layer is in contact with the second bonding insulating layer, and the first bonding pad is the A semiconductor memory device in which a second bonding pad is in contact, the third bonding insulating layer is in contact with the fourth bonding insulating layer, and the third bonding pad is in contact with the fourth bonding pad. Claim 10 A semiconductor memory device comprising: a first cell structure including first local bit lines extending in a vertical direction, first memory cells connected to each of the first local bit lines and arranged in the vertical direction, first global bit lines on the first memory cells, first local bit line multiplexers electrically connected to the first global bit lines and the first local bit lines, and first global bit line multiplexers electrically connected to the first global bit lines; a second cell structure including second local bit lines extending in the vertical direction, second memory cells connected to each of the second local bit lines and arranged in the vertical direction, second global bit lines on the second memory cells, second local bit line multiplexers electrically connected to the second global bit lines and the second local bit lines, and second global bit line multiplexers electrically connected to the second global bit lines; and a peripheral circuit structure including a sense amplifier electrically connected to the first global bit lines and the second global bit lines on the second cell structure.

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