Single Bitline 7T-SRAM

Abstract

A single-bitline 7T-SRAM capable of performing read and write operations with only a single bitline is disclosed. Since read and write operations can be performed with only a single bitline using the 7T-SRAM, the number of bitlines can be reduced by half, thereby making manufacturing easier. In addition, only one access transistor connected to a single bitline is required, and in particular, since the access transistor is turned off during a read operation to read data '1', the static noise margin (SNM) can be increased, thereby improving stability.

Description

Technology Field

[0001] The present invention relates to a 7T-SRAM, and more specifically, to a single bitline 7T-SRAM capable of read and write operations using only a single bitline. Background Technology

[0002] Static Random Access Memory (SRAM) is a type of semiconductor memory capable of high-speed operation, making it widely used in speed-critical applications such as internal CPU memory. Recently, various studies are continuing to develop on-chip memory with faster speeds and larger capacities.

[0003] A typical memory cell of SRAM is a 6T (6-transistor) memory cell composed of 6 transistors.

[0004] Figure 1 is a diagram showing a conventional 6T-SRAM configuration.

[0005] Figure 2 is a diagram showing an SRAM array structure using a conventional 6T-SRAM cell.

[0006] FIG. 3 is a diagram showing another embodiment of an SRAM array structure using a conventional 6T-SRAM cell.

[0007] Referring to FIGS. 1 to 3, a conventional 6T-SRAM is composed of two access transistors (AX) and a latch (10) connected to the two access transistors (AX). Here, the latch (10) is composed of two inverters (11, 12) cross-coupled using four transistors (PU, PD).

[0008] Two access transistors (AX) are activated by the word line (WL) and connected to the bit line (BL) and the inverted bit line (BLb) to transmit data between the latch (10) and the bit line (BL) and the inverted bit line (BLb). Additionally, each bit is stored by the latch (10) forming two cross-coupled inverters (11, 12).

[0009] When configuring an SRAM array using these 6T-SRAM cells, as shown in Fig. 2, one column shares two bit lines (BL, BLb). However, this structure inevitably results in low efficiency because it cannot simultaneously read or write data from cells connected to the same column. To overcome this disadvantage, as shown in Fig. 3, two bit lines (BL, BLb) can be connected to each cell to enable simultaneous parallel read and write operations even for cells connected to the same column. However, this parallel array structure has the disadvantage of increasing area due to the need for many bit lines (BL, BLb) and presents a problem of difficult manufacturing. Prior art literature

[0010] Korean Published Patent 10-2011-0013212 The problem to be solved

[0011] The technical problem that the present invention aims to solve is to provide a single bitline 7T-SRAM that can reduce area and improve safety by enabling read and write operations with only a single bitline using a 7T-SRAM structure. means of solving the problem

[0012] The single bitline 7T-SRAM of the present invention for solving the above problem comprises a wordline, an access transistor with a gate connected to the wordline, a latch unit connected to one end of the access transistor through a data node and storing data by the operation of a cross-coupled first inverter and a second inverter, a single bitline connected to the other end of the access transistor and inputting and outputting data, and an input / output control unit connected to the latch unit and controlling the operation of the latch unit so that data reading and writing operations are performed through the single bitline.

[0013] Depending on whether the above input / output control unit is operating, a read operation or a write operation through the single bit line may be determined.

[0014] When the above read operation is performed, the above input / output control unit is activated, and when the above write operation is performed, the above input / output control unit may be deactivated.

[0015] When the above write operation is performed, data of '0' or '1' can be stored in the data node through the single bit line.

[0016] The above input / output control unit may include a first control transistor whose drain is connected to the data node, and a second control transistor whose drain is connected to the source of the first control transistor, whose source is connected to ground voltage, and whose gate is connected to the first inverter through the control node.

[0017] The first control transistor and the second control transistor may be formed as NMOS transistors.

[0018] The first control transistor above can be turned off when the write operation is performed and turned on when the read operation is performed.

[0019] The first inverter may include a first pull-up transistor, the source of which is connected to the power supply voltage and the drain of which is connected to the data node, and a first pull-down transistor, the source of which is connected to the ground voltage, the drain of which is connected to the data node, and the gate of which is connected to the control node.

[0020] The second inverter may include a second pull-up transistor whose source is connected to the power supply voltage and a second pull-down transistor whose source is connected to the ground voltage, whose drain is connected to the drain of the second pull-up transistor, and whose gate is connected to the drain of the first control transistor.

[0021] The access transistor may have a larger size than the transistors of the first inverter and the second inverter.

[0022] When reading data of '1' stored in the data node, the access transistor is turned off, and when reading data of '0' stored in the data node, the access transistor can be turned on.

[0023] When reading the data of the above '0', a pull-down operation can be performed by turning on the first pull-down transistor and the second control transistor.

[0024] The sizes of the first pull-down transistor and the second control transistor may have a size such that the pull-down is performed in comparison to the driving capability of the access transistor. Effects of the invention

[0025] According to the present invention, since read and write operations are possible using only a single bit line by using a 7T-SRAM, the number of bit lines can be reduced by half, and accordingly, manufacturing can be made easier.

[0026] In addition, only one access transistor connected to a single bit line is required, and since the access transistor is turned off, especially during a read operation to read data of '1', the static noise margin (SNM) can be increased, thereby improving stability.

[0027] The technical effects of the present invention are not limited to those mentioned above, and other unmentioned technical effects will be clearly understood by those skilled in the art from the description below. Brief explanation of the drawing

[0028] Figure 1 is a diagram showing a conventional 6T-SRAM configuration. Figure 2 is a diagram showing an SRAM array structure using a conventional 6T-SRAM cell. FIG. 3 is a diagram showing another embodiment of an SRAM array structure using a conventional 6T-SRAM cell. Figure 4 is a diagram showing the 7T-SRAM of the present invention. FIG. 5 is a diagram showing the write operation of a 7T-SRAM according to the present invention. FIG. 6 is a diagram showing the timing diagram of a 7T-SRAM according to the present invention. FIG. 7 is a diagram showing a read operation for reading data of '1' using a 7T-SRAM according to the present invention. FIG. 8 is a diagram showing a read operation for reading data of '0' using a 7T-SRAM according to the present invention. FIG. 9 is a diagram showing a parallel structure array of a 7T-SRAM according to the present invention. Figure 10 is a simulation result for comparing the HSNM of the 7T-SRAM of the present invention and the conventional 6T-SRAM. Figure 11 is a simulation result for comparing the RSNM of the 7T-SRAM of the present invention and the conventional 6T-SRAM. Figure 12 is a simulation result for comparing the WSNM of the 7T-SRAM of the present invention and the conventional 6T-SRAM. Figure 13 is a graph for comparing the SNM indicators of the 7T-SRAM of the present invention and the conventional 6T-SRAM. Specific details for implementing the invention

[0029] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and it should be understood that it includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the present invention. In describing the present invention, detailed descriptions of related prior art are omitted if it is determined that such detailed descriptions may obscure the essence of the present invention.

[0030] Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In describing with reference to the accompanying drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0032] Examples

[0033] Figure 4 is a diagram showing the 7T-SRAM of the present invention.

[0034] Referring to FIG. 4, the 7T-SRAM according to the present invention includes an access transistor (AX), a latch unit (110), and an input / output control unit (120).

[0035] The gate of the access transistor (AX) can be connected to the word line (WL). That is, the access transistor (AX) can be activated by the word line (WL) signal. Additionally, the drain of the access transistor (AX) can be connected to a single bit line (BL), and the source can be connected to the latch unit (110) through the data node (Q). Thus, by the operation of the access transistor (AX), a write operation to store data in the latch unit (110) and a read operation to read the stored data can be performed. For example, the access transistor (AX) can be an NMOS transistor.

[0036] The latch unit (110) can be connected to the access transistor (AX) through the data node (Q). The latch unit (110) can store data by the operation of the access transistor (AX). Additionally, the latch unit (110) may include a cross-coupled first inverter (111) and a second inverter (112). That is, data can be stored through the data node (Q) by the operation of the first inverter (111) and the second inverter (112).

[0037] The first inverter (111) may include a first pull-up transistor (PU1) and a first pull-down transistor (PD1).

[0038] The source of the first pull-up transistor (PU1) can be connected to a first voltage, and the drain can be connected to a data node (Q). Here, the first voltage can be, for example, a power supply voltage (VDD). Additionally, the first pull-up transistor (PU1) can be a PMOS transistor.

[0039] The source of the first pull-down transistor (PD1) can be connected to the second voltage, and the drain can be connected to the drain of the first pull-up transistor (PU1) through the data node (Q). Additionally, the gate can be connected to the gate of the first pull-up transistor (PU1) through the control node (N). That is, the first pull-up transistor (PU1) and the first pull-down transistor (PD1) can be connected in series between the first voltage and the second voltage to form a first inverter (111) structure. Here, the second voltage may be a voltage lower than the first voltage. For example, the second voltage may be a ground voltage (GND). Additionally, the first pull-down transistor (PD1) may be an NMOS transistor.

[0040] The second inverter (112) may include a second pull-up transistor (PU2) and a second pull-down transistor (PD2).

[0041] The source of the second pull-up transistor (PU2) can be connected to the first voltage, and the drain can be connected to the drain of the second pull-down transistor (PD2). For example, the second pull-up transistor (PU2) can be a PMOS transistor.

[0042] The source of the second pull-down transistor (PD2) can be connected to the second voltage, and the drain can be connected to the drain of the second pull-down transistor (PD2) and the input of the first inverter (111). Additionally, the gate can be connected to the gate of the second pull-up transistor (PU2) and the data node (Q). Here, the second pull-down transistor (PD2) may be an NMPS transistor. That is, the second pull-up transistor (PU2) and the second pull-down transistor (PD2) can be connected in series between the first voltage and the second voltage to form the structure of the second inverter (112).

[0043] Here, the input of the second inverter (112) can be connected to the output of the first inverter (111), and the output of the second inverter (112) can be connected to the input of the first inverter (111). Accordingly, the latch unit (110) can have a latch circuit form in which the first inverter (111) and the second inverter (112) are cross-coupled.

[0044] For example, when data of '1' or '0' to be written is transmitted through a single bit line (BL) to the latch unit (110), the data of '1' or '0' can be stored in the data node (Q) by activating the access transistor (AX). At this time, it is preferable that the access transistor (AX) has a larger size than the transistors of the first inverter (111) and the second inverter (112).

[0045] That is, by forming the access transistor (AX) to have a larger size than the first pull-up transistor (PU1), the first pull-down transistor (PD1), the second pull-up transistor (PU2), and the second pull-down transistor (PD2) to increase driving capability, it is possible to overwrite the data to be written regardless of the data stored in the data node (Q). Therefore, even if a single bit line (BL) and a single access transistor (AX) are used, data of '1' or '0' can be stored in the data node (Q).

[0046] The input / output control unit (120) can be connected to the latch unit (110). The input / output control unit (120) can control the operation of the latch unit (110) so that data writing and reading operations are performed through a single bit line (BL).

[0047] Additionally, the input / output control unit (120) may include a first control transistor (RA) and a second control transistor (APD).

[0048] The drain of the first control transistor (RA) can be connected to a data node (Q). More specifically, the drain of the first control transistor (RA) can be connected to a data node (Q) connected to the input terminal of the first inverter (111) and the output terminal of the second inverter (112). Additionally, the first control transistor (RA) can be activated or deactivated by a driving signal (RE).

[0049] The drain of the second control transistor (APD) can be connected to the source of the first control transistor (RA), and the source can be connected to the second voltage. Additionally, the gate can be connected to the gate of the first pull-down transistor (PD1) through the control node (N). That is, the first control transistor (RA) and the second control transistor (APD) can be connected in series with each other, and when the first control transistor (RA) is activated by a driving signal, the second control transistor (APD) can also be activated. Here, the first control transistor (RA) and the second control transistor (APD) may be NMOS transistors.

[0050] For example, when the input / output control unit (120) performs a write operation, the first control transistor (RA) and the second control transistor (APD) may be disabled, and when it performs a read operation, they may be enabled.

[0051] For example, when a write operation is performed, the access transistor (AX) is enabled, but the input / output control unit (120) is disabled so that data of '1' or '0' transmitted through a single bit line (BL) can be stored in the data node (Q).

[0052] Additionally, when a read operation is performed, a high signal is applied to the driving signal (RE) so that the first control transistor (RA) can be turned on, and the second control transistor (APD) can also be turned on by the turning on of the first control transistor (RA). Here, since the first pull-down transistor (PD1) and the second control transistor (APD) are connected to each other through the control node (N), the magnitude of the pull-down force can be increased. That is, the first pull-down transistor (PD1) has a smaller size than the access transistor (AX), but by additionally connecting the second control transistor (APD) to the first pull-down transistor (PD1), the pull-down force can be increased by simultaneous turning.

[0053] For example, when reading data of '0' stored in the latch unit (110), if the access transistor (AX) is activated by a high signal applied from the word line (WL), the floating voltage precharged in the single bit line (BL) can be discharged by pull-down by the first pull-down transistor (PD1) and the second control transistor (APD). That is, the data of '0' can be read by allowing the discharged voltage to be output.

[0054] To read the '0' data through this pull-down, it is preferable to form the first pull-down transistor (PD1) and the second control transistor (APD) such that the size of the pull-down force is greater than the size of the access transistor (AX).

[0055] That is, when a read operation is performed to read the data of '0' stored in the data node (Q), it is desirable to form the sizes of the first pull-down transistor (PD1) and the second control transistor (APD) such that they have a driving capability greater than that of the access transistor (AX) to form a discharge path by the first pull-down transistor (PD1) and the activated second control transistor (APD).

[0056] Due to the operation of the input / output control unit (120), writing and reading operations can be performed using only a single bit line (BL), so the number of bit lines (BL) can be reduced and metal routing can be easily performed.

[0057] Writing and reading operations using a single bit line (BL) and an input / output control unit (120) are described in detail below.

[0059] Writing operation

[0060] FIG. 5 is a diagram showing the write operation of a 7T-SRAM according to the present invention.

[0061] FIG. 6 is a diagram showing the timing diagram of a 7T-SRAM according to the present invention.

[0062] Referring to FIGS. 5 and 6, the input / output control unit (120) can be deactivated during a write operation. That is, a low signal is applied to the driving signal (RE), so that the first control transistor (RA) and the second control transistor (APD) can be turned off.

[0063] When the input / output control unit (120) is deactivated, data of '1' or '0' is transmitted through a single bit line (BL), and the word line (WL) signal is applied to the access transistor (AX) in a high state.

[0064] The access transistor (AX) can be turned on by an authorized high signal, and data of '1' or '0' transmitted by the turning on of the access transistor (AX) can be written to the data node (Q). At this time, since the access transistor (AX) has a larger size compared to the first pull-up transistor (PU1) and the first pull-down transistor (PD1), the desired data can be reliably overwritten regardless of the data stored in the data node (Q) by the strong access transistor (AX). In addition, data of '1' or '0' written to the data node (Q) through a single bit line (BL) can be stored through the latch unit (110).

[0065] When performing a read operation, the method of operation differs depending on whether the data '1' stored in the data node (Q) is read or '0' is read, so this is explained separately.

[0067] '1' data read operation

[0068] FIG. 7 is a diagram showing a read operation for reading data of '1' using a 7T-SRAM according to the present invention.

[0069] Referring to FIGS. 6 and 7, when a read operation is performed to read the stored data of '1', the input / output control unit (120) can be activated first. That is, a high signal is applied to the driving signal (RE) to turn on the first control transistor (RA), and the second control transistor (APD) can also be turned on by the turning on of the first control transistor (RA). At this time, the data of '1' may be stored in the data node (Q).

[0070] When the input / output control unit (120) is activated, to read data, a single bit line (BL) is precharged to '1' by applying a power supply voltage (VDD), and a word line (WL) signal is applied to the access transistor (AX) in a high state. However, since data of '1' is stored in the data node (Q), even if the word line (WL) signal is applied in a high state, the access transistor (AX) cannot be turned on because a voltage greater than the threshold voltage cannot be applied. In other words, the access transistor (AX) is deactivated. Therefore, the floating voltage precharged in the single bit line (BL) is output as is, allowing the data of '1' to be read.

[0072] '0' data read operation

[0073] FIG. 8 is a diagram showing a read operation for reading data of '0' using a 7T-SRAM according to the present invention.

[0074] Referring to FIGS. 6 and FIGS. 8, when a read operation is performed to read stored data of '0', the input / output control unit (120) can be activated in the same way as when a read operation is performed to read data of '1'. That is, a high signal is applied to the driving signal (RE) to turn on the first control transistor (RA), and the second control transistor (APD) can also be turned on by the turning on of the first control transistor (RA). At this time, data of '0' may be stored in the data node (Q).

[0075] When the input / output control unit (120) is activated, a single bit line (BL) is precharged to '1' by applying a power supply voltage (VDD) to read data, and a word line (WL) signal is applied to the access transistor (AX) in a high state. At this time, since data of '0' is stored in the data node (Q), when the word line (WL) signal is applied in a high state, a voltage greater than the threshold voltage can be applied to the access transistor (AX), so it can be turned on. That is, the access transistor (AX) can be activated.

[0076] When the access transistor (AX) is activated, the floating voltage precharged on a single bit line (BL) can be discharged by pull-down by the turn-on of the first pull-down transistor (PD1) and the second control transistor (APD), and the data '0' can be read by outputting the discharged voltage. This is because the sum of the driving capabilities of the first pull-down transistor (PD1) for pull-down and the activated second control transistor (APD) is formed to have a driving capability greater than the driving capability of the access transistor (AX). Therefore, a stable reading operation of '0' can be performed.

[0077] That is, the driving capability for the pull-down operation can be increased by the second control transistor (APD) additionally connected to the first pull-down transistor (PD1), and by making the sizes of the first pull-down transistor (PD1) and the second control transistor (APD) larger so that they become greater than the driving capability of the access transistor (AX), a stable reading operation of '0' can be performed.

[0078] FIG. 9 is a diagram showing a parallel structure array of a 7T-SRAM according to the present invention.

[0079] Referring to FIG. 9, the parallel structure array of the 7T-SRAM according to the present invention shows a 4×4 parallel SRAM array configuration using 7T-SRAM cells including a single bit line (BL) and 7 transistors, and shows a form in which a single bit line (BL) is connected to each cell.

[0080] The parallel structure array of the 7T-SRAM of the present invention can increase the memory operation speed and, at the same time, reduce the number of bit lines (BL) by half compared to the conventional 6T-SRAM parallel structure array shown in FIG. 3. Therefore, the chip area and defect rate can be reduced, and manufacturing is easy, thereby improving productivity.

[0081] Figure 10 is a simulation result for comparing the HSNM of the 7T-SRAM of the present invention and the conventional 6T-SRAM.

[0082] Here, FIG. 10(a) shows the hold static noise margin (HSNM) for a conventional 6T-SRAM, and FIG. 10(b) shows the hold static noise margin (HSNM) for a 7T-SRAM of the present invention.

[0083] As shown in FIG. 10(a) and FIG. 10(b), since the size of the pull-down transistor for the 7T-SRAM of the present invention is smaller than the size of the pull-down transistor for the conventional 6T-SRAM, it can be seen that the hold static noise margin (HSNM) is improved compared to the conventional 6T-SRAM.

[0084] Figure 11 is a simulation result for comparing the RSNM of the 7T-SRAM of the present invention and the conventional 6T-SRAM.

[0085] Here, FIG. 11(a) shows the Read Static Noise Margin (RSNM) for a conventional 6T-SRAM, and FIG. 11(b) shows the Read Static Noise Margin (RSNM) for a 7T-SRAM of the present invention.

[0086] Referring to FIG. 11(a) and FIG. 11(b), first, in the 7T-SRAM according to the present invention, the driving signal of the first control transistor (RA) is turned on during a read operation, and due to asymmetry, a difference occurs in the read static noise margin (RSNM) when reading data of '0' and when reading data of '1'.

[0087] When looking at the case of reading '0' data considering these characteristics, both the conventional 6T-SRAM and the 7T-SRAM according to the present invention have a method of discharging a 1 precharged in the bit line (BL) to 0 by the access transistor (AX) and the pull-down transistor, so there is no significant difference in the read static noise margin (RSNM).

[0088] However, when looking at the case of reading data of '1', the 7T-SRAM according to the present invention can improve stability because it operates with only one access transistor (AX) compared to the conventional 6T-SRAM. Therefore, it can be confirmed that the read static noise margin (RSNM) of the 7T-SRAM according to the present invention is improved compared to the conventional 6T-SRAM.

[0089] Figure 12 is a simulation result for comparing the WSNM of the 7T-SRAM of the present invention and the conventional 6T-SRAM.

[0090] Here, FIG. 12(a) shows the Write Static Noise Margin (WSNM) for a conventional 6T-SRAM, and FIG. 11(b) shows the Write Static Noise Margin (WSNM) for a 7T-SRAM of the present invention.

[0091] As shown in FIG. 12(a) and FIG. 12(b), it can be seen that the write static noise margin (WSNM) is improved compared to the conventional 6T-SRAM because the size of the access transistor (AX) for the 7T-SRAM of the present invention is larger than the size of the pull-down transistor (PD) of the conventional 6T-SRAM.

[0092] Figure 13 is a graph for comparing the SNM of the 7T-SRAM of the present invention and the conventional 6T-SRAM.

[0093] Referring to FIG. 13, when comprehensively comparing the static noise margin (SNM) of the 7T-SRAM of the present invention with that of a conventional 6T-SRAM, it can be seen that only the read static noise margin (RSNM) in the operation of reading '0' data shows slightly lower performance, but all other static noise margins (SNM) show improved performance.

[0095] As described above, the single bitline (BL) 7T-SRAM according to the present invention enables read and write operations using only a single bitline (BL) by utilizing the 7T-SRAM, thereby reducing the number of bitlines (BL) by half and making manufacturing easier. In addition, only one access transistor (AX) connected to the single bitline (BL) is required, and in particular, since the access transistor (AX) is turned off during a read operation to read data of '1', the static noise margin (SNM) can be increased, thereby improving stability.

[0096] Meanwhile, the embodiments of the present invention disclosed in this specification and drawings are merely specific examples provided to aid understanding and are not intended to limit the scope of the present invention. It is obvious to those skilled in the art that other variations based on the technical concept of the present invention are possible in addition to the embodiments disclosed herein. Explanation of the symbols

[0097] 110 : Latch 111: 1st inverter 112: Second inverter 120 : Input / Output Control Unit AX: Access transistor WL : Wordline BL : Single bitline PU1: 1st pull-up transistor PD1: 1st pull-down transistor PU2: Second pull-up transistor PD2: Second pull-down transistor RA: First control transistor APD: Second control transistor

Claims

Claim 1 A single bitline 7T-SRAM comprising: a wordline; an access transistor with a gate connected to the wordline; a latch portion connected to one end of the access transistor via a data node and storing data by the operation of a cross-coupled first inverter and a second inverter; a single bitline connected to the other end of the access transistor and inputting and outputting data; and an input / output control portion connected to the latch portion and controlling the operation of the latch portion so that data reading and writing operations are performed through the single bitline. Claim 2 A single bitline 7T-SRAM according to claim 1, wherein a read operation or a write operation through the single bitline is determined depending on whether the input / output control unit is operated. Claim 3 A single bitline 7T-SRAM according to claim 1, wherein the input / output control unit is activated when the read operation is performed, and the input / output control unit is deactivated when the write operation is performed. Claim 4 A single bitline 7T-SRAM according to claim 1, wherein when the write operation is performed, data of '0' or '1' is stored in the data node through the single bitline. Claim 5 In claim 1, the input / output control unit comprises: a first control transistor having a drain connected to the data node; and a second control transistor having a drain connected to the source of the first control transistor, the source connected to a ground voltage, and a gate connected to the first inverter through the control node, for a single bitline 7T-SRAM. Claim 6 In claim 5, the single bitline 7T-SRAM wherein the first control transistor and the second control transistor are formed as NMOS transistors. Claim 7 In claim 5, the single bitline 7T-SRAM wherein the first control transistor is turned off when the write operation is performed and turned on when the read operation is performed. Claim 8 In claim 5, the first inverter comprises: a first pull-up transistor having its source connected to a power supply voltage and its drain connected to the data node; and a first pull-down transistor having its source connected to a ground voltage, its drain connected to the data node, and its gate connected to the control node, for a single bitline 7T-SRAM. Claim 9 In claim 5, the second inverter comprises: a second pull-up transistor whose source is connected to a power supply voltage; and a second pull-down transistor whose source is connected to a ground voltage, whose drain is connected to the drain of the second pull-up transistor, and whose gate is connected to the drain of the first control transistor, for a single bitline 7T-SRAM. Claim 10 A single bitline 7T-SRAM according to claim 1, wherein the access transistor has a larger size than the transistors of the first inverter and the second inverter. Claim 11 A single bitline 7T-SRAM according to claim 8, wherein when reading data of '1' stored in the data node, the access transistor is turned off, and when reading data of '0' stored in the data node, the access transistor is turned on. Claim 12 A single bitline 7T-SRAM according to claim 11, which is pulled down by turning on the first pull-down transistor and the second control transistor when reading the data of '0'. Claim 13 In claim 12, a single bitline 7T-SRAM wherein the sizes of the first pull-down transistor and the second control transistor are such that the pull-down is performed in comparison to the driving capability of the access transistor.

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