Memory sharing system and operating method of memory sharing system

Abstract

A method of operation of a memory sharing system according to an embodiment of the present invention comprises: a step in which a shared memory manager generates initial connection information based on state information related to hosts, an optical line switch, and memory controllers; a step in which a shared memory manager generates global memory map data based on memory information related to memory controllers; a step in which hosts transmit allocation requests to a shared memory manager; a step in which, based on the allocation requests and the global memory map data, a shared memory manager outputs allocation responses each containing allocation information; a step in which a host performs address mapping based on the allocation responses; a step in which a shared memory manager outputs a control signal based on the initial connection information and the allocation information; and a step in which an optical line switch changes an optical path based on the control signal.

Description

Technology Field

[0001] The present invention relates to a memory sharing system using the CXL protocol, and more specifically, to a memory sharing system including an optical line switch and a shared memory manager, and a method of operating the memory sharing system. Background Technology

[0002] A memory sharing system using the CXL protocol includes multiple hosts and multiple memories that constitute a memory pool. To connect the hosts and memories, the memory sharing system may include a memory controller. When a memory controller is used, there are limitations to scalability. For example, the number of hosts connected to multiple memories is limited.

[0003] Meanwhile, to increase scalability, memory sharing systems can use CXL switches. However, using CXL switches increases memory access times due to the latency caused by the switches. Additionally, complexity increases because a fabric manager is required to control the CXL switches.

[0004] Therefore, in a memory sharing system using the CXL protocol, a method is required to ensure the scalability of shared memory and minimize latency. The problem to be solved

[0005] The objective of the present invention is to provide a memory sharing system using an optical line switch and a shared memory manager, and a method of operation of the memory sharing system. means of solving the problem

[0006] A method of operation of a memory sharing system according to an embodiment of the present invention comprises: a step in which a shared memory manager generates initial connection information based on state information related to hosts, an optical line switch, and memory controllers; a step in which a shared memory manager generates global memory map data based on memory information related to memory controllers; a step in which hosts transmit allocation requests to a shared memory manager; a step in which, based on the allocation requests and the global memory map data, a shared memory manager outputs allocation responses each containing allocation information; a step in which a host performs address mapping based on the allocation responses; a step in which a shared memory manager outputs a control signal based on the initial connection information and the allocation information; and a step in which an optical line switch changes an optical path based on the control signal. Effects of the invention

[0007] According to the present invention, a memory sharing system can improve memory scalability and reduce the delay time that occurs when accessing memory. Brief explanation of the drawing

[0008] FIG. 1 shows an example of a memory sharing system according to one embodiment of the present invention. FIG. 2a shows a flowchart of the operation of a memory sharing system according to one embodiment of the present invention. FIG. 2b shows a memory sharing system configured to perform operations according to the flowchart of FIG. 2a. FIG. 3 shows an example of global memory map data according to one embodiment of the present invention. FIG. 4 shows an example of managing a memory area of ​​a host according to one embodiment of the present invention. Figure 5 shows an example of shared memory being allocated in the memory sharing system of Figure 2b. Specific details for implementing the invention

[0009] In the following, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention.

[0010] The components described by reference to terms such as part or unit, module, block, ~or, ~er used in the detailed description and the functional blocks illustrated in the drawings may be implemented in the form of software, hardware, or a combination thereof. For example, software may be machine code, firmware, embedded code, and application software. For example, hardware may include electrical circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive components, or a combination thereof.

[0011] FIG. 1 shows an example of a memory sharing system according to an embodiment of the present invention. Referring to FIG. 1, the memory sharing system (100) may include a plurality of hosts (110_1 to 110_n, where n is a natural number greater than 1), an optical line switch (120), a plurality of memory controllers (130_1 to 130_m, where m is a natural number greater than 1), a plurality of memories (140_1 to 140_(4m)), and a shared memory manager (150).

[0012] Multiple hosts (110_1 to 110_n) can access multiple memories (140_1 to 140_(4m)) through an optical line switch (120).

[0013] Multiple hosts (110_1 to 110_n) can output usage requests for multiple memories (140_1 to 140_(4m)). For example, multiple hosts (110_1 to 110_n) can send allocation requests for multiple memories (140_1 to 140_(4m)) to a shared memory manager (150).

[0014] The optical circuit switch (120) may include a plurality of optical paths. An optical path may represent a path for the movement of a signal through an optical network. That is, an optical path may represent a data transmission path between an input optical port and an output optical port.

[0015] Optical paths can connect multiple hosts (110_1 to 110_n) and multiple memory controllers (130_1 to 130_m). The multiple hosts (110_1 to 110_n) and multiple memory controllers (130_1 to 130_m) can exchange data through the optical paths.

[0016] A plurality of memory controllers (130_1 to 130_m) can control or manage a plurality of memories (140_1 to 140_(4m)). For example, the first memory controller (130_1) can control the memories (140_1 to 140_4). The m-th memory controller (130_m) can control the memories (140_(4m-3) to 140_(4m)). However, the scope of the present invention is not limited thereto, and each of the plurality of memory controllers (130_1 to 130_m) can control two or more memories.

[0017] Multiple memory controllers (130_1 to 130_m) can interpret frames transmitted by hosts (110_1 to 110_n) to identify the physical addresses of multiple memories (140_1 to 140_(4m)).

[0018] In one embodiment, the frame transmitted by the hosts (110_1 to 110_n) may be a frame defined in a CXL fleet, an Ethernet frame, or a memory sharing system.

[0019] Multiple memories (140_(4m-3) to 140_(4m)) can form a memory pool. Each of the multiple memories (140_(4m-3) to 140_(4m)) may be a CXL memory or a CXL storage. In one embodiment, the capacities of the multiple memories (140_(4m-3) to 140_(4m)) may all be the same.

[0020] The shared memory manager (150) can control the memory sharing operation of the memory sharing system (100) overall. That is, the shared memory manager (150) can control the sharing relationship between the hosts (110_1 to 110_n) and the multiple memories (140_1 to 140_(4m)).

[0021] The shared memory manager (150) can output an allocation response containing allocation information in response to an allocation request received from hosts (110_1 to 110_n). For example, the shared memory manager (150) can send an allocation response containing allocation information to the hosts (110_1 to 110_n) in response to an allocation request received from hosts (110_1 to 110_n).

[0022] The shared memory manager (150) can control the optical line switch (120) based on the usage requests and memory pool of the hosts (110_1 to 110_n). For example, the shared memory manager (150) can transmit a control signal to the optical line switch (120) to change the optical path of the optical line switch (120) based on the allocation requests and memory pool of the hosts (110_1 to 110_n).

[0023] In one embodiment, the shared memory manager (150) can manage the memory pool as a single global memory.

[0024] FIG. 2a shows a flowchart of the operation of a memory sharing system according to an embodiment of the present invention. FIG. 2b shows a memory sharing system configured to perform the operation according to the flowchart of FIG. 2a. In FIG. 2b, it is assumed that the capacities of the memories (240_1 to 240_8) are all the same.

[0025] Referring to FIGS. 2a and 2b, in step S110, the hosts (210_1 to 210_3), the optical line switch (220), and the memory controllers (230_1, 230_2) can transmit status information to the shared memory manager (250).

[0026] For example, the first to third hosts (210_1 to 210_3) can transmit host status information to the shared memory manager (250). Specifically, the first host (210_1) can transmit the first host status information to the shared memory manager (250), the second host (210_2) can transmit the second host status information to the shared memory manager (250), and the third host (210_3) can transmit the third host status information to the shared memory manager (250).

[0027] In one embodiment, host status information may include optical port information of an optical circuit switch (220) to which hosts (210_1 to 210_3) are connected. For example, the first host status information may include optical port information of an optical circuit switch (220) to which the first host (210_1) is connected, the second host status information may include optical port information of an optical circuit switch (220) to which the second host (210_2) is connected, and the third host status information may include optical port information of an optical circuit switch (220) to which the third host (210_3) is connected.

[0028] For example, the optical line switch (220) can transmit switch status information to the shared memory manager (250). The switch status information may include optical path information per optical port.

[0029] For example, memory controllers (230_1, 230_2) can transmit controller status information to a shared memory manager (250). Specifically, the first memory controller (230_1) can transmit the first controller status information to the shared memory manager (250), and the second memory controller (230_2) can transmit the second controller status information to the shared memory manager (250).

[0030] In one embodiment, the controller status information may include optical port information of an optical line switch (220) to which memory controllers (230_1, 230_2) are connected. For example, the first controller status information may include optical port information of an optical line switch (220) to which the first memory controller (230_1) is connected, and the second controller status information may include optical port information of an optical line switch (220) to which the second memory controller (230_2) is connected.

[0031] In one embodiment, the operation of step S110 may be performed after the system initialization operation of the memory sharing system (200) is completed.

[0032] In step S120, memory controllers (230_1, 230_2) can transmit memory information for corresponding memories to a shared memory manager (250). For example, the first memory controller (230_1) can transmit first memory information for the first to fourth memories (240_1 to 240_4) to the shared memory manager (250), and the second memory controller (230_2) can transmit second memory information for the fifth to eighth memories (240_5 to 240_8) to the shared memory manager (250).

[0033] In one embodiment, the memory information may include activation information and capacity information for each memory. The activation information may indicate whether the memory is activated. For example, the first memory information may include activation information and capacity information for each of the first to fourth memories (240_1 to 240_4). The second memory information may include activation information and capacity information for each of the fifth to eighth memories (240_5 to 240_8).

[0034] In one embodiment, the operation of step S120 may be performed after the system initialization operation of the memory sharing system (200) is completed.

[0035] In step S130, the shared memory manager (250) can generate initial connection information indicating the connection status of the initial optical line switch based on the status information. For example, the shared memory manager (250) can generate initial connection information based on the first to third host status information, switch status information, and first and second controller status information.

[0036] In step S140, the shared memory manager (250) can generate global memory map data for the memories (240_1 to 240_8) that constitute the memory pool based on memory information. For example, the shared memory manager (250) can generate global memory map data based on the first and second memory information. In one embodiment, the information for the memories (240_1 to 240_8) included in the global memory map data can be generated and managed independently for each memory.

[0037] In step S150, hosts (210_1 to 210_3) may output allocation requests to use at least a portion of the memories (240_1 to 240_8) as shared memory. For example, the first host (210_1) may send a first allocation request to the shared memory manager (250) to use at least a portion of the memories (240_1 to 240_8) as shared memory. The second host (210_2) may send a second allocation request to the shared memory manager (250) to use at least a portion of the memories (240_1 to 240_8) as shared memory. The third host (210_3) may send a third allocation request to the shared memory manager (250) to use at least a portion of the memories (240_1 to 240_8) as shared memory.

[0038] In one embodiment, each of the allocation requests may include memory capacity information and delay time information required by a host. For example, the first allocation request may include memory capacity information and delay time information required by the first host (210_1), the second allocation request may include memory capacity information and delay time information required by the second host (210_2), and the third allocation request may include memory capacity information and delay time information required by the third host (210_3).

[0039] In one embodiment, each of the allocation requests may correspond to some memory regions of the memories (240_1 to 240_8).

[0040] In step S160, the shared memory manager (250) may output allocation responses each containing allocation information based on allocation requests. For example, the shared memory manager (250) may send a first allocation response containing allocation information for the first host (210_1) to the first host (210_1) in response to a first allocation request. The shared memory manager (250) may send a second allocation response containing allocation information for the second host (210_2) to the second host (210_2) in response to a second allocation request. The shared memory manager (250) may send a third allocation response containing allocation information for the third host (210_3) to the third host (210_3) in response to a third allocation request.

[0041] In one embodiment, the shared memory manager (250) can generate allocation information by searching for available memory (or available memory area within memory) within the global memory map data.

[0042] In one embodiment, the allocation information may be associated with a physical address for available memory (or an available memory region within memory). For example, the allocation information may be associated with physical address values ​​for available memory (or an available memory region within memory).

[0043] In one embodiment, the allocation information may include virtual address values ​​associated with physical address values ​​for available memory.

[0044] In one embodiment, if the memory capacity required by each host can be allocated to memories managed by the same memory controller, the shared memory manager (250) can prioritize allocating to memories managed by the same memory controller.

[0045] In step S170, the shared memory converters (210_1a to 210_3a) can perform address mapping based on the allocation responses.

[0046] For example, the first shared memory converter (210_1a) can convert virtual address values ​​for a shared memory area of ​​the first host (210_1) into physical address values ​​related to the allocation information included in the first allocation response. The second shared memory converter (210_2a) can convert virtual address values ​​for a shared memory area of ​​the second host (210_2) into physical address values ​​related to the allocation information included in the second allocation response. The third shared memory converter (210_3a) can convert virtual address values ​​for a shared memory area of ​​the third host (210_3) into physical address values ​​related to the allocation information included in the third allocation response.

[0047] In step S180, the shared memory manager (250) may output a control signal for interconnecting hosts (210_1 to 210_3) and memory controllers (230_1, 230_2) based on initial connection information and allocation information included in allocation requests. For example, the shared memory manager (250) may transmit a control signal for interconnecting hosts (210_1 to 210_3) and memory controllers (230_1, 230_2) to an optical line switch (220) based on initial connection information and allocation information included in the first to third allocation requests.

[0048] In step S190, the optical line switch (220) can change the optical path based on a control signal.

[0049] FIG. 3 shows an example of global memory map data according to an embodiment of the present invention. Referring to FIGS. 2a through 3, the global memory map data may include information about memories (240_1 to 240_8). For example, the global memory map data may include information about virtual address values ​​associated with physical address values ​​of the memories (240_1 to 240_8).

[0050] For example, the virtual address range of the first memory (240_1) may be from '0x00 0000 0000' to '0x0F FFFF FFFF'. The virtual address range of the second memory (240_2) may be from '0x10 0000 0000' to '0x1F FFFF FFFF'. The virtual address range of the third memory (240_3) may be from '0x20 0000 0000' to '0x2F FFFF FFFF'. The virtual address range of the fourth memory (240_4) may be from '0x30 0000 0000' to '0x3F FFFF FFFF'. The virtual address range of the fifth memory (240_5) may be from '0x40 0000 0000' to '0x4F FFFF FFFF'. The virtual address range of the 6th memory (240_6) may be from '0x50 0000 0000' to '0x5F FFFF FFFF'. The virtual address range of the 7th memory (240_7) may be from '0x60 0000 0000' to '0x6F FFFF FFFF'. The virtual address range of the 8th memory (240_8) may be from '0x70 0000 0000' to '0x7F FFFF FFFF'.

[0051] The upper 4 bits of each virtual address value can be used to distinguish the memories (240_1 to 240_8).

[0052] FIG. 4 shows an example of managing a memory area of ​​a host according to an embodiment of the present invention. Referring to FIGS. 2a through 4, each of the hosts (210_1 to 210_3) can manage a memory area by separating it into a local memory area and a shared memory area. In one embodiment, the local memory area is associated with a memory (not shown) included in the host, and the shared memory area may be associated with memories (240_1 to 240_8).

[0053] The capacities of the memory (not shown) and the memories (240_1 to 240_8) included in the host may all be the same. For example, the capacities of the memory (not shown) and the memories (240_1 to 240_8) included in the host may all be 64GB. Thus, the size of the local memory area may be 64GB, and the size of the shared memory area may be 512GB. That is, each host may use all of the memories (240_1 to 240_8) as a shared memory area.

[0054] The local memory area and the shared memory area may have virtual address values ​​associated with the physical address values ​​of the memory (not shown) and memories (240_1 to 240_8) included in the host.

[0055] For example, the virtual address range of the local memory area may be from '0x00 0000 0000' to '0x0F FFFF FFFF'. The virtual address range of the shared memory area may be from '0x10 0000 0000' to '0x8F FFFF FFFF'.

[0056] In the shared memory area, the upper 4 bits of each virtual address value can be used to distinguish the memories (240_1 to 240_8).

[0057] FIG. 5 shows an example of memory allocation in the memory sharing system of FIG. 2b. Referring to FIG. 2a through FIG. 5, the first and second memories (240_1, 240_2) are allocated to the shared memory area of ​​the first host (210_1), the third memory (240_3) is allocated to the shared memory area of ​​the second host (210_2), and the fourth and fifth memories (240_4, 240_5) are allocated to the shared memory area of ​​the third host (210_3).

[0058] If the memory capacity required by the host can be allocated to memories managed by the same memory controller, the shared memory manager (250) can prioritize allocating to memories managed by the same memory controller.

[0059] The memory capacity required by the first host (210_1) is 128GB. Since the memory capacity required by the first host (210_1) can be allocated to the memories (240_1 to 240_4) managed by the first memory controller (230_1), the shared memory manager (250) can allocate the first and second memories (240_1, 240_2) to the first host (210_1).

[0060] The memory capacity required by the second host (210_2) is 64GB. Since the memory capacity required by the second host (210_2) can be allocated to the remaining memories (240_3, 240_4) among the memories (240_1~240_4) managed by the second memory controller (230_2), the shared memory manager (250) can allocate the third memory (240_3) to the second host (210_2).

[0061] The memory capacity required by the third host (210_3) is 128GB. Since the memory capacity required by the third host (210_3) cannot be allocated to the fourth memory (240_4), which is the remaining memory among the memories (240_1 to 240_4) managed by the first memory controller (230_1), the shared memory manager (250) can allocate the fourth memory (240_4) managed by the first memory controller (230_1) and the fifth memory (240_5) managed by the second memory controller (230_2) to the third host (210_3). In one embodiment, the shared memory manager (250) may allocate two of the memories (240_5 to 240_8) managed by the second memory controller (230_2) to the third host (210_3) instead of allocating the fourth memory (240_4) and the fifth memory (240_5).

[0062] As described above, the optical port utilization of the optical circuit switch (220) can be improved by preferentially allocating memories managed by the same memory controller.

[0063] In the embodiments described above, components according to the technical concept of the present invention have been described using terms such as first, second, third, etc. However, terms such as first, second, third, etc. are used to distinguish the components from one another and do not limit the present invention. For example, terms such as first, second, third, etc. do not imply a sequential order or any numerical meaning.

[0064] The description above describes specific examples for implementing the present invention. The present invention will include not only the embodiments described above, but also embodiments that can be easily modified or simply changed. Furthermore, the present invention will include technologies that can be easily modified and implemented in the future using the embodiments described above. Explanation of the symbols

[0065] 100, 200: Memory sharing system

Claims

Claim 1 A method of operation of a memory sharing system comprising: a shared memory manager generating initial connection information based on state information related to hosts, an optical line switch, and memory controllers; a shared memory manager generating global memory map data based on memory information related to memory controllers; the hosts transmitting allocation requests to the shared memory manager; based on the allocation requests and the global memory map data, the shared memory manager outputting allocation responses each containing allocation information; based on the allocation responses, the hosts performing address mapping; based on the initial connection information and the allocation information, the shared memory manager outputting a control signal; and based on the control signal, the optical line switch changing an optical path.

Images