Semiconductor device and method of forming stacked aip structure

Abstract

A semiconductor device comprises an antenna substrate, an electrical component disposed on the antenna substrate, and a semiconductor assembly disposed on the electrical component. The electrical component has a first active surface and a second active surface facing the first active surface, and a conductive via extends between the first active surface and the second active surface. An encapsulating agent is deposited on and around the antenna substrate and the electrical component. The encapsulating agent may be deposited on the semiconductor assembly. A portion of the encapsulating agent is removed to expose the semiconductor assembly. A mask is placed on the semiconductor assembly. A shielding layer is placed on and around the antenna substrate, the electrical component, and the semiconductor assembly. The mask prevents the shielding layer from covering a portion of the semiconductor assembly. The mask is removed, and an electrical connector is placed on the semiconductor assembly that was protected by the mask.

Description

Technology Field

[0001] The present invention generally relates to semiconductor devices, and more specifically, to a semiconductor device and a method for forming a stacked antenna-in-package (AiP) package structure from separate assemblies using a bonding material. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, including signal processing, high-speed computing, electromagnetic signal transmission and reception, electronic device control, optoelectronics, and the generation of visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. They are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor devices often include one or more integrated passive devices (IPDs) to perform electrical functions required, particularly in high-frequency applications such as radio frequency (RF) communication. Integrating multiple semiconductor dies and IPDs into a System-in-Package (SiP) module enables higher density and expanded electrical functionality within a small space. Within the SiP module, the semiconductor dies and IPDs are placed on a first surface of a substrate for structural support and electrical interconnection. An encapsulant is deposited over the semiconductor dies, IPDs, and the substrate. The problem to be solved

[0004] Wireless communication capabilities can be provided to the SiP module by placing an antenna on the second surface of the substrate. By adding the antenna, the SiP constitutes an AiP. As the semiconductor die and IPD are horizontally distributed across the substrate surface, no single device can become excessively large. Otherwise, the semiconductor package may exceed size requirements. Therefore, current AiP modules limit the size of any single semiconductor device. Brief explanation of the drawing

[0005] FIGS. 1a to 1e show various semiconductor wafers, each having a plurality of semiconductor dies separated by a saw street. FIGS. 2a to 2o show a process for forming an AiP module having double-sided electrical components and a semiconductor assembly stacked on an antenna interposer. FIGS. 3a to 3c show the process of forming the semiconductor assembly used in FIGS. 2a to 2o. Figures 4a and 4b show an alternative semiconductor assembly. FIGS. 5a through 5h show another process for forming an AiP module having double-sided electrical components and a semiconductor assembly stacked on an antenna interposer. Figure 6 shows various types of packages placed on the surface of a printed circuit board (PCB). Specific details for implementing the invention

[0006] The present invention is described below with reference to one or more embodiments with reference to the drawings, and identical or similar elements are indicated by the same reference numerals. Although the present invention is described based on the best mode for achieving the object of the invention, those skilled in the art will understand that it is intended to include alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and equivalents supported by this specification and drawings. As used herein, the term "semiconductor die" refers to both singular and plural forms and may mean both a single semiconductor device and multiple semiconductor devices.

[0007] Semiconductor devices are generally manufactured through two complex processes: front-end and back-end manufacturing. The front-end manufacturing process involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form a functional electrical circuit. Active electrical components, such as transistors and diodes, possess the ability to control current flow. Passive electrical components, such as capacitors, inductors, and resistors, generate the relationship between voltage and current necessary to perform the functions of the electrical circuit.

[0008] Backend manufacturing refers to the process of cutting or separating a finished wafer into individual semiconductor dies and packaging the dies for structural support, electrical interconnection, and environmental isolation. To separate the semiconductor dies, the wafer is cut and broken along non-functional areas of the wafer known as saw streets or scribes. The wafers are separated using laser cutting tools or saw blades. After singulation, the individual semiconductor dies are placed on a package substrate containing pins or contact pads for interconnection with other system components. Contact pads formed on the semiconductor dies connect to contact pads inside the package. Electrical connections can be implemented using conductive layers, bumps, stud bumps, conductive paste, or wire bonds. An encapsulant or other molding material is applied over the package for physical support and electrical isolation. The finished package is inserted into an electrical system, and the functionality of the semiconductor device is provided to other system components.

[0009] FIG. 1a shows a semiconductor wafer (100a) having a substrate material (102) such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials for structural support. A plurality of semiconductor dies or components (104a) are formed on the wafer (100a) and are separated by wafer regions or top streets (106) between the dies in an inactive state. The top street (106) provides a cutting region for separating the semiconductor wafer (100a) into individual semiconductor dies (104a). In one embodiment, the width or diameter of the semiconductor wafer (100a) is 100 to 450 millimeters (mm). The semiconductor dies (104a) can process RF signals transmitted and received through an antenna.

[0010] FIG. 1b shows a cross-sectional view of a portion of a semiconductor wafer (100a). In one embodiment, each semiconductor die (104a) is a double-sided device having an active surface (108) and an active surface (110), and each active surface includes an analog or digital circuit implemented by an active element, a passive element, a conductive layer, and a dielectric layer formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface (108 and 110) to implement an analog circuit or a digital circuit (e.g., a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a memory, or other signal processing circuit). The semiconductor die (104a) may also include IPDs such as inductors, capacitors, and resistors for RF signal processing. In one embodiment, the semiconductor die (104a) is a die of the RFIC, single-chip microwave integrated circuit (MMIC), or system-on-chip (SoC) type.

[0011] A plurality of vias are formed between the active surface (110) and the active surface (108) through the base material (102) using an etching process or laser direct cutting (LDA). The vias are filled with an electrically conductive material such as Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material to form a conductive via (111) extending between the active surface (110) and the active surface (108).

[0012] An electrically conductive layer (112) is formed on an active surface (110) using a PVD, CVD, electroplating, electroless plating process, or other suitable metal deposition process. Likewise, an electrically conductive layer (113) is formed on an active surface (108) using a PVD, CVD, electroplating, electroless plating process, or other suitable metal deposition process. The conductive layers (112 and 113) may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive materials. The conductive layers (112 and 113) each serve as contact pads electrically connected to the circuits of the active surfaces (110 and 108).

[0013] In FIG. 1c, the semiconductor wafer (100a) is separated into individual semiconductor dies (104a) using a saw blade or laser cutting tool (118) through the saw street (106). After separation, the individual semiconductor dies (104a) can be inspected and electrically tested to identify known good dies or units (KGD / KGU).

[0014] Different types of semiconductor dies can be manufactured using a wafer (100b) similar to the semiconductor wafer (100a). For example, FIG. 1d shows a semiconductor die (104b) having a back or inactive surface (109) and an active surface (110), respectively. The active surface (110) is formed inside the die and includes an analog or digital circuit implemented with an active element, a passive element, a conductive layer, and a dielectric layer that are electrically interconnected according to the electrical design and function of the die. Components with similar functions are given the same reference number. The circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface (110) to implement an analog circuit or a digital circuit such as a DSP, ASIC, memory, or other signal processing circuit. The semiconductor die (104b) may also include IPDs such as inductors, capacitors, and resistors for RF signal processing.

[0015] In FIG. 1e, the semiconductor wafer (100b) is separated into individual semiconductor dies (104b) via a saw street (106) using a saw blade or a laser cutting tool (118). After separation, the individual semiconductor dies (104b) can be inspected and electrically tested for KGD / KGU identification.

[0016] FIGS. 2a through 2o illustrate a process for forming an AiP module having double-sided electrical components and a semiconductor assembly stacked on an antenna interposer. FIG. 2a shows a cross-sectional view of an antenna substrate (120) comprising a core material (124) such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials for structural support. Alternatively, the core material (124) may be a multilayer flexible laminate, ceramic, CCL, glass, or epoxy molding compound. The core material (124) may include one or more silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentooxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), polybenzoxazole-based materials (e.g., PBO), and other materials having insulating and structural properties. The antenna substrate (120) has a surface (126) and a surface (128) facing the surface (126).

[0017] An electrically conductive layer (122) is formed on and penetrates the antenna substrate (120) using a PVD, CVD, electroplating, electroless plating process, or other suitable metal deposition process. The conductive layer (122) may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive materials. The conductive layer (122) penetrates the antenna substrate (120) vertically and horizontally to provide electrical interconnection. The conductive layer (122) is also formed on the surface (128) to serve as an antenna (130) for transmitting and receiving RF signals. A portion of the conductive layer (122) may be electrically common or electrically insulated depending on the design and function of the attached electrical component.

[0018] FIG. 2b is a plan view of one embodiment of an antenna (130) on a surface (128). The conductive layer (130) comprises an array of islands (134) made of a conductive material suitable for transmitting and receiving RF signals, i.e., providing RF antenna functions. In particular, the antenna islands (134) of the conductive layer (122) are exposed on the surface (128) to improve RF transmission and reception performance and quality.

[0019] FIG. 2c shows a cross-sectional view of an interconnect substrate or interposer (140) comprising one or more conductive layers (142) and one or more insulating layers (144). The conductive layer (142) may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive materials. The conductive layer (142) may be formed using PVD, CVD, electroplating, electroless plating processes, or other suitable metal deposition processes. The conductive layer (142) provides horizontal electrical interconnection across the entire substrate and provides vertical electrical interconnection between the upper surface (146) and the lower surface (148) of the substrate (140). A portion of the conductive layer (142) may be electrically common or electrically insulated depending on the design and function of the semiconductor dies (104a and 104b) and other electrical components. The insulating layer (144) comprises one or more layers of SiO2, Si3N4, SiON, Ta2O3, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. The insulating layer (144) may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer (144) provides insulation between the conductive layers (142). There may be multiple conductive layers, such as conductive layers (142), separated by the insulating layer (144).

[0020] The surface (148) of the interposer (140) is bonded to the surface (126) of the antenna substrate (120). The interposer (140) can be bonded to the antenna substrate (120) using direct wafer bonding (DWB). In DWB, the surface (148) of the interposer (140) and the surface (126) of the antenna substrate (120) are flattened and smoothed through planarization, polishing, and cleaning before bonding. The lattice structure of the interfacial layer can be aligned to optimize adhesion. Water molecules can be applied to the surface (148) and the surface (126) to aid in the bonding process. The surface (148) of the interposer (140) comes into contact with the surface (126) of the antenna substrate (120). DWB is achieved through chemical bonding and intermolecular interactions at temperature, including van der Waals forces, hydrogen bonding, and covalent bonding, between the surface (148) and the surface (126). The DWB temperature varies from room temperature to over 100°C. FIG. 2d shows an interposer (140) directly wafer-bonded to the surface (126) of an antenna substrate (120). Alternatively, the interposer (140) may be bonded to the antenna substrate (120) using an adhesive.

[0021] In another embodiment, an interposer (140) is formed on the surface (126) of an antenna substrate (120) using a build-up interconnection process. A first conductive layer (142) is formed on the surface (126) of the antenna substrate (120). A first insulating layer (144) is formed on the first conductive layer (142). A portion of the first insulating layer (144) is removed to expose the first conductive layer (142). A second conductive layer (142) is formed on the first insulating layer (144) and comes into contact with the first conductive layer (142). A second insulating layer (144) is formed on the first insulating layer (144) and the second conductive layer (142). A portion of the second insulating layer (144) is removed to expose the second conductive layer (142). A third conductive layer (142) is formed on the second insulating layer (144) and comes into contact with the second conductive layer (142). A third insulating layer (144) is formed over the second insulating layer (144) and the third conductive layer (142). A portion of the third insulating layer (144) is removed to expose the third conductive layer (142). This process continues until the interposer (140) has all the necessary conductive layers (142) and insulating layers (144) as shown in FIG. 2e.

[0022] In any case, the combination of the antenna substrate (120) and the interposer (140) forms the antenna interposer (150) shown in FIG. 2d or FIG. 2e.

[0023] In FIG. 2f, one or more electrical components (152) are placed on the surface (146) of the interposer (140). The electrical components (152) are placed on the interposer substrate (140) using a pick-and-place operation. For example, the electrical components (152) may be similar to the semiconductor die (104a) of FIG. 1c, and the bumps (114) are arranged to face the surface (146). Alternatively, the electrical components (152) may include other semiconductor dies, semiconductor packages, surface mount devices, individual electrical devices, or IPDs. The bumps (114) are reflowed after contact with the conductive layer (162) to form electrical and mechanical interconnections. FIG. 2g shows the electrical components (152) placed on the surface (146) of the interposer (140). The electrical component (152) may be a relatively large component, such as a double-sided RFIC having interconnected conductive vias (111), and occupies a significant portion of the interposer (140). The enlargement of the electrical component (152) allows more components to be placed on both active surfaces (108 and 110), which are interconnected by conductive vias (111). A double-sided device offers higher space efficiency and increases component density per unit area. The large electrical component (152) can replace many small components that were traditionally distributed across the surface area of ​​the antenna interposer (150). In one embodiment, the electrical component (152) occupies more than 50% of the surface area of ​​the antenna interposer (150). Preferably, the electrical component (152) occupies more than 60% of the surface area of ​​the antenna interposer (150).

[0024] FIG. 3a shows a cross-sectional view of an interconnected substrate or interposer (160) comprising one or more conductive layers (162) and one or more insulating layers (164). The conductive layer (162) may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive materials. The conductive layer (162) may be formed using PVD, CVD, electroplating, electroless plating processes, or other suitable metal deposition processes. The conductive layer (162) provides horizontal electrical interconnection across the entire substrate and provides vertical electrical interconnection between the upper surface (166) and the lower surface (168) of the substrate (160). A portion of the conductive layer (162) may be electrically common or electrically insulated depending on the design and function of the semiconductor dies (104a and 104b) and other electrical components. The insulating layer (164) comprises one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. The insulating layer (164) may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer (164) provides insulation between the conductive layers (162). There may be multiple conductive layers, such as conductive layers (162), separated by the insulating layer (164).

[0025] In FIG. 3b, a plurality of electrical components (170a, 170b, 170c) are placed on the surface (166) of the interposer (160). Each of the electrical components (170a-170c) is placed on the interposer substrate (160) through a pick-and-place operation. For example, the electrical components (170a and 170b) are individual semiconductor devices such as resistors, capacitors, inductors, diodes, and transistors, and their terminals (172) may be connected to the conductive layer (162) via solder or conductive paste (174). The electrical component (170c) may be similar to the semiconductor die (104b) of FIG. 1e, and is placed so that the bump (114) faces the surface (166) of the interposer substrate (160). Alternatively, the electrical components (170a-170c) may include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical devices, or IPDs. The bumps (114) are reflowed after contact with the conductive layer (162) to form electrical and mechanical interconnections. FIG. 3c shows the electrical components (170a-170c) placed on the surface (166) of the interposer (160) with the bumps (114) electrically and mechanically connected to the conductive layer (162).

[0026] An electrically conductive bump material is deposited on a surface (168) on a conductive layer (162) using an evaporation, electroplating, electroless plating, ball drop, or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, and may optionally contain a flux solution. For example, the bump material may be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer (162) using a suitable attachment or bonding process. In one embodiment, the bump material is heated above its melting point and reflowed to form a ball or bump (176). In one embodiment, the bump (176) is formed on an under-bump metallization (UBM) having a wetting layer, a blocking layer, and an adhesive layer. The bump (176) may also be bonded to the conductive layer (162) via a compression bond or a thermal compression bond. A bump (176) represents a type of interconnect structure that can be formed on a conductive layer (162). The interconnect structure may use bond wires, conductive paste, stud bumps, microbumps, or other electrical interconnects. The electrical components (170a-170c) and interposer (160) having the bump (176) of FIG. 3c represent a semiconductor assembly (178). In one embodiment, the semiconductor assembly (178) includes a power management (PMIC) such as the electrical component (170c). The PMIC controls the operation of a power device such as the electrical component (152) implemented as an RFIC.

[0027] Returning to FIG. 2h, the semiconductor assembly (178) of FIG. 3c is placed on the active surface (108) of the electrical component (152) of FIG. 2g. The semiconductor assembly (178) is positioned on the electrical component (152) using a pick-and-place operation. The bump (176) is reflowed after contact with the conductive layer (142) to form electrical and mechanical interconnections. FIG. 2i shows the semiconductor assembly (178) placed on the surface (108) of the electrical component (152) with the bump (176) electrically and mechanically connected to the conductive layer (142).

[0028] In FIG. 2j, the encapsulating agent or molding compound (180) is applied over and around the semiconductor assembly (178), electrical component (152), and antenna interposer (150) using paste printing, compression molding, transfer molding, liquid encapsulating agent molding, vacuum lamination, spin coating, or other suitable applicators. The encapsulating agent (180) may be a polymer composite material such as an epoxy resin containing a filler, an epoxy acrylate containing a filler, or a polymer containing a suitable filler. The encapsulating agent (180) is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants. A portion of the encapsulating agent (180) is removed by a grinder (181) to expose an area (182) of the interposer (160).

[0029] In FIG. 2k, the mask (184) is placed in the area (182) above the interposer (160). Note the gap between the mask (184) and the surface (185) of the encapsulating agent (180).

[0030] The electrical components (152 and 170a-170c) may include IPDs that are susceptible to or cause EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPDs included in the electrical components (152 and 170a-170c) provide electrical characteristics required for high-frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetric high-Q resonant transformers, and regulating capacitors. In another embodiment, the electrical components (152 and 170a-170c) include digital circuits that switch at high frequencies, which may cause interference with the operation of the IPDs within the assembly.

[0031] To address EMI, RFI, harmonic distortion, and inter-device interference, an electromagnetic shielding material (186) is applied over a mask (184) and an encapsulating agent (180) covering a semiconductor assembly (178) and an antenna interposer (150), which includes side surfaces (188 and 190) of the encapsulating agent (180) and the antenna interposer (150) (see FIG. 2L). The electromagnetic shielding material (186) may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, the electromagnetic shielding material (186) may be carbonyl iron, stainless steel, nickel silver, low carbon steel, silicon-steel, foil, conductive resin, carbon black, aluminum flakes, and other metals and composite materials capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference.

[0032] In FIG. 2m, a portion of the shielding material (186) on the mask (184) is removed by etching, LDA, or grinding, leaving a conductive layer (162) exposed on the surface (166) of the interposer (160). In FIG. 2n, an electrical connector (194) having contacts (196) and a bump material or conductive paste (198) is placed on the conductive layer (162) exposed on the surface (166) of the interposer (160). The bumps (198) are placed to contact the exposed conductive layer (162) and are reflowed or cured to form electrical and mechanical interconnections with the conductive layer. FIG. 2o shows the state in which the shielding material (186) is placed on the encapsulating agent (180) and the electrical connector (194) is connected to the interposer (160) and the antenna interposer (150).

[0033] FIG. 20 shows an AiP module (200) having a double-sided electrical component (152) (active surfaces interconnected by conductive vias (111)) placed between an antenna interposer (150) and a semiconductor assembly (178) (including a PMIC). The electrical component (152) has a larger footprint and accommodates a higher density of circuits and functions due to the nature of the double-sided structure having conductive vias (111) that provide connectivity between the two active surfaces (108 and 110). By stacking the semiconductor assembly (178) on top of the electrical component (152) and the electrical component (152) on top of the antenna interposer (150), the AiP module (200) minimizes the overall package size while accommodating the large electrical component (152).

[0034] In another embodiment, following FIG. 3c, as shown in FIG. 4a, an encapsulating agent or molding compound (202) is applied over and around the semiconductor assembly (178) using paste printing, compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, spin coating, or other suitable applicators. Parts having similar functions are given the same reference number. The encapsulating agent (202) may be a polymer composite material such as an epoxy resin containing a filler, an epoxy acrylate containing a filler, or a polymer containing a suitable filler. The encapsulating agent (202) is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants. Similar to FIG. 2j, a portion of the encapsulating agent (202) is removed by grinding, thereby exposing the area (204) of the interposer (160). The semiconductor assembly (178) containing the encapsulating agent (202) constitutes the semiconductor assembly (210). In one embodiment, the semiconductor assembly (210) includes a PMIC such as an electrical component (170c). The PMIC controls a power device such as an electrical component (152) that implements an RFIC.

[0035] In FIG. 4b, an electrically conductive bump material is deposited on a surface (168) on a conductive layer (162) using an evaporation, electroplating, electroless plating, ball drop, or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, and may optionally contain a flux solution. For example, the bump material may be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer (162) using a suitable attachment or bonding process. In one embodiment, the bump material is heated above its melting point and reflowed to form a ball or bump (206). In one embodiment, the bump (206) is formed on an under-bump metallization (UBM) having a wetting layer, a blocking layer, and an adhesive layer. The bump (206) may also be press-bonded or hot-pressed to the conductive layer (162). The bump (206) represents one type of interconnect structure that can be formed on the conductive layer (162). The interconnect structure may also use bond wire, conductive paste, stud bumps, microbumps, or other electrical interconnects. The electrical components (170a–170c) and the interposer (160) having the bump (206) of FIG. 4b represent a semiconductor assembly (210). In one embodiment, the semiconductor assembly (210) includes a PMIC such as the electrical component (170c).

[0036] Following FIG. 2g, as illustrated in FIG. 5a, an encapsulating agent or molding compound (214) is applied over and around the electrical component (152) and antenna interposer (150) using paste printing, compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, spin coating, or other suitable applicators. The encapsulating agent (214) may be a polymer composite material such as an epoxy resin containing a filler, an epoxy acrylate containing a filler, or a polymer containing a suitable filler. The encapsulating agent (214) is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

[0037] In FIG. 5b, the semiconductor assembly (210) of FIG. 4 is placed on the active surface (108) of the electrical component (152) of FIG. 5a. The semiconductor assembly (210) is positioned on the electrical component (152) using a pick-and-place operation. The bump (206) is reflowed after contact with the conductive layer (142) to form electrical and mechanical interconnections. FIG. 5c shows the semiconductor assembly (210) placed on the surface (108) of the electrical component (152) with the bump (206) electrically and mechanically connected to the conductive layer (142).

[0038] In FIG. 5d, an underfill material (216), such as epoxy resin, is applied between the semiconductor assembly (210) and the electrical component (152).

[0039] In FIG. 5e, a mask (220) is placed in the area (204) above the interposer (160). Note the gap between the mask (220) and the surface (222) of the encapsulating agent (202).

[0040] The electrical components (152 and 170a-170c) may include IPDs that are susceptible to or cause EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPDs included in the electrical components (152 and 170a-170c) provide electrical characteristics required for high-frequency applications such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetric high-Q resonant transformers, and regulating capacitors. In another embodiment, the electrical components (152 and 170a-170c) may include digital circuits that switch at high frequencies, which may cause interference with the operation of the IPDs within the assembly.

[0041] To address EMI, RFI, harmonic distortion, and inter-device interference, an electromagnetic shielding material (224) is applied over a mask (220) and an encapsulating agent (202 and 214) covering the semiconductor assembly (210) and the antenna interposer (150). This includes a side surface (222) of the encapsulating agent (202) and a side surface (223) of the encapsulating agent (214), as illustrated in FIG. 5f. The electromagnetic shielding material (224) may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, the electromagnetic shielding material (224) may be carbonyl iron, stainless steel, nickel silver, low carbon steel, silicon-steel, foil, conductive resin, carbon black, aluminum flakes, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference.

[0042] In FIG. 5g, a portion of the shielding material (224) on the mask (220) is removed by an etching, LDA, or grinding process, leaving a conductive layer (162) exposed on the surface (166) of the interposer (160). In FIG. 5h, similar to FIG. 2n, an electrical connector (230) having contacts (232) and a bump material or conductive paste (234) is placed on the conductive layer (162) exposed on the surface (166) of the interposer (160). The bumps (234) are placed to contact the exposed conductive layer (162) and are reflowed or cured to form electrical and mechanical interconnections with the conductive layer.

[0043] FIG. 5h shows an AiP module (240) having a double-sided electrical component (152) (interconnected via conductive vias (111)) placed between an antenna interposer (150) and a semiconductor assembly (210) (including a PMIC). Due to the nature of the double-sided structure, the electrical component (152) has a larger footprint to accommodate higher density circuits and functions through conductive vias (111) that provide connectivity between the two active surfaces (108 and 110). By stacking the semiconductor assembly (210) on top of the electrical component (152) and the electrical component (152) on top of the antenna interposer (150), the AiP module (240) accommodates the large electrical component (152) while minimizing the overall package size.

[0044] FIG. 6 shows an electrical device (400) comprising a chip carrier substrate or PCB (402) having a plurality of semiconductor packages (including AiP modules (200 and 240)) disposed on the surface of the PCB (402). Depending on the application, the electrical device (400) may have one type of semiconductor package or multiple types of semiconductor packages.

[0045] The electrical device (400) may be a standalone system that performs one or more electrical functions using a semiconductor package. Alternatively, the electrical device (400) may be a sub-component of a larger system. For example, the electrical device (400) may be part of a tablet, mobile phone, digital camera, communication system, or other electrical device. Alternatively, the electrical device (400) may be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package may include a microprocessor, memory, ASIC, logic circuit, analog circuit, RF circuit, discrete component, or other semiconductor die or electrical component. Miniaturization and lightweighting are essential for the product to be accepted in the market. The distance between semiconductor devices can be reduced to achieve higher density.

[0046] In FIG. 6, the PCB (402) provides a general substrate for structural support and electrical interconnection of semiconductor packages placed on the PCB. Conductive signal traces (404) are formed on the surface or within a layer of the PCB (402) using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. The signal traces (404) provide electrical communication between each semiconductor package, mounted components, and other external system components. The traces (404) also provide power and ground connections to each semiconductor package.

[0047] In some embodiments, the semiconductor device may have two packaging levels. The first level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only the first level packaging in which the die itself is mechanically and electrically placed directly onto the PCB.

[0048] For illustrative purposes, various types of primary level packaging, including bond wire packages (406) and flip chips (408), are shown on the PCB (402). Additionally, a ball grid array (BGA) (410), a bump chip carrier (BCC) (412), a land grid array (LGA) (416), a multichip module (MCM) or SIP module (418), a quad flat non-lead package (QFN) (420), a quad flat package (422), an embedded wafer level ball grid array (eWLB) (424), and a wafer level chip scale package (WLCSP) (426) are shown placed on the PCB (402). In one embodiment, the eWLB (424) is a fan-out wafer level package (Fo-WLP), and the WLCSP (426) is a fan-in wafer level package (Fi-WLP). Depending on system requirements, any combination of semiconductor packages and other electrical components composed of any combination of first and second level packaging styles may be connected to the PCB (402). In some embodiments, the electrical device (400) includes a single attached semiconductor package, whereas in other embodiments, multiple interconnected packages are required. By combining one or more semiconductor packages on a single substrate, the manufacturer can integrate prefabricated components into the electrical device and system. Since the semiconductor package contains sophisticated functions, the electrical device can be manufactured using cheaper components and a simplified manufacturing process. As a result, the produced device has a low failure rate and low manufacturing costs, providing lower costs to the consumer.

[0049] Although one or more embodiments of the present invention have been described in detail, those skilled in the art will understand that modifications and adaptations to such embodiments are possible without departing from the scope of the invention as specified in the claims of this application.

Claims

Claim 1 A semiconductor device comprising: an antenna substrate; an electrical component disposed on the antenna substrate, wherein the electrical component has a first active surface and a second active surface facing the first active surface, and a conductive via extending between the first active surface and the second active surface; and a semiconductor assembly disposed on the electrical component. Claim 2 A semiconductor device according to claim 1, further comprising an encapsulation agent deposited on and around the antenna substrate and the electrical component. Claim 3 A semiconductor device according to claim 1, further comprising an encapsulation agent deposited on the semiconductor assembly. Claim 4 A semiconductor device according to claim 1, further comprising a shielding layer disposed on and around the antenna substrate, the electrical component, and the semiconductor assembly. Claim 5 A semiconductor device according to claim 1, further comprising a mask disposed on the semiconductor assembly. Claim 6 A semiconductor device, wherein the semiconductor device comprises: an antenna substrate; an electrical component disposed on the antenna substrate; and a semiconductor assembly disposed on the electrical component. Claim 7 A semiconductor device according to claim 6, wherein the electrical component comprises a first active surface and a second active surface facing the first active surface, and a conductive via extending between the first active surface and the second active surface. Claim 8 A semiconductor device according to claim 6, further comprising an encapsulation agent deposited on and around the antenna substrate and the electrical component. Claim 9 A semiconductor device according to claim 6, further comprising a shielding layer disposed on and around the antenna substrate, the electrical component, and the semiconductor assembly. Claim 10 A semiconductor device according to claim 6, further comprising a mask disposed on the semiconductor assembly. Claim 11 A method for manufacturing a semiconductor device, wherein the method comprises: providing an antenna substrate; placing an electrical component on the antenna substrate, wherein the electrical component has a first active surface and a second active surface facing the first active surface, and a conductive via extends between the first active surface and the second active surface; and placing a semiconductor assembly on the electrical component. Claim 12 A method for manufacturing a semiconductor device according to claim 11, further comprising the step of depositing an encapsulation agent on and around the antenna substrate and the electrical component. Claim 13 A method for manufacturing a semiconductor device according to claim 11, further comprising the step of depositing an encapsulation agent on the semiconductor assembly. Claim 14 A method for manufacturing a semiconductor device according to claim 11, further comprising the step of placing a shielding layer on and around the antenna substrate, the electrical component, and the semiconductor assembly. Claim 15 A method for manufacturing a semiconductor device according to claim 11, further comprising the step of placing a mask on the semiconductor assembly.

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