Structure and manufacturing method thereof, semiconductor chip package and manufacturing method thereof, and semiconductor device

Abstract

[Problem] To provide a structure capable of suppressing warping after mounting a semiconductor chip and a method for manufacturing the same. [Solution] A method for manufacturing a structure for mounting a semiconductor chip; The structure comprises a core substrate, a chip-side build-up layer formed on a first side of the core substrate, and an opposite-side build-up layer formed on a second side opposite to the first side of the core substrate; A chip-side build-up layer comprises a plurality of insulating layers, wherein all of the plurality of insulating layers provided by the chip-side build-up layer do not include a fiber substrate, or, wherein a portion of the plurality of insulating layers provided by the chip-side build-up layer includes a fiber substrate; The opposite side build-up layer comprises a plurality of insulating layers, and a portion of the plurality of insulating layers provided by the opposite side build-up layer comprises a fiber substrate; A method for manufacturing a structure comprises a plurality of processes (i) for forming an insulating layer on a first side of a core substrate and a plurality of processes (ii) for forming an insulating layer on a second side of a core substrate; A method for manufacturing a structure, wherein the number of insulating layers containing fiber substrates in the opposite side build-up layer is 5% or more and 80% or less with respect to 100% of the total number of insulating layers in the opposite side build-up layer; and the number of insulating layers containing fiber substrates in the opposite side build-up layer is greater than the number of insulating layers containing fiber substrates in the chip side build-up layer.

Description

Technology Field

[0001] The present invention relates to a structure for mounting a semiconductor chip on one side and a method for manufacturing the same. The present invention also relates to a semiconductor chip package having the above structure, a method for manufacturing the same, and a semiconductor device. Background Technology

[0002] When mounting a semiconductor chip on a wiring board, structures such as package substrates are sometimes used. For example, a semiconductor chip is mounted on a structure to form a semiconductor chip package, and the semiconductor chip package is placed on the wiring board. Generally, the structure has wiring. Therefore, since the semiconductor chip and the wiring board are electrically connected through the wiring of the structure, mounting the semiconductor chip onto the wiring board can be achieved.

[0003] The above structure may be manufactured by a method including, for example, forming a conductor layer by interposing insulating layers on both sides of a core substrate (Patent Documents 1 and 2). In this case, the conductor layer may form wiring that connects a semiconductor chip and a wiring board. Additionally, the insulating layer may be manufactured using a prepreg comprising a fiber substrate (Patent Document 3). Prior art literature

[0004] Japanese Patent Publication No. JP 2015-122386, Japanese Patent Publication No. JP 2024-125831, International Publication No. 2009 / 119621 The problem to be solved

[0005] The above structure may include a build-up layer having a plurality of insulating layers. This build-up layer typically includes a plurality of insulating layers and a plurality of conductive layers, and is provided, for example, by a method of alternately forming insulating layers and conductive layers. Recently, there have been cases where the number of layers included in this build-up layer has increased, and consequently, the thickness of the build-up layer has increased. When the thickness of the build-up layer is large, significant warping may occur in the semiconductor chip package obtained by mounting a semiconductor chip on the structure.

[0006] The present invention, conceived in consideration of the above-mentioned problem, aims to provide a structure capable of suppressing warping after mounting a semiconductor chip and a method for manufacturing the same; a semiconductor chip package including the structure and a method for manufacturing the same; and a semiconductor device having the semiconductor chip package. means of solving the problem

[0007] The inventors carefully examined the above-mentioned problem to solve it. As a result, the inventors discovered that the above-mentioned problem could be solved by introducing an insulating layer containing a fiber substrate into a part of the build-up layer to satisfy specific requirements, thereby completing the present invention.

[0008] That is, the present invention includes the following.

[0009] <1> A method for manufacturing a structure for mounting a semiconductor chip;

[0010] The structure,

[0011] Core substrate and,

[0012] A chip-side build-up layer formed on the first side of the core substrate, and

[0013] It has an opposite build-up layer formed on a second side opposite to the first side of the core substrate;

[0014] The chip-side build-up layer has a plurality of insulating layers;

[0015] All of the plurality of insulating layers provided by the chip-side build-up layer do not include a fiber substrate, or, a portion of the plurality of insulating layers provided by the chip-side build-up layer includes a fiber substrate;

[0016] The opposite side build-up layer is provided with a plurality of insulating layers;

[0017] A portion of the plurality of insulating layers provided by the opposite side build-up layer includes a fiber substrate;

[0018] The method of manufacturing the structure,

[0019] A plurality of processes (i) for forming an insulating layer on the first side of a core substrate and

[0020] (ii) A plurality of processes for forming an insulating layer on the second side of the core substrate

[0021] Includes,

[0022] The number of insulating layers including fiber substrates in the opposite build-up layer is 5% or more and 80% or less with respect to 100% of the total number of multiple insulating layers in the opposite build-up layer;

[0023] A method for manufacturing a structure in which the number of insulating layers containing fiber substrates in the opposite side build-up layer is greater than the number of insulating layers containing fiber substrates in the chip side build-up layer.

[0024] <2> A method for manufacturing a structure for mounting a semiconductor chip;

[0025] The structure,

[0026] Core substrate and,

[0027] A chip-side build-up layer formed on the first side of the core substrate, and

[0028] It has an opposite build-up layer formed on a second side opposite to the first side of the core substrate;

[0029] The chip-side build-up layer has a plurality of insulating layers;

[0030] All of the plurality of insulating layers provided by the chip-side build-up layer do not include a fiber substrate, or, a portion of the plurality of insulating layers provided by the chip-side build-up layer includes a fiber substrate;

[0031] The opposite side build-up layer is provided with a plurality of insulating layers;

[0032] A portion of the plurality of insulating layers provided by the opposite side build-up layer includes a fiber substrate;

[0033] The method of manufacturing the structure,

[0034] A plurality of processes (i) for forming an insulating layer on the first side of a core substrate and

[0035] (ii) A plurality of processes for forming an insulating layer on the second side of the core substrate

[0036] Including;

[0037] The sum of the thicknesses of the insulating layers including the fiber substrates in the opposite build-up layer is 5% or more and 80% or less when the sum of the thicknesses of the plurality of insulating layers in the opposite build-up layer is set to 100%;

[0038] A method for manufacturing a structure in which the sum of the thicknesses of the insulating layers including fiber substrates in the opposite side build-up layer is greater than the sum of the thicknesses of the insulating layers including fiber substrates in the chip side build-up layer.

[0039] <3> A plurality of processes (ii) for forming an insulating layer on the second side of a core substrate includes a process for forming an insulating layer comprising a fiber substrate;

[0040] A process for forming an insulating layer including a fiber substrate comprises laminating a fiber-containing sheet having a prepreg layer;

[0041] A prepreg layer comprising a fiber substrate and a resin composition impregnated in the fiber substrate, <1> or <2> Method for manufacturing a structure described in

[0042] <4> Lamination of fiber-containing sheets by a lamination method <3> Method for manufacturing a structure described in

[0043] <5> A fiber-containing sheet comprises a prepreg layer and a cured layer formed on one side of the prepreg layer, and

[0044] A cured layer comprising a cured product of a thermosetting resin composition, <3> or <4> Method for manufacturing a structure described in

[0045] <6> A prepreg layer having a minimum melt viscosity of 10,000 poise or less in a temperature range of 100°C to 140°C, <3> inside <5> A method for manufacturing a structure described in any one of the claims.

[0046] <7> A cured sample obtained by curing a fiber-containing sheet, wherein the glass transition temperature of the cured sample is 250℃ or lower, <3> inside <6> A method for manufacturing a structure described in any one of the claims.

[0047] <8> A plurality of processes (ii) for forming an insulating layer on the second side of the core substrate includes a process for forming an insulating layer that does not include a fiber substrate;

[0048] A process for forming an insulating layer not comprising a fiber substrate comprises laminating a resin composition layer not comprising a fiber substrate;

[0049] The absolute value of the difference between the glass transition temperature of a cured sample obtained by curing a fiber-containing sheet and the glass transition temperature of a cured sample obtained by curing a resin composition layer is 80℃ or less, <3> inside <7> A method for manufacturing a structure described in any one of the claims.

[0050] <9> A core substrate having a thickness of 0.1 mm or more and 2 mm or less, <1> inside <8> A method for manufacturing a structure described in any one of the claims.

[0051] <10> The opposite side build-up layer has four or more insulating layers, <1> inside <9> A method for manufacturing a structure described in any one of the claims.

[0052] <11> The opposite build-up layer has a thickness of 60㎛ or more and 700㎛ or less, <1> inside <10> A method for manufacturing a structure described in any one of the claims.

[0053] <12> The number of insulating layers provided by the chip-side build-up layer and the number of insulating layers provided by the opposite-side build-up layer are the same. <1> inside <11> A method for manufacturing a structure described in any one of the claims.

[0054] <13> As a structure for mounting a semiconductor chip;

[0055] The structure,

[0056] Core substrate and,

[0057] A chip-side build-up layer formed on the first side of the core substrate, and

[0058] It has an opposite build-up layer formed on a second side opposite to the first side of the core substrate;

[0059] The chip-side build-up layer has a plurality of insulating layers;

[0060] All of the plurality of insulating layers provided by the chip-side build-up layer do not include a fiber substrate, or, a portion of the plurality of insulating layers provided by the chip-side build-up layer includes a fiber substrate;

[0061] The opposite side build-up layer is provided with a plurality of insulating layers;

[0062] A portion of the plurality of insulating layers provided by the opposite side build-up layer includes a fiber substrate;

[0063] The number of insulating layers including fiber substrates in the opposite build-up layer is 5% or more and 80% or less with respect to 100% of the total number of multiple insulating layers in the opposite build-up layer;

[0064] A structure in which the number of insulating layers containing fiber substrates in the opposite side build-up layer is greater than the number of insulating layers containing fiber substrates in the chip side build-up layer.

[0065] <14> As a structure for mounting a semiconductor chip;

[0066] The structure,

[0067] Core substrate and,

[0068] A chip-side build-up layer formed on the first side of the core substrate, and

[0069] It has an opposite build-up layer formed on a second side opposite to the first side of the core substrate;

[0070] The chip-side build-up layer has a plurality of insulating layers;

[0071] All of the plurality of insulating layers provided by the chip-side build-up layer do not include a fiber substrate, or, a portion of the plurality of insulating layers provided by the chip-side build-up layer includes a fiber substrate;

[0072] The opposite side build-up layer is provided with a plurality of insulating layers;

[0073] A portion of the plurality of insulating layers provided by the opposite side build-up layer includes a fiber substrate;

[0074] The sum of the thicknesses of the insulating layers including the fiber substrates in the opposite build-up layer is 5% or more and 80% or less when the sum of the thicknesses of the plurality of insulating layers in the opposite build-up layer is set to 100%;

[0075] A structure in which the sum of the thicknesses of the insulating layers containing fiber substrates in the opposite side build-up layer is greater than the sum of the thicknesses of the insulating layers containing fiber substrates in the chip side build-up layer.

[0076] <15> <13> or <14> A method for manufacturing a semiconductor chip package, comprising a process of mounting a semiconductor chip on a chip-side build-up layer of a structure described in the above.

[0077] <16> <13> or <14> A semiconductor chip package comprising a structure described in the above and a semiconductor chip mounted on a chip-side build-up layer of the structure.

[0078] <17> <16> A semiconductor device having a semiconductor chip package described in Effects of the invention

[0079] According to the present invention, a structure capable of suppressing bending after mounting a semiconductor chip and a method for manufacturing the same; a semiconductor chip package including the structure and a method for manufacturing the same; and a semiconductor device having the semiconductor chip package can be provided. Brief explanation of the drawing

[0080] FIG. 1 is a cross-sectional view schematically showing a structure according to one embodiment of the present invention. FIG. 2 is a plan view schematically showing a portion of a fiber substrate according to an example, viewed in the thickness direction. FIG. 3 is a schematic cross-sectional view illustrating the manufacturing process of a structure according to an example. FIG. 4 is a schematic cross-sectional view illustrating the manufacturing process of a structure according to an example. FIG. 5 is a schematic cross-sectional view illustrating the manufacturing process of a structure according to an example. FIG. 6 is a schematic cross-sectional view illustrating the manufacturing process of a structure according to an example. FIG. 7 is a schematic cross-sectional view illustrating the manufacturing process of a structure according to an example. FIG. 8 is a cross-sectional view schematically showing a semiconductor chip package according to one embodiment of the present invention. FIG. 9 is a cross-sectional view schematically showing an intermediate laminate obtained in the process of manufacturing a semiconductor chip package according to one embodiment of the present invention. FIG. 10 is a cross-sectional view schematically showing a semiconductor chip package according to one embodiment of the present invention. Specific details for implementing the invention

[0081] Hereinafter, embodiments and examples of the present invention will be described. However, the present invention is not limited to the embodiments and examples shown below, and may be modified and implemented within the scope of the claims and their equivalents without departing from the scope of the claims and their equivalents.

[0082] In the following description, "parallel" and "perpendicular" are preferably free of error unless specifically noted otherwise, but may include error. The range of error is typically ±5°, preferably ±3°, more preferably ±1°, and even more preferably ±0.5°.

[0083] <Overview of Embodiments of the Structure>

[0084] FIG. 1 is a cross-sectional view schematically illustrating a structure (10) according to an embodiment of the present invention. As shown in FIG. 1, the structure (10) according to an embodiment of the present invention comprises a core substrate (100), a chip-side build-up layer (200) formed on a first side (100U) of the core substrate (100), and an opposite-side build-up layer (300) formed on a second side (100D) opposite to the first side (100U) of the core substrate (100). The structure (10) is a member for mounting a semiconductor chip (not shown) on one side thereof, and specifically, a semiconductor chip is mounted on the chip-side build-up layer (200). Accordingly, the first side (100U) of the core substrate (100) corresponds to the chip-side surface, and the second side (100D) corresponds to the opposite-side surface. Therefore, below, the first side (100U) may be referred to as the "chip side" (100U), and the second side (100D) may also be referred to as the "opposite side" (100D).

[0085] The chip-side build-up layer (200) comprises a plurality of insulating layers (211, 212, 213, and 214). Hereinafter, the insulating layers (211, 212, 213, and 214) provided by the chip-side build-up layer (200) may be referred to as "chip-side insulating layers" (211, 212, 213, and 214). In this embodiment, an example of a chip-side build-up layer (200) is shown having the chip-side insulating layer (211), the chip-side insulating layer (212), the chip-side insulating layer (213), and the chip-side insulating layer (214) in that order from the core substrate (100) side.

[0086] Additionally, the opposite side build-up layer (300) is provided with a plurality of insulating layers (311, 312, 313, and 314). Hereinafter, the insulating layers (311, 312, 313, and 314) provided by the opposite side build-up layer (300) may be referred to as "opposite side insulating layers" (311, 312, 313, and 314). In this embodiment, an example is shown of an opposite side build-up layer (300) provided with the opposite side insulating layer (311), the opposite side insulating layer (312), the opposite side insulating layer (313), and the opposite side insulating layer (314) in that order from the core substrate (100) side. Accordingly, in the thickness direction, the structure (10) is provided with an opposite side insulating layer (314), an opposite side insulating layer (313), an opposite side insulating layer (312), an opposite side insulating layer (311), a core substrate (100), a chip side insulating layer (211), a chip side insulating layer (212), a chip side insulating layer (213), and a chip side insulating layer (214) in this order.

[0087] The chip-side insulating layers (211 to 214) and the opposite-side insulating layers (311 to 314) all comprise a cured product of a resin composition. Additionally, a portion of the opposite-side insulating layers (311 to 314) comprises a fiber substrate (400). At this time, the fiber substrate (400) is used such that the number of opposite-side insulating layers comprising the fiber substrate (400) in the opposite-side build-up layer (300) is greater than the number of chip-side insulating layers comprising the fiber substrate (400) in the chip-side build-up layer (200). Accordingly, a portion of the plurality of chip-side insulating layers (211 to 214) provided by the chip-side build-up layer (200) may comprise the fiber substrate (400). Additionally, all of the plurality of chip-side insulating layers (211 to 214) may not comprise the fiber substrate (400).

[0088] In addition, with respect to 100% of the total number of opposite insulating layers (311 to 314) in the opposite build-up layer (300), the ratio of the number of opposite insulating layers (314) containing fiber substrates (400) in the opposite build-up layer (300) is within a specific range. The above ratio may be referred to as the "fiber substrate content ratio" or the "fiber substrate content ratio based on the number of layers" below. The fiber substrate content ratio based on the number of layers of the opposite build-up layer (300) is typically 5% or more, preferably 8% or more, more preferably 12% or more, preferably 80% or less, more preferably 65% ​​or less, and even more preferably 50% or less.

[0089] FIG. 1 illustrates an example in which the outermost opposite insulating layer (314) of the opposite build-up layer (300) comprises a fiber substrate (400), while the other opposite insulating layers (311 to 313) and all chip-side insulating layers (211 to 214) do not comprise a fiber substrate (400). Accordingly, in the example shown in FIG. 1, the opposite build-up layer (300) comprises four opposite insulating layers (311 to 314), and since one of the opposite insulating layers (314) comprises a fiber substrate (400), the fiber substrate content ratio based on the number of layers is 25%.

[0090] According to this structure (10), bending can be suppressed after mounting a semiconductor chip on the chip-side build-up layer (200) of the structure (10). Specifically, according to the structure (10) of the present embodiment, bending can be suppressed after the reflow process of mounting a semiconductor chip.

[0091] In part or all of the chip-side insulating layers (211 to 214) provided by the chip-side build-up layer (200), holes (221 to 224), such as via holes, may be formed. Additionally, the chip-side build-up layer (200) may have any layer combined with the chip-side insulating layers (211 to 214), for example, may have a conductor layer (231, 232, 233 and 234). The conductor layer (231 to 234) may be formed on the surface of the insulating layers (211 to 214) or may be formed within the holes (221 to 224).

[0092] In part or all of the opposite insulating layers (311 to 314) provided by the opposite build-up layer (300), holes (321 to 324), such as via holes, may be formed. Additionally, the opposite build-up layer (300) may have any layer combined with the opposite insulating layers (311 to 314), for example, may have a conductor layer (331, 332, 333 and 334). The conductor layer (331 to 334) may be formed on the surface of the insulating layers (311 to 314) or may be formed within the holes (321 to 324).

[0093] In the above description, a suitable embodiment of the present invention has been described based on the ratio of fiber substrates based on the number of layers, but the present invention may be specified by the ratio of the thickness of the insulating layer containing fiber substrates instead of the ratio of the number of insulating layers containing fiber substrates. Accordingly, in another embodiment of the present invention, the sum of the thicknesses of the opposite insulating layer containing fiber substrates (400) in the opposite build-up layer (300) is greater than the sum of the thicknesses of the chip insulating layer containing fiber substrates (400) in the chip build-up layer (200), and the ratio of the sum of the thicknesses of the opposite insulating layer (314) containing fiber substrates in the opposite build-up layer (300) to 100% of the sum of the thicknesses of the plurality of opposite insulating layers (311 to 314) in the opposite build-up layer (300) is within a specific range. The above ratio may be referred to as the "fiber substrate content ratio based on thickness" below. The fiber substrate content ratio based on the thickness of the opposite insulating layer (314) containing the fiber substrate (400) in the opposite build-up layer (300) is typically 5% or more, preferably 8% or more, more preferably 12% or more, preferably 80% or less, more preferably 65% ​​or less, and more preferably 50% or less. In this embodiment, the fiber substrate (400) is used such that the total thickness of the opposite insulating layer containing the fiber substrate (400) in the opposite build-up layer (300) is greater than the total thickness of the chip insulating layer containing the fiber substrate (400) in the chip build-up layer (200). In this embodiment as well, some of the plurality of chip insulating layers (211 to 214) provided by the chip build-up layer (200) may contain the fiber substrate (400), and all of the plurality of chip insulating layers (211 to 214) may not contain the fiber substrate (400). The present invention may satisfy at least one of the following conditions (1) and (2).

[0094] (1) The number of opposite insulating layers containing fiber substrates (400) in the opposite build-up layer (300) is greater than the number of chip insulating layers containing fiber substrates (400) in the chip build-up layer (200), and the “fiber substrate ratio based on the number of layers” in the opposite build-up layer (300) is within the above specific range.

[0095] (2) The total thickness of the opposite side insulation layer containing the fiber substrate (400) in the opposite side build-up layer (300) is greater than the total thickness of the chip side insulation layer containing the fiber substrate (400) in the chip side build-up layer (200), and the “fiber substrate content ratio based on thickness” in the opposite side build-up layer (300) is within the above specific range.

[0096] <Core substrate (100)>

[0097] The core substrate (100) is a member that serves as a substrate for the structure (10), and examples include a glass epoxy substrate, a metal substrate, a polyester substrate, a polyimide substrate, a BT resin substrate, a thermosetting polyphenylene ether substrate, etc. Additionally, the core substrate (100) may have conductive layers (120 and 130) on one or both sides thereof. For example, the core substrate (100) may have a support substrate (110) and conductive layers (120 and 130) formed on the support substrate (110). The conductive layers (120 and 130) provided by the core substrate (100) may be patterned. These conductive layers (120 and 130) may function as circuits. Additionally, a core substrate (100) provided with a component (not shown) may be used.

[0098] The thickness of the core substrate (100) is preferably 2 mm or less, more preferably 1 mm or less, and even more preferably 0.5 mm or less. In the past, when such a thin core substrate was used, there was a tendency for warping to occur, but according to the structure (10) of the present embodiment, it is possible to suppress warping even when such a thin core substrate (100) is used. The lower limit of the thickness of the core substrate (100) is preferably 0.1 mm or more, and more preferably 0.2 mm or more. When the lower limit of the thickness of the core substrate (100) is within the above range, warping after mounting the semiconductor chip can be effectively suppressed.

[0099] <Opposite side build-up layer (300)>

[0100] As described above, the opposite side build-up layer (300) has a plurality of opposite side insulating layers (311 to 314). The range of the number of opposite side insulating layers (311 to 314) provided by the opposite side build-up layer (300) is, specifically, typically 2 layers or more, preferably 3 layers or more, more preferably 4 layers or more, preferably 20 layers or less, more preferably 15 layers or less, even more preferably 10 layers or less, particularly preferably 8 layers or less.

[0101] A plurality of opposite insulating layers (311 to 314) each comprise a cured product obtained by curing a resin composition. The resin composition is typically a thermosetting resin composition, and thus, the cured product may be obtained by thermosetting the resin composition. Details of the resin composition will be described later.

[0102] A portion of the opposite insulating layer (314) provided by the opposite build-up layer (300) comprises a fiber substrate (400) in combination with a cured resin composition. The fiber substrate (400) generally comprises a plurality of filaments (411 and 421). A gap is formed between these plurality of filaments (411 and 421), and a cured resin composition may be retained in this gap. For example, after the resin composition is impregnated into the fiber substrate (400), the resin composition is cured to form a cured product, thereby obtaining a state in which the cured product is retained in the gap between the filaments (411 and 421). Additionally, the cured product may be retained not only in the gap between the filaments (411 and 421) of the fiber substrate (400), but also around the filaments (411 and 421).

[0103] The fiber substrate (400) may be, for example, a nonwoven fabric. Additionally, for example, the fiber substrate (400) may include yarns (410 and 420) formed by bundling multiple filaments (411 and 412). FIG. 2 is a schematic plan view showing a portion of the fiber substrate (400) according to an example in the thickness direction. As shown in FIG. 2, the fiber substrate (400) may be a woven material woven with warp threads (410) and weft threads (420). In this embodiment, the fiber substrate (400) as a woven material comprising multiple warp threads (410) and multiple weft threads (420) as shown in FIG. 2 is described as an example.

[0104] The warp (410) is a thread formed by binding a plurality of filaments (411) and thus includes a plurality of filaments (411). Additionally, the weft (420) is a thread formed by binding a plurality of filaments (421) and thus includes a plurality of filaments (421). As shown in FIG. 2, the fiber substrate (400) is formed by weaving the warp (410) and the weft (420). Therefore, when viewed in the thickness direction, the warp (410) and the weft (420) can be arranged to intersect perpendicularly.

[0105] The range of the number of threads per unit dimension included in the fiber substrate (400) is preferably 50 threads / 25mm or more, more preferably 55 threads / 25mm or more, even more preferably 60 threads / 25mm or more, even more preferably 70 threads / 25mm or more, preferably 150 threads / 25mm or less, more preferably 130 threads / 25mm or less, and even more preferably 120 threads / 25mm or less. "Number of threads per unit dimension" refers to the number of threads per unit dimension in the in-plane direction perpendicular to the direction in which the threads extend. Accordingly, for example, the number of warp threads per unit dimension of the warp (410) refers to the number of warp threads per unit dimension in the in-plane direction perpendicular to the direction in which the warp (410) extends (usually, the direction in which the weft extends). Hereinafter, the number of warp threads per unit dimension of the warp (410) may be referred to as "warp density." In addition, the number of weft threads (420) per unit dimension is sometimes referred to as "weft density." The warp density and weft density may be the same or different. When the number of threads per unit dimension is within the above range, the bending of the semiconductor chip after mounting can be effectively suppressed.

[0106] As for the material of the filaments (411 and 421), it is preferable to use an insulating material, and a material with a small dielectric loss tangent is even more preferable. Preferred examples of the material of the filaments (411 and 421) include glass materials; resin materials such as aramid resin and liquid crystal polymer; among these, glass materials are preferred. When using glass materials, the fiber substrate (400) may be glass cloth, and the filaments (411 and 421) may be glass filaments.

[0107] The fiber substrate (400) may be surface-treated with a surface treatment agent. By performing surface treatment, the formation of voids in the insulating layer (in the example shown in this embodiment, the opposite insulating layer (414)) containing the fiber substrate (400) can be suppressed. Examples of surface treatment agents include coupling agents such as silane coupling agents and titanate coupling agents; silane compounds such as alkoxysilanes and organosilazan compounds, and among these, coupling agents are preferred, and silane coupling agents are more preferred. Examples of silane coupling agents include aminosilane-based coupling agents, fluorine-containing silane coupling agents, epoxysilane-based coupling agents, mercaptosilane-based coupling agents, etc., and aminosilane-based coupling agents are more preferred. The surface treatment agent may be used as a single type or in combination of two or more types.

[0108] The weight per unit area of ​​the fiber substrate (400) is sometimes referred to as "fabric weight." The range of the fabric weight of the fiber substrate (400) is preferably 5 g / m² or more, more preferably 10 g / m² or more, even more preferably 15 g / m² or more, preferably 50 g / m² or less, more preferably 40 g / m² or less, and even more preferably 30 g / m² or less. When the fabric weight is within the above range, warping after mounting the semiconductor chip can be effectively suppressed.

[0109] As for the fiber material (400), commercially available products may be used. Examples of commercially available fiber materials (400) include glass cloths manufactured by Nitto Boseki Co., Ltd., such as “Style WEA1017”, “Style WEA1024”, “Style WEA1010”, “Style WEA1027”, “Style WEA1035”, and “Style WEA1037”; glass cloths manufactured by Asahi Schuebel Co., Ltd., such as “Style 1027MS” and “Style 1037MS”; glass cloths manufactured by Arisawa Sesakusho Co., Ltd., such as “1078”, “1037NS”, “1027NS”, “1015NS”, and “1000NS”; and nonwoven fabrics manufactured by Kuraray Co., Ltd., such as “Veclus” and “Vectran”.

[0110] The fiber substrate (400) is preferably thin. The specific thickness range of the fiber substrate (400) is preferably 50 μm or less, more preferably 40 μm or less, even more preferably 30 μm or less, and even more preferably 20 μm or less. The lower limit may be, for example, 5 μm or more or 10 μm or more.

[0111] The number of opposite insulating layers (opposite insulating layers (314), etc.) containing fiber substrates can be set so that the fiber substrate content ratio falls within the above range. Specifically, the number of opposite insulating layers containing fiber substrates is typically 1 or more, preferably 3 layers or less, more preferably 2 layers or less. When the number of opposite insulating layers containing fiber substrates is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed.

[0112] The opposite side build-up layer (300) preferably includes a fiber substrate (400) in the opposite side insulating layer (314) furthest from the core substrate (100), as shown in FIG. 1. In this case, warping after mounting of the semiconductor chip can be effectively suppressed.

[0113] The opposite insulating layer (opposite insulating layer (314), etc.) containing the fiber substrate preferably has a small linear thermal expansion coefficient in a high-temperature measurement range corresponding to the reflow temperature. Specifically, the range of the linear thermal expansion coefficient CTE (FOh) of the opposite insulating layer containing the fiber substrate in the high-temperature measurement range is preferably 25 ppm / °C or less, more preferably 20 ppm / °C or less, and even more preferably 16 ppm / °C or less. The lower limit may be, for example, 5 ppm / °C or more. The "high-temperature measurement range" may be, for example, a temperature range of 150°C or more and 240°C or less, and the same applies to the following description. When the linear thermal expansion coefficient CTE (FOh) of the opposite insulating layer containing the fiber substrate is in the above range, warping after mounting the semiconductor chip can be effectively suppressed. When the opposite side build-up layer (300) comprises a plurality of opposite side insulating layers including fiber substrates, the coefficient of linear thermal expansion CTE (FOh) of each of these opposite side insulating layers may be different, but it is preferable that they be the same.

[0114] It is preferable that the difference between the coefficient of linear thermal expansion CTE(FOh) in the high-temperature measurement range of the opposite insulating layer (opposite insulating layer (314), etc.) containing the fiber substrate and the coefficient of linear thermal expansion CTE(FOl) in the low-temperature measurement range lower than the high-temperature measurement range be small. Specifically, the range of the difference “CTE(FOh)-CTE(FOl)” between the coefficient of linear thermal expansion CTE(FOh) in the high-temperature measurement range of the opposite insulating layer containing the fiber substrate and the coefficient of linear thermal expansion CTE(FOl) in the low-temperature measurement range is preferably 10 ppm / ℃ or less, more preferably 5 ppm / ℃ or less, and even more preferably 2 ppm / ℃ or less. At this time, it is even more preferable that the coefficient of linear thermal expansion CTE(FOh) in the high-temperature measurement range of the opposite insulating layer containing the fiber substrate be smaller than the coefficient of linear thermal expansion CTE(FOl) in the low-temperature measurement range. Accordingly, the difference in the linear thermal expansion coefficient “CTE(FOh)-CTE(FOl)” above is more preferably less than 0 ppm / ℃, and particularly preferably less than -1 ppm / ℃. The lower limit may be, for example, -10 ppm / ℃ or higher, -5 ppm / ℃ or higher, etc. The “low temperature measurement range” may be, for example, a temperature range of 25℃ or higher and 150℃ or lower, and the same applies to the following description. When the difference in the linear thermal expansion coefficient “CTE(FOh)-CTE(FOl)” of the opposite insulating layer including the fiber substrate is within the above range, warping after mounting the semiconductor chip can be effectively suppressed.

[0115] Preferably, the coefficient of linear thermal expansion CTE (FOh) in the high-temperature measurement range of the opposite insulating layer (opposite insulating layer (314), etc.) containing the fiber substrate is smaller than the coefficient of linear thermal expansion CTE (ROh) in the high-temperature measurement range of the opposite insulating layer (opposite insulating layers (311 to 313), etc.) not containing the fiber substrate. At this time, the difference “CTE(ROh)-CTE(FOh)” between the coefficient of linear thermal expansion CTE (ROh) in the high-temperature measurement range of the opposite insulating layer not containing the fiber substrate and the coefficient of linear thermal expansion CTE (FOh) in the high-temperature measurement range of the opposite insulating layer containing the fiber substrate is preferably within a specific range. Specifically, the range of the difference in the coefficient of linear thermal expansion “CTE(ROh)-CTE(FOh)” is preferably 10 ppm / ℃ or more, more preferably 15 ppm / ℃ or more, even more preferably 20 ppm / ℃ or more, preferably 70 ppm / ℃ or less, more preferably 50 ppm / ℃ or less, and even more preferably 35 ppm / ℃ or less. When the difference in the coefficient of linear thermal expansion “CTE(ROh)-CTE(FOh)” is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0116] Preferably, the coefficient of linear thermal expansion CTE (FOh) in the high-temperature measurement range of the opposite insulating layer (opposite insulating layer (314) etc.) containing the fiber substrate is smaller than the coefficient of linear thermal expansion CTE (RCh) in the high-temperature measurement range of the chip-side insulating layer (chip-side insulating layers (211 to 214) etc.) not containing the fiber substrate. At this time, the difference “CTE(RCh)-CTE(FOh)” between the coefficient of linear thermal expansion CTE (RCh) in the high-temperature measurement range of the chip-side insulating layer not containing the fiber substrate and the coefficient of linear thermal expansion CTE (FOh) in the high-temperature measurement range of the opposite insulating layer containing the fiber substrate is preferably within a specific range. Specifically, the range of the difference in linear thermal expansion coefficients “CTE(RCh)-CTE(FOh)” may be the same as the range of the difference “CTE(ROh)-CTE(FOh)” between the linear thermal expansion coefficient CTE(ROh) in the high-temperature measurement range of the opposite insulating layer that does not include the fiber substrate and the linear thermal expansion coefficient CTE(FOh) in the high-temperature measurement range of the opposite insulating layer that includes the fiber substrate. When the difference in linear thermal expansion coefficients “CTE(RCh)-CTE(FOh)” is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0117] When the chip-side build-up layer (200) includes a chip-side insulating layer (not shown in FIG. 1) that includes a fiber substrate, the coefficient of linear thermal expansion CTE (FOh) in the high-temperature measurement range of the opposite-side insulating layer that includes the fiber substrate and the coefficient of linear thermal expansion CTE (FCh) in the high-temperature measurement range of the chip-side insulating layer that includes the fiber substrate may be different, but it is preferable that the difference be small. In one example, the range of the absolute value |CTE(FOh)-CTE(FCh)| of "CTE(FOh)-CTE(FCh)", which is the difference between the coefficient of linear thermal expansion CTE (FOh) in the high-temperature measurement range of the opposite-side insulating layer that includes the fiber substrate and the coefficient of linear thermal expansion CTE (FCh) in the high-temperature measurement range of the chip-side insulating layer that includes the fiber substrate, is preferably 10 ppm / ℃ or less, more preferably 5 ppm / ℃ or less, even more preferably 3 ppm / ℃ or less, and particularly preferably 0 ppm / ℃. Accordingly, it is particularly desirable that the coefficient of linear thermal expansion CTE(FCh) in the high-temperature measurement range of the chip-side insulating layer containing the fiber substrate and the coefficient of linear thermal expansion CTE(FOh) in the high-temperature measurement range of the opposite-side insulating layer containing the fiber substrate are the same.

[0118] Preferably, the opposite insulating layer (opposite insulating layer (314), etc.) containing the fiber substrate has a small linear thermal expansion coefficient in a low-temperature measurement range lower than the high-temperature measurement range above. Specifically, the range of the linear thermal expansion coefficient CTE(FOl) in the low-temperature measurement range of the opposite insulating layer (opposite insulating layer (314), etc.) containing the fiber substrate is preferably 30 ppm / °C or less, more preferably 25 ppm / °C or less, even more preferably 20 ppm / °C or less, and particularly preferably 19 ppm / °C or less. The lower limit may be, for example, 5 ppm / °C or more. When the linear thermal expansion coefficient CTE(FOl) of the opposite insulating layer containing the fiber substrate in the low-temperature measurement range is within the above range, warping after mounting the semiconductor chip can be effectively suppressed. When the opposite side build-up layer (300) comprises a plurality of opposite side insulating layers including fiber substrates, the coefficient of linear thermal expansion CTE (FOl) of each of these opposite side insulating layers may be different, but it is preferable that they be the same.

[0119] Preferably, the coefficient of linear thermal expansion CTE(FOl) in the low-temperature measurement range of the opposite insulating layer (opposite insulating layer 314, etc.) containing a fiber substrate is close to the coefficient of linear thermal expansion CTE(ROl) in the low-temperature measurement range of the opposite insulating layer (opposite insulating layers (311 to 313), etc.) not containing a fiber substrate. At this time, the range of the absolute value |CTE(ROl)-CTE(FOl)| of the difference "CTE(ROl)-CTE(FOl)" between the coefficient of linear thermal expansion CTE(ROl) in the low-temperature measurement range of the opposite insulating layer not containing a fiber substrate and the coefficient of linear thermal expansion CTE(FOl) in the low-temperature measurement range of the opposite insulating layer containing a fiber substrate is preferably 25 ppm / ℃ or less, more preferably 20 ppm / ℃ or less, and even more preferably 10 ppm / ℃ or less. When the absolute value of the difference in the coefficient of linear thermal expansion |CTE(RO1)-CTE(FOl)| is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0120] Preferably, the coefficient of linear thermal expansion CTE (FOl) in the low-temperature measurement range of the opposite side insulating layer (opposite side insulating layer (314) etc.) containing the fiber substrate is close to the coefficient of linear thermal expansion CTE (RCl) in the low-temperature measurement range of the chip side insulating layer (chip side insulating layers (211 to 214) etc.) not containing the fiber substrate. At this time, the range of the absolute value |CTE(RCl)-CTE(FOl)| of the difference “CTE(RCl)-CTE(FOl)” between the coefficient of linear thermal expansion CTE(RCl) in the low-temperature measurement range of the chip-side insulating layer not including the fiber substrate and the coefficient of linear thermal expansion CTE(FOl) in the low-temperature measurement range of the opposite-side insulating layer including the fiber substrate may be equal to the range of the absolute value |CTE(ROl)-CTE(FOl)| of the difference “CTE(ROl)-CTE(FOl)” between the coefficient of linear thermal expansion CTE(ROl) in the low-temperature measurement range of the opposite-side insulating layer not including the fiber substrate and the coefficient of linear thermal expansion CTE(FOl) in the low-temperature measurement range of the opposite-side insulating layer including the fiber substrate. When the absolute value of the difference in the coefficients of linear thermal expansion |CTE(RCl)-CTE(FOl)| is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0121] When the chip-side build-up layer (200) includes a chip-side insulating layer (not shown in FIG. 1) that includes a fiber substrate, the coefficient of linear thermal expansion CTE(FOl) in the low-temperature measurement range of the opposite-side insulating layer that includes the fiber substrate and the coefficient of linear thermal expansion CTE(FCl) in the low-temperature measurement range of the chip-side insulating layer that includes the fiber substrate may be different, but it is preferable that the difference be small. In one example, the range of the absolute value |CTE(FOl)-CTE(FCl)| of the difference "CTE(FOl)-CTE(FCl)" between the coefficient of linear thermal expansion CTE(FOl) in the low-temperature measurement range of the opposite-side insulating layer that includes the fiber substrate and the coefficient of linear thermal expansion CTE(FCl) in the low-temperature measurement range of the chip-side insulating layer that includes the fiber substrate is preferably 10 ppm / ℃ or less, more preferably 5 ppm / ℃ or less, even more preferably 3 ppm / ℃ or less, and particularly preferably 0 ppm / ℃. Accordingly, it is particularly desirable that the coefficient of linear thermal expansion CTE(FOl) in the low-temperature measurement range of the opposite insulating layer containing the fiber substrate and the coefficient of linear thermal expansion CTE(FCl) in the low-temperature measurement range of the chip-side insulating layer containing the fiber substrate are the same.

[0122] The opposite insulating layer having the aforementioned linear thermal expansion coefficients CTE(FOh) and CTE(FOl) can be formed by a cured product of a resin composition containing a fiber substrate. In particular, the opposite insulating layer having the aforementioned preferred linear thermal expansion coefficient CTE(FOh) in a high-temperature measurement range is difficult to form by a cured product of a resin composition that does not contain a fiber substrate. One of the technical significances of the fiber substrate is that it enables the smooth acquisition of an insulating layer having such a preferred linear thermal expansion coefficient.

[0123] The linear thermal expansion coefficients CTE(FOh) and CTE(FOl) of the opposite insulating layer containing the fiber substrate can be measured by thermomechanical analysis. Such thermomechanical analysis can be performed by a tensile weighted method with a load of 1 N and a heating rate of 5°C / min. The measurement can be performed twice, with the first measurement in a temperature range of 25°C to 200°C and the second measurement in a temperature range of 25°C to 260°C. Then, the linear thermal expansion coefficient can be calculated from the results of the second measurement. Specifically, among the results of the second measurement, the linear thermal expansion coefficient CTE(FOl) [ppm / °C] in the low-temperature measurement range can be calculated from the results from 25°C to 150°C, and the linear thermal expansion coefficient CTE(FOh) [ppm / °C] in the high-temperature measurement range can be calculated from the results from 150°C to 240°C.

[0124] The range of the glass transition temperature of the opposite insulating layer (opposite insulating layer (314), etc.) containing the fiber substrate is preferably 250°C or lower, more preferably 200°C or lower, even more preferably 180°C or lower, preferably 140°C or higher, more preferably 150°C or higher, and even more preferably 160°C or higher. When the glass transition temperature of the opposite insulating layer containing the fiber substrate is within the above range, warping after mounting the semiconductor chip can be effectively suppressed. When the opposite build-up layer (300) has a plurality of opposite insulating layers containing the fiber substrate, the glass transition temperatures of each of these opposite insulating layers may be different, but are preferred to be the same.

[0125] It is preferable that the glass transition temperature of the opposite insulating layer (opposite insulating layer (314, etc.)) containing the fiber substrate be close to the glass transition temperature of the opposite insulating layer (opposite insulating layer (311 to 313, etc.)) not containing the fiber substrate. At this time, the glass transition temperature of the opposite insulating layer containing the fiber substrate may be higher, lower, or equal to the glass transition temperature of the opposite insulating layer not containing the fiber substrate. The range of the absolute value of the difference between the glass transition temperature of the opposite insulating layer containing the fiber substrate and the glass transition temperature of the opposite insulating layer not containing the fiber substrate is preferably 80°C or less, more preferably 60°C or less, even more preferably 40°C or less, even more preferably 20°C or less, and even more preferably 10°C or less. The lower limit may be 0°C or more, 1°C or more, 2°C or more, or 3°C or more. When the absolute value of the difference in glass transition temperatures is within the above range, warping after mounting the semiconductor chip can be effectively suppressed.

[0126] In addition, the glass transition temperature of the opposite insulating layer (opposite insulating layer (314, etc.)) containing the fiber substrate is preferably close to the glass transition temperature of the chip-side insulating layer (chip-side insulating layer (211 to 214, etc.)) that does not contain the fiber substrate. At this time, the glass transition temperature of the opposite insulating layer containing the fiber substrate may be higher, lower, or equal to the glass transition temperature of the chip-side insulating layer that does not contain the fiber substrate. The range of the absolute value of the difference between the glass transition temperature of the opposite insulating layer containing the fiber substrate and the glass transition temperature of the chip-side insulating layer that does not contain the fiber substrate may be the same as the range of the absolute value of the difference between the glass transition temperature of the opposite insulating layer containing the fiber substrate and the glass transition temperature of the opposite insulating layer that does not contain the fiber substrate. When the absolute value of the difference in glass transition temperatures is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed.

[0127] When the chip-side build-up layer (200) includes a chip-side insulating layer (not shown in FIG. 1) that includes a fiber substrate, the glass transition temperature of the opposite-side insulating layer that includes the fiber substrate and the glass transition temperature of the chip-side insulating layer that includes the fiber substrate may be different, but it is preferable that the difference be small. In one example, the absolute value of the difference between the glass transition temperature of the opposite-side insulating layer that includes the fiber substrate and the glass transition temperature of the chip-side insulating layer that includes the fiber substrate is preferably 80°C or less, more preferably 60°C or less, even more preferably 40°C or less, even more preferably 20°C or less, even more preferably 10°C or less, and particularly preferably 0°C. Accordingly, it is particularly preferable that the glass transition temperature of the opposite-side insulating layer that includes the fiber substrate and the glass transition temperature of the chip-side insulating layer that includes the fiber substrate are the same.

[0128] The glass transition temperature of the opposite insulating layer containing the fiber substrate can be measured by thermomechanical analysis using the tensile weighting method. This thermomechanical analysis measures the storage modulus and loss modulus under measurement conditions of a load of 200 mN and a heating rate of 5°C / min. The glass transition temperature Tg (°C) can be obtained from the peak top of the temperature dependence curve of tanδ (ratio of storage modulus to loss modulus) obtained as a measurement result after heating up to 260°C.

[0129] The opposite insulating layer (opposite insulating layer (314, etc.)) containing a fiber substrate preferably has a large tensile modulus at a high temperature corresponding to the reflow temperature. Specifically, the range of the tensile modulus E(FOh) of the opposite insulating layer containing a fiber substrate at 260°C is preferably 2 GPa or more, more preferably 3 GPa or more, and even more preferably 4 GPa or more. The upper limit may be, for example, 15 GPa or less, 10 GPa or less, etc. When the tensile modulus E(FOh) of the opposite insulating layer containing a fiber substrate is within the above range, warping after mounting the semiconductor chip can be effectively suppressed. When the opposite build-up layer comprises a plurality of opposite insulating layers containing a fiber substrate, the tensile modulus E(FOh) of each of these opposite insulating layers may be different, but it is preferable that they be the same.

[0130] Generally, the tensile modulus of an insulating layer may decrease as the temperature rises. Here, it is desirable that the opposite insulating layer (opposite insulating layer (314, etc.)) containing the fiber substrate has a small degree of decrease in tensile modulus as the temperature rises. Specifically, the range of the ratio “E(FOh) / E(FOl)” of the tensile modulus E(FOh) of the opposite insulating layer containing the fiber substrate at 260°C to the tensile modulus E(FOl) of the opposite insulating layer containing the fiber substrate at 23°C is preferably 0.1 or higher, more preferably 0.15 or higher, and even more preferably 0.2 or higher. The upper limit is typically less than 1, and may be 0.8 or lower or 0.6 or lower. When the ratio “E(FOh) / E(FOl)” of the tensile modulus of the opposite insulating layer containing the fiber substrate is within the above range, warping after mounting the semiconductor chip can be effectively suppressed.

[0131] Preferably, the tensile modulus at high temperature of the opposite insulating layer (opposite insulating layer (314, etc.)) containing the fiber substrate is greater than the tensile modulus at high temperature of the opposite insulating layer (opposite insulating layer (311 to 313, etc.)) not containing the fiber substrate. At this time, the difference “E(FOh)-E(ROh)” between the tensile modulus E(FOh) at 260°C of the opposite insulating layer containing the fiber substrate and the tensile modulus E(ROh) at 260°C of the opposite insulating layer not containing the fiber substrate is preferably within a specific range. Specifically, the range of the difference “E(FOh)-E(ROh)” of the tensile modulus is preferably 1 GPa or more, more preferably 2 GPa or more, even more preferably 3 GPa or more, preferably 15 GPa or less, more preferably 10 GPa or less, and even more preferably 8 GPa or less. When the difference in tensile modulus “E(FOh)-E(ROh)” is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0132] Preferably, the tensile modulus at high temperature of the opposite insulating layer (opposite insulating layer (314, etc.)) containing the fiber substrate is greater than the tensile modulus at high temperature of the chip-side insulating layer (chip-side insulating layer (211 to 214, etc.)) not containing the fiber substrate. At this time, the difference “E(FOh)-E(RCh)” between the tensile modulus E(FOh) at 260°C of the opposite insulating layer containing the fiber substrate and the tensile modulus E(RCh) at 260°C of the chip-side insulating layer not containing the fiber substrate is preferably within a specific range. Specifically, the range of the difference in tensile modulus “E(FOh)-E(RCh)” may be the same as the range of the difference “E(FOh)-E(ROh)” between the tensile modulus E(FOh) at 260°C of the opposite insulating layer containing the fiber substrate and the tensile modulus E(ROh) at 260°C of the opposite insulating layer not containing the fiber substrate. When the difference in tensile modulus “E(FOh)-E(RCh)” is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0133] When the chip-side build-up layer (200) includes a chip-side insulating layer (not shown in FIG. 1) that includes a fiber substrate, the tensile elastic modulus at high temperature of the opposite insulating layer that includes the fiber substrate and the tensile elastic modulus at high temperature of the chip-side insulating layer that includes the fiber substrate may be different, but it is preferable that the difference is small. In one example, the range of the absolute value |E(FOh)-E(FCh)| of "E(FOh)-E(FCh)", which is the difference between the tensile elastic modulus E(FOh) at 260°C of the opposite insulating layer that includes the fiber substrate and the tensile elastic modulus E(FCh) at 260°C of the chip-side insulating layer that includes the fiber substrate, is preferably 5 GPa or less, more preferably 3 GPa or less, even more preferably 1 GPa or less, and particularly preferably 0 GPa. Accordingly, it is particularly desirable that the tensile modulus E(FCh) at 260°C of the chip-side insulating layer containing the fiber substrate and the tensile modulus E(FOh) at 260°C of the opposite-side insulating layer containing the fiber substrate are the same.

[0134] Preferably, the opposite insulating layer (opposite insulating layer (314, etc.)) containing the fiber substrate has a large tensile modulus at a low temperature lower than the reflow temperature. Specifically, the range of the tensile modulus E(FOl) at 23°C of the opposite insulating layer (opposite insulating layer (314, etc.)) containing the fiber substrate is preferably 10 GPa or more, more preferably 12 GPa or more, even more preferably 14 GPa or more, preferably 30 GPa or less, more preferably 25 GPa or less, and even more preferably 22 GPa or less. When the tensile modulus E(FOl) at 23°C of the opposite insulating layer containing the fiber substrate is within the above range, warping after mounting the semiconductor chip can be effectively suppressed. When the opposite build-up layer (300) has a plurality of opposite insulating layers containing the fiber substrate, the tensile modulus E(FOl) of each of these opposite insulating layers may be different, but it is preferable that they be the same.

[0135] Preferably, the tensile modulus E(FOl) at 23°C of the opposite insulating layer (opposite insulating layer (314) etc.) containing the fiber substrate is greater than the tensile modulus E(ROl) at 23°C of the opposite insulating layer (opposite insulating layer (311 to 313, etc.)) not containing the fiber substrate. At this time, the range of the difference “E(FOl)-E(ROl)” between the tensile modulus E(FOl) at 23°C of the opposite insulating layer containing the fiber substrate and the tensile modulus E(ROl) at 23°C of the opposite insulating layer not containing the fiber substrate is preferably 0.5 GPa or more, more preferably 1 GPa or more, even more preferably 1.5 GPa or more, preferably 10 GPa or less, more preferably 8 GPa or less, and even more preferably 5 GPa or less. When the difference in tensile modulus “E(FOl)-E(ROl)” is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0136] Preferably, the tensile modulus E(FOl) at 23°C of the opposite insulating layer (opposite insulating layer (314, etc.)) containing the fiber substrate is greater than the tensile modulus E(RCl) at 23°C of the chip-side insulating layer (chip-side insulating layer (211 to 214, etc.)) not containing the fiber substrate. At this time, the range of the difference “E(FOl)-E(RCl)” between the tensile modulus E(FOl) at 23°C of the opposite insulating layer containing the fiber substrate and the tensile modulus E(RCl) at 23°C of the chip-side insulating layer not containing the fiber substrate may be the same as the range of the difference “E(FOl)-E(ROl)” between the tensile modulus E(FOl) at 23°C of the opposite insulating layer containing the fiber substrate and the tensile modulus E(ROl) at 23°C of the opposite insulating layer not containing the fiber substrate. When the difference in tensile modulus “E(FOl)-E(RCl)” is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0137] When the chip-side build-up layer (200) includes a chip-side insulating layer (not shown in FIG. 1) that includes a fiber substrate, the tensile modulus E(FOl) at 23°C of the opposite-side insulating layer that includes the fiber substrate and the tensile modulus E(FCl) at 23°C of the chip-side insulating layer that includes the fiber substrate may be different, but it is preferable that the difference be small. In one example, the range of the absolute value |E(FOl)-E(FCl)| of the difference “E(FOl)-E(FCl)” between the tensile modulus E(FOl) at 23°C of the opposite-side insulating layer that includes the fiber substrate and the tensile modulus E(FCl) at 23°C of the chip-side insulating layer that includes the fiber substrate is preferably 5 GPa or less, more preferably 3 GPa or less, even more preferably 1 GPa or less, and particularly preferably 0 GPa. Therefore, it is particularly desirable that the tensile modulus E(FOl) at 23°C of the opposite insulating layer containing the fiber substrate and the tensile modulus E(FCl) at 23°C of the chip-side insulating layer containing the fiber substrate are the same.

[0138] The opposite insulating layer having the aforementioned tensile modulus E(FOh) and E(FOl) can be formed from a cured product of a resin composition containing a fiber substrate. In particular, the opposite insulating layer having the aforementioned preferred range of tensile modulus E(FOh) in a high-temperature measurement range is difficult to form from a cured product of a resin composition that does not contain a fiber substrate. One of the technical significances of the fiber substrate is that it enables the smooth acquisition of an insulating layer having such a preferred tensile modulus.

[0139] The tensile modulus E(FOh) and E(FOl) of the opposite insulating layer containing the fiber substrate can be measured by a tensile test in accordance with Japanese Industrial Standard JIS K7127.

[0140] The opposite insulating layer (opposite insulating layer (314, etc.)) containing the fiber substrate preferably has a low dielectric loss tangent Df. The range of the dielectric loss tangent Df of the opposite insulating layer containing the fiber substrate is preferably 0.0200 or less, more preferably 0.0180 or less, and even more preferably 0.0150 or less. There is no particular limit on the lower limit of the dielectric loss tangent Df, and it may be, for example, 0.0010 or more. The dielectric loss tangent Df of the opposite insulating layer containing the fiber substrate can be measured by the cavity resonance perturbation method under measurement conditions of a measurement frequency of 5.8 GHz and a measurement temperature of 23°C.

[0141] The thickness range per layer of the opposite insulating layer (opposite insulating layer (314, etc.)) containing a fiber substrate is preferably 5 μm or more, more preferably 10 μm or more, even more preferably 20 μm or more, preferably 100 μm or less, more preferably 80 μm or less, and even more preferably 60 μm or less. When the opposite build-up layer (300) has a plurality of opposite insulating layers containing a fiber substrate, the thickness of each of these opposite insulating layers may be different, but is preferred to be the same.

[0142] In the structure (10), a conductive layer may generally be formed on the surface of each insulating layer (chip-side insulating layer (211 to 214) and opposite-side insulating layer (311 to 314, etc.). Accordingly, the thickness of the insulating layer may be measured by using the surface of the core substrate side of the conductive layer (i.e., the interface between the insulating layer and the conductive layer formed on the insulating layer) as a reference. For example, as shown in FIG. 1, when the opposite-side insulating layer (313) and the opposite-side insulating layer (314) are bonded, it may be difficult to determine the interface between the two by optical observation. Even in this case, since a conductive layer (333) is generally formed on the opposite-side insulating layer (313), the location of the interface between the opposite-side insulating layer (313) and the opposite-side insulating layer (314) can be determined from the location of the interface between the opposite-side insulating layer (313) and the conductive layer (333). Therefore, the thickness of the opposite insulating layer (314) can be measured.

[0143] Among the plurality of opposite insulating layers (311 to 314) provided by the opposite build-up layer (300), the opposite insulating layers (311 to 313), other than the opposite insulating layer (314) containing the fiber substrate described above, do not contain fiber material. Typically, these opposite insulating layers (311 to 313) that do not contain fiber substrate only contain a cured product of a resin composition. The cured product of the resin composition included in the opposite insulating layers (311 to 313) that do not contain fiber substrate may be the same as or different from the cured product of the resin composition included in the opposite insulating layer (314) containing fiber substrate.

[0144] The opposite insulating layer that does not include a fiber substrate (opposite insulating layers (311 to 313, etc.)) generally has a greater coefficient of linear thermal expansion than the opposite insulating layer that includes a fiber substrate in the high-temperature measurement range. The range of the coefficient of linear thermal expansion CTE (ROh) of the opposite insulating layer that does not include a fiber substrate in the high-temperature measurement range is typically greater than 25 ppm / ℃, preferably 26 ppm / ℃ or more, more preferably 28 ppm / ℃ or more, preferably 100 ppm / ℃ or less, more preferably 80 ppm / ℃ or less, and even more preferably 60 ppm / ℃ or less. When the coefficient of linear thermal expansion CTE (ROh) of the opposite insulating layer that does not include a fiber substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the opposite side build-up layer (300) has a plurality of opposite side insulation layers that do not include fiber substrates, the coefficient of linear thermal expansion CTE (ROh) of each of these opposite side insulation layers may be different, but it is preferable that they be the same.

[0145] The coefficient of linear thermal expansion CTE(ROh) in the high-temperature measurement range of the opposite insulating layer (opposite insulating layer (311 to 313, etc.)) that does not contain fiber substrates and the coefficient of linear thermal expansion CTE(RCh) in the high-temperature measurement range of the chip insulating layer (chip insulating layer (211 to 214)) that does not contain fiber substrates may be different, but it is preferable that the difference is small. In one example, the range of the absolute value |CTE(ROh)-CTE(RCh)| of the difference "CTE(ROh)-CTE(RCh)" between the coefficient of linear thermal expansion CTE(ROh) in the high-temperature measurement range of the opposite insulating layer that does not contain fiber substrates and the coefficient of linear thermal expansion CTE(RCh) in the high-temperature measurement range of the chip insulating layer that does not contain fiber substrates is preferably 30 ppm / ℃ or less, more preferably 25 ppm / ℃ or less, even more preferably 20 ppm / ℃ or less, and even more preferably 10 ppm / ℃ or less. It is particularly desirable that the coefficient of linear thermal expansion CTE(ROh) in the high-temperature measurement range of the opposite insulating layer not containing fiber substrates and the coefficient of linear thermal expansion CTE(RCh) in the high-temperature measurement range of the chip-side insulating layer not containing fiber substrates are the same.

[0146] The range of the coefficient of linear thermal expansion CTE(ROl) in the low-temperature measurement range of the opposite insulating layer (opposite insulating layers (311 to 313, etc.)) that does not include a fiber substrate is preferably 40 ppm / °C or less, more preferably 30 ppm / °C or less, and even more preferably 25 ppm / °C or less. The lower limit is, for example, 5 ppm / °C or more, 10 ppm / °C or more, or 15 ppm / °C or more, and may be greater than 19 ppm / °C. When the coefficient of linear thermal expansion CTE(ROl) in the low-temperature measurement range of the opposite insulating layer that does not include a fiber substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the opposite build-up layer (300) has a plurality of opposite insulating layers that do not include a fiber substrate, the coefficient of linear thermal expansion CTE(ROl) of each of these opposite insulating layers may be different, but it is preferable that they be the same.

[0147] The coefficient of linear thermal expansion CTE(ROl) in the low-temperature measurement range of the opposite insulating layer (opposite insulating layer (311 to 313, etc.)) that does not contain fiber substrates and the coefficient of linear thermal expansion CTE(RCl) in the low-temperature measurement range of the chip insulating layer (chip insulating layer (211 to 214)) that does not contain fiber substrates may be different, but it is preferable that the difference be small. In one example, the range of the absolute value |CTE(ROl)-CTE(RCl)| of the difference “CTE(ROl)-CTE(RCl)” between the coefficient of linear thermal expansion CTE(ROl) in the low-temperature measurement range of the opposite insulating layer that does not contain fiber substrates and the coefficient of linear thermal expansion CTE(RCl) in the low-temperature measurement range of the chip insulating layer that does not contain fiber substrates is preferably 10 ppm / ℃ or less, more preferably 5 ppm / ℃ or less, even more preferably 3 ppm / ℃ or less, and particularly preferably 0 ppm / ℃. Therefore, it is particularly desirable that the linear thermal expansion coefficient of the opposite insulating layer not containing fiber substrates and the linear thermal expansion coefficient of the chip-side insulating layer not containing fiber substrates are the same.

[0148] The linear thermal expansion coefficient of the opposite insulating layer that does not include a fiber substrate can be measured using the same method as the measurement method for the linear thermal expansion coefficient of the opposite insulating layer that includes a fiber substrate.

[0149] The range of the glass transition temperature of the opposite insulating layer (opposite insulating layers (311 to 313, etc.)) that does not include a fiber substrate is preferably 250°C or lower, more preferably 200°C or lower, even more preferably 180°C or lower, preferably 140°C or higher, more preferably 150°C or higher, and even more preferably 160°C or higher. When the glass transition temperature of the opposite insulating layer that does not include a fiber substrate is within the above range, warping after mounting the semiconductor chip can be effectively suppressed. When the opposite build-up layer (300) has a plurality of opposite insulating layers that do not include a fiber substrate, the glass transition temperatures of each of these opposite insulating layers may be different, but it is preferable that they be the same.

[0150] The glass transition temperature of the opposite insulating layer (opposite insulating layer (311 to 313, etc.)) that does not contain fiber substrates and the glass transition temperature of the chip insulating layer (chip insulating layer (211 to 214)) that does not contain fiber substrates may be different, but it is preferable that the difference is small. In one example, the range of the absolute value of the difference between the glass transition temperature of the opposite insulating layer that does not contain fiber substrates and the glass transition temperature of the chip insulating layer that does not contain fiber substrates is preferably 80°C or less, more preferably 60°C or less, even more preferably 40°C or less, even more preferably 20°C or less, even more preferably 10°C or less, and particularly preferably 0°C. Accordingly, it is particularly preferable that the glass transition temperature of the opposite insulating layer that does not contain fiber substrates and the glass transition temperature of the chip insulating layer that does not contain fiber substrates are the same.

[0151] The glass transition temperature of the opposite insulating layer that does not contain a fiber substrate can be measured by the same measurement method as the glass transition temperature of the opposite insulating layer that contains a fiber substrate.

[0152] The opposite insulating layer that does not include a fiber substrate (opposite insulating layers (311 to 313, etc.)) generally has a smaller tensile modulus than the opposite insulating layer that includes a fiber substrate at a high temperature corresponding to the reflow temperature. The range of the tensile modulus E(ROh) of the opposite insulating layer that does not include a fiber substrate at 260°C is typically 0.1 GPa or more, preferably 0.2 GPa or more, more preferably 0.3 GPa or more, preferably less than 2 GPa, more preferably 1.5 GPa or less, and even more preferably 1 GPa or less. When the tensile modulus E(ROh) of the opposite insulating layer that does not include a fiber substrate is within the above range, warping after mounting the semiconductor chip can be effectively suppressed. When the opposite build-up layer (300) has a plurality of opposite insulating layers that do not include a fiber substrate, the tensile modulus E(ROh) of each of these opposite insulating layers may be different, but it is preferable that they be the same.

[0153] The tensile modulus E(ROh) at 260°C of the opposite insulating layer (opposite insulating layers (311 to 313, etc.)) that does not contain fiber substrates and the tensile modulus E(RCh) at 260°C of the chip-side insulating layer (chip-side insulating layers (211 to 214)) that does not contain fiber substrates may be different, but it is preferable that the difference be small. In one example, the range of the absolute value |E(ROh)-E(RCh)| of the difference "E(ROh)-E(RCh)" between the tensile modulus E(ROh) at 260°C of the opposite insulating layer that does not contain fiber substrates and the tensile modulus E(RCh) at 260°C of the chip-side insulating layer that does not contain fiber substrates is preferably 5 GPa or less, more preferably 3 GPa or less, even more preferably 1 GPa or less, and particularly preferably 0 GPa. Accordingly, the tensile modulus E(ROh) at 260°C of the opposite insulating layer that does not contain fiber substrates and fiber It is particularly desirable that the tensile modulus E(RCh) at 260°C of the chip-side insulating layer not containing the substrate is the same.

[0154] The range of the tensile modulus E(ROl) at 23°C of the opposite insulating layer (opposite insulating layers (311 to 313, etc.)) that does not contain a fiber substrate is preferably 5 GPa or more, more preferably 10 GPa or more, even more preferably 12 GPa or more, preferably 30 GPa or less, more preferably 20 GPa or less, and even more preferably 15 GPa or less. When the tensile modulus E(ROl) at 23°C of the opposite insulating layer that does not contain a fiber substrate is within the above range, warping after mounting the semiconductor chip can be effectively suppressed. When the opposite build-up layer (300) has a plurality of opposite insulating layers that do not contain a fiber substrate, the tensile modulus E(ROl) of each of these opposite insulating layers may be different, but is preferred to be the same.

[0155] The tensile modulus E(ROl) at 23°C of the opposite insulating layer (opposite insulating layer (311 to 313, etc.)) that does not contain fibers and the tensile modulus R(RCl) at 23°C of the chip insulating layer (chip insulating layer (211 to 214)) that does not contain fibers may be different, but the difference is preferably small. In one example, the range of the absolute value |E(ROl)-E(RCl)| of the difference “E(ROl)-E(RCl)” between the tensile modulus E(ROl) at 23°C of the opposite insulating layer that does not contain fibers and the tensile modulus E(RCl) at 23°C of the chip insulating layer that does not contain fibers is preferably 5 GPa or less, more preferably 3 GPa or less, even more preferably 1 GPa or less, and particularly preferably 0 GPa. Therefore, it is particularly desirable that the tensile modulus E(ROl) at 23°C of the opposite insulating layer not containing fiber substrate and the tensile modulus E(RCl) at 23°C of the chip-side insulating layer not containing fiber substrate are the same.

[0156] The tensile modulus of the opposite insulating layer that does not contain fiber substrates can be measured by the same measurement method as the tensile modulus of the opposite insulating layer that contains fiber substrates.

[0157] The opposite insulating layer that does not include a fiber substrate (opposite insulating layers (311 to 313, etc.)) preferably has a low dielectric loss tangent Df. The range of the dielectric loss tangent Df of the opposite insulating layer that does not include a fiber substrate may be the same as the range of the dielectric loss tangent Df of the opposite insulating layer that includes a fiber substrate. The dielectric loss tangent Df of the opposite insulating layer that does not include a fiber substrate can be measured by the same measurement method as the dielectric loss tangent Df of the opposite insulating layer that includes a fiber substrate.

[0158] The thickness range per layer of the opposite insulating layer (opposite insulating layers (311 to 313, etc.)) that does not include a fiber substrate may be the same as the thickness range per layer of the opposite insulating layer (opposite insulating layer (314, etc.)) that includes a fiber substrate. When the opposite build-up layer (300) has a plurality of opposite insulating layers that do not include a fiber substrate, the thickness of each of these opposite insulating layers may be different, but it is preferable that they be the same.

[0159] Holes (321 to 324) may be formed in part or all of the aforementioned opposite insulating layers (311 to 314). Examples of such holes (321 to 324) include via holes, through holes, etc. The location, dimensions, and shape of the holes (321 to 324) may be appropriately determined according to the design of the structure (10).

[0160] The opposite side build-up layer (300) may have a conductor layer (331 to 334). In this embodiment, an example is shown in which the conductor layer (331 to 334) is formed in the opposite side surface (311D, 312D, 313D, and 314D) of the opposite side insulating layer (311, 312, 313, and 314) opposite to the core substrate (100) and in the hole (321, 322, 323, and 324).

[0161] The conductor layer (331 to 334) is typically formed from a conductor material and thus includes a conductor material. As a conductor material, for example, one or more metals selected from the group consisting of gold, platinum, palladium, silver, copper, aluminum, cobalt, chromium, zinc, nickel, titanium, tungsten, iron, tin, and indium may be used. The conductor layer (331 to 334) may be a single metal layer or an alloy layer. As an alloy layer, for example, a layer formed from an alloy of two or more metals selected from the above group (for example, a nickel-chromium alloy, a copper-nickel alloy, and a copper-titanium alloy) may be used. Among these, in terms of the universality, cost, and ease of patterning of forming the conductor layer (331 to 334), a single metal layer of chromium, nickel, titanium, aluminum, zinc, gold, palladium, silver, or copper, or an alloy layer of nickel-chromium alloy, copper-nickel alloy, or copper-titanium alloy is preferred; a single metal layer of chromium, nickel, titanium, aluminum, zinc, gold, palladium, silver, or copper, or an alloy layer of nickel-chromium alloy is more preferred; and a single metal layer of copper is even more preferred.

[0162] The conductor layers (331 to 334) may have a single-layer structure, or a multi-layer structure including two or more single-metal layers or alloy layers made of different types of metals or alloys. When the conductor layers (331 to 334) have a multi-layer structure, the layer in contact with the insulating layer (311 to 314) on the core substrate (100) side of the conductor layers (331 to 334) is preferably a single-metal layer of chromium, zinc, or titanium, or an alloy layer of a nickel-chromium alloy.

[0163] The thickness of each layer of the conductor layer (331 to 334) depends on the design of the structure (10), but is preferably 3 μm to 35 μm, more preferably 5 μm to 30 μm.

[0164] The thickness range of the opposite side build-up layer (300) is preferably 60 μm or more, more preferably 80 μm or more, and even more preferably 100 μm or more. In the past, when such a thick build-up layer was used, there was a tendency for warping to occur, but according to the structure (10) of the present embodiment, even when such a thick opposite side build-up layer (300) is used, warping can be suppressed and the effects according to the present embodiment can be effectively utilized. The upper limit of the thickness of the opposite side build-up layer (300) is preferably 700 μm or less, more preferably 500 μm or less, and even more preferably 300 μm or less. When the upper limit of the thickness of the opposite side build-up layer (300) is within the above range, warping after mounting the semiconductor chip can be effectively suppressed.

[0165] Thickness T of the core substrate (100) 100 and the thickness T of the opposite side build-up layer (300) 300 The ratio of liver thickness T 300 / T 100The range is preferably 0.1 or more, more preferably 0.2 or more, and even more preferably 0.3 or more. Conventionally, there was a tendency for warping to occur when the build-up layer was thicker than the thickness of the core substrate, as indicated by the thickness ratio above. In contrast, according to the structure (10) according to the present embodiment, such a thickness ratio T 300 / T 100 Since bending can be suppressed even in this large case, the effect according to the present embodiment can be effectively utilized. Thickness ratio T 300 / T 100 The upper limit of is preferably 1.5 or less, more preferably 1.2 or less, and even more preferably 1.0 or less. Thickness ratio T 300 / T 100 If it is within the above range, warping after mounting the semiconductor chip can be effectively suppressed.

[0166] <Chip-side build-up layer (200)>

[0167] As described above, the chip-side build-up layer (200) comprises a plurality of chip-side insulating layers (211 to 214). The range of the number of chip-side insulating layers (211 to 214) provided by the chip-side build-up layer (200) is typically the same as the range of the number of opposite-side insulating layers (311 to 314) provided by the opposite-side build-up layer (300). The number of chip-side insulating layers (211 to 214) provided by the chip-side build-up layer (200) and the number of opposite-side insulating layers (311 to 314) provided by the opposite-side build-up layer (300) may differ within a range where bending can be suppressed, but it is preferable that they be the same.

[0168] A plurality of chip-side insulating layers (211 to 214) all comprise a cured product of a resin composition. The resin composition is typically a thermosetting resin composition, and therefore, the cured product may be a material obtained by thermosetting the resin composition. The cured product of the resin composition included in the chip-side insulating layers (211 to 214) may be the same as or different from the cured product of the resin composition included in the opposite-side insulating layers (311 to 314). Details of the resin composition will be described later.

[0169] A portion of the chip-side insulating layer provided by the chip-side build-up layer (200) may include a fiber substrate (not shown) in combination with the cured resin composition. The range of the fiber substrate included in the chip-side insulating layer may be the same as the range of the fiber substrate (400) included in the opposite-side insulating layer (314). Therefore, a fabric material may be used as the fiber substrate included in the chip-side insulating layer. Furthermore, the range of the number of threads per unit dimension, the range of the filament material, the range of the fabric weight, and the range of the thickness included in the fiber substrate included in the chip-side insulating layer may be the same as the ranges for the fiber substrate (400) included in the opposite-side insulating layer (314). Among these, it is preferable that the fiber substrate included in the chip-side insulating layer and the fiber substrate (400) included in the opposite-side insulating layer (314) are the same.

[0170] The number of chip-side insulating layers containing fiber substrates can be set to a range smaller than that of opposite-side insulating layers (opposite-side insulating layers (314, etc.)) containing fiber substrates. Specifically, the number of chip-side insulating layers containing fiber substrates is preferably 2 or less, and more preferably 1 or less. When the number of chip-side insulating layers containing fiber substrates is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0171] When the chip-side build-up layer (200) is provided with a chip-side insulating layer including a fiber substrate, it is preferable that the chip-side insulating layer including the fiber substrate be provided at the position closest to the core substrate (100). Accordingly, it is preferable that the first chip-side insulating layer (211), counting from the core substrate (100) side, includes a fiber substrate. In this case, warping after mounting the semiconductor chip can be effectively suppressed.

[0172] The range of the coefficient of linear thermal expansion CTE (FCh) in the high-temperature measurement range of the chip-side insulating layer (not shown in FIG. 1) containing a fiber substrate may be the same as the range of the coefficient of linear thermal expansion CTE (FOh) in the high-temperature measurement range of the opposite-side insulating layer (opposite-side insulating layer (314, etc.)) containing a fiber substrate. When the coefficient of linear thermal expansion CTE (FCh) of the chip-side insulating layer containing a fiber substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the chip-side build-up layer (200) has a plurality of chip-side insulating layers containing a fiber substrate, the coefficient of linear thermal expansion CTE (FCh) of each of these chip-side insulating layers may be different, but it is preferable that they be the same.

[0173] Preferably, the coefficient of linear thermal expansion CTE (FCh) in the high-temperature measurement range of a chip-side insulating layer (not shown in FIG. 1) containing a fiber substrate is smaller than the coefficient of linear thermal expansion CTE (RCh) in the high-temperature measurement range of a chip-side insulating layer (211 to 214, etc.) that does not contain a fiber substrate. At this time, the range of the difference “CTE(RCh)-CTE(FCh)” between the coefficient of linear thermal expansion CTE (RCh) in the high-temperature measurement range of a chip-side insulating layer that does not contain a fiber substrate and the coefficient of linear thermal expansion CTE (FCh) in the high-temperature measurement range of a chip-side insulating layer containing a fiber substrate may be the same as the range of the difference “CTE(ROh)-CTE(FOh)” between the coefficient of linear thermal expansion CTE (ROh) in the high-temperature measurement range of an opposite-side insulating layer that does not contain a fiber substrate and the coefficient of linear thermal expansion CTE (FOh) in the high-temperature measurement range of an opposite-side insulating layer containing a fiber substrate. When the difference in the coefficient of linear thermal expansion “CTE(RCh)-CTE(FCh)” is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0174] Preferably, the coefficient of linear thermal expansion CTE(FCh) in the high-temperature measurement range of the chip-side insulating layer (not shown in FIG. 1) containing the fiber substrate is smaller than the coefficient of linear thermal expansion CTE(ROh) in the high-temperature measurement range of the opposite-side insulating layer (opposite-side insulating layers (311 to 313, etc.)) that does not contain the fiber substrate. At this time, the range of the difference “CTE(ROh)-CTE(FCh)” between the coefficient of linear thermal expansion CTE(ROh) in the high-temperature measurement range of the opposite-side insulating layer that does not contain the fiber substrate and the coefficient of linear thermal expansion CTE(FCh) in the high-temperature measurement range of the chip-side insulating layer containing the fiber substrate may be the same as the range of the difference “CTE(ROh)-CTE(FOh)” between the coefficient of linear thermal expansion CTE(ROh) in the high-temperature measurement range of the opposite-side insulating layer that does not contain the fiber substrate and the coefficient of linear thermal expansion CTE(FOh) in the high-temperature measurement range of the opposite-side insulating layer containing the fiber substrate. When the difference in the coefficient of linear thermal expansion “CTE(ROh)-CTE(FCh)” is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0175] The range of the coefficient of linear thermal expansion CTE (FCl) in the low-temperature measurement range of the chip-side insulating layer (not shown in FIG. 1) containing the fiber substrate may be the same as the range of the coefficient of linear thermal expansion CTE (FOl) in the low-temperature measurement range of the opposite-side insulating layer (opposite-side insulating layer (314), etc.) containing the fiber substrate. When the coefficient of linear thermal expansion CTE (FCl) of the chip-side insulating layer containing the fiber substrate is within the above range, warping after mounting the semiconductor chip can be effectively suppressed. When the chip-side build-up layer (200) has a plurality of chip-side insulating layers containing the fiber substrate, the coefficient of linear thermal expansion CTE (FCl) of each of these chip-side insulating layers may be different, but it is preferable that they be the same.

[0176] Preferably, the coefficient of linear thermal expansion CTE (FCl) in the low-temperature measurement range of a chip-side insulating layer (not shown in FIG. 1) containing a fiber substrate is close to the coefficient of linear thermal expansion CTE (RCl) in the low-temperature measurement range of a chip-side insulating layer (chip-side insulating layers (211 to 214, etc.)) not containing a fiber substrate. At this time, the range of the absolute value |CTE(RCl)-CTE(FCl)| of the difference “CTE(RCl)-CTE(FCl)” between the coefficient of linear thermal expansion CTE(RCl) in the low-temperature measurement range of the chip-side insulating layer not including the fiber substrate and the coefficient of linear thermal expansion CTE(FCl) in the low-temperature measurement range of the chip-side insulating layer including the fiber substrate may be the same as the range of the absolute value |CTE(ROl)-CTE(FOl)| of the difference “CTE(ROl)-CTE(FOl)” between the coefficient of linear thermal expansion CTE(ROl) in the low-temperature measurement range of the opposite-side insulating layer not including the fiber substrate and the coefficient of linear thermal expansion CTE(FOl) in the low-temperature measurement range of the opposite-side insulating layer including the fiber substrate. When the absolute value of the difference in the coefficients of linear thermal expansion |CTE(RCl)-CTE(FCl)| is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0177] Preferably, the coefficient of linear thermal expansion CTE (FCl) in the low-temperature measurement range of the chip-side insulating layer (not shown in FIG. 1) containing the fiber substrate is close to the coefficient of linear thermal expansion CTE (ROl) in the low-temperature measurement range of the opposite-side insulating layer (opposite-side insulating layers (311 to 313, etc.)) that does not contain the fiber substrate. At this time, the range of the absolute value |CTE(ROl)-CTE(FCl)| of the difference “CTE(ROl)-CTE(FCl)” between the coefficient of linear thermal expansion CTE(ROl) of the opposite insulating layer in the low-temperature measurement range not including the fiber substrate and the coefficient of linear thermal expansion CTE(FCl) of the chip-side insulating layer in the low-temperature measurement range including the fiber substrate may be the same as the range of the absolute value |CTE(ROl)-CTE(FOl)| of the difference “CTE(ROl)-CTE(FOl)” between the coefficient of linear thermal expansion CTE(ROl) of the opposite insulating layer in the low-temperature measurement range not including the fiber substrate and the coefficient of linear thermal expansion CTE(FOl) of the opposite insulating layer in the low-temperature measurement range including the fiber substrate. When the absolute value of the difference in the coefficients of linear thermal expansion |CTE(ROl)-CTE(FCl)| is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0178] The linear thermal expansion coefficient of the chip-side insulating layer containing the fiber substrate can be measured by the same method as the measurement method of the linear thermal expansion coefficient of the opposite-side insulating layer containing the fiber substrate.

[0179] The range of the glass transition temperature of a chip-side insulating layer (not schematically illustrated in FIG. 1) containing a fiber substrate may be the same as the range of the glass transition temperature of an opposite-side insulating layer (opposite-side insulating layer (314, etc.)) containing a fiber substrate. When the glass transition temperature of the chip-side insulating layer containing the fiber substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the chip-side build-up layer (200) comprises a plurality of chip-side insulating layers containing a fiber substrate, the glass transition temperatures of each of these chip-side insulating layers may be different, but are preferred to be the same.

[0180] The glass transition temperature of a chip-side insulating layer (not shown in FIG. 1) containing a fiber substrate is preferably close to the glass transition temperature of a chip-side insulating layer (chip-side insulating layers (211 to 214, etc.)) that does not contain a fiber substrate. At this time, the glass transition temperature of the chip-side insulating layer containing a fiber substrate may be higher, lower, or equal to the glass transition temperature of the chip-side insulating layer that does not contain a fiber substrate. The range of the absolute value of the difference between the glass transition temperature of the chip-side insulating layer containing a fiber substrate and the glass transition temperature of the chip-side insulating layer that does not contain a fiber substrate may be the same as the range of the absolute value of the difference between the glass transition temperature of the opposite-side insulating layer containing a fiber substrate and the glass transition temperature of the opposite-side insulating layer that does not contain a fiber substrate. When the absolute value of the difference in glass transition temperatures is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0181] In addition, the glass transition temperature of the chip-side insulating layer (not shown in FIG. 1) containing the fiber substrate is preferably close to the glass transition temperature of the opposite-side insulating layer (opposite-side insulating layers (311 to 313, etc.)) that does not contain the fiber substrate. At this time, the glass transition temperature of the chip-side insulating layer containing the fiber substrate may be higher, lower, or equal to the glass transition temperature of the opposite-side insulating layer that does not contain the fiber substrate. The range of the absolute value of the difference between the glass transition temperature of the chip-side insulating layer containing the fiber substrate and the glass transition temperature of the opposite-side insulating layer that does not contain the fiber substrate may be the same as the range of the absolute value of the difference between the glass transition temperature of the opposite-side insulating layer containing the fiber substrate and the glass transition temperature of the opposite-side insulating layer that does not contain the fiber substrate. When the absolute value of the difference in glass transition temperatures is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0182] The glass transition temperature of the chip-side insulating layer containing the fiber substrate can be measured by the same method as the measurement method of the glass transition temperature of the opposite-side insulating layer containing the fiber substrate.

[0183] The range of the tensile modulus E(FCh) at 260°C of the chip-side insulating layer (not shown in FIG. 1) containing a fiber substrate may be the same as the range of the tensile modulus E(FOh) at 260°C of the opposite-side insulating layer (opposite-side insulating layer (314, etc.)) containing a fiber substrate. When the tensile modulus E(FCh) of the chip-side insulating layer containing a fiber substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the chip-side build-up layer (200) has a plurality of chip-side insulating layers containing a fiber substrate, the tensile modulus E(FCh) of each of these chip-side insulating layers may be different, but it is preferable that they be the same.

[0184] Preferably, the tensile modulus E(FCh) at 260°C of a chip-side insulating layer (not shown in FIG. 1) containing a fiber substrate is greater than the tensile modulus E(RCh) at 260°C of a chip-side insulating layer (chip-side insulating layers (211 to 214, etc.)) not containing a fiber substrate. At this time, the range of the difference “E(FCh)-E(RCh)” between the tensile modulus E(FCh) at 260°C of a chip-side insulating layer containing a fiber substrate and the tensile modulus E(RCh) at 260°C of a chip-side insulating layer not containing a fiber substrate may be the same as the range of the difference “E(FOh)-E(ROh)” between the tensile modulus E(FOh) at 260°C of an opposite-side insulating layer containing a fiber substrate and the tensile modulus E(ROh) at 260°C of an opposite-side insulating layer not containing a fiber substrate. When the difference in tensile modulus “E(FCh)-E(RCh)” is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0185] Preferably, the tensile modulus E(FCh) at 260°C of the chip-side insulating layer (not shown in FIG. 1) containing the fiber substrate is greater than the tensile modulus E(ROh) at 260°C of the opposite-side insulating layer (opposite-side insulating layers (311 to 313, etc.)) not containing the fiber substrate. At this time, the range of the difference “E(FCh)-E(ROh)” between the tensile modulus E(FCh) at 260°C of the chip-side insulating layer containing the fiber substrate and the tensile modulus E(ROh) at 260°C of the opposite-side insulating layer not containing the fiber substrate may be the same as the range of the difference “E(FOh)-E(ROh)” between the tensile modulus E(FOh) at 260°C of the opposite-side insulating layer containing the fiber substrate and the tensile modulus E(ROh) at 260°C of the opposite-side insulating layer not containing the fiber substrate. When the difference in tensile modulus “E(FCh)-E(ROh)” is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0186] The range of tensile modulus E(FCl) at 23°C of a chip-side insulating layer (not schematically illustrated in FIG. 1) containing a fiber substrate may be the same as the range of tensile modulus E(FOl) at 23°C of an opposite-side insulating layer (opposite-side insulating layer (314, etc.)) containing a fiber substrate. When the tensile modulus E(FCl) of the chip-side insulating layer containing a fiber substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the chip-side build-up layer (200) comprises a plurality of chip-side insulating layers containing a fiber substrate, the tensile modulus E(FCl) of each of these chip-side insulating layers may be different, but it is preferable that they be the same.

[0187] Preferably, the tensile modulus E(FCl) at 23°C of a chip-side insulating layer (not shown in FIG. 1) containing a fiber substrate is greater than the tensile modulus E(RCl) at 23°C of a chip-side insulating layer (chip-side insulating layers (211 to 214, etc.)) not containing a fiber substrate. At this time, the range of the difference “E(FCl)-E(RCl)” between the tensile modulus E(FCl) at 23°C of a chip-side insulating layer containing a fiber substrate and the tensile modulus E(RCl) at 23°C of a chip-side insulating layer not containing a fiber substrate may be the same as the range of the difference “E(FOl)-E(ROl)” between the tensile modulus E(FOl) at 23°C of an opposite-side insulating layer containing a fiber substrate and the tensile modulus E(ROl) at 23°C of an opposite-side insulating layer not containing a fiber substrate. When the difference in tensile modulus “E(FCl)-E(RCl)” is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0188] Preferably, the tensile modulus E(FCl) at 23°C of the chip-side insulating layer (not shown in FIG. 1) containing the fiber substrate is greater than the tensile modulus E(ROl) at 23°C of the opposite-side insulating layer (opposite-side insulating layers (311 to 313, etc.)) not containing the fiber substrate. At this time, the range of the difference “E(FCl)-E(ROl)” between the tensile modulus E(FCl) at 23°C of the chip-side insulating layer containing the fiber substrate and the tensile modulus E(ROl) at 23°C of the opposite-side insulating layer not containing the fiber substrate may be the same as the range of the difference “E(FOl)-E(ROl)” between the tensile modulus E(FOl) at 23°C of the opposite-side insulating layer containing the fiber substrate and the tensile modulus E(ROl) at 23°C of the opposite-side insulating layer not containing the fiber substrate. When the difference in tensile modulus “E(FCl)-E(ROl)” is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0189] The tensile elastic modulus of the chip-side insulating layer containing the fiber substrate can be measured by the same measurement method as the tensile elastic modulus of the opposite-side insulating layer containing the fiber substrate.

[0190] It is preferable that the chip-side insulating layer containing the fiber substrate has a low dielectric loss tangent Df. The range of the dielectric loss tangent Df of the chip-side insulating layer containing the fiber substrate may be the same as the range of the dielectric loss tangent Df of the opposite-side insulating layer containing the fiber substrate. The dielectric loss tangent Df of the chip-side insulating layer containing the fiber substrate can be measured by the same measurement method as the dielectric loss tangent Df of the opposite-side insulating layer containing the fiber substrate.

[0191] The thickness range per layer of a chip-side insulating layer (not shown in FIG. 1) containing a fiber substrate may be the same as the thickness range per layer of an opposite-side insulating layer (opposite-side insulating layer (314, etc.)) containing a fiber substrate. When the chip-side build-up layer (200) has a plurality of chip-side insulating layers containing a fiber substrate, the thickness of each of these chip-side insulating layers may be different, but it is preferable that they be the same.

[0192] Among the plurality of chip-side insulating layers (211 to 214) provided by the chip-side build-up layer (200), the chip-side insulating layers (211 to 214) other than the chip-side insulating layer (not shown in FIG. 1) containing the fiber substrate described above do not contain the fiber substrate. Typically, these chip-side insulating layers (211 to 214) that do not contain the fiber substrate contain only the cured product of the resin composition. The cured product of the resin composition included in the chip-side insulating layers (211 to 214) that do not contain the fiber substrate may be the same as or different from the cured product of the resin composition included in the chip-side insulating layer containing the fiber substrate.

[0193] The range of the linear thermal expansion coefficient of the chip-side insulating layer (chip-side insulating layer (211 to 214, etc.)) that does not include fiber substrates may be the same as the range of the linear thermal expansion coefficient of the opposite-side insulating layer (opposite-side insulating layer (311 to 313, etc.)) that does not include fiber substrates. Accordingly, the range of the linear thermal expansion coefficient CTE (RCh) in the high-temperature measurement range of the chip-side insulating layer that does not include fiber substrates may be the same as the range of the linear thermal expansion coefficient CTE (ROh) in the high-temperature measurement range of the opposite-side insulating layer that does not include fiber substrates. In addition, the range of the linear thermal expansion coefficient CTE (RCl) in the low-temperature measurement range of the chip-side insulating layer that does not include fiber substrates may be the same as the range of the linear thermal expansion coefficient CTE (ROl) in the low-temperature measurement range of the opposite-side insulating layer that does not include fiber substrates. When the linear thermal expansion coefficients CTE(RCh) and CTE(RCl) of the chip-side insulating layer that does not include a fiber substrate are within the above range, warping after mounting the semiconductor chip can be effectively suppressed. When the chip-side build-up layer (200) has a plurality of chip-side insulating layers that do not include a fiber substrate, the linear thermal expansion coefficients CTE(RCh) and CTE(RCl) of each of these chip-side insulating layers may be different, but it is preferable that they be the same.

[0194] The linear thermal expansion coefficient of the chip-side insulating layer that does not contain fiber substrates can be measured by the same method as the measurement method for the linear thermal expansion coefficient of the opposite-side insulating layer that contains fiber substrates.

[0195] The range of the glass transition temperature of the chip-side insulating layer (chip-side insulating layer (211 to 214, etc.)) that does not include a fiber substrate may be the same as the range of the glass transition temperature of the opposite-side insulating layer (opposite-side insulating layer (311 to 313, etc.)) that does not include a fiber substrate. When the glass transition temperature of the chip-side insulating layer that does not include a fiber substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the chip-side build-up layer (200) has a plurality of chip-side insulating layers that do not include a fiber substrate, the glass transition temperatures of each of these chip-side insulating layers may be different, but it is preferable that they be the same.

[0196] The glass transition temperature of the chip-side insulating layer that does not contain a fiber substrate can be measured by the same measurement method as the glass transition temperature of the opposite-side insulating layer that contains a fiber substrate.

[0197] The range of tensile elasticity of the chip-side insulating layer (chip-side insulating layer (211 to 214, etc.)) that does not contain fiber substrates may be the same as the range of tensile elasticity of the opposite-side insulating layer (opposite-side insulating layer (311 to 313, etc.)) that does not contain fiber substrates. Accordingly, the range of tensile elasticity E(RCh) at 260°C of the chip-side insulating layer that does not contain fiber substrates may be the same as the range of tensile elasticity E(ROh) at 260°C of the opposite-side insulating layer that does not contain fiber substrates. In addition, the range of tensile elasticity E(RCl) at 23°C of the chip-side insulating layer that does not contain fiber substrates may be the same as the range of tensile elasticity E(ROl) at 23°C of the opposite-side insulating layer that does not contain fiber substrates. When the tensile elasticity E(RCh) and E(RCl) of the chip-side insulating layer that does not contain fiber substrates are within the above ranges, warping after mounting of the semiconductor chip can be effectively suppressed. When the chip-side build-up layer (200) comprises a plurality of chip-side insulating layers that do not include a fiber substrate, the tensile elastic modulus E(RCh) and E(RCl) of each of these chip-side insulating layers may be different, but it is preferable that they be the same.

[0198] The tensile modulus of the chip-side insulating layer that does not contain fiber substrates can be measured by the same measurement method as the tensile modulus of the opposite-side insulating layer that contains fiber substrates.

[0199] It is preferable that the chip-side insulating layer (chip-side insulating layer (211 to 214, etc.)) that does not include a fiber substrate has a low dielectric loss tangent Df. The range of the dielectric loss tangent Df of the chip-side insulating layer that does not include a fiber substrate may be the same as the range of the dielectric loss tangent Df of the opposite-side insulating layer that includes a fiber substrate. The dielectric loss tangent Df of the chip-side insulating layer that does not include a fiber substrate can be measured by the same measurement method as the dielectric loss tangent Df of the opposite-side insulating layer that includes a fiber substrate.

[0200] The thickness range per layer of the chip-side insulating layer (chip-side insulating layer (211 to 214, etc.)) that does not include a fiber substrate may be the same as the thickness range per layer of the opposite-side insulating layer (opposite-side insulating layer (314, etc.)) that includes a fiber substrate. When the chip-side build-up layer (200) has a plurality of chip-side insulating layers that do not include a fiber substrate, the thickness of each of these chip-side insulating layers may be different, but it is preferable that they be the same.

[0201] Holes (221 to 224) may be formed in part or all of the chip-side insulating layers (211 to 214) described above. Examples of such holes (221 to 224) include via holes, through holes, etc. The location, dimensions, and shape of the holes (221 to 224) may be appropriately determined according to the design of the structure (10).

[0202] The chip-side build-up layer (200) may have conductive layers (231 to 234). In this embodiment, an example is shown in which the conductive layers (231 to 234) are formed on the surface (211U, 212U, 213U and 214U) opposite to the core substrate (100) of the chip-side insulating layer (211, 212, 213 and 214) and within the holes (221, 222, 223 and 224).

[0203] The conductor layers (231 to 234) are typically formed by a conductor material in the same way as the conductor layers (331 to 334) of the opposite side build-up layer (300). Accordingly, examples of conductor materials, layer structure, and thickness of the conductor layers (231 to 234) of the chip-side build-up layer (200) may be the same as the conductor layers (331 to 334) of the opposite side build-up layer (300).

[0204] The thickness range of the chip-side build-up layer (200) may be the same as the thickness range of the opposite-side build-up layer (300) for the same reason as the opposite-side build-up layer (300). The thickness of the chip-side build-up layer (200) and the thickness of the opposite-side build-up layer (300) may differ, but it is preferable that the difference be smaller. The range of the difference between the thickness of the chip-side build-up layer (200) and the thickness of the opposite-side build-up layer (300) is preferably 10 μm or less, more preferably 5 μm or less. Therefore, it is particularly preferable that the thickness of the chip-side build-up layer (200) and the thickness of the opposite-side build-up layer (300) are the same.

[0205] Thickness T of the core substrate (100) 100 and the thickness T of the chip-side build-up layer (200) 200 The thickness ratio T 200 / T 100 The range is the thickness T of the core substrate (100). 100 and the thickness T of the opposite side build-up layer (300) 300 The thickness ratio T 300 / T 100 For the same reason as, the above thickness ratio T 300 / T 100 It can be the same as the range of.

[0206] Method of manufacturing a structure

[0207] The structure (10) according to the present embodiment is,

[0208] A plurality of processes (i) for forming chip-side insulating layers (211 to 214) on the chip-side surface (first side) (100U) of the core substrate (100), and

[0209] A plurality of processes (ii) for forming an opposite insulating layer (311 to 314) on the opposite side (second side) (100D) of the core substrate (100)

[0210] It can be manufactured by a manufacturing method including

[0211] Typically, one layer among a plurality of chip-side insulating layers (211 to 214) can be formed by one process (i). Accordingly, a chip-side build-up layer (200) having a plurality of chip-side insulating layers (211 to 214) can be formed by a method including repeating this process (i) a plurality of times.

[0212] In addition, typically, one layer among a plurality of opposite side insulating layers (311 to 314) can be formed by one process (ii). Accordingly, by a method including repeating this process (ii) multiple times, an opposite side build-up layer (300) having a plurality of opposite side insulating layers (311 to 314) can be formed.

[0213] The structure (10) comprises an insulating layer (314) comprising a fiber substrate (400) and insulating layers (211 to 214 and 311 to 313) not comprising a fiber substrate, in combination as described above. Accordingly, the process (ii) includes a process of forming an opposite insulating layer (314) comprising a fiber substrate (400) and a process of forming an opposite insulating layer (311 to 313) not comprising a fiber substrate. Additionally, the process (i) includes a process of forming a chip-side insulating layer (211 to 214) not comprising a fiber substrate. Additionally, the process (i) may include a process of forming a chip-side insulating layer (not shown in FIG. 1) comprising a fiber substrate.

[0214] An insulating layer containing a fiber substrate (opposite insulating layer (314, etc.)) is preferably formed by a method comprising laminating a fiber-containing sheet (a1) having a prepreg layer (a11). This method typically comprises laminating the fiber-containing sheet (a1) and curing the fiber-containing sheet (a1). Additionally, an insulating layer not containing a fiber substrate (chip-side insulating layer (211 to 214) and opposite insulating layer (311 to 313, etc.)) is preferably formed by a method comprising laminating a resin composition layer (b1). This method typically comprises laminating the resin composition layer (b1) and curing the resin composition layer (b1).

[0215] Below, each of these desirable methods will be explained.

[0216] (Method for forming an insulating layer including a fiber substrate)

[0217] First, a method for forming an insulating layer including a fiber substrate is described. It is preferable that the insulating layer including the fiber substrate be formed by a method comprising laminating a fiber-containing sheet (a1) having a prepreg layer (a11) as described above.

[0218] (a11) The prepreg layer represents a layer comprising a fiber substrate and a resin composition impregnated in the fiber substrate. Hereinafter, the resin composition included in the (a11) prepreg layer may be referred to as the "first resin composition." The (a11) prepreg layer may comprise only the fiber substrate and the first resin composition. The fiber substrate is as described above. Typically, since the first resin composition has thermosetting properties, an insulating layer including the fiber substrate can be formed by curing the first resin composition. For example, an insulating layer including the fiber substrate can be formed on the core substrate (100) by a method comprising laminating a (a1) fiber-containing sheet on the core substrate (100) and curing the first resin composition included in the (a11) prepreg layer of the (a1) fiber-containing sheet. In addition, for example, an insulating layer (n+1th insulating layer) containing a fiber substrate can be formed on the insulating layer (nth insulating layer) by a method comprising laminating a fiber-containing sheet (a1) on an insulating layer (nth insulating layer) and curing a first resin composition included in a prepreg layer (a11) of the fiber-containing sheet (a1). The above “n” represents a natural number.

[0219] (a11) The range of the lowest melt viscosity of the prepreg layer in the temperature range from 100°C to 140°C is preferably 100 poise or more, more preferably 200 poise or more, even more preferably 400 poise or more, preferably 10000 poise or less, more preferably 7000 poise or less, and even more preferably 4000 poise or less. Typically, the lowest melt viscosity of the prepreg layer in the temperature range from 100°C to 140°C corresponds to the lowest melt viscosity of the first resin composition included in the prepreg layer of (a11) in the temperature range from 100°C to 140°C. When the prepreg layer of (a11) has the lowest melt viscosity of the above range in the temperature range from 100°C to 140°C, the conductor layer of the surface bonded to (a11) can be well embedded by the prepreg layer of (a11).

[0220] (a11) When the temperature of the prepreg layer is increased, the melt viscosity of the prepreg layer (a11) generally decreases as the temperature increases, and after reaching the lowest value at a certain temperature, it may increase. At this time, the temperature at which the melt viscosity of the prepreg layer (a11) exhibits the lowest value is preferably in a specific temperature range lower than conventional. Specifically, the temperature range at which the melt viscosity of the prepreg layer (a11) exhibits the lowest value is preferably 100°C or higher and 150°C or lower. When the temperature at which the melt viscosity of the prepreg layer (a11) exhibits the lowest value is within the above range, the lamination of the fiber-containing sheet (a1) having the prepreg layer (a11) can be performed well.

[0221] (a11) The melt viscosity of the prepreg layer can be measured using a dynamic viscoelasticity measuring device. The measurement can be performed by increasing the temperature in a temperature range from 60°C to 200°C and measuring the dynamic viscoelasticity of the sample for measurement. The measurement conditions may be a heating rate of 5°C / min, a measurement temperature interval of 2.5°C, a frequency of 1 Hz, and a strain of 1 deg. From the measured results, the lowest melt viscosity in a temperature range from 100°C to 140°C, and the temperature at which the melt viscosity shows the lowest value among the measurement temperature ranges can be obtained.

[0222] (a11) The thickness of the prepreg layer is preferably 10 μm or more, more preferably 15 μm or more, even more preferably 20 μm or more, preferably 100 μm or less, more preferably 90 μm or less, even more preferably 80 μm or less, even more preferably 70 μm or less.

[0223] (a1) The fiber-containing sheet may have only (a11) prepreg layer, but may also have (a12) a cured layer formed on one side of (a11) prepreg layer in combination with (a11) prepreg layer. Hereinafter, this (a12) cured layer may be referred to as the “(a12) primer cured layer.” For example, (a1) the fiber-containing sheet may have only (a11) prepreg layer and (a12) primer cured layer.

[0224] (a12) The primer cured layer comprises a cured product obtained by curing a thermosetting resin composition, and may comprise only said cured product. Hereinafter, the thermosetting resin composition that serves as the raw material for the cured product included in the (a12) primer cured layer may be referred to as the “second resin composition.” Typically, the (a12) primer cured layer does not include a fiber substrate. Since the (a12) primer cured layer includes a cured product of the second resin composition, it typically has high hardness. Therefore, in the process of laminating the (a1) fiber-containing sheet, when pressure is applied to the (a1) fiber-containing sheet, it is possible to suppress the formation of irregularities reflecting the shape of the fiber substrate on the surface of the (a1) fiber-containing sheet due to the pressure, or the exposure of the fiber substrate on the surface of the (a1) fiber-containing sheet.

[0225] (a12) In the primer cured layer, the second resin composition may be completely cured, but it does not necessarily have to be completely cured. The second resin composition may be cured to the extent that, in the process of laminating the (a1) fiber-containing sheet, irregularities reflecting the shape of the fiber substrate are formed on the surface of the (a1) fiber-containing sheet, or the fiber substrate is exposed on the surface of the (a1) fiber-containing sheet. Specifically, in the process of laminating the (a1) fiber-containing sheet, it is preferable that the curing of the second resin composition is advanced to the extent that the cured product of the second resin composition included in the (a12) primer cured layer has low fluidity. Furthermore, in the process of laminating the (a1) fiber-containing sheet, it is more preferable that the curing of the second resin composition is advanced to the extent that the cured product of the second resin composition included in the (a12) primer cured layer does not have fluidity.

[0226] (a12) The degree of curing of the second resin composition in the primer cured layer can be expressed, for example, as the maximum extrusion length. This maximum extrusion length can be measured by a test specimen having the (a12) primer cured layer and a polyethylene terephthalate film (hereinafter referred to as "PET film") having the same area and planar shape as the (a12) primer cured layer. Specifically, in the test specimen for measuring the maximum extrusion length, a rectangular test specimen is used having a PET film with dimensions of 12 cm in length × 15 cm in width and a (a12) primer cured layer with dimensions of 12 cm in length × 15 cm in width formed on the entire surface of the PET film. This test specimen is laminated onto an FR4 substrate with dimensions of 20 cm on each side and a thickness of 0.8 mm. This lamination is performed using a vacuum laminator so that the (a12) primer cured layer is bonded to an FR4 substrate. More specifically, the lamination is performed by vacuum suctioning for 30 seconds at a temperature of 80°C, followed by pressing for 60 seconds with a heat-resistant rubber interposed under conditions of a temperature of 80°C and a pressure of 7.0 kgf / ㎠. Afterward, a smoothing treatment is further performed under atmospheric pressure using a SUS end plate, by pressing for 90 seconds under conditions of a temperature of 80°C and a pressure of 5.5 kgf / ㎠. After performing this test, the maximum length of the (a12) primer cured layer seeping out from the end of the PET film is measured as the "maximum eruption length." The maximum eruption length of the (a12) primer cured layer is preferably 0.3 mm or less, more preferably 0.2 mm or less, even more preferably 0.1 mm or less, and particularly preferably 0 mm.

[0227] In addition, the degree of curing of the second resin composition in the (a12) primer cured layer can be indicated, for example, by the glass transition temperature of the cured product of the second resin composition included in the (a12) primer cured layer. The range of the glass transition temperature of the cured product of the second resin composition is preferably 80°C or higher, more preferably 140°C or higher, even more preferably 150°C or higher, and even more preferably 160°C or higher. A cured product having such a glass transition temperature may not have substantially fluidity under temperature conditions during lamination (e.g., 70°C to 140°C). The upper limit of the glass transition temperature of the cured product of the second resin composition is preferably 300°C or lower, more preferably 250°C or lower, even more preferably 200°C or lower, and even more preferably 180°C or lower. The glass transition temperature of the cured product of the second resin composition can be measured by the same measurement method as the glass transition temperature of the opposite insulating layer containing the fiber substrate.

[0228] (a12) The thickness of the primer cured layer is preferably 1 μm or more, more preferably 2 μm or more, even more preferably 3 μm or more, preferably 30 μm or less, more preferably 20 μm or less, even more preferably 10 μm or less.

[0229] Typically, when a cured sample is obtained by curing a fiber-containing sheet (a1), the cured sample may have the same composition as an insulating layer containing fiber substrates. Therefore, when a CTE measurement test is performed to measure the coefficient of linear thermal expansion of the cured sample of the fiber-containing sheet (a1), the cured sample may have the same coefficient of linear thermal expansion as the coefficient of linear thermal expansion of the insulating layer formed using the fiber-containing sheet (a1). In the following description, "cured sample of the fiber-containing sheet (a1)" refers, unless otherwise specified, to a cured sample obtained by curing the fiber-containing sheet (a1) under the same curing conditions as the curing conditions of the fiber-containing sheet (a1) in the method for manufacturing a structure. As an example, the condition of 200°C for 90 minutes may be adopted as this curing condition.

[0230] Accordingly, it is preferable that the range of the linear thermal expansion coefficient of the cured sample of the fiber-containing sheet (a1) for forming the opposite insulating layer containing the fiber substrate be the same as the range of the linear thermal expansion coefficient of the opposite insulating layer containing the fiber substrate described above. For example, it is preferable that the range of the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of the fiber-containing sheet (a1) for forming the opposite insulating layer containing the fiber substrate be the same as the range of the linear thermal expansion coefficient CTE(FOh) in the high-temperature measurement range of the opposite insulating layer containing the fiber substrate described above. Furthermore, for example, it is preferable that the range of the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the fiber-containing sheet (a1) for forming the opposite insulating layer containing the fiber substrate be the same as the range of the linear thermal expansion coefficient CTE(FOl) in the low-temperature measurement range of the opposite insulating layer containing the fiber substrate described above. In addition, for example, the range of the difference between the coefficient of linear thermal expansion in the high-temperature measurement range of a cured sample of a fiber-containing sheet for forming an opposite insulating layer including a fiber substrate (a1) and the coefficient of linear thermal expansion in the low-temperature measurement range of said cured sample (coefficient of linear thermal expansion in the high-temperature measurement range - coefficient of linear thermal expansion in the low-temperature measurement range) is preferably the same as the range of the difference “CTE(FOh)-CTE(FOl)” between the coefficient of linear thermal expansion CTE(FOh) in the high-temperature measurement range and the coefficient of linear thermal expansion CTE(FOl) in the low-temperature measurement range of the opposite insulating layer including the fiber substrate described above.

[0231] In addition, the range of the linear thermal expansion coefficient of the cured sample of the fiber-containing sheet (a1) for forming a chip-side insulating layer including a fiber substrate is preferably the same as the range of the linear thermal expansion coefficient of the chip-side insulating layer including the fiber substrate described above. Accordingly, for example, the range of the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of the fiber-containing sheet (a1) for forming a chip-side insulating layer including a fiber substrate is preferably the same as the range of the linear thermal expansion coefficient CTE(FCh) in the high-temperature measurement range of the chip-side insulating layer including the fiber substrate described above. In addition, for example, the range of the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the fiber-containing sheet (a1) for forming a chip-side insulating layer including a fiber substrate is preferably the same as the range of the linear thermal expansion coefficient CTE(FCl) in the low-temperature measurement range of the chip-side insulating layer including the fiber substrate described above.

[0232] In addition, the range of difference between the linear thermal expansion coefficient of the cured sample of the fiber-containing sheet (a1) for forming the opposite side insulating layer including the fiber substrate and the linear thermal expansion coefficient of the cured sample of the fiber-containing sheet (a1) for forming the chip-side insulating layer including the fiber substrate is preferably the same as the range of difference between the linear thermal expansion coefficient of the opposite side insulating layer including the fiber substrate and the linear thermal expansion coefficient of the chip-side insulating layer including the fiber substrate described above. Accordingly, for example, the range of the absolute value of the difference between the coefficient of linear thermal expansion in the high-temperature measurement range of a cured sample of a fiber-containing sheet (a1) for forming an opposite insulating layer including a fiber substrate and the coefficient of linear thermal expansion in the high-temperature measurement range of a cured sample of a fiber-containing sheet (a1) for forming a chip-side insulating layer including a fiber substrate is preferably the same as the range of the absolute value |CTE(FOh)-CTE(FCh)| of the difference “CTE(FOh)-CTE(FCh)” between the coefficient of linear thermal expansion CTE(FOh) in the high-temperature measurement range of the opposite insulating layer including the fiber substrate and the coefficient of linear thermal expansion CTE(FCh) in the high-temperature measurement range of the chip-side insulating layer including the fiber substrate described above. In addition, for example, the range of the absolute value of the difference between the linear thermal expansion coefficient of a cured sample of (a1) fiber-containing sheet for forming an opposite side insulating layer including a fiber substrate in a low-temperature measurement range and the linear thermal expansion coefficient of a cured sample of (a1) fiber-containing sheet for forming a chip-side insulating layer including a fiber substrate in a low-temperature measurement range is preferably the same as the range of the absolute value of "CTE(FOl)-CTE(FCl)" between the linear thermal expansion coefficient CTE(FOl) of the opposite side insulating layer including a fiber substrate in a low-temperature measurement range and the linear thermal expansion coefficient CTE(FCl) of the chip-side insulating layer including a fiber substrate in a low-temperature measurement range |CTE(FOl)-CTE(FCl)|.

[0233] In addition, typically, when a cured sample is obtained by curing the resin composition layer (b1), the cured sample may have the same composition as an insulating layer that does not contain fiber substrates. Therefore, when a CTE measurement test is performed to measure the coefficient of linear thermal expansion of the cured sample of the resin composition layer (b1), the cured sample may have the same coefficient of linear thermal expansion as the coefficient of linear thermal expansion of an insulating layer that does not contain fiber substrates formed using the resin composition layer (b1). In the following description, "cured sample of the resin composition layer (b1)" refers, unless otherwise specified, to a cured sample obtained by curing the resin composition layer (b1) under the same curing conditions as the curing conditions of the resin composition layer (b1) in the method for manufacturing a structure. In one example, the condition of 200°C for 90 minutes may be adopted as this curing condition.

[0234] Accordingly, it is preferable that the coefficient of linear thermal expansion in the high-temperature measurement range of the cured sample of the fiber-containing sheet (a1) for forming the opposite insulating layer containing the fiber substrate is smaller than the coefficient of linear thermal expansion in the high-temperature measurement range of the cured sample of the resin composition layer (b1) for forming the opposite insulating layer not containing the fiber substrate. At this time, the range of the difference between the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of the resin composition layer (b1) for forming the opposite insulating layer that does not include the fiber substrate and the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of the fiber-containing sheet (a1) for forming the opposite insulating layer that includes the fiber substrate (linear thermal expansion coefficient of the cured sample of the resin composition layer (b1) - linear thermal expansion coefficient of the cured sample of the fiber-containing sheet (a1)) is preferably the same as the range of “CTE(ROh) - CTE(FOh)”, which is the difference between the linear thermal expansion coefficient CTE(ROh) in the high-temperature measurement range of the opposite insulating layer that does not include the fiber substrate and the linear thermal expansion coefficient CTE(FOh) in the high-temperature measurement range of the opposite insulating layer that includes the fiber substrate.

[0235] In addition, it is preferable that the coefficient of linear thermal expansion in the high-temperature measurement range of the cured sample of the fiber-containing sheet (a1) for forming the opposite side insulating layer containing the fiber substrate is smaller than the coefficient of linear thermal expansion in the high-temperature measurement range of the cured sample of the resin composition layer (b1) for forming the chip side insulating layer not containing the fiber substrate. At this time, the range of the difference between the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of the resin composition layer (b1) for forming the chip-side insulation layer not including the fiber substrate and the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of the fiber-containing sheet (a1) for forming the opposite-side insulation layer including the fiber substrate (linear thermal expansion coefficient of the cured sample of the resin composition layer (b1) - linear thermal expansion coefficient of the cured sample of the fiber-containing sheet (a1)) is preferably the same as the range of “CTE(RCh) - CTE(FOh)”, the difference between the linear thermal expansion coefficient CTE(RCh) in the high-temperature measurement range of the chip-side insulation layer not including the fiber substrate and the linear thermal expansion coefficient CTE(FOh) in the high-temperature measurement range of the opposite-side insulation layer including the fiber substrate.

[0236] In addition, it is preferable that the coefficient of linear thermal expansion in the low-temperature measurement range of the cured sample of the fiber-containing sheet (a1) for forming the opposite insulating layer containing the fiber substrate is close to the coefficient of linear thermal expansion in the low-temperature measurement range of the cured sample of the resin composition layer (b1) for forming the opposite insulating layer not containing the fiber substrate. At this time, the range of the absolute value of the difference between the coefficient of linear thermal expansion in the low-temperature measurement range of the cured sample of the resin composition layer (b1) for forming the opposite insulating layer that does not include the fiber substrate and the coefficient of linear thermal expansion in the low-temperature measurement range of the cured sample of the fiber-containing sheet (a1) for forming the opposite insulating layer that includes the fiber substrate is preferably the same as the range of the absolute value |CTE(ROl)-CTE(FOl)| of the difference “CTE(ROl)-CTE(FOl)” between the coefficient of linear thermal expansion CTE(ROl) in the low-temperature measurement range of the opposite insulating layer that does not include the fiber substrate and the coefficient of linear thermal expansion CTE(FOl) in the low-temperature measurement range of the opposite insulating layer that includes the fiber substrate.

[0237] In addition, it is preferable that the coefficient of linear thermal expansion in the low-temperature measurement range of the cured sample of the fiber-containing sheet (a1) for forming the opposite side insulating layer containing the fiber substrate is close to the coefficient of linear thermal expansion in the low-temperature measurement range of the cured sample of the resin composition layer (b1) for forming the chip side insulating layer not containing the fiber substrate. At this time, the range of the absolute value of the difference between the coefficient of linear thermal expansion in the low-temperature measurement range of the cured sample of the resin composition layer (b1) for forming the chip-side insulating layer not including the fiber substrate and the coefficient of linear thermal expansion in the low-temperature measurement range of the cured sample of the fiber-containing sheet (a1) for forming the opposite-side insulating layer including the fiber substrate is preferably the same as the range of the absolute value |CTE(RCl)-CTE(FOl)| of the difference “CTE(RCl)-CTE(FOl)” between the coefficient of linear thermal expansion CTE(RCl) in the low-temperature measurement range of the chip-side insulating layer not including the fiber substrate and the coefficient of linear thermal expansion CTE(FOl) in the low-temperature measurement range of the opposite-side insulating layer including the fiber substrate.

[0238] In addition, it is preferable that the coefficient of linear thermal expansion in the high-temperature measurement range of the cured sample of (a1) fiber-containing sheet for forming a chip-side insulating layer including fiber substrate is smaller than the coefficient of linear thermal expansion in the high-temperature measurement range of the cured sample of (b1) resin composition layer for forming a chip-side insulating layer not including fiber substrate. At this time, the range of the difference between the linear thermal expansion coefficient of the cured sample of the resin composition layer (b1) for forming a chip-side insulation layer not including a fiber substrate and the linear thermal expansion coefficient of the cured sample of the fiber-containing sheet (a1) for forming a chip-side insulation layer including a fiber substrate (linear thermal expansion coefficient of the cured sample of the resin composition layer (b1) - linear thermal expansion coefficient of the cured sample of the fiber-containing sheet (a1)) is preferably the same as the range of the difference “CTE(RCh) - CTE(FCh)” between the linear thermal expansion coefficient CTE(RCh) in the high-temperature measurement range of the chip-side insulation layer not including a fiber substrate and the linear thermal expansion coefficient CTE(FCh) in the high-temperature measurement range of the chip-side insulation layer including a fiber substrate.

[0239] In addition, it is preferable that the coefficient of linear thermal expansion in the high-temperature measurement range of the cured sample of the fiber-containing sheet (a1) for forming the chip-side insulating layer containing the fiber substrate is smaller than the coefficient of linear thermal expansion in the high-temperature measurement range of the cured sample of the resin composition layer (b1) for forming the opposite-side insulating layer not containing the fiber substrate. The range of the difference between the coefficient of linear thermal expansion in the high-temperature measurement range of the cured sample of the resin composition layer (b1) for forming the opposite side insulation layer that does not include a fiber substrate and the coefficient of linear thermal expansion in the high-temperature measurement range of the cured sample of the fiber-containing sheet (a1) for forming the chip-side insulation layer that includes a fiber substrate (coefficient of linear thermal expansion of the cured sample of the resin composition layer (b1) - coefficient of linear thermal expansion of the cured sample of the fiber-containing sheet (a1)) is preferably the same as the range of the difference “CTE(ROh) - CTE(FCh)” between the coefficient of linear thermal expansion CTE(ROh) in the high-temperature measurement range of the opposite side insulation layer that does not include a fiber substrate and the coefficient of linear thermal expansion CTE(FCh) in the high-temperature measurement range of the chip-side insulation layer that includes a fiber substrate.

[0240] In addition, the coefficient of linear thermal expansion in the low-temperature measurement range of the cured sample of (a1) a fiber-containing sheet for forming a chip-side insulating layer including a fiber substrate is preferably close to the coefficient of linear thermal expansion in the low-temperature measurement range of the cured sample of (b1) a resin composition layer for forming a chip-side insulating layer not including a fiber substrate. At this time, the range of the absolute value of the difference between the coefficient of linear thermal expansion in the low-temperature measurement range of the cured sample of the resin composition layer (b1) for forming a chip-side insulating layer that does not include a fiber substrate and the coefficient of linear thermal expansion in the low-temperature measurement range of the cured sample of the fiber-containing sheet (a1) for forming a chip-side insulating layer that includes a fiber substrate is preferably the same as the range of the absolute value |CTE(RCl)-CTE(FCl)| of the difference “CTE(RCl)-CTE(FCl)” between the coefficient of linear thermal expansion CTE(RCl) in the low-temperature measurement range of the chip-side insulating layer that does not include a fiber substrate and the coefficient of linear thermal expansion CTE(FCl) in the low-temperature measurement range of the chip-side insulating layer that includes a fiber substrate.

[0241] In addition, it is preferable that the coefficient of linear thermal expansion in the low-temperature measurement range of the cured sample of the fiber-containing sheet (a1) for forming the chip-side insulating layer containing the fiber substrate is close to the coefficient of linear thermal expansion in the low-temperature measurement range of the cured sample of the resin composition layer (b1) for forming the opposite-side insulating layer not containing the fiber substrate. At this time, the range of the absolute value of the difference between the coefficient of linear thermal expansion in the low-temperature measurement range of the cured sample of the resin composition layer (b1) for forming the opposite side insulation layer not including the fiber substrate and the coefficient of linear thermal expansion in the low-temperature measurement range of the cured sample of the fiber-containing sheet (a1) for forming the chip side insulation layer including the fiber substrate is preferably the same as the range of the absolute value |CTE(ROl)-CTE(FCl)| of the difference “CTE(ROl)-CTE(FCl)” between the coefficient of linear thermal expansion CTE(ROl) in the low-temperature measurement range of the opposite side insulation layer not including the fiber substrate and the coefficient of linear thermal expansion CTE(FCl) in the low-temperature measurement range of the chip side insulation layer including the fiber substrate.

[0242] (a1) If the coefficient of linear thermal expansion of the cured sample of the fiber-containing sheet satisfies the above desirable requirements, warping after mounting of the semiconductor chip can be effectively suppressed.

[0243] (a1) The linear thermal expansion coefficient of a cured sample of a fiber-containing sheet can be measured by the same measurement method as the linear thermal expansion coefficient of an insulating layer on the opposite side containing fiber substrate.

[0244] In addition, when a Tg measurement test is performed to measure the glass transition temperature of a cured sample of (a1) a fiber-containing sheet, the cured sample may have the same glass transition temperature as the glass transition temperature of the insulating layer formed using (a1) a fiber-containing sheet.

[0245] Accordingly, the range of the glass transition temperature of the cured sample of the fiber-containing sheet (a1) for forming an opposite insulating layer containing a fiber substrate is preferably the same as the range of the glass transition temperature of the opposite insulating layer containing the fiber substrate described above.

[0246] In addition, the range of the glass transition temperature of the cured sample of the fiber-containing sheet (a1) for forming a chip-side insulating layer including a fiber substrate is preferably the same as the range of the glass transition temperature of the chip-side insulating layer including the fiber substrate described above.

[0247] In addition, the range of the absolute value of the difference between the glass transition temperature of the cured sample of the fiber-containing sheet (a1) for forming the opposite side insulating layer including the fiber substrate and the glass transition temperature of the cured sample of the fiber-containing sheet (a1) for forming the chip side insulating layer including the fiber substrate is preferably the same as the range of the absolute value of the difference between the glass transition temperature of the opposite side insulating layer including the fiber substrate and the glass transition temperature of the chip side insulating layer including the fiber substrate described above.

[0248] In addition, when a Tg measurement test is performed to measure the glass transition temperature of a cured sample of (b1) resin composition layer, the cured sample may have the same glass transition temperature as the glass transition temperature of an insulating layer formed using (b1) resin composition layer.

[0249] Accordingly, the glass transition temperature of the cured sample of the fiber-containing sheet (a1) for forming the opposite insulating layer containing the fiber substrate may be higher, lower, or equal to the glass transition temperature of the cured sample of the resin composition layer (b1) for forming the opposite insulating layer not containing the fiber substrate. At this time, it is preferable that the range of the absolute value of the difference between the glass transition temperature of the cured sample of the fiber-containing sheet (a1) for forming the opposite insulating layer containing the fiber substrate and the glass transition temperature of the cured sample of the resin composition layer (b1) for forming the opposite insulating layer not containing the fiber substrate be the same as the range of the absolute value of the difference between the glass transition temperature of the opposite insulating layer containing the fiber substrate and the glass transition temperature of the opposite insulating layer not containing the fiber substrate described above.

[0250] In addition, the glass transition temperature of the cured sample of the fiber-containing sheet (a1) for forming the opposite side insulation layer containing the fiber substrate may be higher, lower, or equal to the glass transition temperature of the cured sample of the resin composition layer (b1) for forming the chip side insulation layer not containing the fiber substrate. At this time, it is preferable that the range of the absolute value of the difference between the glass transition temperature of the cured sample of the fiber-containing sheet (a1) for forming the opposite side insulation layer containing the fiber substrate and the glass transition temperature of the cured sample of the resin composition layer (b1) for forming the chip side insulation layer not containing the fiber substrate be the same as the range of the absolute value of the difference between the glass transition temperature of the opposite side insulation layer containing the fiber substrate and the glass transition temperature of the chip side insulation layer not containing the fiber substrate described above.

[0251] In addition, the glass transition temperature of the cured sample of the fiber-containing sheet (a1) for forming a chip-side insulating layer containing a fiber substrate may be higher, lower, or equal to the glass transition temperature of the cured sample of the resin composition layer (b1) for forming a chip-side insulating layer not containing a fiber substrate. At this time, it is preferable that the range of the absolute value of the difference between the glass transition temperature of the cured sample of the fiber-containing sheet (a1) for forming a chip-side insulating layer containing a fiber substrate and the glass transition temperature of the cured sample of the resin composition layer (b1) for forming a chip-side insulating layer not containing a fiber substrate is the same as the range of the absolute value of the difference between the glass transition temperature of the chip-side insulating layer containing a fiber substrate and the glass transition temperature of the chip-side insulating layer not containing a fiber substrate.

[0252] In addition, the glass transition temperature of the cured sample of the fiber-containing sheet (a1) for forming the chip-side insulating layer containing the fiber substrate may be higher, lower, or equal to the glass transition temperature of the cured sample of the resin composition layer (b1) for forming the opposite-side insulating layer not containing the fiber substrate. It is preferable that the range of the absolute value of the difference between the glass transition temperature of the cured sample of the fiber-containing sheet (a1) for forming the chip-side insulating layer containing the fiber substrate and the glass transition temperature of the cured sample of the resin composition layer (b1) for forming the opposite-side insulating layer not containing the fiber substrate be the same as the range of the absolute value of the difference between the glass transition temperature of the chip-side insulating layer containing the fiber substrate and the glass transition temperature of the opposite-side insulating layer not containing the fiber substrate.

[0253] (a1) If the glass transition temperature of the cured sample of the fiber-containing sheet satisfies the above desirable requirements, warping after mounting of the semiconductor chip can be effectively suppressed.

[0254] (a1) The glass transition temperature of a cured sample of a fiber-containing sheet can be measured by the same measurement method as the glass transition temperature of an insulating layer on the opposite side containing fiber substrate.

[0255] In addition, when a modulus measurement test is performed to measure the tensile modulus of a cured sample of (a1) a fiber-containing sheet, the cured sample may have the same tensile modulus as the tensile modulus of an insulating layer formed using (a1) a fiber-containing sheet.

[0256] Accordingly, the range of tensile modulus of the cured sample of the fiber-containing sheet (a1) for forming an opposite insulating layer containing a fiber substrate is preferably the same as the range of tensile modulus of the opposite insulating layer containing a fiber substrate described above. For example, the range of tensile modulus at 260°C of the cured sample of the fiber-containing sheet (a1) for forming an opposite insulating layer containing a fiber substrate is preferably the same as the range of tensile modulus E(FOh) at 260°C of the opposite insulating layer containing a fiber substrate described above. In addition, for example, the range of tensile modulus at 23°C of the cured sample of the fiber-containing sheet (a1) for forming an opposite insulating layer containing a fiber substrate is preferably the same as the range of tensile modulus E(FOl) at 23°C of the opposite insulating layer containing a fiber substrate described above. In addition, for example, the range of the ratio of the tensile modulus at 260°C of the cured sample of (a1) fiber-containing sheet for forming an opposite insulating layer containing a fiber substrate to the tensile modulus at 23°C of the cured sample is preferably the same as the range of the ratio “E(FOh) / E(FOl)” of the tensile modulus at 260°C of the opposite insulating layer containing the fiber substrate to the tensile modulus at 23°C of the opposite insulating layer containing the fiber substrate described above.

[0257] In addition, the range of tensile modulus of the cured sample of the fiber-containing sheet (a1) for forming a chip-side insulating layer including a fiber substrate is preferably the same as the range of tensile modulus of the chip-side insulating layer including a fiber substrate described above. Accordingly, for example, the range of tensile modulus at 260°C of the cured sample of the fiber-containing sheet (a1) for forming a chip-side insulating layer including a fiber substrate is preferably the same as the range of tensile modulus E(FCh) at 260°C of the chip-side insulating layer including a fiber substrate described above. In addition, for example, the range of tensile modulus at 23°C of the cured sample of the fiber-containing sheet (a1) for forming a chip-side insulating layer including a fiber substrate is preferably the same as the range of tensile modulus E(FCl) at 23°C of the chip-side insulating layer including a fiber substrate described above.

[0258] In addition, the range of difference between the tensile modulus of the cured sample of the fiber-containing sheet (a1) for forming the opposite side insulating layer containing the fiber substrate and the tensile modulus of the cured sample of the fiber-containing sheet (a1) for forming the chip side insulating layer containing the fiber substrate is preferably the same as the range of difference between the tensile modulus of the opposite side insulating layer containing the fiber substrate and the tensile modulus of the chip side insulating layer containing the fiber substrate described above. Accordingly, for example, the range of the absolute value of the difference between the tensile modulus at 260°C of the cured sample of the fiber-containing sheet (a1) for forming the opposite side insulating layer containing the fiber substrate and the tensile modulus at 260°C of the cured sample of the fiber-containing sheet (a1) for forming the chip side insulating layer containing the fiber substrate is preferably the same as the range of the absolute value |E(FOh)-E(FCh)| of the difference “E(FOh)-E(FCh)” between the tensile modulus E(FOh) at 260°C of the opposite side insulating layer containing the fiber substrate and the tensile modulus E(FOh) at 260°C of the chip side insulating layer containing the fiber substrate described above. In addition, for example, the range of the absolute value of the difference between the tensile modulus of a cured sample of (a1) fiber-containing sheet at 23°C for forming an opposite side insulating layer containing a fiber substrate and the tensile modulus of a cured sample of (a1) fiber-containing sheet at 23°C for forming a chip-side insulating layer containing a fiber substrate is preferably the same as the range of the absolute value of the difference "E(FOl)-E(FCl)" between the tensile modulus E(FOl) of the opposite side insulating layer containing a fiber substrate at 23°C and the tensile modulus E(FCl) of the chip-side insulating layer containing a fiber substrate at 23°C |E(FOl)-E(FCl)|.

[0259] In addition, when a modulus measurement test is performed to measure the tensile modulus of a cured sample of (b1) resin composition layer, the cured sample may have the same tensile modulus as the tensile modulus of an insulating layer formed using (b1) resin composition layer.

[0260] Accordingly, it is preferable that the tensile elastic modulus of the cured sample of the fiber-containing sheet (a1) for forming an opposite insulating layer containing a fiber substrate is greater than the tensile elastic modulus of the cured sample of the resin composition layer (b1) for forming an opposite insulating layer not containing a fiber substrate. At this time, it is preferable that the range of the difference between the tensile elastic modulus at 260°C of the cured sample of the fiber-containing sheet (a1) for forming an opposite insulating layer containing a fiber substrate and the tensile elastic modulus at 260°C of the cured sample of the resin composition layer (b1) for forming an opposite insulating layer not containing a fiber substrate (tensile elastic modulus of the cured sample of the fiber-containing sheet (a1) - tensile elastic modulus of the cured sample of the resin composition layer (b1)) is the same as the range of the difference “E(FOh) - E(ROh)” between the tensile elastic modulus E(FOh) at 260°C of the opposite insulating layer containing a fiber substrate and the tensile elastic modulus E(ROh) at 260°C of the opposite insulating layer not containing a fiber substrate described above. In addition, the range of the difference between the tensile modulus at 23°C of the cured sample of the fiber-containing sheet (a1) for forming an opposite insulating layer containing a fiber substrate and the tensile modulus at 23°C of the cured sample of the resin composition layer (b1) for forming an opposite insulating layer not containing a fiber substrate (tensile modulus of the cured sample of the fiber-containing sheet (a1) - tensile modulus of the cured sample of the resin composition layer (b1)) is preferably the same as the range of the difference “E(FOl)-E(ROl)” between the tensile modulus at 23°C of the opposite insulating layer containing a fiber substrate and the tensile modulus at 23°C of the opposite insulating layer not containing a fiber substrate E(FOl) described above and the tensile modulus at 23°C of the opposite insulating layer not containing a fiber substrate E(ROl).

[0261] In addition, it is preferable that the tensile elastic modulus of the cured sample of the fiber-containing sheet (a1) for forming the opposite side insulation layer containing the fiber substrate is greater than the tensile elastic modulus of the cured sample of the resin composition layer (b1) for forming the chip side insulation layer not containing the fiber substrate. At this time, it is preferable that the range of the difference between the tensile elastic modulus at 260°C of the cured sample of the fiber-containing sheet (a1) for forming the opposite side insulation layer containing the fiber substrate and the tensile elastic modulus at 260°C of the cured sample of the resin composition layer (b1) for forming the chip side insulation layer not containing the fiber substrate (tensile elastic modulus of the cured sample of the fiber-containing sheet (a1) - tensile elastic modulus of the cured sample of the resin composition layer (b1)) is the same as the range of the difference “E(FOh)-E(RCh)” between the tensile elastic modulus E(FOh) at 260°C of the opposite side insulation layer containing the fiber substrate and the tensile elastic modulus E(RCh) at 260°C of the chip side insulation layer not containing the fiber substrate described above. In addition, the range of the difference between the tensile modulus at 23°C of the cured sample of the fiber-containing sheet (a1) for forming an opposite side insulating layer containing a fiber substrate and the tensile modulus at 23°C of the cured sample of the resin composition layer (b1) for forming a chip side insulating layer not containing a fiber substrate (tensile modulus of the cured sample of the fiber-containing sheet (a1) - tensile modulus of the cured sample of the resin composition layer (b1)) is preferably the same as the range of the difference “E(FOl)-E(RCl)” between the tensile modulus at 23°C of the opposite side insulating layer containing a fiber substrate and the tensile modulus at 23°C of the chip side insulating layer not containing a fiber substrate E(RCl) described above.

[0262] In addition, it is preferable that the tensile elastic modulus of the cured sample of the fiber-containing sheet (a1) for forming a chip-side insulating layer containing a fiber substrate is greater than the tensile elastic modulus of the cured sample of the resin composition layer (b1) for forming a chip-side insulating layer not containing a fiber substrate. At this time, it is preferable that the range of the difference between the tensile elastic modulus at 260°C of the cured sample of the fiber-containing sheet (a1) for forming a chip-side insulating layer containing a fiber substrate and the tensile elastic modulus at 260°C of the cured sample of the resin composition layer (b1) for forming a chip-side insulating layer not containing a fiber substrate (tensile elastic modulus of the cured sample of the fiber-containing sheet (a1) - tensile elastic modulus of the cured sample of the resin composition layer (b1)) is the same as the range of the difference “E(FCh)-E(RCh)” between the tensile elastic modulus E(FCh) at 260°C of the chip-side insulating layer containing a fiber substrate and the tensile elastic modulus E(RCh) at 260°C of the chip-side insulating layer not containing a fiber substrate. In addition, the range of the difference between the tensile modulus at 23°C of the cured sample of (a1) fiber-containing sheet for forming a chip-side insulating layer containing fibers and the tensile modulus at 23°C of the cured sample of (b1) resin composition layer for forming a chip-side insulating layer not containing fibers (tensile modulus of the cured sample of (a1) fiber-containing sheet - tensile modulus of the cured sample of (b1) resin composition layer) is preferably the same as the range of the difference “E(FCl)-E(RCl)” between the tensile modulus E(FCl) at 23°C of the chip-side insulating layer containing fibers and the tensile modulus E(RCl) at 23°C of the chip-side insulating layer not containing fibers.

[0263] In addition, it is preferable that the tensile elastic modulus of the cured sample of the fiber-containing sheet (a1) for forming a chip-side insulating layer containing a fiber substrate is greater than the tensile elastic modulus of the cured sample of the resin composition layer (b1) for forming an opposite-side insulating layer not containing a fiber substrate. At this time, it is preferable that the range of the difference between the tensile elastic modulus at 260°C of the cured sample of the fiber-containing sheet (a1) for forming a chip-side insulating layer containing a fiber substrate and the tensile elastic modulus at 260°C of the cured sample of the resin composition layer (b1) for forming an opposite-side insulating layer not containing a fiber substrate (tensile elastic modulus of the cured sample of the fiber-containing sheet (a1) - tensile elastic modulus of the cured sample of the resin composition layer (b1)) is the same as the range of the difference “E(FCh)-E(ROh)” between the tensile elastic modulus E(FCh) at 260°C of the chip-side insulating layer containing a fiber substrate and the tensile elastic modulus E(ROh) at 260°C of the opposite-side insulating layer not containing a fiber substrate. In addition, the range of the difference between the tensile modulus at 23°C of the cured sample of the fiber-containing sheet (a1) for forming a chip-side insulating layer containing a fiber substrate and the tensile modulus at 23°C of the cured sample of the resin composition layer (b1) for forming an opposite-side insulating layer not containing a fiber substrate (tensile modulus of the cured sample of the fiber-containing sheet (a1) - tensile modulus of the cured sample of the resin composition layer (b1)) is preferably the same as the range of the difference “E(FC1)-E(RO1)” between the tensile modulus E(FC1) at 23°C of the chip-side insulating layer containing a fiber substrate and the tensile modulus E(RO1) at 23°C of the opposite-side insulating layer not containing a fiber substrate.

[0264] (a1) If the tensile modulus of the cured sample of the fiber-containing sheet satisfies the above desirable requirements, the bending of the semiconductor chip after mounting can be effectively suppressed.

[0265] (a1) The tensile modulus of a cured sample of a fiber-containing sheet can be measured by the same measurement method as the tensile modulus of an insulating layer on the opposite side containing fiber substrate.

[0266] (a1) The thickness range of the fiber-containing sheet may be the same as the thickness range per layer of the insulating layer formed using the fiber-containing sheet (a1).

[0267] In terms of ensuring good handling, it is preferable to prepare (a1) a fiber-containing sheet in a state where it is provided on (a) an insulating multilayer sheet. At this time, (a) the insulating multilayer sheet comprises (a2) a support and (a1) a fiber-containing sheet formed on the (a2) support.

[0268] (a1) When the fiber-containing sheet comprises (a11) a prepreg layer and (a12) a primer-cured layer, (a) the insulating multilayer sheet may comprise (a11) a prepreg layer, (a12) a primer-cured layer and (a2) a support in this order. (a2) As the support, examples include a film of plastic material, a metal foil, etc.

[0269] (a2) When a film of a plastic material is used as a support, the plastic material may be, for example, a polyester such as polyethylene terephthalate (hereinafter abbreviated as “PET”), polyethylene naphthalate (hereinafter abbreviated as “PEN”), an acrylic such as polymethyl methacrylate (PMMA), a cyclic polyolefin, triacetylcellulose (TAC), polyether sulfide (PES), polyether ketone, polyimide, etc. Among these, polyethylene terephthalate and polyethylene naphthalate are preferred, and inexpensive polyethylene terephthalate is particularly preferred.

[0270] (a2) When using a metal foil as a support, examples of metal foils include copper foil, aluminum foil, etc., and copper foil is preferred. As for the copper foil, a foil made of copper may be used, or a foil made of an alloy of copper and other metals (e.g., tin, chromium, silver, magnesium, nickel, zirconium, silicon, titanium, etc.) may be used.

[0271] (a2) The support may have surface treatments such as mat treatment, corona treatment, or antistatic treatment applied to the surface in contact with the (a1) fiber-containing sheet. Additionally, as the (a2) support, a support with a release layer attached having a release layer may be used. The release layer can typically be formed by a release agent. Examples of release agents include one or more release agents selected from the group consisting of alkyd-based release agents, polyolefin-based release agents, urethane-based release agents, and silicone-based release agents. The support with the release layer attached may be a commercially available product, and examples include PET films having a release layer with a silicone-based release agent or an alkyd resin-based release agent as the main component, such as "PET501010", "SK-1", "AL-5", and "AL-7" manufactured by Lintec; "Lumira T60" manufactured by Tore; and "Purex" manufactured by Teijin. Examples include "Unifil" manufactured by Unichika Co.

[0272] (a2) The thickness of the support is preferably 1 μm or more, more preferably 5 μm or more, even more preferably 10 μm or more, preferably 75 μm or less, more preferably 60 μm or less, and even more preferably 50 μm or less. When using a support with a release layer attached, it is preferable that the total thickness of the support with the release layer attached is within the above range.

[0273] (a) The insulating multilayer sheet may additionally have any element in combination with (a1) the fiber-containing sheet and (a2) the support. For example, (a) the insulating multilayer sheet may have (a3) ​​a protective film layer that protects the (a1) fiber-containing sheet. (a3) ​​the protective film layer is typically provided on the side of (a1) the fiber-containing sheet that is not bonded to the (a2) support (i.e., the side opposite to the (a2) support). The thickness of (a3) ​​the protective film layer is not particularly limited, but is, for example, 1 μm to 40 μm. The (a3) ​​protective film can suppress the adhesion of dust and scratches to the surface of (a1) the fiber-containing sheet. Generally, when (a) the insulating multilayer sheet has (a3) ​​the protective film layer, (a) the insulating multilayer sheet becomes usable by removing the (a3) ​​protective film layer.

[0274] (a1) A fiber-containing sheet can be manufactured by a method including a process of forming (a11) a prepreg layer. (a11) The prepreg layer can be manufactured by a method such as a hot melt method or a solvent method. (a11) Preferred methods for manufacturing the prepreg layer include the following methods (1) to (4).

[0275] (1) A layer of the first resin composition is formed by coating the first resin composition onto a support substrate without dissolving the first resin composition in a solvent. The layer of the first resin composition is laminated with a fiber substrate to form a prepreg layer (a11) on the support substrate.

[0276] (2) The first resin composition is coated onto a fiber substrate without dissolving it in a solvent to form (a11) a prepreg layer.

[0277] (3) Prepare a resin varnish by dissolving the first resin composition in a solvent. Immerse the fiber substrate in the resin varnish to impregnate the fiber substrate with the resin varnish. Then, dry the resin varnish to form a prepreg layer (a11).

[0278] (4) A resin varnish is applied to a support substrate and dried as needed to form a layer of the first resin composition. The layer of the first resin composition is laminated with a fiber substrate to form a prepreg layer (a11) on the support substrate.

[0279] In the above method, as a supporting material, for example, a (a2) support may be used.

[0280] As a solvent for preparing the resin varnish, for example, the same as the (F) solvent that may be included in the resin composition may be used. In addition, in one example, the drying temperature is preferably 80°C or higher, more preferably 90°C or higher, preferably 180°C or lower, more preferably 140°C or lower. In addition, the drying time is preferably 3 minutes or more, preferably 13 minutes or less, more preferably 10 minutes or less.

[0281] (a11) The process of forming the prepreg layer may include, if necessary, laminating (a2) a support and (a3) ​​a protective film layer onto the (a11) prepreg layer.

[0282] (a1) A method for manufacturing a fiber-containing sheet may additionally include (a12) a process for forming a primer-cured layer. (a12) The primer-cured layer may be formed by a method comprising forming a layer of a second resin composition and curing the layer of the second resin composition.

[0283] The layer of the second resin composition may be formed, for example, by applying a liquid second resin composition onto the support (a2). Alternatively, the layer of the second resin composition may be formed, for example, by mixing the second resin composition with a solvent to prepare a liquid resin varnish, applying this onto the support (a2), and further drying it as needed. As for the solvent, for example, the same as the solvent (F) that may be included in the resin composition may be used. Additionally, drying is performed so that the solvent content in the layer of the second resin composition is typically 10 mass% or less, preferably 5 mass% or less.

[0284] After forming a layer of the second resin composition, the layer is cured to form (a12) a primer cured layer. At this time, the layer of the second resin composition is usually cured by heating. For example, the layer of the second resin composition may be cured by heating for 10 minutes to 10 hours at a temperature of 50°C to 200°C. In addition, drying and curing of the layer of the second resin composition may be performed simultaneously.

[0285] By adhering the obtained (a12) primer cured layer to the (a11) prepreg layer, a fiber-containing sheet (a1) comprising a combination of the (a11) prepreg layer and the (a12) primer cured layer can be obtained. For example, the fiber-containing sheet (a1) may be manufactured by laminating the (a11) prepreg layer with a cured sheet comprising a (a2) support and a (a12) primer cured layer. Additionally, the method for manufacturing the (a1) fiber-containing sheet may further include any other process, for example, may include a process of laminating a (a3) ​​protective film layer.

[0286] (a1) A method for forming an insulating layer using a fiber-containing sheet includes laminating the fiber-containing sheet (a1). For example, by laminating so that the core substrate and the fiber-containing sheet (a1) are bonded, the fiber-containing sheet (a1) is formed directly on the core substrate. Here, "directly" forming the fiber-containing sheet (a1) on the core substrate means that there is no other layer between the core substrate and the fiber-containing sheet (a1). In addition, for example, by laminating so that the fiber-containing sheet (a1) is bonded to an insulating layer already formed on the core substrate, the fiber-containing sheet (a1) is formed on the core substrate with the insulating layer interposed therein. When the fiber-containing sheet (a1) includes a combination of a prepreg layer (a11) and a primer-cured layer (a2), typically, in order to ensure that the primer-cured layer (a2) is positioned further away from the core substrate than the prepreg layer (a11), lamination is performed so that the prepreg layer (a11) is bonded to the core substrate or the insulating layer.

[0287] (a1) Lamination of the fiber-containing sheet is performed by pressing the fiber-containing sheet (a1) onto the core substrate. This lamination may be performed using an insulating multilayer sheet (a) equipped with a support (a2). In this case, it is preferable to perform lamination by pressing the insulating multilayer sheet (a) from the support (a2). As for the member performing the above pressing (hereinafter also referred to as the "heat pressing member"), for example, a heated metal plate (such as a SUS hard plate) or a metal roll (such as a SUS roll) may be used. The heating pressing member may be pressed directly onto the insulating multilayer sheet (a), but it is preferable to press by interposing an elastic material such as heat-resistant rubber so that the prepreg layer (a11) sufficiently follows the surface irregularities of the core substrate or the already formed insulating layer.

[0288] (a1) Lamination of fiber-containing sheets is preferably carried out by a lamination method. In general, the lamination method compresses the (a1) fiber-containing sheets at a lower pressure compared to compression molding and vacuum press methods. Therefore, in addition to saving space for the equipment, it is possible to effectively suppress the formation of irregularities reflecting the shape of the fiber substrate on the surface of the (a1) fiber-containing sheets, or to effectively suppress the exposure of the fiber substrate on the surface of the (a1) fiber-containing sheets.

[0289] Among the lamination conditions in the lamination method, the heating condition is preferably in the range of 60°C to 160°C, more preferably 80°C to 140°C. In addition, the pressing condition is preferably in the range of 0.098 MPa to 1.77 MPa, more preferably 0.29 MPa to 1.47 MPa. In addition, the pressing time is preferably in the range of 10 seconds to 400 seconds, more preferably 30 seconds to 300 seconds. This lamination is preferably carried out under reduced pressure conditions of 26.7 hPa or less.

[0290] Lamination may be performed using a commercially available vacuum laminator. Examples of commercially available vacuum laminators include the vacuum pressure laminator manufactured by Meiki Sesakusho Co., Ltd., the vacuum applicator manufactured by Nikko Materials Co., Ltd., and the batch vacuum pressure laminator.

[0291] (a1) A method for forming an insulating layer using a fiber-containing sheet may include smoothing the fiber-containing sheet (a1) under atmospheric pressure after laminating the fiber-containing sheet (a1). As a specific example, the method for forming an insulating layer may include smoothing the fiber-containing sheet (a1) by pressing it with a heat-pressing member. (a2) When using an insulating multilayer sheet (a) having a support, the fiber-containing sheet (a1) can be smoothed by pressing the insulating multilayer sheet (a) from the (a2) support side. The pressing conditions for the smoothing treatment may be the same as the lamination conditions of the above lamination method. The smoothing treatment may be performed using a commercially available laminator. Lamination and the smoothing treatment may be performed continuously using the above commercially available vacuum laminator.

[0292] (a1) A method for forming an insulating layer using a fiber-containing sheet typically comprises laminating the (a1) fiber-containing sheet and then curing the (a1) fiber-containing sheet. By curing the (a1) fiber-containing sheet, the (a11) prepreg layer containing the fiber substrate is cured, thereby forming an insulating layer containing the fiber substrate.

[0293] (a1) Curing of the fiber-containing sheet is typically performed by heat curing. (a1) The heat curing conditions of the fiber-containing sheet may vary depending on the type of the first resin composition included in the prepreg layer (a11). For example, the curing temperature is preferably 120°C to 240°C, more preferably 150°C to 220°C, and even more preferably 170°C to 210°C. In addition, the curing time may be preferably 5 minutes to 120 minutes, more preferably 10 minutes to 100 minutes, and even more preferably 15 minutes to 100 minutes.

[0294] (a1) A method for forming an insulating layer using a fiber-containing sheet may include preheating the fiber-containing sheet (a1) at a temperature lower than the curing temperature before heat curing the fiber-containing sheet (a1). For example, prior to heat curing the fiber-containing sheet (a1), the fiber-containing sheet (a1) may be preheated for at least 5 minutes (preferably 5 minutes to 150 minutes, more preferably 15 minutes to 120 minutes, even more preferably 15 minutes to 100 minutes) at a temperature of typically 50°C to 150°C (preferably 60°C to 140°C, more preferably 70°C to 130°C). Preheating is typically performed after lamination of the fiber-containing sheet (a1). Additionally, if a smoothing treatment is performed after lamination, preheating may typically be performed after the smoothing treatment.

[0295] (a2) When using an insulating multilayer sheet (a) having a support, the method for forming the insulating layer may include peeling off the support (a2) after laminating the fiber-containing sheet (a1). The peeling off of the support (a2) may be performed before curing the fiber-containing sheet (a1) or after curing the fiber-containing sheet (a1).

[0296] (Method for forming an insulating layer that does not include a fiber substrate)

[0297] Next, a method for forming an insulating layer that does not include a fiber substrate is described. It is preferable that the insulating layer that does not include a fiber substrate be formed by a method comprising laminating a (b1) resin composition layer that does not include a fiber substrate as described above.

[0298] (b1) The resin composition layer may include a resin composition, or may include only the resin composition. Hereinafter, the resin composition included in the (b1) resin composition layer may be referred to as the "third resin composition." Typically, since the third resin composition has thermosetting properties, an insulating layer that does not include a fiber substrate can be formed by curing the (b1) resin composition layer containing the third resin composition. For example, an insulating layer that does not include a fiber substrate can be formed on the core substrate (100) by a method including laminating the (b1) resin composition layer onto the core substrate (100) and thermosetting the third resin composition included in the (b1) resin composition layer. Additionally, for example, an insulating layer that does not include a fiber substrate (n+1th insulating layer) can be formed on the insulating layer (nth insulating layer) by a method including laminating the (b1) resin composition layer onto an insulating layer (nth insulating layer) and thermosetting the third resin composition included in the (b1) resin composition layer. The above “n” represents a natural number.

[0299] (b1) The range of the lowest melt viscosity of the resin composition layer in the temperature range from 100°C to 140°C is preferably 100 poise or more, more preferably 200 poise or more, even more preferably 400 poise or more, preferably 10000 poise or less, more preferably 7000 poise or less, and even more preferably 4000 poise or less. Typically, the lowest melt viscosity of the resin composition layer in the temperature range from 100°C to 140°C corresponds to the lowest melt viscosity of the third resin composition included in the resin composition layer in the (b1) layer in the temperature range from 100°C to 140°C. When the resin composition layer in the (b1) layer has the lowest melt viscosity of the above range in the temperature range from 100°C to 140°C, the conductor layer on the surface bonded to the resin composition layer in the (b1) layer can be well embedded.

[0300] (b1) When the temperature of the resin composition layer is increased, the melt viscosity of the resin composition layer of (b1) generally decreases sequentially with increasing temperature, and after reaching the lowest value at a certain temperature, it may increase. At this time, the temperature at which the melt viscosity of the resin composition layer of (b1) exhibits the lowest value is preferably low from the perspective of effectively embedding a conductor layer such as wiring. In one example, the temperature range at which the melt viscosity of the resin composition layer of (b1) exhibits the lowest value is preferably 100°C or higher and 150°C or lower.

[0301] (b1) The melt viscosity of the resin composition layer can be measured by the same method as the melt viscosity of the prepreg layer (a11). From the measured results, the lowest melt viscosity in the temperature range from 100°C to 140°C, and the temperature at which the melt viscosity has the lowest value among the measured temperature ranges can be determined.

[0302] As described above, when a CTE measurement test is performed to measure the coefficient of linear thermal expansion of a cured sample of (b1) resin composition layer, the cured sample may have a coefficient of linear thermal expansion identical to the coefficient of linear thermal expansion of an insulating layer formed using (b1) resin composition layer.

[0303] Accordingly, it is preferable that the range of the linear thermal expansion coefficient of the cured sample of the resin composition layer (b1) for forming the opposite insulating layer not containing fiber substrates is the same as the range of the linear thermal expansion coefficient of the opposite insulating layer not containing fiber substrates. For example, it is preferable that the range of the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of the resin composition layer (b1) for forming the opposite insulating layer not containing fiber substrates is the same as the range of the linear thermal expansion coefficient CTE(ROh) in the high-temperature measurement range of the opposite insulating layer not containing fiber substrates. Furthermore, for example, it is preferable that the range of the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the resin composition layer (b1) for forming the opposite insulating layer not containing fiber substrates is the same as the range of the linear thermal expansion coefficient CTE(ROh) in the low-temperature measurement range of the opposite insulating layer not containing fiber substrates.

[0304] In addition, it is preferable that the range of the linear thermal expansion coefficient of the cured sample of the resin composition layer (b1) for forming a chip-side insulation layer not including a fiber substrate is the same as the range of the linear thermal expansion coefficient of the chip-side insulation layer not including a fiber substrate. Accordingly, for example, it is preferable that the range of the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of the resin composition layer (b1) for forming a chip-side insulation layer not including a fiber substrate is the same as the range of the linear thermal expansion coefficient CTE(RCh) in the high-temperature measurement range of the chip-side insulation layer not including a fiber substrate. In addition, for example, it is preferable that the range of the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the resin composition layer (b1) for forming a chip-side insulation layer not including a fiber substrate is the same as the range of the linear thermal expansion coefficient CTE(RCl) in the low-temperature measurement range of the chip-side insulation layer not including a fiber substrate.

[0305] In addition, the range of difference between the linear thermal expansion coefficient of the cured sample of the resin composition layer (b1) for forming the opposite side insulation layer not including the fiber substrate and the linear thermal expansion coefficient of the cured sample of the resin composition layer (b1) for forming the chip side insulation layer not including the fiber substrate is preferably the same as the range of difference between the linear thermal expansion coefficient of the opposite side insulation layer not including the fiber substrate and the linear thermal expansion coefficient of the chip side insulation layer not including the fiber substrate. Accordingly, for example, the range of the absolute value of the difference between the coefficient of linear thermal expansion in the high-temperature measurement range of the cured sample of the resin composition layer (b1) for forming the opposite insulating layer not containing fiber substrates and the coefficient of linear thermal expansion in the high-temperature measurement range of the cured sample of the resin composition layer (b1) for forming the chip-side insulating layer not containing fiber substrates is preferably the same as the range of the absolute value of "CTE(ROh)-CTE(RCh)" |CTE(ROh)-CTE(RCh)|, which is the difference between the coefficient of linear thermal expansion CTE(ROh) in the high-temperature measurement range of the opposite insulating layer not containing fiber substrates and the coefficient of linear thermal expansion CTE(RCh) in the high-temperature measurement range of the chip-side insulating layer not containing fiber substrates. In addition, for example, the range of the absolute value of the difference between the coefficient of linear thermal expansion in the low-temperature measurement range of the resin composition layer (b1) for forming the opposite side insulation layer not including the fiber substrate and the coefficient of linear thermal expansion in the low-temperature measurement range of the resin composition layer (b1) for forming the chip side insulation layer not including the fiber substrate is preferably the same as the range of the absolute value of "CTE(ROl)-CTE(RCl)" between the coefficient of linear thermal expansion CTE(ROl) in the low-temperature measurement range of the opposite side insulation layer not including the fiber substrate and the coefficient of linear thermal expansion CTE(RCl) in the low-temperature measurement range of the chip side insulation layer not including the fiber substrate |CTE(ROl)-CTE(RCl)|.

[0306] When using a resin composition layer (b1) in which a cured sample having such a linear thermal expansion coefficient is obtained, warping after mounting of the semiconductor chip can be effectively suppressed.

[0307] (b1) The linear thermal expansion coefficient of the cured sample of the resin composition layer can be measured by the same method as the measurement method of the linear thermal expansion coefficient of the opposite insulating layer containing the fiber substrate.

[0308] As described above, when a Tg measurement test is performed to measure the glass transition temperature of a cured sample of the resin composition layer (b1), the cured sample may have a glass transition temperature identical to the glass transition temperature of the insulating layer formed using the resin composition layer (b1). Therefore, it is preferable that the range of the glass transition temperature of the cured sample of the resin composition layer (b1) for forming an opposite insulating layer that does not include fiber substrates is the same as the range of the glass transition temperature of the opposite insulating layer that does not include fiber substrates. Furthermore, it is preferable that the range of the glass transition temperature of the cured sample of the resin composition layer (b1) for forming a chip-side insulating layer that does not include fiber substrates is the same as the range of the glass transition temperature of the chip-side insulating layer that does not include fiber substrates. In addition, the absolute range of the difference between the glass transition temperature of the cured sample of the resin composition layer (b1) for forming the opposite insulating layer not containing fibers and the glass transition temperature of the cured sample of the resin composition layer (b1) for forming the chip insulating layer not containing fibers is preferably the same as the absolute range of the difference between the glass transition temperature of the opposite insulating layer not containing fibers and the glass transition temperature of the chip insulating layer not containing fibers. When using the resin composition layer (b1) from which a cured sample having such a glass transition temperature is obtained, warping after mounting of the semiconductor chip can be effectively suppressed.

[0309] (b1) The glass transition temperature of the cured sample of the resin composition layer can be measured by the same method as the glass transition temperature of the opposite insulating layer containing the fiber substrate.

[0310] As described above, when a modulus measurement test is performed to measure the tensile modulus of a cured sample of (b1) resin composition layer, the cured sample may have the same tensile modulus as the tensile modulus of an insulating layer formed using (b1) resin composition layer.

[0311] Accordingly, it is preferable that the range of tensile modulus of the cured sample of the resin composition layer (b1) for forming the opposite insulating layer not containing fibers be the same as the range of tensile modulus of the opposite insulating layer not containing fibers. For example, it is preferable that the range of tensile modulus at 260°C of the cured sample of the resin composition layer (b1) for forming the opposite insulating layer not containing fibers be the same as the range of tensile modulus E(ROh) at 260°C of the opposite insulating layer not containing fibers. In addition, for example, it is preferable that the range of tensile modulus at 23°C of the cured sample of the resin composition layer (b1) for forming the opposite insulating layer not containing fibers be the same as the range of tensile modulus E(ROh) at 23°C of the opposite insulating layer not containing fibers.

[0312] In addition, the range of tensile modulus of the cured sample of the resin composition layer (b1) for forming a chip-side insulating layer not including a fiber substrate is preferably the same as the range of tensile modulus of the chip-side insulating layer not including a fiber substrate. Accordingly, for example, the range of tensile modulus at 260°C of the cured sample of the resin composition layer (b1) for forming a chip-side insulating layer not including a fiber substrate is preferably the same as the range of tensile modulus E(RCh) at 260°C of the chip-side insulating layer not including a fiber substrate. In addition, for example, the range of tensile modulus at 23°C of the cured sample of the resin composition layer (b1) for forming a chip-side insulating layer not including a fiber substrate is preferably the same as the range of tensile modulus E(RCl) at 23°C of the chip-side insulating layer not including a fiber substrate.

[0313] Additionally, the range of difference between the tensile modulus of the cured sample of the resin composition layer (b1) for forming the opposite side insulation layer not including fiber substrates and the tensile modulus of the cured sample of the resin composition layer (b1) for forming the chip side insulation layer not including fiber substrates is preferably the same as the range of difference between the tensile modulus of the opposite side insulation layer not including fiber substrates and the tensile modulus of the chip side insulation layer not including fiber substrates. Accordingly, for example, the range of the absolute value of the difference between the tensile modulus at 260°C of the cured sample of the resin composition layer (b1) for forming the opposite side insulation layer not including the fiber substrate and the tensile modulus at 260°C of the cured sample of the resin composition layer (b1) for forming the chip side insulation layer not including the fiber substrate is preferably the same as the range of the absolute value of the difference “E(ROh)-E(RCh)” between the tensile modulus E(ROh) at 260°C of the opposite side insulation layer not including the fiber substrate and the tensile modulus E(RCh) at 260°C of the chip side insulation layer not including the fiber substrate, |E(ROh)-E(RCh)|. In addition, for example, the range of the absolute value of the difference between the tensile modulus at 23°C of the cured sample of the resin composition layer (b1) for forming the opposite side insulation layer not including the fiber substrate and the tensile modulus at 23°C of the cured sample of the resin composition layer (b1) for forming the chip side insulation layer not including the fiber substrate is preferably the same as the range of the absolute value |E(ROl)-E(RCl)| of the difference “E(ROl)-E(RCl)” between the tensile modulus E(ROl) at 23°C of the opposite side insulation layer not including the fiber substrate and the tensile modulus E(RCl) at 23°C of the chip side insulation layer not including the fiber substrate.

[0314] When using a resin composition layer (b1) in which a cured sample having such tensile elastic modulus is obtained, warping after mounting of the semiconductor chip can be effectively suppressed.

[0315] (b1) The tensile modulus of the cured sample of the resin composition layer can be measured by the same method as the measurement method of the tensile modulus of the opposite insulating layer containing the fiber substrate.

[0316] (b1) The range of thickness of the resin composition layer may be the same as the range of thickness per layer of the insulating layer formed using the (b1) resin composition layer.

[0317] From the perspective of ensuring good handling, it is preferable to prepare the (b1) resin composition layer in a state provided on the (b) resin sheet. At this time, the (b) resin sheet comprises a (b2) support and the (b1) resin composition layer formed on the (b2) support. As the (b2) support, the same as the support (a2) of the (a) insulating multilayer sheet may be used.

[0318] (b) The resin sheet may additionally have any element in combination with (b1) the resin composition layer and (b2) the support. For example, the (b) resin sheet may have a (b3) protective film layer that protects the (b1) resin composition layer. The (b3) protective film layer is typically provided on the side of the (b1) resin composition layer that is not bonded to the (b2) support (i.e., the side opposite to the (b2) support). As for the (a3) ​​protective film layer, the same as the (a3) ​​protective film layer that can be provided by the (a) insulating multilayer sheet may be used. Generally, when the (b) resin sheet has the (b3) protective film layer, the (b) resin sheet becomes usable by removing the (b3) protective film layer.

[0319] (b) The resin sheet may be manufactured by a method including, for example, forming a layer of the resin composition (b1) on a support (b2). Specifically, the layer of the resin composition (b1) may be formed by applying the liquid third resin composition as is onto the support (b2). Alternatively, for example, a liquid resin varnish may be prepared by mixing a solvent with the third resin composition, applied onto the support (b2), and further dried as needed to form the layer of the resin composition (b1). As for the solvent, for example, the same as the solvent (F) that may be included in the resin composition may be used.

[0320] Coating can be performed using a coating device such as a die coater. Additionally, drying can be carried out by drying methods such as heating or hot air spraying. The drying conditions are not particularly limited, but the solvent content in the (b1) resin composition layer is typically 10 mass% or less, preferably 5 mass% or less. This may vary depending on the boiling point of the solvent; for example, when using a resin varnish containing 30 mass% to 60 mass% of solvent, the (b1) resin composition layer can be formed by drying at 50°C to 150°C for 3 to 10 minutes.

[0321] (b1) A method for forming an insulating layer using a resin composition layer includes laminating the (b1) resin composition layer. For example, by laminating so that the core substrate and the (b1) resin composition layer are bonded, the (b1) resin composition layer is formed directly on the core substrate. Here, "directly" forming the (b1) resin composition layer on the core substrate means that there is no other layer between the core substrate and the (b1) resin composition layer. In addition, for example, by laminating so that the (b1) resin composition layer is bonded to an insulating layer already formed on the core substrate, the (b1) resin composition layer is formed on the core substrate with the insulating layer interposed therein.

[0322] (b1) Lamination of the resin composition layer is performed by pressing the (b1) resin composition layer onto the core substrate. This lamination may be performed using a (b) resin sheet having a (b2) support. In this case, it is preferable to perform lamination by pressing the (b) resin sheet from the (b2) support side. At this time, a heat-pressing member may be pressed directly onto the (b) resin sheet, but it is preferable to press by interposing an elastic material such as heat-resistant rubber so that the (b1) resin composition layer sufficiently follows the surface irregularities of the core substrate or the insulating layer.

[0323] (b1) Lamination of the resin composition layer is preferably carried out by a lamination method. (b1) The lamination conditions of the resin composition layer may be the same as the lamination conditions of the fiber-containing sheet (a1). Additionally, the lamination of the resin composition layer (b1) may be carried out using a commercially available vacuum laminator.

[0324] (b1) A method for forming an insulating layer using a resin composition layer may include smoothing the (b1) resin composition layer under atmospheric pressure after laminating the (b1) resin composition layer. As a specific example, the method for forming an insulating layer may include smoothing the (b1) resin composition layer by pressing it with a heat-pressing member. (b2) When using a resin sheet (b) having a support, the (b1) resin composition layer can be smoothed by pressing the (b) resin sheet from the (b2) support side. The pressing conditions for the smoothing treatment may be the same as the lamination conditions of the above lamination method. The smoothing treatment may be performed using a commercially available laminator. Lamination and smoothing treatment may be performed continuously using the above commercially available vacuum laminator.

[0325] (b1) A method for forming an insulating layer using a resin composition layer typically comprises (b) laminating resin sheets and then (b1) curing the resin composition layer. By curing the (b1) resin composition layer, an insulating layer that does not include a fiber substrate can be formed.

[0326] (b1) The curing of the resin composition layer is typically carried out by thermal curing. (b1) The thermal curing conditions of the resin composition layer may vary depending on the type of third resin composition included in the (b1) resin composition layer. In one example, the range of curing temperature and curing time for the process of curing the (b1) resin composition layer may be the same as the range of curing temperature and curing time for the process of curing the (a1) fiber-containing sheet.

[0327] (b1) A method for forming an insulating layer using a resin composition layer may include preheating the resin composition layer (b1) at a temperature lower than the curing temperature before the thermal curing of the resin composition layer (b1). The temperature and time range for preheating the resin composition layer (b1) may be the same as the temperature and time range for preheating the fiber-containing sheet (a1). Preheating is usually performed after lamination of the resin sheet (b). In addition, if a smoothing treatment is performed after lamination, preheating is usually performed after the smoothing treatment.

[0328] (b2) When using a resin sheet (b) having a support, the method for forming the insulating layer may include peeling off the support (b2) after laminating the resin composition layer (b1). The peeling off of the support (b2) may be performed before curing the resin composition layer (b1) or after curing the resin composition layer (b1).

[0329] (Timing of formation of the chip-side insulation layer and the opposite-side insulation layer)

[0330] The process of forming the insulating layer on the chip side and the process of forming the insulating layer on the opposite side may be performed at different times, but it is preferable to perform them simultaneously. Specifically, by performing the process of forming the insulating layer on the chip side and the process of forming the insulating layer on the opposite side simultaneously, it is preferable to form one layer of the insulating layer on the chip side and one layer of the insulating layer on the opposite side at the same time. In this case, a lamination treatment such as a laminate can be performed once to simultaneously form a resin composition layer or a fiber-containing sheet on the chip side and the opposite side of the core substrate. Additionally, a curing treatment can be performed once to simultaneously cure these resin composition layers or fiber-containing sheets. Therefore, since there is no need to perform the lamination and curing treatments for forming the insulating layer included in the chip-side build-up layer and the lamination and curing treatments for forming the insulating layer included in the opposite-side build-up layer separately, the number of processes can be reduced, thereby simplifying the manufacturing method of the structure. In addition, since the insulating layer on the chip side and the insulating layer on the opposite side can be formed simultaneously, the stress acting on the chip side of the core layer and the stress acting on the opposite side can be balanced, and thus, the bending of the intermediate product obtained during the manufacturing process of the structure can be suppressed.

[0331] (Formation of holes)

[0332] The method for manufacturing a structure according to the present embodiment may include a process of forming holes, such as via holes or through holes, in the insulating layer after forming the insulating layer. Examples of methods for forming holes include drilling, laser processing, and plasma processing. Among these, laser processing is preferred. When an insulating multilayer sheet having (a2) a support or a resin sheet having (b2) a support is used to form the insulating layer, a hole may be formed by irradiating the insulating layer with laser light after peeling off the (a2) support or (b2) support, or a hole may be formed by irradiating the insulating layer with laser light interposed between the (a2) support or (b2) support before peeling.

[0333] (Formation of a conductive layer)

[0334] The method for manufacturing a structure according to the present embodiment may include a process of forming a conductor layer on an insulating layer after forming an insulating layer. If the method for manufacturing a structure includes a process of forming a hole, the process of forming the conductor layer is typically preferably performed after the process of forming the hole.

[0335] The conductor layer may be formed by plating. For example, a conductor layer having a desired wiring pattern can be formed by plating on the surface of an insulating layer using conventionally known techniques such as the semi-additive method or the full-additive method. From the perspective of ease of manufacturing, the semi-additive method is preferred. Below, an example of forming a conductor layer by the semi-additive method is shown.

[0336] First, an electroless plating layer (plating seed layer) is formed on the surface of an insulating layer by electroless plating. Then, a mask pattern is formed on the formed electroless plating layer to expose a portion of the electroless plating layer corresponding to a desired wiring pattern. After forming an electrolytic plating layer on the exposed electroless plating layer by electroplating, the mask pattern is removed. Subsequently, the unnecessary electroless plating layer is removed by etching to form a conductor layer having a desired wiring pattern.

[0337] The conductor layer is generally formed to have a pattern shape according to the design of the structure. Unless otherwise specified, the term "pattern shape" refers to the shape viewed in the thickness direction. At this time, the pitch of the conductor layer formed on the outermost chip-side insulating layer (conductor layer (234) in the example shown in FIG. 1) and the pitch of the conductor layer formed on the outermost opposite insulating layer (conductor layer (334) in the example shown in FIG. 1) may be the same, the former may be larger, or the latter may be larger. The conductor layer formed on the outermost chip-side insulating layer is often formed with a relatively narrow pitch to connect to the terminals of the minute semiconductor chip. In addition, the conductor layer formed on the outermost opposite insulating layer is often formed with a relatively large pitch to connect to the terminals of the wiring board on which the semiconductor chip package is to be mounted. Therefore, typically, the pitch of the conductor layer formed on the opposite side of the outermost insulating layer is formed to be larger than the pitch of the conductor layer formed on the outermost chip-side insulating layer.

[0338] (Other processes)

[0339] The method for manufacturing a structure according to the present embodiment may additionally include any process in combination with the process described above. For example, the method for manufacturing a structure may include a process of performing a shaping treatment on an insulating layer. By performing the shaping treatment, the surface of the insulating layer is shaped, thereby increasing the adhesion of the conductor layer formed by plating on the surface. In addition, when a hole is formed, a smear (resin residue) may be formed within the hole, but the shaping treatment above can remove this smear. The shaping treatment may be performed dry or wet. Specifically, the shaping treatment may be performed by a method comprising performing a swelling treatment with a swelling liquid, an oxidation treatment with an oxidizing agent, and a neutralization treatment with a neutralizing liquid on the insulating layer in this order. Typically, the formation of a hole, the shaping treatment, and the formation of a conductor layer are performed in this order.

[0340] In addition, the method for manufacturing the structure may include performing an annealing treatment on the insulating layer after forming the conductor layer. By performing the annealing treatment, the adhesion between the insulating layer and the conductor layer can be increased. The annealing treatment can be performed, for example, by heating at 150°C to 210°C for 20 minutes to 180 minutes.

[0341] (Specific example of manufacturing method)

[0342] Hereinafter, a preferred example of a method for manufacturing a structure (10) shown in FIG. 1 will be described. FIGS. 3 to 7 are schematic cross-sectional views for explaining the manufacturing process of a structure (10) according to an example. In the method for manufacturing a structure (10) according to this example, a resin composition layer (241 and 341) is placed on the chip side (100U) and the opposite side (100D) of a core substrate (100), and laminated to obtain an intermediate product (20) shown in FIG. 3. After that, the resin composition layer (241 and 341) is cured to form a chip-side insulating layer (211) and an opposite-side insulating layer (311) that do not contain a fiber substrate, as shown in FIG. 4. In addition, holes (221 and 321) are formed in the chip-side insulating layer (211) and the opposite-side insulating layer (311) as shown in FIG. 5, and conductor layers (231 and 331) are formed as shown in FIG. 6.

[0343] Afterwards, in the method of manufacturing the structure (10) according to this example, the lamination of resin composition layers, the formation of an insulating layer by curing the resin composition layers, the formation of holes, and the formation of a conductor layer are repeated to obtain an intermediate product (30) shown in FIG. 7. In this intermediate product (30), a chip-side insulating layer (212 to 213) is formed on the chip side (100U) of the core substrate (10) through a previously formed chip-side insulating layer (211). Additionally, an opposite-side insulating layer (312 to 323) is formed on the opposite side (100D) of the core substrate (10) through a previously formed opposite-side insulating layer (311). Holes (222 to 223 and 322 to 323) are formed within each insulating layer (212 to 213 and 312 to 313), and additionally, conductor layers (232 to 233 and 332 to 333) are formed on each insulating layer (212 to 213 and 312 to 313) and within the holes (222 to 223 and 322 to 323).

[0344] In addition, thereafter, in the method of manufacturing the structure (10) according to this example, a resin composition layer (not shown) is placed on a chip-side insulating layer (213) formed on a chip-side surface (100U), and a fiber-containing sheet (not shown) is placed on an opposite-side insulating layer (313) formed on an opposite-side surface (100D). Then, lamination is performed to form a resin composition layer on the chip-side surface (100U) with the chip-side insulating layers (211 to 213) interposed, and a fiber-containing sheet is formed on the opposite-side surface (100D) with the opposite-side insulating layers (311 to 313) interposed. After that, the resin composition layer and the fiber-containing sheet are cured to form a chip-side insulating layer (214) that does not contain fiber substrates and an opposite-side insulating layer (314) that includes an insulating layer. And, holes (224 and 324) are formed, and additionally, conductor layers (234 and 334) are formed to form a chip-side build-up layer (200) and an opposite-side build-up layer (300) as shown in FIG. 1. Thus, a structure (10) can be obtained.

[0345] As described above, the method for manufacturing a structure according to the present embodiment includes a process (ii) for forming an opposite insulating layer on the opposite side of a core substrate, wherein the process (ii) for forming an opposite insulating layer including a fiber substrate is included. Additionally, the method for manufacturing a structure according to the present embodiment may include a process (i) for forming a chip insulating layer on the chip side of a core substrate, wherein the process (i) for forming a chip insulating layer including a fiber substrate is included. At this time, the structure of the present invention described above can be manufactured by performing the process (i) and the process (ii) in such a way that at least one of the following conditions (1) and (2) is satisfied.

[0346] (1) The number of opposite insulating layers containing fiber substrates (400) in the opposite build-up layer (300) is greater than the number of chip insulating layers containing fiber substrates (400) in the chip build-up layer (200), and the “fiber substrate ratio based on the number of layers” in the opposite build-up layer (300) is within the above specific range.

[0347] (2) The total thickness of the opposite side insulation layer containing the fiber substrate (400) in the opposite side build-up layer (300) is greater than the total thickness of the chip side insulation layer containing the fiber substrate (400) in the chip side build-up layer (200), and the “fiber substrate content ratio based on thickness” in the opposite side build-up layer (300) is within the above specific range.

[0348] In one embodiment, with respect to the ease of satisfying at least one of the above conditions (1) and (2), the ratio of the number of steps (ii) forming the opposite insulating layer including the fiber substrate to the total number of steps (ii) forming the opposite insulating layer (100%) is typically 5% or more, preferably 8% or more, more preferably 12% or more, preferably 80% or less, more preferably 65% ​​or less, and more preferably 50% or less. Additionally, in one embodiment, with respect to the ease of satisfying at least one of the above conditions (1) and (2), the number of steps (ii) forming the opposite insulating layer including the fiber substrate is greater than the number of steps (i) forming the chip-side insulating layer including the fiber substrate.

[0349] Semiconductor chip packaging

[0350] A semiconductor chip can be mounted on the chip-side build-up layer of the above-described structure. A semiconductor chip package can be manufactured by a method including the process of mounting a semiconductor chip on the chip-side build-up layer of the structure in this manner.

[0351] FIG. 8 is a cross-sectional view schematically illustrating a semiconductor chip package (40) according to an embodiment of the present invention. As shown in FIG. 8, the semiconductor chip package (40) comprises a structure (10) and a semiconductor chip (500) mounted on a chip side surface (10U) which is the surface of the chip-side build-up layer (200) of the structure (10). The semiconductor chip (500) is generally mounted by a reflow method using solder. Accordingly, solder powder (510) may be provided between the semiconductor chip (500) and the structure (10). Typically, electrical connection between the conductor layer (not shown in FIG. 8) of the structure (10) and the semiconductor chip (500) is achieved by interposing the solder powder (510). Additionally, an underfill material (520) may be filled between the structure (10) and the semiconductor chip (500) as needed.

[0352] A mounting method for mounting a semiconductor chip (500) on a chip-side build-up layer (200) of a structure (10) typically includes placing the semiconductor chip (500) on the chip side (10U) of the structure (10). At this time, the semiconductor chip (500) is placed on the chip side (10U) of the structure (10) through solder powder (510). Below, a laminate having the structure (10) obtained in this way and the semiconductor chip (500) placed on the chip side (10U) may be referred to as an "intermediate laminate."

[0353] Afterward, the mounting method includes performing soldering by reflow processing. In the reflow processing, solder powder (510) is melted by heating, and the molten solder powder (510) is adhered to the structure (10) and the semiconductor chip (500). The reflow temperature is generally set above the melting point of the solder powder (510) and below the heat resistance temperature of the semiconductor chip (500), and the peak temperature is often set to about 260°C. Generally, the reflow processing is performed by placing the intermediate laminate into the reflow furnace and carrying it out in the reflow furnace. Accordingly, not only the solder powder (510), but also the structure (10) and the semiconductor chip (500) are heated to the above reflow temperature.

[0354] After that, the mounting method includes cooling the structure (10), semiconductor chip (500), and solder powder (510) heated as described above. This cooling is carried out, for example, by removing the intermediate laminate from the reflow furnace and cooling it. As the solder powder (510) solidifies due to cooling, the structure (10) and the semiconductor chip (500) are bonded through the solder powder (510). In this way, the semiconductor chip (500) is mounted on the chip side (10U) of the structure (10), and a semiconductor chip package (40) is obtained.

[0355] In the above-described mounting method, since heating for reflow processing and subsequent cooling are performed, expansion and contraction may occur within the structure (10). Below, this expansion and contraction will be explained with reference to drawings.

[0356] FIG. 9 is a cross-sectional view schematically showing an intermediate laminate (50) obtained in the process of a method for manufacturing a semiconductor chip package (40) according to an embodiment of the present invention. When the intermediate laminate (50) is heated in a reflow furnace, expansion stress is generated within the structure (10). Accordingly, the chip-side build-up layer (200) having chip-side insulating layers (211 to 214) tends to expand in the in-plane direction as indicated by arrow A1. Unless otherwise specified, the term "in-plane direction" refers to a direction perpendicular to the thickness direction. Additionally, the opposite-side build-up layer (300) having opposite-side insulating layers (311 to 314) tends to expand in the in-plane direction as indicated by arrow A2.

[0357] FIG. 10 is a cross-sectional view schematically illustrating a semiconductor chip package (40) according to an embodiment of the present invention. In the semiconductor chip package (40) obtained by cooling an intermediate laminate (50), shrinkage stress occurs within the structure (10) due to the cooling. Accordingly, the chip-side build-up layer (200) having chip-side insulating layers (211 to 214) tends to shrink in the in-plane direction as indicated by arrow A3. At this time, the semiconductor chip (500) is bonded to the chip side surface (10U) by solder powder (510). In addition, the semiconductor chip (500) typically has a small linear thermal expansion coefficient. Therefore, the shrinkage of the portion (250) of the chip-side build-up layer (200) covered by the semiconductor chip (500) is relatively small, and the expansion of the portion (260) of the chip-side build-up layer (200) not covered by the semiconductor chip (500) is relatively large. In addition, the opposite build-up layer (300) having the opposite insulating layer (311 to 314) tends to shrink in the in-plane direction as indicated by arrow A4. Normally, the entire opposite build-up layer (300) tends to shrink to the same degree.

[0358] Therefore, conventionally, there was a tendency for a difference in the degree of shrinkage between the chip-side build-up layer and the opposite-side build-up layer due to the influence of constraint by the semiconductor chip, so the structure was prone to warping after mounting the semiconductor chip. In addition, this warping tended to increase further when an underfill material (520) was filled between the structure (10) and the semiconductor chip (500).

[0359] In this regard, according to the structure (10) according to the present embodiment, which is provided with an insulating layer (opposite insulating layer) (314) including a fiber substrate (400) as described above, bending of the structure (10) after mounting the semiconductor chip (500) can be suppressed. Furthermore, according to the structure (10) according to the present embodiment, bending can be suppressed not only after mounting the semiconductor chip (500), but also before mounting the semiconductor chip on the structure (10).

[0360] Accordingly, according to the structure (10) of the present embodiment, bending of the structure (10) can be suppressed after mounting the semiconductor chip (500). This effect is beneficial in the manufacturing process of the actual semiconductor chip package (40).

[0361] If it is assumed that the bending of the structure can be suppressed only after the semiconductor chip is mounted, it is conceivable to pre-bend the structure before mounting the semiconductor chip to the extent that the bending can be offset. However, if the structure is bent before mounting the semiconductor chip in such a way, the handling of the structure may be reduced, or precise positional alignment of the semiconductor chip may become difficult.

[0362] In this regard, according to the structure (10) capable of suppressing bending after mounting the semiconductor chip (500), it is possible to suppress bending of the structure (10) after mounting the semiconductor chip (500) while achieving improved handling of the structure (10) before mounting the semiconductor chip (500) and smooth alignment of the semiconductor chip (500), thereby enabling the suppression of bending of the semiconductor chip package (40). Accordingly, smooth manufacturing of the semiconductor chip package (40) can be achieved.

[0363] From the perspective of suppressing warping after reflow processing, it is desirable to employ an insulating layer containing a fiber substrate that has a linear thermal expansion coefficient and a tensile modulus that satisfy the aforementioned desirable requirements in a high-temperature environment during reflow processing. If the insulating layer containing the fiber substrate has a small linear thermal expansion coefficient in a high-temperature environment, indicated by a high-temperature measurement range, it can suppress the generation of stress caused by expansion and contraction. Furthermore, if the insulating layer containing the fiber substrate has a large tensile modulus in a high-temperature environment, such as 260°C, it can resist stress and suppress deformation of the structure. Having both a small linear thermal expansion coefficient and a large tensile modulus in such a high-temperature environment is generally difficult to achieve with an insulating layer that does not contain a fiber substrate. In the above-described embodiment, by appropriately combining an insulating layer that does not include a fiber substrate and an insulating layer that includes a fiber substrate having different characteristics from the insulating layer that does not include a fiber substrate (specifically, a coefficient of linear thermal expansion and a tensile modulus in a high-temperature environment), the bending of the semiconductor chip (500) after mounting can be effectively suppressed.

[0364] As described above, the stress during the reflow process influences the occurrence of bending. Therefore, if the insulating layer can absorb and reduce this stress, the bending of the structure (10) can be effectively reduced. Typically, when the insulating layer has a glass transition temperature lower than the reflow temperature, the insulating layer becomes flexible during the reflow process and can absorb stress, thus enabling effective reduction of bending. In this regard, it is preferable that the glass transition temperature of the insulating layer, such as the chip-side insulating layer and the opposite-side insulating layer, be lower than the reflow temperature. Specifically, it is preferable that the glass transition temperature of the insulating layer be lower than the peak temperature of the reflow process. In one example, the range of the difference between the peak temperature of the reflow process and the glass transition temperature of the insulating layer (including both the insulating layer containing the fiber substrate and the insulating layer not containing the fiber substrate) is preferably 10°C or higher, more preferably 20°C or higher, even more preferably 30°C or higher, preferably 160°C or lower, more preferably 140°C or lower, and even more preferably 120°C or lower. Here, the term "glass transition temperature of the insulating layer" includes any glass transition temperature of the chip-side insulating layer containing the fiber substrate, the chip-side insulating layer not containing the fiber substrate, the opposite-side insulating layer containing the fiber substrate, and the opposite-side insulating layer not containing the fiber substrate. In addition, from the same perspective, it is preferable that the glass transition temperature of the cured sample of (a1) the fiber-containing sheet for forming the insulating layer containing the fiber substrate, and the glass transition temperature of the cured sample of (b1) the resin composition layer for forming the insulating layer not containing the fiber substrate, are also lower than the peak temperature of the reflow process. In addition, it is desirable that the range of difference between the peak temperature of the reflow treatment and the glass transition temperature of these cured samples be the same as the range of difference between the peak temperature of the reflow treatment and the glass transition temperature of the insulating layer described above.

[0365] In addition, from the perspective of effectively suppressing warping, it is desirable for each insulating layer to become flexible at a timing close to the heating period during the reflow process, and also desirable for each insulating layer to become rigid at a timing close to the cooling period after the reflow process. Accordingly, it is desirable for the glass transition temperature of each insulating layer to be close as described above.

[0366] As described above, the structure (10) according to the present embodiment can suppress bending after mounting the semiconductor chip (500), so the amount of bending can be reduced. In one example, the range of the amount of bending of the structure (10) after mounting the semiconductor chip (500) is preferably 500 μm or less, more preferably 400 μm or less, even more preferably 300 μm or less, and particularly preferably 200 μm or less. The lower limit is ideally 0 μm, but it may be 10 μm or more or 50 μm or more.

[0367] Additionally, preferably, the structure (10) according to the present embodiment can suppress warping before mounting the semiconductor chip (500), so the amount of warping before the reflow process can be reduced. In one example, the range of the amount of warping of the structure (10) at a temperature of 35°C before mounting the semiconductor chip (500) is preferably 1000 μm or less, more preferably 800 μm or less, even more preferably 600 μm or less, and particularly preferably 500 μm or less. The lower limit is ideally 0 μm, but it may be 100 μm or more or 200 μm or more.

[0368] Additionally, preferably, the structure (10) according to the present embodiment can reduce the amount of warping during the reflow process. In one example, the range of warping of the structure (10) at a temperature of 260°C before mounting the semiconductor chip (500) is preferably 500 μm or less, more preferably 400 μm or less, even more preferably 300 μm or less, and particularly preferably 200 μm or less. The lower limit is ideally 0 μm, but may be 10 μm or more or 50 μm or more.

[0369] The amount of bending of the structure (10) can be measured using a shadow moiré measuring device in accordance with JEITA EDX-7311-24 of the Electronic Information Technology Industry Association standard. The specific measurement method may adopt the method described in the following examples.

[0370] The semiconductor chip package (40) may additionally have any element in combination with the structure (10) and the semiconductor chip (500). For example, the semiconductor chip package (40) may have a solder resist layer (not shown) that seals the semiconductor chip (500). Accordingly, the manufacturing method of the semiconductor chip package (40) may include a process of additionally forming a solder resist layer in combination with the process of mounting the semiconductor chip (500) on the structure (10). In addition, the manufacturing method of the semiconductor chip package (40) may include a process of filling an underfill material (520) between the structure (10) and the semiconductor chip (500).

[0371] In addition, in the above-described embodiment, an example was shown in which holes (221 to 224 and 321 to 324) are formed in the insulating layers (211 to 214 and 311 to 314), but some or all of these holes (221 to 224 and 321 to 324) may not be formed. In addition, in the above-described embodiment, an example was shown in which conductor layers (231 to 234 and 331 to 334) are formed, but some or all of these conductor layers (231 to 234 and 331 to 334) may not be formed.

[0372] Semiconductor Device

[0373] The semiconductor chip package described above can be used in the manufacture of a semiconductor device. The semiconductor device comprises the semiconductor chip package described above. Typically, the semiconductor device comprises a circuit board and a semiconductor chip package mounted on the circuit board. Examples of semiconductor devices include various semiconductor devices used in electrical products (e.g., computers, mobile phones, smartphones, tablet devices, wearable devices, digital cameras, medical devices, and TVs, etc.) and vehicles (e.g., motorcycles, automobiles, trains, ships, and aircraft, etc.).

[0374] A semiconductor device may be manufactured, for example, by a manufacturing method comprising a process of mounting the above-described semiconductor chip package onto a wiring board. As a specific example, a semiconductor device may be manufactured by mounting a semiconductor chip package onto a suitable wiring board to obtain a mounting board, and then placing this mounting board on another component constituting the semiconductor device.

[0375] <Resin Composition>

[0376] Hereinafter, a resin composition used for forming the insulation layer described above will be described. The resin composition used for forming the insulation layer may be one capable of forming the insulation layer described above upon curing. Generally, a thermosetting resin composition is used as the resin composition. The specific composition of this resin composition may be selected within a range capable of forming the insulation layer described above after curing. Hereinafter, the composition of a resin composition according to a preferred example will be described.

[0377] Since the resin composition has thermosetting properties, it typically includes (A) a thermosetting resin. Examples of (A) thermosetting resins include epoxy resin, phenol resin, active ester resin, benzoxazine resin, cyanate ester resin, carbodiimide resin, acid anhydride resin, amine resin, radical polymerizable resin, etc. One type of thermosetting resin may be used alone, or two or more types may be used in combination.

[0378] Among these, (A) the thermosetting resin preferably includes an epoxy resin. The epoxy resin may be a curable resin having epoxy groups. As epoxy resins, for example, bisphenol A type epoxy resin, bisphenol C type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, bisphenol AF type epoxy resin, dicyclopentadiene type epoxy resin, trisphenol type epoxy resin, naphthol novolak type epoxy resin, phenol novolak type epoxy resin, tert-butyl-catechol type epoxy resin, naphthalene type epoxy resin, naphthol type epoxy resin, anthracene type epoxy resin, glycidylamine type epoxy resin, glycidyl ester type epoxy resin, cresol novolak type epoxy resin, phenol aralkyl type epoxy resin, biphenyl type epoxy resin, linear aliphatic epoxy resin, epoxy resin having a butadiene structure, alicyclic epoxy resin, heterocyclic epoxy resin, spiro-ring containing epoxy resin, cyclohexane type epoxy resin, cyclohexanedimethanol type epoxy resin, naphthylene ether type epoxy resin, trimethylol type epoxy resin, tetraphenylethane type epoxy resin, Examples include isocyanurate-type epoxy resins and imide-backed bisphenol-type epoxy resins. Biphenyl-type epoxy resins refer to epoxy resins having a biphenyl structure, wherein the biphenyl structure may have substituents such as alkyl groups, alkoxy groups, or aryl groups. Accordingly, bixylenol-type epoxy resins and biphenylalkyl-type epoxy resins may be included in biphenyl-type epoxy resins. One type of epoxy resin may be used alone, or two or more types may be used in combination.

[0379] From the perspective of obtaining a cured product with excellent heat resistance, it is desirable for the epoxy resin to include an epoxy resin containing an aromatic structure. An aromatic structure is a chemical structure generally defined as aromatic, and includes polycyclic aromatics and aromatic heterocyclic groups. As epoxy resins containing an aromatic structure, for example, bisphenol A type epoxy resin, bisphenol C type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, bisphenol AF type epoxy resin, dicyclopentadiene type epoxy resin, trisphenol type epoxy resin, naphthol novolak type epoxy resin, phenol novolak type epoxy resin, tert-butyl-catechol type epoxy resin, naphthalene type epoxy resin, naphthol type epoxy resin, anthracene type epoxy resin, bicyllenol type epoxy resin, glycidylamine type epoxy resin having an aromatic structure, glycidyl ester type epoxy resin having an aromatic structure, cresol novolak type epoxy resin, biphenyl type epoxy resin, linear aliphatic epoxy resin having an aromatic structure, epoxy resin having a butadiene structure having an aromatic structure, alicyclic epoxy resin having an aromatic structure, heterocyclic epoxy resin, spiro-ring containing epoxy resin having an aromatic structure, cyclohexanedimethanol type epoxy resin having an aromatic structure, Examples include naphthylene ether-type epoxy resins, trimethylol-type epoxy resins having an aromatic structure, and tetraphenylethane-type epoxy resins having an aromatic structure. Among these, bisphenol A-type epoxy resins, naphthalene-type epoxy resins, and biphenyl-type epoxy resins are preferred.

[0380] It is preferable that the epoxy resin comprises an epoxy resin having two or more epoxy groups in one molecule. With respect to 100 mass% of the non-volatile component of the epoxy resin, the ratio of the epoxy resin having two or more epoxy groups in one molecule is preferably 50 mass% or more, more preferably 60 mass% or more, and even more preferably 70 mass% or more.

[0381] Epoxy resins can be classified into epoxy resins that are in a liquid state at a temperature of 20°C (hereinafter referred to as "liquid epoxy resin") and epoxy resins that are in a solid state at a temperature of 20°C (hereinafter referred to as "solid epoxy resin"). The epoxy resins may contain only liquid epoxy resins, may contain only solid epoxy resins, or may contain a combination of liquid epoxy resins and solid epoxy resins.

[0382] As a liquid epoxy resin, a liquid epoxy resin having two or more epoxy groups in one molecule is preferred. As a liquid epoxy resin, bisphenol A type epoxy resin, bisphenol C type epoxy resin, bisphenol F type epoxy resin, bisphenol AF type epoxy resin, naphthalene type epoxy resin, glycidyl ester type epoxy resin, glycidylamine type epoxy resin, phenol novolak type epoxy resin, alicyclic epoxy resin having an ester backbone, cyclohexane type epoxy resin, cyclohexanedimethanol type epoxy resin, and epoxy resin having a butadiene structure are preferred; bisphenol A type epoxy resin is more preferred.

[0383] Specific examples of liquid epoxy resins include “HP-4032”, “HP-4032-D”, and “HP-4032-SS” (naphthalene-type epoxy resins) manufactured by DIC; “828US”, “828EL”, “jER828”, “jER828EL”, “825”, and “Epicot 828EL” (bisphenol A-type epoxy resins) manufactured by Mitsubishi Chemical; “jER807” and “1750” (bisphenol F-type epoxy resins) manufactured by Mitsubishi Chemical; “jER152” (phenol novolak-type epoxy resin) manufactured by Mitsubishi Chemical; “630”, “630LSD”, and “604” (glycidylamine-type epoxy resins) manufactured by Mitsubishi Chemical; and “ED-523T” (glycirol-type epoxy resin) manufactured by ADEKA. "EP-3950L" and "EP-3980S" manufactured by ADEKA (glycidylamine-type epoxy resin); "EP-4088S" manufactured by ADEKA (dicyclopentadiene-type epoxy resin); "ED-506" manufactured by ADEKA (polypropylene glycol-type epoxy resin); "ZX1059" manufactured by Nittetsu Chemical & Materials (mixture of bisphenol A-type epoxy resin and bisphenol F-type epoxy resin); "EX-721" manufactured by Nagase Chemtex (glycidyl ester-type epoxy resin); "Celoxide 2021P" manufactured by Daicel (alicyclic epoxy resin having an ester backbone); "PB-3600" manufactured by Daicel, and "JP-100" and "JP-200" manufactured by Nippon Soda (epoxy resin having a butadiene structure); Examples include "ZX1658" and "ZX1658GS" (liquid 1,4-glycidylcyclohexane type epoxy resin) manufactured by Nittetsu Chemical & Material.

[0384] As for the solid-phase epoxy resin, a solid-phase epoxy resin having three or more epoxy groups in one molecule is preferred, and an aromatic solid-phase epoxy resin having three or more epoxy groups in one molecule is more preferred. As for the solid-phase epoxy resin, bixylenol-type epoxy resin, naphthalene-type epoxy resin, naphthalene-type tetrafunctional epoxy resin, naphthol novolak-type epoxy resin, cresol novolak-type epoxy resin, dicyclopentadiene-type epoxy resin, trisphenol-type epoxy resin, naphthol-type epoxy resin, biphenyl-type epoxy resin, naphtylene ether-type epoxy resin, anthracene-type epoxy resin, bisphenol A-type epoxy resin, bisphenol AF-type epoxy resin, phenol-aralkyl-type epoxy resin, tetraphenylethane-type epoxy resin, and imide-skeleton-containing bisphenol-type epoxy resin are preferred; biphenyl-type epoxy resin and naphthalene-type tetrafunctional epoxy resin are more preferred.

[0385] Specific examples of solid-phase epoxy resins include “HP4032H” (naphthalene-type epoxy resin) manufactured by DIC; “HP-4700” and “HP-4710” (naphthalene-type tetrafunctional epoxy resins) manufactured by DIC; “N-690” (cresol novolak-type epoxy resin) manufactured by DIC; “N-695” (cresol novolak-type epoxy resin) manufactured by DIC; and “HP-7200”, “HP-7200HH”, “HP-7200H”, and “HP-7200L” (dicyclopentadiene-type epoxy resins) manufactured by DIC. "EXA-7311", "EXA-7311-G3", "EXA-7311-G4", "EXA-7311-G4S", "HP-6000", "HP-6000L" (naphtylene ether type epoxy resin) manufactured by DIC; "EPPN-502H" (trisphenol type epoxy resin) manufactured by Nippon Kayakusha; "NC7000L" (naphthol novolak type epoxy resin) manufactured by Nippon Kayakusha; "NC3000H", "NC3000", "NC3000L", "NC3000FH", "NC3100" (biphenyl type epoxy resin) manufactured by Nippon Kayakusha; "ESN475V", "ESN4100V", and "ESN-4100VEK75" (naphthalene-type epoxy resins) manufactured by Nittetsu Chemical & Materials; "ESN485" (naphthol-type epoxy resin) manufactured by Nittetsu Chemical & Materials; "ESN375" (dihydroxynaphthalene-type epoxy resin) manufactured by Nittetsu Chemical & Materials; "YX4000H", "YX4000", "YX4000HK", and "YL7890" (bicylenol-type epoxy resins) manufactured by Mitsubishi Chemical; "YL6121" (biphenyl-type epoxy resin) manufactured by Mitsubishi Chemical; and "YX8800" (anthracene-type epoxy resin) manufactured by Mitsubishi Chemical. "YX7700" (phenol-aralkyl type epoxy resin) manufactured by Mitsubishi Chemical Corporation; "PG-100" and "CG-500" manufactured by Osaka Gas Chemical Corporation; "YX7760" (bisphenol-AF type epoxy resin) manufactured by Mitsubishi Chemical Corporation; "YL7800" (fluorene type epoxy resin) manufactured by Mitsubishi Chemical Corporation;Examples include “jER1010” (bisphenol A type epoxy resin) manufactured by Mitsubishi Chemical Corporation; “jER1031S” (tetraphenylethane type epoxy resin) manufactured by Mitsubishi Chemical Corporation; and “WHR991S” (imide backbone containing bisphenol type epoxy resin) manufactured by Nippon Kayaku Corporation.

[0386] When using a combination of liquid epoxy resin and solid epoxy resin, the mass ratio of the two (liquid epoxy resin:solid epoxy resin) is preferably 20:1 to 1:20, more preferably 10:1 to 1:10, and particularly preferably 7:1 to 1:7.

[0387] The range of epoxy equivalents of the epoxy resin is preferably 50 g / eq. to 5,000 g / eq., more preferably 60 g / eq. to 3,000 g / eq., even more preferably 80 g / eq. to 2,000 g / eq., and particularly preferably 110 g / eq. to 1,000 g / eq. Epoxy equivalents represent the mass of the resin per epoxy group equivalent. These epoxy equivalents can be measured according to JIS K7236.

[0388] The range of the amount of epoxy resin is, with respect to 100 mass% of the resin component of the resin composition, preferably 10 mass% or more, more preferably 20 mass% or more, even more preferably 30 mass% or more, even more preferably 40 mass% or more, preferably 80 mass% or less, more preferably 70 mass% or less, even more preferably 60 mass% or less, and even more preferably 50 mass% or less. Unless otherwise specified, the resin component of the resin composition refers to the component of the non-volatile component of the resin composition excluding (B) inorganic filler. In addition, unless otherwise specified, the non-volatile component of the resin composition refers to the component of the resin composition excluding (F) solvent.

[0389] (A) When the thermosetting resin includes an epoxy resin, it is preferable that the thermosetting resin includes a resin capable of reacting with the epoxy resin to form a bond. The "resin capable of reacting with the epoxy resin to form a bond" may be referred to as a "curing agent" below. Examples of curing agents include phenol resin, benzoxazine resin, cyanate ester resin, carbodiimide resin, acid anhydride resin, and amine resin. One type of curing agent may be used alone, or two or more types may be used in combination. Among these, phenol resin and active ester resin are preferred.

[0390] As for the phenolic resin, a resin having one or more, preferably two or more, hydroxyl groups (phenolic hydroxyl groups) bonded to aromatic rings such as benzene rings and naphthalene rings in one molecule may be used. From the perspective of heat resistance and water resistance, a phenolic resin having a novolak structure is preferred. Furthermore, from the perspective of adhesion, a nitrogen-containing phenolic resin is preferred, and a triazine-frame-containing phenolic resin is more preferred. Among these, a triazine-frame-containing phenolic novolak resin is preferred from the perspective of highly satisfying heat resistance, water resistance, and adhesion.

[0391] Specific examples of phenolic resins include “MEH-7700”, “MEH-7810”, “MEH-7851”, and “MEH-8000H” manufactured by Meiwa Kasei Co., Ltd.; “NHN”, “CBN”, and “GPH” manufactured by Nippon Kayaku Co., Ltd.; and “SN-170”, “SN-180”, “SN-190”, “SN-475”, “SN-485”, “SN-495”, “SN-495V”, “SN-375”, and “SN-395” manufactured by Nittetsu Chemical & Material Co., Ltd. Examples include the “TD-2090”, “TD-2090-60M”, “LA-7052”, “LA-7054”, “LA-1356”, “LA-3018”, “LA-3018-50P”, “LA-1356”, “TD2090”, and “TD-2090-60M” manufactured by DIC; and the “GDP-6115L”, “GDP-6115H”, and “ELPC75” manufactured by Gunei Kagaku Co., Ltd.

[0392] As an active ester resin, a resin containing typically one or more, preferably two or more, active ester groups per molecule may be used. An active ester group refers to a group formed by an ester bond directly bonded to an aromatic ring. Here, the term "ester bond" may include thioester bonds (-C(=O)-S-) in a broad sense. From the perspective of improving heat resistance, an ester bond (-C(=O)-O-) in a narrow sense formed by a carbonyloxy group is preferred. Furthermore, this active ester group includes not only ester bonds included in the structure of "aromatic carbon-C(=O)-O-aromatic carbon," but also ester bonds included in the structure of "aliphatic carbon-C(=O)-O-aromatic carbon" insofar as they can react with an epoxy group to form a bond. Additionally, the term "aromatic carbon" refers to a carbon atom constituting the aromatic ring.

[0393] As an active ester resin, compounds having two or more highly reactive ester groups in one molecule, such as phenol ester compounds, thiophenol ester compounds, N-hydroxyamine ester compounds, and esters of heterocyclic hydroxy compounds, are preferred.

[0394] It is preferable that the active ester resin be obtained by a condensation reaction between a carboxylic acid compound and / or a thiocarboxylic acid compound and a hydroxyl compound and / or a thiol compound. Particularly from the perspective of improving heat resistance, an active ester resin obtained from a carboxylic acid compound and a hydroxyl compound is preferred, and an active ester resin obtained from a carboxylic acid compound and a phenol compound and / or naphthol compound is more preferred. Examples of carboxylic acid compounds include benzoic acid, acetic acid, succinic acid, maleic acid, itaconic acid, phthalic acid, isophthalic acid, terephthalic acid, pyromellitic acid, etc. In addition, examples of phenol compounds or naphthol compounds include hydroquinone, resorcinol, bisphenol A, bisphenol F, bisphenol S, phenolphthalein, methylated bisphenol A, methylated bisphenol F, methylated bisphenol S, phenol, o-cresol, m-cresol, p-cresol, catechol, α-naphthol, β-naphthol, 1,5-dihydroxynaphthalene, 1,6-dihydroxynaphthalene, 2,6-dihydroxynaphthalene, dihydroxybenzophenone, trihydroxybenzophenone, tetrahydroxybenzophenone, phloroglucine, benzenetriol, dicyclopentadiene-type diphenol compounds, phenol novolac, etc. Here, "dicyclopentadiene-type diphenol compound" refers to a diphenol compound obtained by condensing two molecules of phenol into one molecule of dicyclopentadiene.

[0395] Specifically, as the active ester resin, a dicyclopentadiene-type active ester resin, a naphthalene-type active ester resin containing a naphthalene structure, an active ester resin containing an acetylated compound of phenol novolak, and an active ester resin containing a benzoylated compound of phenol novolak are preferred. As the dicyclopentadiene-type active ester resin, an active ester resin containing a dicyclopentadiene-type diphenol structure is preferred.

[0396] As commercially available active ester resins, for example, active ester resins containing a dicyclopentadiene-type diphenol structure such as “EXB9451”, “EXB9460”, “EXB9460S”, “HPC-8000L-65TM”, “HPC-8000-65T”, “EXB-8000H”, “EXB-8000L-65TM” (manufactured by DIC); active ester resins containing a naphthalene structure such as “EXB-9416-70BK”, “EXB-8100L-65T”, “HPC-8150-62T”, “EXB-8150L-65T”, “EXB-8100L-65T”, “EXB-8” (manufactured by DIC); and phosphorus-containing active ester resins such as “EXB9401” (manufactured by DIC); Examples of active ester resins containing acetylated phenol novolak include “DC808” (manufactured by Mitsubishi Chemical); active ester resins containing benzoylated phenol novolak include “YLH1026”, “YLH1030”, “YLH1048” (manufactured by Mitsubishi Chemical), and “EXB-8500-65T” (manufactured by DIC); and active ester resins containing stylyl groups and naphthalene structures include “PC1300-02-65T” and “PC1300-02-65MA” (manufactured by Airwater).

[0397] The active group equivalent of the curing agent is preferably 50 g / eq. to 3,000 g / eq., more preferably 100 g / eq. to 1,000 g / eq., even more preferably 100 g / eq. to 500 g / eq., and particularly preferably 100 g / eq. to 300 g / eq. The active group equivalent represents the mass of the resin per 1 equivalent of the active group. In addition, the active group of the curing agent refers to a group capable of reacting with the epoxy group of the epoxy resin, and examples include phenolic hydroxyl groups and active ester groups.

[0398] The amount of curing agent is preferably 10 mass% or more, more preferably 20 mass% or more, even more preferably 30 mass% or more, even more preferably 40 mass% or more, with respect to 100 mass% of the resin component of the resin composition, and preferably 80 mass% or less, more preferably 70 mass% or less, even more preferably 60 mass% or less, and even more preferably 50 mass% or less.

[0399] The number of active groups of the curing agent is preferably 0.01 or more, more preferably 0.1 or more, even more preferably 0.5 or more, preferably 3 or less, more preferably 2 or less, and even more preferably 1 or less, when the number of epoxy groups of the epoxy resin is set to 1. The "number of epoxy groups of the epoxy resin" of the resin composition refers to the sum of all values ​​obtained by dividing the mass of the non-volatile components of the epoxy resin present in the resin composition by their epoxy equivalents. In addition, the "number of active groups of the curing agent" of the resin composition refers to the sum of all values ​​obtained by dividing the mass of the non-volatile components of the curing agent present in the resin composition by their active group equivalents.

[0400] The range of the weight average molecular weight (Mw) of (A) thermosetting resins, such as epoxy resins and curing agents, is preferably 100 to 5,000, more preferably 250 to 3,000, and even more preferably 400 to 1,500. The weight average molecular weight can be measured as a polystyrene equivalent value by gel permeation chromatography (GPC).

[0401] (A) The amount of thermosetting resin is preferably 10 mass% or more, preferably 12 mass% or more, more preferably 15 mass% or more, with respect to 100 mass% of the non-volatile component of the resin composition, preferably 80 mass% or less, more preferably 70 mass% or less, more preferably 60 mass% or less.

[0402] In particular, the first resin composition and the second resin composition used to form an insulating layer including a fiber substrate preferably contain a relatively large amount of (A) thermosetting resin. In the first resin composition and the second resin composition according to one example, the range of the amount of (A) thermosetting resin with respect to 100 mass% of the resin composition is preferably 15 mass% or more, more preferably 20 mass% or more, even more preferably 25 mass% or more, preferably 80 mass% or less, more preferably 70 mass% or less, and even more preferably 60 mass% or less.

[0403] On the other hand, the third resin composition used to form an insulating layer that does not include a fiber substrate preferably contains a relatively small amount of (A) thermosetting resin. In the third resin composition according to one example, the range of the amount of (A) thermosetting resin with respect to 100 mass% of the resin composition is preferably 10 mass% or more, preferably 12 mass% or more, more preferably 15 mass% or more, preferably 80 mass% or less, more preferably 70 mass% or less, and even more preferably 60 mass% or less.

[0404] It is preferable that the resin composition further comprises (B) an inorganic filler in combination with (A) a thermosetting resin. (B) The inorganic filler is a particle of an inorganic material. Accordingly, (B) the inorganic filler is included in the resin composition in the form of particles, and is typically included in the cured product of the resin composition while maintaining the state of the particles.

[0405] (B) As an inorganic material forming an inorganic filler, an inorganic compound is typically used. (B) Examples of materials for the inorganic filler include silica, alumina, glass, cordierite, silicon oxide, barium sulfate, barium carbonate, talc, clay, mica powder, zinc oxide, hydrotalcite, boehmite, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, magnesium oxide, boron nitride, aluminum nitride, manganese nitride, aluminum borate, strontium carbonate, strontium titanate, calcium titanate, magnesium titanate, bismuth titanate, titanium oxide, zirconium oxide, barium titanate, barium zirconate titanate, barium zirconate, calcium zirconate, zirconium phosphate, and zirconium tungstate phosphate. Among these, silica and alumina are suitable, and silica is particularly suitable. Therefore, (B) the inorganic filler preferably contains silica, but may contain only silica. Examples of silica include amorphous silica, fused silica, crystalline silica, synthetic silica, hollow silica, etc. In addition, spherical silica is preferred as silica. Since the above inorganic materials generally have insulating properties, (B) the inorganic filler also typically has insulating properties. (B) the inorganic filler may be used as a single type or in combination of two or more types.

[0406] (B) Examples of commercially available inorganic fillers include, for instance, “SP60-05” and “SP507-05” manufactured by Nittetsu Chemical & Material Co., Ltd.; “YC100C”, “YA050C”, “YA050C-MJE”, “YA010C”, “SC2500SQ”, “SO-C4”, “SO-C2”, and “SO-C1” manufactured by Adomatex Co., Ltd.; “UFP-30”, “DAW-03”, and “FB-105FD” manufactured by Denka Co., Ltd.; “Silfil NSS-3N”, “Silfil NSS-4N” and “Silfil NSS-5N” manufactured by Tokuyama Co., Ltd.; and “Cellspheres” and “MGH-005” manufactured by Taiheiyo Cement Co., Ltd.

[0407] (B) The average particle diameter of the inorganic filler is preferably 0.01 μm or more, more preferably 0.05 μm or more, even more preferably 0.1 μm or more, preferably 10 μm or less, more preferably 5 μm or less, even more preferably 3 μm or less, and even more preferably 1 μm or less.

[0408] (B) The average particle diameter of the inorganic filler can be measured by a laser diffraction scattering method based on the Mie scattering theory. Specifically, the average particle diameter can be measured by creating a volume-based particle diameter distribution of the inorganic filler using a laser diffraction scattering particle diameter distribution measuring device and taking the intermediate diameter as the average particle diameter. For the measurement sample, 100 mg of inorganic filler and 10 g of methyl ethyl ketone can be weighed into a vial and dispersed by ultrasound for 10 minutes. Using a laser diffraction particle diameter distribution measuring device, the wavelength of the light source used is set to blue and red, and the volume-based particle diameter distribution of the inorganic filler is measured using a flow cell method. From the obtained particle diameter distribution, the average particle diameter can be calculated as the intermediate diameter. Examples of laser diffraction particle diameter distribution measuring devices include the "LA-960" manufactured by Horiba Sesakusho Co., Ltd.

[0409] (B) The specific surface area of ​​the inorganic filler is preferably 0.1 m² / g or more, more preferably 0.5 m² / g or more, even more preferably 1 m² / g or more, particularly preferably 3 m² / g or more, preferably 100 m² / g or less, more preferably 70 m² / g or less, even more preferably 50 m² / g or less, and particularly preferably 40 m² / g or less. (B) The specific surface area of ​​the inorganic filler can be measured by adsorbing nitrogen gas onto the surface of a sample using a specific surface area measuring device (Macsorb HM-1210 manufactured by Mounttec) according to the BET method, and calculating the specific surface area using the BET multi-point method.

[0410] (B) It is desirable that the inorganic filler be treated with a surface treatment agent to improve moisture resistance and dispersibility. Examples of surface treatment agents include fluorine-containing silane coupling agents, aminosilane-based coupling agents, epoxysilane-based coupling agents, mercaptosilane-based coupling agents, silane-based coupling agents, alkoxysilanes, organosilazanes, titanate-based coupling agents, etc. One type of surface treatment agent may be used alone, or two or more types may be used in combination.

[0411] As commercially available surface treatment agents, for example, "KBM403" (3-glycidoxypropyltrimethoxysilane) manufactured by Shin-Etsu Kagaku Kogyo Co., Ltd., "KBM803" (3-mercaptopropyltrimethoxysilane) manufactured by Shin-Etsu Kagaku Kogyo Co., Ltd., "KBE903" (3-aminopropyltriethoxysilane) manufactured by Shin-Etsu Kagaku Kogyo Co., Ltd., "KBM573" (N-phenyl-3-aminopropyltrimethoxysilane) manufactured by Shin-Etsu Kagaku Kogyo Co., Ltd., "SZ-31" (hexamethyldisilazane) manufactured by Shin-Etsu Kagaku Kogyo Co., Ltd., "KBM103" (phenyltrimethoxysilane) manufactured by Shin-Etsu Kagaku Kogyo Co., Ltd., "KBM-4803" (long-chain epoxy-type silane coupling agent) manufactured by Shin-Etsu Kagaku Kogyo Co., Ltd. Examples include “KBM-7103” (3,3,3-trifluoropropyltrimethoxysilane).

[0412] The degree of surface treatment by the surface treatment agent is preferably within a specific range from the perspective of improving the dispersibility of the inorganic filler. Specifically, 100 mass% of the inorganic filler is preferably surface-treated with 0.2 mass% to 5 mass% of a surface treatment agent, more preferably surface-treated with 0.2 mass% to 3 mass% of a surface treatment agent, and even more preferably surface-treated with 0.3 mass% to 2 mass% of a surface treatment agent.

[0413] The degree of surface treatment by a surface treatment agent can be evaluated by the carbon content per unit surface area of ​​the inorganic filler. From the perspective of improving the dispersibility of the inorganic filler, the carbon content per unit surface area of ​​the inorganic filler is preferably 0.02 mg / m² or more, more preferably 0.1 mg / m² or more, and even more preferably 0.2 mg / m² or more. Meanwhile, from the perspective of suppressing the increase in melt viscosity of the resin composition, it is preferably 1.0 mg / m² or less, more preferably 0.8 mg / m² or less, and even more preferably 0.5 mg / m² or less.

[0414] (B) The carbon content per unit surface area of ​​the inorganic filler can be measured after the inorganic filler is cleaned with a solvent (e.g., methyl ethyl ketone (MEK)) following surface treatment. Specifically, a sufficient amount of MEK is added as a solvent to the inorganic filler surface-treated with a surface treatment agent, and ultrasonically cleaned at 25°C for 5 minutes. After removing the supernatant and drying the solids, the carbon content per unit surface area of ​​the inorganic filler can be measured using a carbon analyzer. As a carbon analyzer, the "EMIA-320V" manufactured by Horiba Sesakusho Co., Ltd. can be used.

[0415] (B) The amount of inorganic filler is preferably 10 mass% or more, preferably 20 mass% or more, more preferably 30 mass% or more, with respect to 100 mass% of the non-volatile component of the resin composition, preferably 90 mass% or less, more preferably 80 mass% or less, and more preferably 70 mass% or less.

[0416] In particular, the first resin composition and the second resin composition used to form an insulating layer including a fiber substrate preferably contain a relatively small amount of (B) inorganic filler. In the first resin composition and the second resin composition according to one example, the range of the amount of (B) inorganic filler with respect to 100 mass% of the resin composition is preferably 10 mass% or more, preferably 20 mass% or more, more preferably 30 mass% or more, preferably 80 mass% or less, more preferably 75 mass% or less, and even more preferably 70 mass% or less.

[0417] On the other hand, the third resin composition used to form an insulating layer that does not include a fiber substrate preferably contains a relatively large amount of (B) inorganic filler. In the third resin composition according to one example, the range of the amount of (B) inorganic filler with respect to 100 mass% of the resin composition is preferably 20 mass% or more, more preferably 30 mass% or more, even more preferably 40 mass% or more, preferably 90 mass% or less, more preferably 85 mass% or less, and even more preferably 80 mass% or less.

[0418] The resin composition may include (C) a curing accelerator. (C) The curing accelerator can act as a catalyst in the reaction of (A) the thermosetting resin to promote the curing of the resin composition. Examples of (C) curing accelerators include phosphorus-based curing accelerators, urea-based curing accelerators, guanidine-based curing accelerators, imidazole-based curing accelerators, metal-based curing accelerators, amine-based curing accelerators, etc. (C) The curing accelerator may be used alone or in combination of two or more types. Among these, imidazole-based curing accelerators and amine-based curing accelerators are preferred.

[0419] As imidazole-based curing accelerators, for example, 2-methylimidazole, 2-undecylimidazole, 2-heptadecylimidazole, 1,2-dimethylimidazole, 2-ethyl-4-methylimidazole, 1,2-dimethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-phenyl-4-methylimidazole, 1-benzyl-2-methylimidazole, 1-benzyl-2-phenylimidazole, 1-cyanoethyl-2-methylimidazole, 1-cyanoethyl-2-undecylimidazole, 1-cyanoethyl-2-ethyl-4-methylimidazole, 1-cyanoethyl-2-phenylimidazole, 1-cyanoethyl-2-undecylimidazolium trimellitrate, 1-Cyanoethyl-2-phenylimidazolium trimellitate, 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine, 2,4-diamino-6-[2'-undecylimidazolyl-(1')]-ethyl-s-triazine, 2,4-diamino-6-[2'-ethyl-4'-methylimidazolyl-(1')]-ethyl-s-triazine, 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine isocyanuric acid adduct, 2-phenylimidazole isocyanuric acid adduct, 2-phenyl-4,5-dihydroxymethylimidazole, 2-phenyl-4-methyl-5-hydroxymethylimidazole, Examples include imidazole compounds such as 2,3-dihydro-1H-pyrrolo[1,2-a]benzimidazole, 1-dodecyl-2-methyl-3-benzylimidazolium chloride, 2-methylimidazoline, and 2-phenylimidazoline, as well as adducts of imidazole compounds and epoxy resins. Examples of commercially available imidazole-based curing accelerators include “1B2PZ”, “2E4MZ”, “2MZA-PW”, “2MZ-OK”, “2MA-OK”, “2MA-OK-PW”, “2PHZ”, “2PHZ-PW”, “Cl1Z”, “Cl1Z-CN”, “Cl1Z-CNS”, and “C11Z-A” manufactured by Shikoku Kasei Kogyo; and “P200-H50” manufactured by Mitsubishi Chemical.

[0420] Examples of amine-based curing accelerators include trialkylamines such as triethylamine and tributylamine, 4-dimethylaminopyridine, benzyldimethylamine, 2,4,6-tris(dimethylaminomethyl)phenol, and 1,8-diazabicyclo(5,4,0)-undecene. As amine-based curing accelerators, commercially available products may be used, for example, "MY-25" manufactured by Ajinomoto Fine Techno Co., Ltd.

[0421] (C) The amount of curing accelerator is preferably 0.01 mass% or more, more preferably 0.05 mass% or more, with respect to 100 mass% of the resin component of the resin composition, preferably 2 mass% or less, more preferably 1 mass% or less, and even more preferably 0.5 mass% or less.

[0422] The resin composition may include (D) a polymer resin. (D) The polymer resin does not include components corresponding to (A) to (C) described above. (D) The polymer resin is typically thermoplastic. In addition, (D) the polymer resin is typically included in the resin composition in a state compatible with (A) the thermosetting resin, and is included in the cured product in that compatible state. (D) The polymer resin may be used as a single type or in combination of two or more types.

[0423] (D) Polymer resins typically have a large molecular weight. Specifically, the range of the weight average molecular weight Mw of (D) polymer resin is preferably greater than 5,000, more preferably 8,000 or more, even more preferably 10,000 or more, even more preferably 20,000 or more, preferably 100,000 or less, more preferably 70,000 or less, even more preferably 60,000 or less, and even more preferably 50,000 or less. The weight average molecular weight Mw of (D) polymer resin can be measured as a polystyrene equivalent value by gel permeation chromatography (GPC).

[0424] (D) Examples of polymer resins include phenoxy resin, polyimide resin, polyvinyl acetal resin, polystyrene-based resin, polyolefin resin, polybutadiene resin, polyamideimide resin, polyethersulfone resin, polysulfone resin, polyetherimide resin, polyphenylene ether resin, polycarbonate resin, polyetheretherketone resin, polyester resin, etc. Among these, phenoxy resin and polyvinyl acetal resin are preferred.

[0425] Examples of phenoxy resins include phenoxy resins having one or more skeletons selected from the group consisting of bisphenol A skeleton, bisphenol F skeleton, bisphenol S skeleton, bisphenol acetophenone skeleton, novolac skeleton, biphenyl skeleton, fluorene skeleton, dicyclopentadiene skeleton, norbornene skeleton, naphthalene skeleton, anthracene skeleton, adamantane skeleton, terpene skeleton, and trimethylcyclohexane skeleton. The terminals of the phenoxy resin may be any functional group, such as phenolic hydroxyl groups or epoxy groups. Specific examples of phenoxy resins include "1256" and "4250" manufactured by Mitsubishi Chemical Corporation (both phenoxy resins containing a bisphenol A skeleton); and "YX8100" manufactured by Mitsubishi Chemical Corporation (phenoxy resin containing a bisphenol S skeleton). Examples include “YX7800BH40” (fluorene backbone containing phenoxy resin) manufactured by Mitsubishi Chemical Corporation; “YX6954” (bisphenol acetophenone backbone containing phenoxy resin) manufactured by Mitsubishi Chemical Corporation; “FX280” and “FX293” manufactured by Nittetsu Chemical & Materials Corporation; “YL7500BH30”, “YX6954BH30”, “YX7553”, “YX7553BH30”, “YL7769BH30”, “YL6794”, “YL7213”, “YL7290”, “YL7482”, “YL7891BH30”, “YL7891T30” and “YL9142T30” manufactured by Mitsubishi Chemical Corporation.

[0426] Examples of polyvinyl acetal resins include polyvinyl formal resin and polyvinyl butyral resin, and polyvinyl butyral resin is preferred. Specific examples of polyvinyl acetal resins include the S-Rec BH series, BX series (e.g., BX-5Z), KS series (e.g., KS-1), BL series, BM series manufactured by Sekisui Kagaku Kogyo Co., Ltd.

[0427] (D) The amount of polymer resin is preferably 0.1 mass% or more, more preferably 0.5 mass% or more, even more preferably 1 mass% or more, with respect to 100 mass% of the resin component of the resin composition, preferably 20 mass% or less, preferably 10 mass% or less, more preferably 5 mass% or less.

[0428] The resin composition may additionally include (E) any additive as an optional component. (E) The optional additive does not include those corresponding to the components (A) to (D) described above. (E) Optional additives include, for example, organometallic compounds such as organocopper compounds, organozinc compounds, and organocobalt compounds; coloring agents such as phthalocyanine blue, phthalocyanine green, iodine green, diazo yellow, crystal violet, titanium oxide, and carbon black; polymerization inhibitors such as hydroquinone, catechol, pyrogallol, and phenothiazine; leveling agents such as silicone-based leveling agents and acrylic polymer-based leveling agents; thickeners such as benton and montmorillonite; defoaming agents such as silicone-based defoaming agents, acrylic-based defoaming agents, fluorine-based defoaming agents, and vinyl resin-based defoaming agents; UV absorbers such as benzotriazole-based UV absorbers; adhesion improvers such as urea silane; and adhesion promoters such as triazole-based adhesion promoters, tetrazole-based adhesion promoters, and triazine-based adhesion promoters. Examples include antioxidants such as hindered phenolic antioxidants; fluorescent whitening agents such as stilbene derivatives; surfactants such as fluorine-based surfactants and silicone-based surfactants; flame retardants such as phosphorus-based flame retardants (e.g., phosphate ester compounds, phosphazene compounds, phosphinic acid compounds, red phosphate), nitrogen-based flame retardants (e.g., melamine sulfate), halogen-based flame retardants, and inorganic flame retardants (e.g., antimony trioxide); dispersants such as phosphate ester-based dispersants, polyoxyalkylene-based dispersants, acetylene-based dispersants, silicone-based dispersants, anionic dispersants, and cationic dispersants; and stabilizers such as borate-based stabilizers, titanate-based stabilizers, aluminite-based stabilizers, zirconate-based stabilizers, isocyanate-based stabilizers, carboxylic acid-based stabilizers, and carboxylic acid anhydride-based stabilizers. (E) Any additive may be used as a single type or in combination of two or more types.

[0429] The resin composition may additionally include a solvent (F) as an optional volatile component in combination with non-volatile components such as the components (A) to (E) described above. Typically, an organic solvent is used as the solvent (F). Examples of organic solvents include ketone-based solvents such as acetone, methyl ethyl ketone, methyl isobutyl ketone, and cyclohexanone; ester-based solvents such as methyl acetate, ethyl acetate, butyl acetate, isobutyl acetate, isoamyl acetate, methyl propionate, ethyl propionate, and γ-butyrolactone; ether-based solvents such as tetrahydropyran, tetrahydrofuran, 1,4-dioxane, diethyl ether, diisopropyl ether, dibutyl ether, diphenyl ether, and anisole; and alcohol-based solvents such as methanol, ethanol, propanol, butanol, and ethylene glycol. Ether ester solvents such as 2-ethoxyethyl acetate, propylene glycol monomethyl ether acetate, diethylene glycol monoethyl ether acetate, ethyl diglycol acetate, γ-butyrolactone, methyl methoxypropionate, etc.; ester alcohol solvents such as methyl lactate, ethyl lactate, methyl 2-hydroxyisobutyrate, etc.; ether alcohol solvents such as 2-methoxypropanol, 2-methoxyethanol, 2-ethoxyethanol, propylene glycol monomethyl ether, diethylene glycol monobutyl ether (butylcarbitol), etc.; amide solvents such as N,N-dimethylformamide, N,N-dimethylacetamide, N-methyl-2-pyrrolidone, etc.; sulfoxide solvents such as dimethyl sulfoxide; nitrile solvents such as acetonitrile, propionitrile, etc.; Examples include aliphatic hydrocarbon solvents such as hexane, cyclopentane, cyclohexane, and methylcyclohexane; aromatic hydrocarbon solvents such as benzene, toluene, xylene, ethylbenzene, and trimethylbenzene. (F) One type of solvent may be used alone, or two or more types may be used in combination.

[0430] (F) The amount of solvent may be, for example, 60 mass% or less, 40 mass% or less, 30 mass% or less, 20 mass% or less, 15 mass% or less, 10 mass% or less, or 5 mass% or less with respect to 100 mass% of the total components of the resin composition, and may be 0 mass%.

[0431] A resin composition can be prepared, for example, by mixing components that may be included in the resin composition. The aforementioned components may be mixed in part or in whole simultaneously, or they may be mixed sequentially. During the process of mixing each component, the temperature may be appropriately set, and thus, heating and / or cooling may be performed temporarily or over time. Additionally, stirring or shaking may be performed during the process of mixing each component.

[0432] [Example]

[0433] The present invention will be described in detail below with reference to examples. However, the present invention is not limited to these examples.

[0434] In the following description, "parts" and "%" indicating quantities refer to "parts by mass" and "% by mass," respectively, unless otherwise specified. Additionally, unless otherwise specified, the temperature and pressure conditions were room temperature (23°C) and atmospheric pressure (1 atm).

[0435] <Manufacturing Example 1. Manufacture of Insulating Multilayer Sheet 1>

[0436] (Manufacture of Resin Varnish 1)

[0437] A polyvinyl butyral resin (manufactured by Sekisui Kagaku Kogyo Co., Ltd. "KS-1") was dissolved in a solvent mixed with ethanol and toluene in a ratio of 1:1 (mass ratio) at 60°C to obtain a polyvinyl butyral resin solution with a solid content of 15%.

[0438] 28 parts of liquid bisphenol A type epoxy resin (epoxy equivalent 180 g / eq., manufactured by Japan Epoxy Resin Co., Ltd. “Epicoat 828EL”) and 28 parts of naphthalene type tetrafunctional epoxy resin (epoxy equivalent 163 g / eq., manufactured by Dainippon Ink & Chemical Co., Ltd. “HP4700”) were heated and dissolved while stirring in a mixed solvent consisting of 15 parts of methyl ethyl ketone (hereinafter abbreviated as “MEK”) and 15 parts of cyclohexanone. Here, 110 parts of phenol resin (naphthol-based curing agent, phenolic hydroxyl group equivalent 215 g / eq., manufactured by Toto Kasei Co., Ltd., MEK solution with 50% solid content), 0.1 parts of curing accelerator (manufactured by Shikoku Kasei Kogyo Co., Ltd., “2E4MZ”), 70 parts of spherical silica (average particle diameter 0.5 μm, manufactured by Adomatex Co., Ltd., “SO-C2”), and 30 parts of the above polyvinyl butyral resin solution were mixed and uniformly dispersed using a high-speed rotary mixer to produce resin varnish 1 as a liquid resin composition.

[0439] (Manufacture of a cured sheet having a primer cured layer)

[0440] A PET film (thickness 38 μm) having a surface treated with an alkyd-based release agent was prepared. The resin varnish 1 described above was uniformly applied to the release-treated surface of the PET film using a die coater and dried at 80°C to 120°C (average 100°C) for 3 minutes to form a thermosetting resin composition layer with a thickness of 3 μm. Subsequently, the thermosetting resin composition layer was heat-cured at 150°C for 15 minutes to obtain a cured sheet having a PET film and a primer cured layer.

[0441] (Manufacturing of prepreg layer)

[0442] Resin varnish 1 was impregnated into a fiber substrate (glass cloth "1015NS" manufactured by Arisawa Sesakusho Co., Ltd., warp density 95 threads / 25 mm, weft density 95 threads / 25 mm, fabric weight 17.5 g / m², thickness 15 μm), and dried until the amount of residual solvent in resin varnish 1 was 0.6% to obtain a prepreg layer with a thickness of 32 μm. A polypropylene film with a thickness of 15 μm was laminated onto one side of this prepreg layer, and a PET film with a thickness of 38 μm was laminated onto the other side.

[0443] (Formation of fiber-containing sheet 1 including a fiber substrate)

[0444] A polypropylene film laminated to one side of the prepreg layer was peeled off to expose the prepreg layer. This prepreg layer was placed on the surface of the primer cured layer of a cured sheet and laminated using a vacuum pressure laminator (manufactured by Meiki Sesakusho Co., Ltd.). This lamination was performed by vacuum suctioning for 30 seconds at a temperature of 120°C, followed by pressing for 30 seconds on a PET film with heat-resistant rubber interposed therein under conditions of a temperature of 120°C and a pressure of 7.0 kg / ㎠. Subsequently, under atmospheric pressure, a press was performed for 60 seconds using a SUS plate under conditions of a temperature of 120°C and a pressure of 5 kg / ㎠ to smooth the prepreg layer and the primer cured layer. Through the above operations, a fiber-containing sheet 1 having a prepreg layer and a primer cured layer was formed, and an insulating multilayer sheet 1 having a layer composition of "PET film / fiber-containing sheet 1 / PET film" was obtained.

[0445] <Manufacturing Example 2. Preparation of Resin Sheet 2>

[0446] (Manufacture of Resin Varnish 2)

[0447] A solution was obtained by heating and dissolving 15 parts of liquid bisphenol A type epoxy resin (epoxy equivalent 180 g / eq., manufactured by Mitsubishi Chemical Corporation “828US”) and 15 parts of biphenyl type epoxy resin (epoxy equivalent 291 g / eq., manufactured by Nippon Kayaku Co., Ltd. “NC3000H”) while stirring, 15 parts of methyl ethyl ketone (hereinafter abbreviated as “MEK”) and 15 parts of cyclohexanone. To this solution, 43 parts of a naphthalene-type active ester compound (active ester group equivalent 272 g / eq., "HPC8000-65T" manufactured by DIC, a toluene solution with 65% solid content), 0.15 parts of a curing accelerator (4-dimethylaminopyridine manufactured by Koei Chemical Co., Ltd.), 100 parts of spherical silica (average particle diameter 0.5 μm, specific surface area 5.8 m² / g, "SO-C2" manufactured by Adomatex, surface-treated with phenylaminosilane, carbon content per unit mass 0.18%), and 15 parts of a phenoxy resin ("YL6954BH30" manufactured by Mitsubishi Chemical, a MEK solution with 30 mass% solid content, weight average molecular weight 40000) were mixed and uniformly dispersed using a high-speed rotary mixer to prepare resin varnish 2 as a liquid resin composition.

[0448] (Manufacture of resin sheet 2)

[0449] A PET film (thickness 38 μm) having a surface treated with an alkyd-based release agent was prepared. The resin varnish 2 described above was uniformly applied to the release-treated surface of the PET film using a die coater, and dried at 80°C to 110°C (average 95°C) for 3 minutes to form a resin composition layer 2 with a thickness of 35 μm. Through the above operation, a resin sheet 2 having a layer structure of "PET film / resin composition layer 2" was obtained.

[0450] <Measurement test of the lowest melt viscosity of the prepreg layer provided by insulating multilayer sheet 1, and the resin composition layer 2 provided by resin sheet 2>

[0451] PET films on both sides were peeled off from insulating multilayer sheet 1 prepared in Preparation Example 1, and a primer cured layer was further peeled off to obtain a prepreg layer. In addition, a PET film was peeled off from resin sheet 2 prepared in Preparation Example 2 to obtain a resin composition layer 2. The minimum melt viscosity of each of the prepreg layer and the resin composition layer 2 was measured by the following measurement method.

[0452] (Method for measuring minimum melt viscosity)

[0453] For the sample (prepreg layer or resin composition layer 2), the melt viscosity was measured using a dynamic viscoelasticity measuring device ("Rheosol-G3000" manufactured by UBM). For a 1g sample, using a parallel plate with a diameter of 18mm, the temperature was raised from an initial temperature of 60℃ to 200℃ at a heating rate of 5℃ / min, and the dynamic viscoelasticity was measured under measurement conditions of a temperature interval of 2.5℃, vibration of 1Hz, and strain of 1deg, and the lowest melt viscosity (poise) in the temperature range from 100℃ to 140℃ was identified. In addition, from the results of the melt viscosity measurement, the temperature at which the lowest melt viscosity value was observed within the entire measurement range was identified.

[0454] <Measurement test of the coefficient of linear thermal expansion (CTE) of cured sample 1 of fiber-containing sheet 1 comprising insulating multilayer sheet 1, and cured sample 2 of resin composition layer 2 comprising resin sheet 2>

[0455] Insulating multilayer sheet 1 prepared in Preparation Example 1 was heated at 200°C for 90 minutes to cure fiber-containing sheet 1, and PET films on both sides were peeled off to obtain cured sample 1. In addition, resin sheet 2 prepared in Preparation Example 2 was heated at 200°C for 90 minutes to cure resin composition layer 2, and PET films were peeled off to obtain cured sample 2. The coefficient of linear thermal expansion (CTE) of each of cured samples 1 and 2 was measured by the following measurement method.

[0456] (Method for measuring the coefficient of linear thermal expansion)

[0457] The sample (hardened sample 1 or 2) was cut into a test specimen with a width of approximately 5 mm and a length of approximately 15 mm, and measured using a thermomechanical analyzer (TMA, manufactured by Hitachi High-Tech Science, TMA / SS7100) in "tensile mode" with a load of 1 N. The measurement was performed twice. The first measurement was performed in the range of 25°C to 200°C with a heating rate of 5°C / min. The second measurement was performed in the range of 25°C to 260°C with a heating rate of 5°C / min. Among the results of the second measurement, the coefficient of linear thermal expansion (ppm / °C) in the range of 25°C to 150°C and the coefficient of linear thermal expansion (ppm / °C) in the range of 150°C to 240°C were calculated.

[0458] <Measurement test of the glass transition temperature Tg of cured sample 1 of fiber-containing sheet 1 comprising insulating multilayer sheet 1, and cured sample 2 of resin composition layer 2 comprising resin sheet 2>

[0459] The glass transition temperature Tg of each of the cured samples 1 and 2 was measured using the following measurement method.

[0460] (Method for measuring glass transition temperature Tg)

[0461] A sample (cured sample 1 or 2) was cut to a width of 5 mm and a length of 15 mm to obtain a test specimen. Thermomechanical analysis was performed on this test specimen using the tensile weighting method with a viscoelasticity measuring device ("DMA7100" manufactured by Hitachi High-Tech Science Co., Ltd.). Specifically, after mounting the test specimen on the thermomechanical analysis device, the storage modulus and loss modulus were measured under measurement conditions of a load of 200 mN and a heating rate of 5°C / min. The glass transition temperature Tg (°C) was obtained from the peak top of the temperature dependence curve of tanδ (ratio of storage modulus to loss modulus) obtained as a measurement result after heating to 260°C.

[0462] <Measurement test of tensile modulus of cured sample 1 of fiber-containing sheet 1 comprising insulating multilayer sheet 1, and cured sample 2 of resin composition layer 2 comprising resin sheet 2>

[0463] The tensile modulus of hardened samples 1 and 2, respectively, was measured using the following measurement method.

[0464] (Method for measuring tensile modulus)

[0465] For the samples (cured samples 1 or 2), a tensile test was performed using a Tensilon universal testing machine (Orientech Co., Ltd. “RTC-1250A”) in accordance with Japanese Industrial Standard JIS K7127, and the tensile modulus was measured. The tensile modulus was measured at room temperature (23℃) and 260℃, respectively.

[0466] <Physical properties of fiber-containing sheet 1, resin composition layer 2, and cured samples thereof>

[0467] The lowest melt viscosity of the prepreg layer and resin composition layer 2 measured by the above method in the temperature range from 100°C to 140°C, the temperature at which the lowest melt viscosity value is observed across the entire measurement range, and the coefficient of linear thermal expansion CTE, glass transition temperature Tg, and tensile modulus of cured sample 1 of fiber-containing sheet 1 and cured sample 2 of resin composition layer 2 are shown in Table 1 below. The lowest melt viscosity value of the prepreg layer and resin composition layer 2 measured here was the lowest melt viscosity in the temperature range from 100°C to 140°C, and at the same time, it was the lowest value among the melt viscosities across the entire measurement range. Therefore, the temperature at which the lowest melt viscosity is observed corresponds to the temperature at which the lowest melt viscosity value is observed across the entire measurement range.

[0468]

[0469] <Example 1>

[0470] (1-1. Preparation of Core Substrate)

[0471] A glass-based epoxy resin double-sided copper laminate having copper layers on both surfaces (copper layer thickness 18 μm, substrate thickness 0.2 mm, manufactured by Resonac “MCL-E-705G”) was prepared as a core substrate. By immersing both sides of this core substrate in an etching agent (manufactured by Mech “CZ8100”), a surface treatment of the copper layers was performed.

[0472] (1-2. Formation of the first insulating layer)

[0473] A resin sheet 2 was placed on the chip side of the core substrate so that the resin composition layer 2 was bonded to the core substrate. Additionally, a resin sheet 2 was placed on the opposite side of the core substrate so that the resin composition layer 2 was bonded to the core substrate. After that, lamination was performed using a vacuum pressure laminator ("MVLP-500" manufactured by Meiki Sesakusho Co., Ltd.). This lamination was carried out by vacuum suctioning for 30 seconds at 120°C, and then pressing for 60 seconds over a PET film with heat-resistant rubber interposed therein under conditions of 120°C and a pressure of 0.7 MPa. Subsequently, under atmospheric pressure, a press was performed for 90 seconds using a SUS plate under conditions of 120°C and a pressure of 0.54 MPa to smooth the resin composition layer 2.

[0474] A PET film was peeled off from the laminated resin composition layer 2. Then, the resin composition layer 2 was heat-cured under curing conditions of 200°C for 90 minutes to form a first insulating layer on each of the chip side and the opposite side of the core substrate. Through the above operation, an intermediate product (I) having a layer configuration of “insulating layer / core substrate / insulating layer” was obtained.

[0475] (1-3. Formation of the second insulating layer)

[0476] A resin sheet 2 was placed on the chip-side insulating layer of the above intermediate product (I) so that the resin composition layer 2 bonded to the intermediate product (I). Additionally, a resin sheet 2 was placed on the insulating layer on the opposite side of the intermediate product (I) so that the resin composition layer 2 bonded to the intermediate product (I). After that, lamination, smoothing, peeling of the PET film, and heat curing were performed under the same conditions as the process (1-2) for forming the first insulating layer, thereby forming the second insulating layer by interposing the first insulating layer on each of the chip-side and opposite-side of the core substrate. Through the above operations, an intermediate product (II) having a layer configuration of “insulating layer (2nd layer) / insulating layer (1st layer) / core substrate / insulating layer (1st layer) / insulating layer (2nd layer)” was obtained.

[0477] (1-4. Formation of the third insulating layer)

[0478] A resin sheet 2 was placed on the insulating layer on the chip side of the above intermediate product (II) so that the resin composition layer 2 was bonded to the intermediate product (II). Additionally, a resin sheet 2 was placed on the insulating layer on the opposite side of the intermediate product (II) so that the resin composition layer 2 was bonded to the intermediate product (II). After that, lamination, smoothing, peeling of the PET film, and heat curing were performed under the same conditions as the process (1-2) for forming the first insulating layer, and a third insulating layer was formed by interposing the first and second insulating layers on the chip side and opposite side of the core substrate, respectively. Through the above operations, an intermediate product (III) having a layer configuration of “insulating layer (3rd layer) / insulating layer (2nd layer) / insulating layer (1st layer) / core substrate / insulating layer (1st layer) / insulating layer (2nd layer) / insulating layer (3rd layer)” was obtained.

[0479] (1-5. Formation of the 4th insulating layer)

[0480] A resin sheet 2 was placed on the chip-side insulating layer of the above intermediate product (III) so that the resin composition layer 2 is bonded to the intermediate product (III).

[0481] In addition, the PET film on one side of the insulating multilayer sheet 1 was peeled off to expose the prepreg layer. The insulating multilayer sheet 1 was placed on the insulating layer on the opposite side of the intermediate product (III) so that the prepreg layer was bonded to the intermediate product (III).

[0482] After that, lamination, smoothing, peeling of the PET film, and heat curing were performed under the same conditions as the process (1-2) for forming the first insulating layer, and the first, second, and third insulating layers were interposed on the chip side and opposite side of the core substrate, respectively, to form the fourth insulating layer. Through the above operations, an evaluation structure having a layer configuration of “insulating layer (4th layer) / insulating layer (3rd layer) / insulating layer (2nd layer) / insulating layer (1st layer) / core substrate / insulating layer (1st layer) / insulating layer (2nd layer) / insulating layer (3rd layer) / insulating layer (4th layer)” was obtained. In this evaluation structure, the fourth insulating layer formed on the opposite side of the core substrate included a fiber substrate, and the other insulating layers did not include a fiber substrate.

[0483] <Example 2>

[0484] In the process (1-4) of forming the third insulating layer, an insulating multilayer sheet 1 with a peeled PET film was placed on the insulating layer opposite the intermediate product (II) instead of the resin sheet 2. This insulating multilayer sheet 1 has a prepreg layer exposed by peeling off the PET film on one side, and the prepreg layer is placed to be bonded to the intermediate product (II).

[0485] Except for the above, an evaluation structure was manufactured by the same method as in Example 1. In this evaluation structure, the third and fourth insulating layers formed on opposite sides of the core substrate included a fiber substrate, and the other insulating layers did not include a fiber substrate.

[0486] <Example 3>

[0487] In the process (1-3) of forming the second insulating layer, an insulating multilayer sheet 1 with a peeled PET film was placed on the insulating layer opposite the intermediate product (I) instead of the resin sheet 2. This insulating multilayer sheet 1 has a prepreg layer exposed by peeling off the PET film on one side, and the prepreg layer is placed to be bonded to the intermediate product (I).

[0488] Additionally, in the process (1-4) of forming the third insulating layer, an insulating multilayer sheet 1 with a peeled PET film was placed on the insulating layer opposite the intermediate product (II) instead of the resin sheet 2. This insulating multilayer sheet 1 has a prepreg layer exposed by peeling off the PET film on one side, and the prepreg layer is placed to be bonded to the intermediate product (II).

[0489] Except for the above, an evaluation structure was manufactured by the same method as in Example 1. In this evaluation structure, the second, third, and fourth insulating layers formed on opposite sides of the core substrate included fiber substrates, and the other insulating layers did not include fiber substrates.

[0490] <Example 4>

[0491] In the process (1-2) of forming the first insulating layer, an insulating multilayer sheet 1 with a peeled PET film was placed on the chip side and opposite side of the core substrate instead of the resin sheet 2. This insulating multilayer sheet 1 has a prepreg layer exposed by peeling off the PET film on one side, and the prepreg layer is placed to bond with the core substrate.

[0492] Except for the above, an evaluation structure was manufactured by the same method as in Example 1. In this evaluation structure, the first insulating layer formed on the chip side of the core substrate, and the first and fourth insulating layers formed on the opposite side of the core substrate, included a fiber substrate, and the other insulating layers did not include a fiber substrate.

[0493] <Example 5>

[0494] In the process (1-2) of forming the first insulating layer, an insulating multilayer sheet 1 with a peeled PET film was placed on the opposite side of the core substrate instead of a resin sheet 2. This insulating multilayer sheet 1 has a prepreg layer exposed by peeling off the PET film on one side, and the prepreg layer is placed to bond with the core substrate.

[0495] Additionally, in the process (1-5) of forming the fourth insulating layer, a resin sheet 2 was placed on the insulating layer opposite the intermediate product (III) instead of an...

Claims

Claim 1 A method for manufacturing a structure for mounting a semiconductor chip, wherein the structure comprises a core substrate, a chip-side build-up layer formed on a first side of the core substrate, and an opposite-side build-up layer formed on a second side opposite to the first side of the core substrate; wherein the chip-side build-up layer comprises a plurality of insulating layers; wherein all of the plurality of insulating layers provided by the chip-side build-up layer do not include a fiber substrate, or wherein a portion of the plurality of insulating layers provided by the chip-side build-up layer includes a fiber substrate; wherein the opposite-side build-up layer comprises a plurality of insulating layers; and wherein a portion of the plurality of insulating layers provided by the opposite-side build-up layer includes a fiber substrate; wherein the method for manufacturing the structure comprises a plurality of steps (i) for forming an insulating layer on a first side of the core substrate and a plurality of steps (ii) for forming an insulating layer on a second side of the core substrate; wherein the number of insulating layers including a fiber substrate in the opposite-side build-up layer is 5% or more and 80% or less with respect to 100% of the total number of insulating layers in the opposite-side build-up layer; and wherein the number of insulating layers including a fiber substrate in the opposite-side build-up layer is the chip-side A method for manufacturing a structure having more than the number of insulating layers containing fiber substrates in the build-up layer. Claim 2 A method for manufacturing a structure for mounting a semiconductor chip, wherein the structure comprises a core substrate, a chip-side build-up layer formed on a first side of the core substrate, and an opposite-side build-up layer formed on a second side opposite to the first side of the core substrate; wherein the chip-side build-up layer comprises a plurality of insulating layers; wherein all of the plurality of insulating layers comprising the chip-side build-up layer do not include a fiber substrate, or wherein a portion of the plurality of insulating layers comprising the chip-side build-up layer includes a fiber substrate; wherein the opposite-side build-up layer comprises a plurality of insulating layers; and wherein a portion of the plurality of insulating layers comprising the opposite-side build-up layer includes a fiber substrate; wherein the method for manufacturing the structure comprises a plurality of steps (i) for forming an insulating layer on a first side of the core substrate and a plurality of steps (ii) for forming an insulating layer on a second side of the core substrate; wherein the sum of the thicknesses of the insulating layers comprising fiber substrates in the opposite-side build-up layer is 5% or more and 80% or less when the sum of the thicknesses of the plurality of insulating layers in the opposite-side build-up layer is set to 100%; and wherein the insulating layer comprising fiber substrates in the opposite-side build-up layer A method for manufacturing a structure in which the total thickness is greater than the total thickness of the insulating layer including the fiber substrate in the chip-side build-up layer. Claim 3 A method for manufacturing a structure according to claim 1 or 2, wherein a plurality of steps (ii) for forming an insulating layer on a second side of a core substrate comprises a step for forming an insulating layer comprising a fiber substrate; the step for forming an insulating layer comprising a fiber substrate comprises laminating a fiber-containing sheet having a prepreg layer; and the prepreg layer comprises a fiber substrate and a resin composition impregnated in the fiber substrate. Claim 4 A method for manufacturing a structure according to claim 3, wherein the lamination of fiber-containing sheets is performed by a lamination method. Claim 5 A method for manufacturing a structure according to claim 3, wherein the fiber-containing sheet comprises a prepreg layer and a cured layer formed on one side of the prepreg layer, and the cured layer comprises a cured product of a thermosetting resin composition. Claim 6 A method for manufacturing a structure according to claim 3, wherein the minimum melt viscosity of the prepreg layer in a temperature range of 100°C to 140°C is 10,000 poise or less. Claim 7 A method for manufacturing a structure according to claim 3, wherein the glass transition temperature of a cured sample obtained by curing a fiber-containing sheet is 250°C or lower. Claim 8 A method for manufacturing a structure according to claim 3, wherein a plurality of steps (ii) for forming an insulating layer on a second side of a core substrate includes a step for forming an insulating layer that does not include a fiber substrate; the step for forming an insulating layer that does not include a fiber substrate includes laminating a resin composition layer that does not include a fiber substrate; and the absolute value of the difference between the glass transition temperature of a cured sample obtained by curing a fiber-containing sheet and the glass transition temperature of a cured sample obtained by curing a resin composition layer is 80°C or less. Claim 9 A method for manufacturing a structure according to claim 1 or 2, wherein the core substrate has a thickness of 0.1 mm or more and 2 mm or less. Claim 10 A method for manufacturing a structure according to claim 1 or 2, wherein the opposite side build-up layer comprises four or more insulating layers. Claim 11 A method for manufacturing a structure according to claim 1 or 2, wherein the opposite side build-up layer has a thickness of 60 μm or more and 700 μm or less. Claim 12 A method for manufacturing a structure according to claim 1 or 2, wherein the number of insulating layers provided by the chip-side build-up layer and the number of insulating layers provided by the opposite-side build-up layer are the same. Claim 13 A structure for mounting a semiconductor chip; the structure comprises a core substrate, a chip-side build-up layer formed on a first side of the core substrate, and an opposite-side build-up layer formed on a second side opposite to the first side of the core substrate; the chip-side build-up layer comprises a plurality of insulating layers; all of the plurality of insulating layers in the chip-side build-up layer do not include a fiber substrate, or a portion of the plurality of insulating layers in the chip-side build-up layer includes a fiber substrate; the opposite-side build-up layer comprises a plurality of insulating layers; a portion of the plurality of insulating layers in the opposite-side build-up layer includes a fiber substrate; the number of insulating layers in the opposite-side build-up layer that include a fiber substrate is 5% or more and 80% or less with respect to 100% of the total number of insulating layers in the opposite-side build-up layer; and the number of insulating layers in the opposite-side build-up layer that include a fiber substrate is greater than the number of insulating layers in the chip-side build-up layer that include a fiber substrate. Claim 14 A structure for mounting a semiconductor chip; the structure comprises a core substrate, a chip-side build-up layer formed on a first side of the core substrate, and an opposite-side build-up layer formed on a second side opposite to the first side of the core substrate; the chip-side build-up layer comprises a plurality of insulating layers; all of the plurality of insulating layers in the chip-side build-up layer do not include a fiber substrate, or a portion of the plurality of insulating layers in the chip-side build-up layer includes a fiber substrate; the opposite-side build-up layer comprises a plurality of insulating layers; a portion of the plurality of insulating layers in the opposite-side build-up layer includes a fiber substrate; the sum of the thicknesses of the insulating layers in the opposite-side build-up layer that include a fiber substrate is 5% or more and 80% or less when the sum of the thicknesses of the plurality of insulating layers in the opposite-side build-up layer is 100%; and the sum of the thicknesses of the insulating layers in the opposite-side build-up layer that include a fiber substrate is greater than the sum of the thicknesses of the insulating layers in the chip-side build-up layer that include a fiber substrate. Claim 15 A method for manufacturing a semiconductor chip package, comprising a process of mounting a semiconductor chip on a chip-side build-up layer of a structure described in claim 13 or 14. Claim 16 A semiconductor chip package comprising a structure described in claim 13 or 14 and a semiconductor chip mounted on a chip-side build-up layer of said structure. Claim 17 A semiconductor device having a semiconductor chip package as described in claim 16.

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